WO2023155262A1 - 接触结构及其制备方法、半导体结构 - Google Patents

接触结构及其制备方法、半导体结构 Download PDF

Info

Publication number
WO2023155262A1
WO2023155262A1 PCT/CN2022/081448 CN2022081448W WO2023155262A1 WO 2023155262 A1 WO2023155262 A1 WO 2023155262A1 CN 2022081448 W CN2022081448 W CN 2022081448W WO 2023155262 A1 WO2023155262 A1 WO 2023155262A1
Authority
WO
WIPO (PCT)
Prior art keywords
contact
contact hole
layer
hole
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2022/081448
Other languages
English (en)
French (fr)
Inventor
王海艳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Changxin Memory Technologies Inc
Original Assignee
Changxin Memory Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Changxin Memory Technologies Inc filed Critical Changxin Memory Technologies Inc
Priority to US17/662,473 priority Critical patent/US20230262963A1/en
Publication of WO2023155262A1 publication Critical patent/WO2023155262A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • the present disclosure relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a contact structure, a preparation method thereof, and a semiconductor structure.
  • Dynamic random access memory (Dynamic Random Access Memory, referred to as DRAM) is a semiconductor memory commonly used in electronic equipment such as computers, which is composed of multiple storage units.
  • the storage unit includes: a storage capacitor, and a transistor electrically connected to the storage capacitor.
  • a transistor includes a gate, a source region and a drain region. The gate of the transistor is used to electrically connect with the word line.
  • the source area of the transistor is used to form a bit line contact area to be electrically connected to the bit line through the bit line contact structure.
  • the drain region of the transistor is used to form a storage node contact region to be electrically connected to the storage capacitor through the storage node contact structure.
  • bit line contact BLC for short
  • TWR Write Recovery Time
  • a contact structure, a manufacturing method thereof, and a semiconductor structure are provided.
  • one aspect of the present disclosure provides a method for manufacturing a contact structure, and the method includes steps as described below.
  • a substrate is provided, and the substrate has a shallow trench isolation structure. Shallow trench isolation structures isolate active regions within the substrate.
  • a dielectric layer covering the substrate and the shallow trench isolation structure is formed.
  • Contact holes are formed in the active area of the substrate and the dielectric layer.
  • the contact hole includes: a first contact hole penetrating through the dielectric layer, and a second contact hole located at the bottom of the first contact hole and formed in the substrate.
  • a diameter of a portion of the second contact hole close to the first contact hole gradually increases in a direction close to the first contact hole, and a maximum diameter of the second contact hole is equal to or smaller than that of the first contact hole.
  • forming a contact hole in the active region of the substrate and the dielectric layer includes the following steps.
  • a contact bottom hole is formed in the active area of the substrate and the dielectric layer.
  • Part of the sidewall of the contact bottom hole is removed to form a first contact hole in the dielectric layer and a second contact hole in the substrate.
  • the sidewalls of the contact bottom holes are formed of shallow trench isolation structures. Removing part of the sidewall of the bottom contact hole to form a first contact hole in the dielectric layer and a second contact hole in the active area of the substrate includes the following steps.
  • part of the dielectric layer is etched back to form a first contact hole and a guide hole at the bottom of the first contact hole.
  • part of the shallow trench isolation structure is removed to form the second contact hole.
  • the etching back to remove part of the dielectric layer includes: cleaning the structure obtained after forming the contact bottom hole, and etching back to remove part of the dielectric layer.
  • removing part of the shallow trench isolation structure based on the first contact hole and the guide hole to form the second contact hole includes the following steps.
  • a hard mask is formed in the guide hole, so that the portion of the shallow trench isolation structure to be removed is exposed above the hard mask.
  • part of the shallow trench isolation structure is removed.
  • the hard mask is removed to form a second contact hole.
  • forming a hard mask in a guide hole includes the following steps.
  • a predetermined thickness of the hard mask material is removed, so that the hard mask material remaining in the guide hole forms a hard mask.
  • removing part of the substrate and part of the shallow trench isolation structure includes: etching the structure obtained after forming the hard mask, so as to remove part of the shallow trench isolation structure.
  • the manufacturing method of the contact structure further includes: forming a contact structure extending along the first direction in the contact hole and on the dielectric layer.
  • forming a contact structure extending along the first direction in the contact hole and on the dielectric layer includes the following steps.
  • a contact conductive layer extending along the first direction is formed in the contact hole and on the dielectric layer.
  • a first barrier layer covering the contact conductive layer is formed.
  • a second barrier layer is formed covering the first barrier layer.
  • the contact conductive layer, the first barrier layer and the second barrier layer together constitute a contact structure.
  • the material of the first barrier layer includes titanium.
  • the thickness of the first barrier layer ranges from 5 nm to 10 nm.
  • the second barrier layer includes a layer group consisting of titanium nitride layers and silicon nitride layers stacked alternately.
  • Forming the second barrier layer covering the first barrier layer includes: periodically depositing a titanium nitride layer and a silicon nitride layer on the first barrier layer.
  • the mass ratio of the titanium nitride layer and the silicon nitride layer for forming the second barrier layer ranges from 10:1 to 20:1.
  • another aspect of the present disclosure provides a contact structure prepared by using the preparation method described in some embodiments above.
  • the contact structure is formed in the contact hole.
  • the contact hole is arranged in the active area of the substrate and the dielectric layer.
  • a dielectric layer covers the substrate.
  • the contact hole includes: a first contact hole penetrating through the dielectric layer, and a second contact hole located at the bottom of the first contact hole and inside the substrate.
  • the contact structure is also located on the dielectric layer and extends along the first direction.
  • a diameter of a portion of the second contact hole close to the first contact hole gradually increases in a direction close to the first contact hole, and a maximum diameter of the second contact hole is equal to or smaller than that of the first contact hole.
  • the contact structure includes: a contact conductive layer, a first barrier layer and a second barrier layer stacked along a direction away from the substrate.
  • the first barrier layer includes a titanium layer.
  • the titanium layer has a thickness ranging from 5 nm to 10 nm.
  • the second barrier layer includes a layer group consisting of titanium nitride layers and silicon nitride layers stacked alternately.
  • the contact conductive layer includes a polysilicon layer.
  • another aspect of the present disclosure provides a semiconductor structure, including the contact structure described in some embodiments above, and a bit line structure or a storage capacitor disposed on the surface of the contact structure away from the substrate.
  • Embodiments of the present disclosure may/at least have the following advantages:
  • the shape of the contact hole is improved, specifically: the contact hole is formed from the first contact hole in the dielectric layer to the second contact hole in the substrate.
  • the two contact holes are connected to each other, and the diameter of a part of the second contact hole increases along the direction close to the first contact hole, and the maximum diameter of the second contact hole is equal to or smaller than that of the first contact hole.
  • the contact structure includes a contact conductive layer, a first barrier layer and a second barrier layer, and the contact conductive layer is a polysilicon layer, the first barrier layer is a titanium layer, and the second barrier layer is a titanium nitride layer A layer group formed by alternately stacking silicon nitride layers.
  • the second barrier layer can be used to effectively block the diffusion of impurity elements (such as boron (B) and phosphorus (P), etc.) in the contact conductive layer into the conductive structure connected to the contact structure, so as to avoid the impact of impurity elements on the aforementioned conductive structure. adverse effects on electricity.
  • the first barrier layer can also be used to effectively isolate the nitrogen ions in the second barrier layer from diffusing to the contact conductive layer, so as to prevent the nitrogen ions from adversely affecting the electrical properties of the contact conductive layer. Therefore, it can be ensured that the electrical properties of the contact structure and the conductive structure connected thereto are good.
  • the method for preparing the contact structure, the contact structure, and the semiconductor structure provided by the embodiments of the present disclosure can improve the electrical properties of the contact structure and the semiconductor structure, so as to increase the yield of the semiconductor structure.
  • FIG. 1 is a schematic flow diagram of a method for preparing a contact structure provided in an embodiment
  • Fig. 2 is a schematic diagram of the structure obtained in step S100 provided in an embodiment
  • Fig. 3 is a schematic diagram of the structure obtained in step S200 provided in an embodiment
  • FIG. 4 is a schematic diagram of the structure obtained in step S300 provided in an embodiment
  • FIG. 5 is a schematic diagram of the structure obtained in step S310 provided in an embodiment
  • FIGS. 6 to 9 are schematic diagrams of the structure obtained in each sub-step in step S320 provided in an embodiment
  • FIG. 10 is a schematic diagram of the structure obtained in step S400 provided in an embodiment; and FIG. 10 is also a schematic structural diagram of a contact structure provided in an embodiment;
  • Fig. 11 is a schematic structural diagram of a second barrier layer provided in an embodiment
  • FIG. 12 is a schematic structural diagram of a semiconductor structure provided in an embodiment
  • FIG. 13 is a schematic structural diagram of a semiconductor structure provided in an embodiment.
  • Embodiments of the invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present disclosure such that variations in the shapes shown as a result, for example, of manufacturing techniques and/or tolerances are contemplated.
  • embodiments of the present disclosure should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing techniques.
  • the regions shown in the figures are schematic in nature and their shapes are not indicative of the actual shape of a region of a device and are not intended to limit the scope of the disclosure.
  • an embodiment of the present disclosure provides a method for preparing a contact structure, and the steps included in the method are as follows.
  • the substrate has a shallow trench isolation structure, and the shallow trench isolation structure isolates an active area in the substrate.
  • the contact hole includes: a first contact hole penetrating through the dielectric layer, and a second contact hole located at the bottom of the first contact hole and formed in the substrate.
  • a diameter of a portion of the second contact hole close to the first contact hole gradually increases along a direction close to the first contact hole, and a maximum diameter of the second contact hole is equal to or smaller than that of the first contact hole.
  • the contact hole is formed by connecting the first contact hole in the dielectric layer with the second contact hole in the substrate, and part of the diameter of the second contact hole increases along the direction close to the first contact hole.
  • the maximum aperture of the second contact hole is equal to or smaller than the aperture of the first contact hole, which can ensure that the contact hole still has a large opening size when the bottom size of the contact hole is small, which is conducive to reducing the contact hole.
  • the aspect ratio and the step coverage of the contact structure can be improved, thereby avoiding the formation of unnecessary pores in the contact structure, thereby avoiding the problem of electrical abnormalities in the semiconductor structure caused by metal penetration and filling of the pores in the contact structure.
  • the embodiments of the present disclosure can improve the electrical properties of the contact structure and the semiconductor structure where the contact structure is located, so as to improve the yield of the semiconductor structure.
  • a substrate 10 is provided.
  • the substrate 10 has a shallow trench isolation structure 11 , and the shallow trench isolation structure 11 isolates an active region S A within the substrate 10 .
  • the substrate 10 includes, but is not limited to, a silicon substrate or a silicon-based substrate.
  • the shallow trench isolation structure 11 is a silicon oxide (SiO 2 ) isolation structure.
  • the shallow trench isolation structure 11 can isolate a plurality of active regions S A arranged in an array in the substrate 10 .
  • the active area SA includes a source area and a drain area. In FIGS. 2 to 10 , only the source region or the drain region of one active region SA is taken as an example for illustration.
  • step S200 referring to S200 in FIG. 1 and FIG. 3 , a dielectric layer 12 covering the substrate 10 and the shallow trench isolation structure 11 is formed.
  • the material of the dielectric layer 12 is different from that of the shallow trench isolation structure 11 , and the dielectric layer 12 can be used as a protective layer for subsequent etching of the shallow trench isolation structure 11 .
  • the thickness of the dielectric layer 12 can be selected and set according to actual needs. Embodiments of the present disclosure do not limit this.
  • the dielectric layer 12 is a silicon nitride layer.
  • step S300 referring to S300 in FIG. 1 and FIG. 4 , a contact hole H is formed in the active region SA of the substrate 10 and the dielectric layer 12 .
  • the contact hole H includes: a first contact hole H 1 penetrating through the dielectric layer 12 , and a second contact hole H 2 located at the bottom of the first contact hole H 1 and formed in the substrate 10 .
  • the diameter of the portion of the second contact hole H2 close to the first contact hole H1 gradually increases along the direction close to the first contact hole H1 , and the maximum diameter of the second contact hole H2 is equal to or smaller than Aperture diameter of the first contact hole H1 .
  • the diameter of the portion of the second contact hole H2 close to the first contact hole H1 increases uniformly (for example, linearly) in the direction close to the first contact hole H1 , or increases according to a preset change rule. Large (for example, increasing in a curve).
  • the second contact hole H2 also includes a second part located on the side of the first part away from the first contact hole H1 .
  • the diameter of the second part may remain constant or gradually increase toward the first part.
  • the change rate of the increase of the aperture diameter of the second part along the direction close to the first part is smaller than that of the first part aperture along the direction close to the first part. The rate of change of the direction of the first contact hole H1 increases.
  • the depths of the first contact hole H1 and the second contact hole H2 can be selected and set according to actual requirements. Since the first contact hole H1 penetrates the dielectric layer 12, the deposition thickness of the dielectric layer 12 is the depth of the first contact hole H1 .
  • the shape of the orthographic projection of any cross-section of the contact hole H on the substrate 10 may be a circle, an ellipse, a rectangle, or a rhombus, which is not limited in the embodiments of the present disclosure.
  • the diameter of the contact hole H refers to the size of the contact hole H on its cross section, which is a cross section parallel to the substrate 10 .
  • the aforementioned maximum diameter of the second contact hole H2 is equal to the diameter of the first contact hole H1 , which means that the upper edge of the second contact hole H2 coincides with the lower edge of the first contact hole H1 .
  • the maximum aperture of the second contact hole H2 is smaller than the aperture of the first contact hole H1 , which means that there is an interval between the upper edge of the second contact hole H2 and the lower edge of the first contact hole H1 , and can be passed through parallel Connected to the plane of the substrate 10.
  • the diameter of the first contact hole H 1 gradually increases or remains the same along the direction away from the second contact hole H 2 , whichever is acceptable.
  • step S300 includes the following steps.
  • the contact bottom hole H 0 is formed by one patterning process, that is, based on the same mask, the dielectric layer 12 and the active region SA of the substrate 10 are etched to form the contact bottom hole H 0 .
  • the bottom contact hole H0 is provided in one-to-one correspondence with the source region and/or the drain region of the active region SA of the substrate 10 .
  • the size of the bottom of the contact bottom hole H0 depends on the size of the contact hole allowed in the semiconductor structure.
  • the sidewall of the contact bottom hole H0 can be composed of the substrate 10 or the shallow trench isolation structure 11 according to the size of the contact bottom hole H0 .
  • the contact bottom hole H 0 exposes part of the STI structure 11 , and the sidewall of the contact bottom hole H 0 is formed by the STI structure 11 .
  • the material of the dielectric layer 12 , the material of the shallow trench isolation structure 11 and the material of the substrate 10 are all different, and the first contact hole H 1 and the second contact hole H 2 can be formed by different etching methods.
  • Step S320 includes steps as described below.
  • the guide hole H20 is the part of the contact bottom hole H0 located in the substrate 10, specifically, it may be a part lower than the initial exposed surface of the active region SA or lower than the initial upper surface of the shallow trench isolation structure 11. .
  • the dielectric layer 12 is a silicon nitride layer, and etching back the silicon nitride layer can effectively remove part of the silicon nitride material, so as to increase the critical dimension of the opening in the silicon nitride layer, that is, it can increase
  • the contact bottom hole H 0 is located in the portion of the dielectric layer 12 to obtain a first contact hole H 1 .
  • the etch-back removal of the dielectric layer 12 can be obtained by cleaning the structure obtained after the contact bottom hole H0 is formed.
  • wet etching is used to etch back and remove the dielectric layer 12 .
  • hydrofluoric acid solution, phosphoric acid solution and standard cleaning solution are used to sequentially clean the structure obtained after forming the contact bottom hole H 0 to etch back part of the dielectric layer 12 to form the first contact hole H 1 .
  • the first contact hole H1 After the first contact hole H1 is formed, a portion of the shallow trench isolation structure 11 is exposed at the bottom of the first contact hole H1 .
  • the upper sidewall of the contact bottom hole H0 located in the inner part of the substrate 10 is removed from top to bottom to form the second contact hole H2 , and part of the diameter of the second contact hole H2 is The direction of a contact hole H1 increases.
  • the sidewall of the contact bottom hole H 0 is formed by the shallow trench isolation structure 11 , and the step S322 includes the following steps.
  • the preparation method of the hard mask 13 is as follows.
  • the hard mask material 130 is filled in the guide hole H 20 .
  • the hard mask material 130 can be selected and set according to actual requirements, such as photoresist material or spin on hard mask (SOH, Spin on Hard mask) material.
  • photoresist material or spin on hard mask (SOH, Spin on Hard mask) material.
  • SOH Spin on Hard mask
  • the hard mask material 130 is a SOH material.
  • the hard mask material 130 may be coated in the first contact hole H1 and the guide hole H20 by using a spin coating process, but is not limited thereto.
  • the hard mask material 130 may be filled only in the portion of the bottom contact hole H0 located in the substrate 10 through a deposition process, that is, filled in the guide hole H20 .
  • the deposition process includes but is not limited to physical vapor deposition (Physical Vapor Deposition, referred to as PVD), chemical vapor deposition (Chemical Vapor Deposition, referred to as CVD) or atomic layer deposition (Atomic Layer Deposition, referred to as ALD).
  • PVD Physical Vapor Deposition
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • a predetermined thickness T of the hard mask material 130 is removed, so that the hard mask material remaining in the guide hole H 20 forms the hard mask 13 , as shown in FIG. 8 .
  • the preset thickness T can be determined according to the molding thickness of the hard mask material 130 and the height of the aperture change portion in the second contact hole H2 , so that part of the shallow trench isolation structure 11 is exposed above the hard mask 13. .
  • part of the shallow trench isolation structure 11 is removed. That is, part of the sidewall of the guide hole H 20 exposed above the hard mask 13 is removed, such as shown in FIG. 9 .
  • the removal of the shallow trench isolation structure 11 may be performed by etching, such as wet etching.
  • the shallow trench isolation structure 11 is a silicon oxide (SiO 2 ) isolation structure, and a hydrofluoric acid solution may be used to perform wet etching on the structure obtained after forming the hard mask 13 .
  • the hard mask 13 can be removed by, for example, a plasma etching process.
  • step S400 referring to S400 in FIG. 1 and FIG. 10 , a contact structure 14 extending along a first direction is formed in the contact hole H and on the dielectric layer 12 .
  • the contact structure 14 is, for example, a bit line contact structure, but not limited thereto.
  • the preparation method of the contact structure 14 is as follows.
  • the contact conductive layer 141 is a polysilicon layer, but it is not limited thereto. Other conductive materials having the same or similar electrical properties as polysilicon can also be used to form the contact conductive layer 141 .
  • the contact conductive layer 141 is formed by a deposition process, and a portion of the contact conductive layer 141 is filled in the contact hole H. Referring to FIG.
  • the deposition process includes but is not limited to physical vapor deposition (Physical Vapor Deposition, referred to as PVD), chemical vapor deposition (Chemical Vapor Deposition, referred to as CVD) or atomic layer deposition (Atomic Layer Deposition, referred to as ALD).
  • PVD Physical Vapor Deposition
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • the contact hole H is formed by connecting the first contact hole H1 and the second contact hole H2 , and part of the diameter of the second contact hole H2 increases along the direction close to the first contact hole H1. is large, and the maximum diameter of the second contact hole H2 is equal to or smaller than the diameter of the first contact hole H1 .
  • the first contact hole H1 can be used to increase the opening size of the contact hole H
  • the second contact hole H2 can be used to connect the diameter change portion of the first contact hole H1 to slow down the slope of the step.
  • the contact conductive layer 141 after the contact conductive layer 141 is formed in the contact hole H, it can not only avoid unnecessary voids in the contact conductive layer 141 , but also ensure good step coverage of the contact conductive layer 141 .
  • the material of the first barrier layer 142 includes titanium.
  • the first blocking layer 142 may be used to block diffusion of nitrogen ions.
  • the first barrier layer 142 is formed by a deposition process, such as physical vapor deposition (Physical Vapor Deposition, PVD for short), chemical vapor deposition (Chemical Vapor Deposition, CVD for short), or atomic layer deposition (Atomic Layer Deposition, Abbreviated as ALD) and so on.
  • a deposition process such as physical vapor deposition (Physical Vapor Deposition, PVD for short), chemical vapor deposition (Chemical Vapor Deposition, CVD for short), or atomic layer deposition (Atomic Layer Deposition, Abbreviated as ALD) and so on.
  • the thickness of the first barrier layer 142 may range from 5 nm to 10 nm, for example, the thickness of the first barrier layer 142 may be 5 nm, 6 nm, 8 nm or 10 nm.
  • the second barrier layer 143 is a layer set (TSN) composed of alternately stacked titanium nitride layers 143A and silicon nitride layers 143B.
  • TSN layer set
  • the thickness of any titanium nitride layer 143A or silicon nitride layer 143B can be selected and set according to actual requirements.
  • the stacking sequence of the titanium nitride layer 143A and the silicon nitride layer 143B can also be adjusted according to actual requirements.
  • the second barrier layer 143 adopts the above structure to effectively block the impurity elements (such as boron (B) and phosphorus (P), etc.) in the contact conductive layer 141 from diffusing to the contact structure 14 In the connected conductive structure, to avoid impurity elements from adversely affecting the electrical properties of the conductive structure.
  • the contact structure 14 is a bit line contact structure
  • the conductive structure connected to the contact structure 14 is a bit line in the bit line structure.
  • the conductive structure connected to the contact structure 14 is a storage capacitor.
  • the preparation step of the second barrier layer 143 includes: periodically depositing the titanium nitride layer 143A and the silicon nitride layer 143B on the first barrier layer 142 .
  • periodically depositing the titanium nitride layer 143A and the silicon nitride layer 143B refers to: taking the deposition of a layer of titanium nitride layer 143A and a layer of silicon nitride layer 143B as a cycle, and repeatedly performing multiple cycles to A layer set (TSN) composed of alternately stacked titanium nitride layers 143A and silicon nitride layers 143B is formed. Since the resistance of silicon nitride is greater than that of titanium and titanium nitride, the contact resistance of the contact structure 14 will also increase as the thickness of silicon nitride increases. The thickness of the silicon nitride layer 143B further helps to reduce the resistance of the layer set (TSN) and improve the conductivity of the contact structure 14 .
  • TSN layer set
  • the cycle ratios corresponding to different formation periods of the titanium nitride layer 143A and the silicon nitride layer 143B may be different.
  • the second barrier layer 143 is formed by Advanced Sequential Flow Deposition (ASFD, Advanced Sequential Flow Deposition) process.
  • ASFD Advanced Sequential Flow Deposition
  • the first barrier layer 142 is a titanium layer.
  • the second barrier layer 143 is a layer group formed by alternately stacking titanium nitride layers 143A and silicon nitride layers 143B. Since the resistance of the titanium layer is lower than that of the titanium nitride layer. Therefore, reducing the mass ratio of the raw materials for forming the titanium nitride layer 143A and the silicon nitride layer 143B in the second barrier layer 143 is beneficial to reduce the resistance of the layer set (TSN) and ensure the electrical performance of the contact structure 14 .
  • TSN layer set
  • the mass ratio of the raw materials for forming the second barrier layer 143 between the titanium nitride layer 143A and the silicon nitride layer 143B ranges from 10:1 to 20:1, for example, the raw material mass ratio can be 10:1, 12:1, 15:1, 18:1 or 20:1.
  • the raw materials used for forming the titanium nitride layer 143A may be titanium chloride and ammonia gas; the raw materials used for forming the silicon nitride layer 143B may be silicon and ammonia gas, but not limited thereto.
  • the contact structure 14 includes a contact conductive layer 141, a first barrier layer 142 and a second barrier layer 143, and the contact conductive layer 141 is a polysilicon layer, the first barrier layer 142 is a titanium layer, and the second barrier layer 143 It is a layer group composed of alternate stacking of titanium nitride layers and silicon nitride layers.
  • the impurity elements such as boron (B) and phosphorus (P), etc.
  • B boron
  • P phosphorus
  • the first barrier layer 142 can also be used to effectively isolate the nitrogen ions in the second barrier layer 143 from diffusing to the contact conductive layer 141 , so as to prevent the nitrogen ions from adversely affecting the electrical properties of the contact conductive layer 141 . Therefore, it can ensure that the electrical properties of the contact structure 14 and the bit line structure are good.
  • the method for fabricating the contact structure provided by the embodiments of the present disclosure can improve the electrical properties of the contact structure and the semiconductor structure where the contact junction is located, so as to improve the yield of the semiconductor structure.
  • Some embodiments of the present disclosure also provide a contact structure, which is prepared by using the preparation methods in some of the above embodiments.
  • the contact structure 14 is formed in the contact hole H, the contact hole H is disposed in the active region of the substrate 10 and the dielectric layer 12 , and the dielectric layer 12 covers the substrate 10 .
  • the substrate 10 includes, but is not limited to, a silicon substrate or a silicon-based substrate.
  • the substrate 10 has a shallow trench isolation structure 11 , and the shallow trench isolation structure 11 isolates a plurality of active regions in the substrate 10 .
  • the shallow trench isolation structure 11 is a silicon oxide (SiO 2 ) isolation structure.
  • the dielectric layer 12 covers the substrate 10 and the shallow trench isolation structure 11 .
  • the material of the dielectric layer 12 is different from that of the shallow trench isolation structure 11 .
  • the dielectric layer 12 may be a silicon nitride layer.
  • the contact hole H includes: a first contact hole H 1 penetrating through the dielectric layer 12 , and a second contact hole H 1 located at the bottom of the first contact hole H 1 and formed in the substrate 10 . contact hole H 2 .
  • the diameter of the portion of the second contact hole H2 close to the first contact hole H1 gradually increases along the direction close to the first contact hole H1, and the maximum diameter of the second contact hole H2 is equal to or smaller than that of the first contact hole H2 .
  • Aperture diameter of contact hole H1 is equal to or smaller than that of the first contact hole H2 .
  • the diameter of the portion of the second contact hole H2 close to the first contact hole H1 increases uniformly (for example, linearly) in the direction close to the first contact hole H1 , or increases according to a preset change rule. Large (for example, increasing in a curve).
  • the second contact hole H 2 also includes a second portion located on the side away from the first contact hole H 1 .
  • the diameter of the second portion can remain constant or gradually increase toward the first portion.
  • the change rate of the increase of the aperture diameter of the second part along the direction close to the first part is smaller than that of the first part aperture along the direction close to the first part. The rate of change of the direction of the first contact hole H1 increases.
  • the depths of the first contact hole H1 and the second contact hole H2 can be selected and set according to actual requirements. Since the first contact hole H1 penetrates the dielectric layer 12, the thickness of the dielectric layer 12 is the depth of the first contact hole H1 .
  • the shape of the orthographic projection of any cross-section of the contact hole H on the substrate 10 may be a circle, an ellipse, a rectangle, or a rhombus, which is not limited in the embodiments of the present disclosure.
  • the diameter of the contact hole H refers to the size of the contact hole H on its cross section, which is a cross section parallel to the substrate 10 .
  • the maximum diameter of the second contact hole H2 is equal to the diameter of the first contact hole H1 , which means that the upper edge of the second contact hole H2 coincides with the lower edge of the first contact hole H1 .
  • the maximum aperture of the second contact hole H2 is smaller than the aperture of the first contact hole H1 , which means that there is an interval between the upper edge of the second contact hole H2 and the lower edge of the first contact hole H1 , and can be passed through parallel Connected to the plane of the substrate 10.
  • the diameter of the first contact hole H 1 gradually increases or remains the same along the direction away from the second contact hole H 2 , whichever is acceptable.
  • the above-mentioned contact structure 14 is formed in the contact hole H, and the contact structure 14 also includes a portion located on the dielectric layer 12 and extending along the first direction.
  • the contact structure 14 is, for example, a bit line contact structure, but not limited thereto.
  • the contact structure 14 may also be a storage node contact structure.
  • the contact structure 14 includes: a contact conductive layer 141 , a first barrier layer 142 and a second barrier layer 143 stacked in a direction away from the substrate 10 .
  • the contact conductive layer 141 is a polysilicon layer. Part of the polysilicon layer fills the contact hole H, and part of the dielectric layer 12 covers the surface away from the substrate 10 and extends along the first direction.
  • the first barrier layer 142 is a titanium layer.
  • the first blocking layer 142 is used to block the diffusion of nitrogen ions.
  • the thickness of the titanium layer may range from 5 nm to 10 nm, for example, the thickness of the titanium layer may be: 5 nm, 6 nm, 8 nm or 10 nm.
  • the second barrier layer 143 is a layer set (TSN) formed by alternately stacking titanium nitride layers 143A and silicon nitride layers 143B.
  • TSN layer set
  • the thickness of any titanium nitride layer 143A or silicon nitride layer 143B can be selected and set according to actual requirements.
  • the stacking sequence of the titanium nitride layer 143A and the silicon nitride layer 143B can also be adjusted according to actual needs.
  • the second barrier layer 143 can effectively block impurity elements (such as boron (B) and phosphorus (P), etc.) in the contact conductive layer 141 from diffusing into the bit line structure, so as to avoid impurity elements from adversely affecting the electrical properties of the bit line structure .
  • impurity elements such as boron (B) and phosphorus (P), etc.
  • some embodiments of the present disclosure also provide a semiconductor structure, including: the contact structure 14 as described in some embodiments above, and the contact structure 14 disposed on the surface away from the substrate 10 bit line structure 20 or storage capacitor 30 .
  • the active region of the substrate 10 includes a source region and a drain region.
  • the contact structure 14 may be a bit line contact structure.
  • the bit line structure 20 includes bit lines. In this way, the bit lines in the bit line structure 20 can be connected to the source area of the active area through the corresponding bit line contact structure.
  • the active region of the substrate 10 includes a source region and a drain region.
  • the contact structure 14 may be a storage node contact structure.
  • the storage capacitor 30 includes a first electrode 31 and a second electrode 32 disposed opposite to each other, and a dielectric layer 33 disposed between the first electrode 31 and the second electrode 32 , wherein the first electrode 31 is connected to the storage node contact structure.
  • the storage capacitor 30 in FIG. 13 is only a schematic representation, and the structure of the storage capacitor 30 can also be arranged in other ways according to actual needs, and is not limited thereto. In this way, the first electrode 31 of the storage capacitor 30 may be connected to the drain region of the active region SA through a corresponding storage node contact structure.
  • the active regions of the substrate 10 may be distributed in an array. Moreover, a plurality of bit line structures 20 are arranged in parallel and at intervals, and the bit line structures 20 extend along the column direction. Based on this, the contact structure 14 corresponding to the source region of each column of the active region SA can be connected to the bit line of a bit line structure 20, and the contact structure 14 corresponding to the drain region of each column of the active region SA can be connected to a storage device. Capacitors 30 are correspondingly connected.
  • the shape of the contact hole H is improved, specifically: the contact hole H is formed from the first contact hole H1 located in the dielectric layer 12 and the first contact hole H1 located in the substrate 10.
  • the second contact hole H2 is connected to each other, and the diameter of a part of the second contact hole H2 increases along the direction close to the first contact hole H1 , and the maximum diameter of the second contact hole H2 is equal to or smaller than that of the first contact hole. H 1 pore size. This can ensure that the contact hole H still has a larger opening size when the size of the bottom of the contact hole H is smaller, which is beneficial to reducing the aspect ratio of the contact hole H and improving the step coverage of the contact structure 14 . Therefore, unnecessary voids in the contact structure 14 (especially the polysilicon layer) can be avoided, thereby avoiding the electrical anomaly of the semiconductor structure due to metal penetration and filling of the voids in the contact structure 14 .
  • the contact conductive layer 141 of the contact structure 14 is a polysilicon layer
  • the first barrier layer 142 is a titanium layer
  • the second barrier layer 143 is a layer group composed of alternately stacked titanium nitride layers and silicon nitride layers. .
  • the impurity elements such as boron (B) and phosphorus (P), etc.
  • the first barrier layer 142 can also be used to effectively isolate the nitrogen ions in the second barrier layer 143 from diffusing to the contact conductive layer 141 , so as to prevent the nitrogen ions from adversely affecting the electrical properties of the contact conductive layer 141 . Therefore, it can be ensured that the electrical performance of the contact structure 14 and its connected conductive structure is good.
  • the contact structure 14 and the semiconductor structure provided by the embodiments of the present disclosure can improve the electrical properties of the contact structure 14 and the semiconductor structure, so as to improve the yield of the semiconductor structure.

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本公开涉及一种接触结构及其制备方法、半导体结构。所述接触结构的制备方法包括：提供衬底，衬底具有浅沟槽隔离结构；形成覆盖衬底及浅沟槽隔离结构的介质层；在衬底的有源区及介质层中形成接触孔，接触孔包括：贯穿介质层的第一接触孔，以及位于第一接触孔底部且形成于衬底内的第二接触孔；在接触孔内以及介质层上形成沿第一方向延伸的接触结构。上述接触结构及其制备方法、半导体结构，可以改善接触结构及半导体结构的电学性能，以提升半导体结构的良率。

Description

接触结构及其制备方法、半导体结构
相关申请的交叉引用
本公开要求于2022年02月17日提交中国专利局、申请号为202210145921.1的中国专利的优先权，所述专利申请的全部内容通过引用结合在本公开中。
技术领域
本公开涉及半导体集成电路制造技术领域，特别是涉及一种接触结构及其制备方法、半导体结构。
背景技术
动态随机存储器(Dynamic Random Access Memory，简称DRAM)是计算机等电子设备中常用的半导体存储器，其由多个存储单元构成。其中，存储单元包括：存储电容器、以及与存储电容器电连接的晶体管。晶体管包括栅极、源区和漏区。晶体管的栅极用于与字线电连接。晶体管的源区用于构成位线接触区，以通过位线接触结构与位线电连接。晶体管的漏区用于构成存储节点接触区，以通过存储节点接触结构与存储电容器电连接。
然而，随着DRAM的尺寸越来越小，用于形成位线接触结构的位线接触孔(Bit line contact，简称BLC)的尺寸也相应缩减。当位线接触孔过小时，位线接触孔中的位线接触结构会存在空洞，从而影响位线接触结构的阻值、电性以及DRAM器件的写恢复时间测试(Write Recovery Time，简称TWR)等，造成DRAM器件不良。
发明内容
根据本公开的各种实施例，提供一种接触结构及其制备方法、半导体结构。
根据一些实施例，本公开一方面提供一种接触结构的制备方法，该制备方法包括的步骤如下所述。
提供衬底，衬底具有浅沟槽隔离结构。浅沟槽隔离结构在衬底内隔离出有源区。
形成覆盖衬底及浅沟槽隔离结构的介质层。
在衬底的有源区及介质层中形成接触孔。接触孔包括：贯穿介质层的第一接触孔，以及位于第一接触孔底部且形成于衬底内的第二接触孔。
根据一些实施例，第二接触孔的靠近第一接触孔的部分的孔径沿靠近第一接触孔的方向逐渐增大，且第二接触孔的最大孔径等于或小于第一接触孔的孔径。
根据一些实施例，在衬底的有源区及介质层中形成接触孔，包括步骤如下。
在衬底的有源区及介质层中形成接触底孔。
去除接触底孔的部分侧壁，以在介质层内形成第一接触孔，在衬底内形成第二接触孔。
根据一些实施例，接触底孔的侧壁由浅沟槽隔离结构构成。去除接触底孔的部分侧壁，以在介质层中形成第一接触孔，在衬底的有源区内形成第二接触孔，包括步骤如下。
基于接触底孔，回蚀去除部分介质层，以形成第一接触孔以及位于第一接触孔底部的导引孔。
基于第一接触孔及导引孔，去除部分浅沟槽隔离结构，以形成第二接触孔。
根据一些实施例，回蚀去除部分介质层，包括：对形成接触底孔后所得的结构进行清洗，回蚀去除部分介质层。
根据一些实施例，基于第一接触孔及导引孔，去除部分浅沟槽隔离结构，以形成第二接触孔，包括步骤如下。
在导引孔内形成硬掩膜，以使浅沟槽隔离结构待去除的部分暴露于硬掩膜的上方。
基于第一接触孔和硬掩膜，去除部分浅沟槽隔离结构。
去除硬掩膜，以形成第二接触孔。
根据一些实施例，在导引孔内形成硬掩膜，包括步骤如下。
在导引孔内填充硬掩膜材料。
去除预设厚度的硬掩膜材料，以使保留于导引孔内的硬掩膜材料形成硬掩膜。
根据一些实施例，去除部分衬底和部分浅沟槽隔离结构，包括：对形成硬掩膜后所得的结构进行刻蚀，以去除部分浅沟槽隔离结构。
根据一些实施例，接触结构的制备方法还包括：在接触孔内以及介质层上形成沿第一方向延伸的接触结构。
根据一些实施例，在接触孔内以及介质层上形成沿第一方向延伸的接触结构，包括步骤如下。
在接触孔内以及介质层上形成沿第一方向延伸的接触导电层。
形成覆盖接触导电层的第一阻挡层。
形成覆盖第一阻挡层的第二阻挡层。
其中，接触导电层、第一阻挡层和第二阻挡层共同构成接触结构。
根据一些实施例，第一阻挡层的材料包括钛。
根据一些实施例，第一阻挡层的厚度范围为5nm～10nm。
根据一些实施例，第二阻挡层包括由氮化钛层和氮化硅层交替层叠构成的层组。形成覆盖第一阻挡层的第二阻挡层，包括：在第一阻挡层上周期性的沉积氮化钛层和氮化硅层。
根据一些实施例，形成第二阻挡层中氮化钛层和氮化硅层的原料质量比范围为10:1～20:1。
根据一些实施例，本公开另一方面提供了一种接触结构，采用如上一些实施例所述的制备方法制备获得。所述接触结构形成于接触孔内。接触孔设置于衬底的有源区及介质层中。介质层覆盖衬底。接触孔包括：贯穿介质层的第一接触孔，以及位于第一接触孔的底部且位于衬底内的第二接触孔。接触结构还位于介质层上，并沿第一方向延伸。
根据一些实施例，第二接触孔的靠近第一接触孔的部分的孔径沿靠近第一接触孔的方向逐渐增大，且第二接触孔的最大孔径等于或小于第一接触孔的孔径。
根据一些实施例，接触结构包括：沿远离衬底的方向层叠设置的接触导电层、第一阻挡层和第二阻挡层。
根据一些实施例，第一阻挡层包括钛层。
根据一些实施例，钛层的厚度范围为5nm～10nm。
根据一些实施例，第二阻挡层包括由氮化钛层和氮化硅层交替层叠构成的层组。
根据一些实施例，接触导电层包括多晶硅层。
根据一些实施例，本公开又一方面提供了一种半导体结构，包括如上一些实施例所述的接触结构，以及设置于接触结构背离衬底表面上的位线结构或存储电容器。
本公开实施例可以/至少具有以下优点：
在本公开实施例提供的接触结构的制备方法及接触结构、半导体结构中，改良了接触孔的形状，具体为：使接触孔由位于介质层中的第一接触孔和位于衬底内的第二接触孔相连通构成，且使第二接触孔的部分孔径沿靠近第一接触孔的方向增大，第二接触孔的最大孔径等于或小于第一接触孔的孔径。这样可以在接触孔底部尺寸较小的情况下确保接触孔仍具有较大的开口尺寸，有利于减小接触孔的深宽比，以及提升接触结构的台阶覆盖率。从而可以避免在接触结构中形成不必要的孔隙。进而可以避免出现因金属渗透并填充接触结构中孔隙而导致半导体结构电性异常的问题。
此外，本公开实施例中，接触结构包括接触导电层、第一阻挡层和第二阻挡层，且接触导电层为多晶硅层，第一阻挡层为钛层，第二阻挡层为氮化钛层和氮化硅层交替层叠构成的层组。这样不仅可以利用第二阻挡层有效阻挡接触导电层中的杂质元素(例如硼(B)和磷(P)等)扩散至该接触结构连接的导电结构中，以避免杂质元素对前述导电结构的电性产生不良影响。并且，还可以利用第一阻挡层有效隔绝第二阻挡层中的氮离子扩散至接触导电层，以避免氮离子对接触导电层的电性产生不良影响。从而能够确保接触结构及其相连接的导电结构的电学性能良好。
综上，本公开实施例提供的接触结构的制备方法及接触结构、半导体结构，能够改善接触结构及半导体结构的电学性能，以提升半导体结构的良率。
本公开的一个或多个实施例的细节在下面的附图和描述中提出。本公开的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的附图。
图1为一实施例中提供的一种接触结构的制备方法的流程示意图；
图2为一实施例中提供的步骤S100所得结构的示意图；
图3为一实施例中提供的步骤S200所得结构的示意图；
图4为一实施例中提供的步骤S300所得结构的示意图；
图5为一实施例中提供的步骤S310所得结构的示意图；
图6～图9为一实施例中提供的步骤S320中各分步骤所得结构的示意图；
图10为一实施例中提供的步骤S400所得结构的示意图；并且，图10亦为一实施例中提供的接触结构的结构示意图；
图11为一实施例中提供的第二阻挡层的结构示意图；
图12为一实施例中提供的一种半导体结构的结构示意图；
图13为一实施例中提供的一种半导体结构的结构示意图。
具体实施方式
为了便于理解本公开，下面将参考相关附图对本公开进行更全面的描述。附图中给出了本公开的首选实施例。但是，本公开可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本公开的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本公开的技术领域的技术人员通常理解的含义相同。本文中在本公开的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本公开。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
应当明白，当元件或层被称为“在...上”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本公开教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本公开的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
这里参考作为本公开的理想实施例(和中间结构)的示意图的横截面图来描述发明的实施例，这样可以预期由于例如制造技术和/或容差导致的所示形状的变化。因此，本公开的实施例不应当局限于在此所示的区的特定形状，而是包括由于例如制造技术导致的形状偏差。图中显示的区实质上是示意性的，它们的形状并不表示器件的区的实际形状，且并不限定本公开的范围。
请参阅图1，本公开一实施例提供了一种接触结构的制备方法，该制备方法包括的步骤如下所述。
S100，提供衬底。衬底具有浅沟槽隔离结构，浅沟槽隔离结构在衬底内隔离出有源区。
S200，形成覆盖衬底及浅沟槽隔离结构的介质层。
S300，在衬底的有源区及介质层中形成接触孔。其中，接触孔包括：贯穿介质层的第一接触孔，以及位于第一接触孔底部且形成于衬底内的第二接触孔。
S400，在接触孔内以及介质层上形成沿第一方向延伸的接触结构。
在一些实施例中，第二接触孔的靠近第一接触孔的部分的孔径沿靠近第一接触孔的方向逐渐增大，且第二接触孔的最大孔径等于或小于第一接触孔的孔径。
本公开实施例中，接触孔由位于介质层中的第一接触孔和位于衬底内的第二接触孔相连通构成，并且，第二接触孔的部分孔径沿靠近第一接触孔的方向增大，第二接触孔的最大孔径等于或小于第一接触孔的孔径，这样可以在接触孔底部尺寸较小的情况下，确保接触孔仍具有较大的开口尺寸，有利于减小接触孔的深宽比，以及提升接触结构的台阶覆盖率，从而可以避免在接触结构中形成不必要的孔隙，进而可以避免出现因金属渗透并填充接触结构中孔隙而导致半导体结构电性异常的问题。本公开实施例能够改善接触结构及接触结构所在半导体结构的电学性能，以提升半导体结构的良率。
在步骤S100中，请参阅图1中的S100及图2，提供衬底10。衬底10具有浅沟槽隔离结构11，浅沟槽隔离结构11在衬底10内隔离出有源区S A。
在一些实施例中，衬底10包括但不仅限于硅衬底或硅基衬底。
在一些实施例中，浅沟槽隔离结构11为氧化硅(SiO 2)隔离结构。浅沟槽隔离结构11可以在衬底10内隔离出多个呈阵列状排布的有源区S A。有源区S A包括源区和漏区。图2～图10中仅以一个有源区S A的源区或漏区为例进行了示意。
在步骤S200中，请参阅图1中的S200及图3，形成覆盖衬底10及浅沟槽隔离结构11的介质层12。
此处，介质层12的材料与浅沟槽隔离结构11的材料不同，介质层12可以作为后续刻蚀浅沟槽隔离结构11的保护层使用。
此外，介质层12的厚度可以根据实际需求选择设置。本公开实施例对此不做限定。
在一些实施例中，介质层12为氮化硅层。
在步骤S300中，请参阅图1中的S300及图4，在衬底10的有源区S A及介质层12中形成接触孔H。
示例的，接触孔H包括：贯穿介质层12的第一接触孔H 1，以及位于第一接触孔H 1底部且形成于衬底10内的第二接触孔H 2。
在一些示例中，第二接触孔H 2的靠近第一接触孔H 1的部分的孔径沿靠近第一接触孔H 1的方向逐渐增大，且第二接触孔H 2的最大孔径等于或小于第一接触孔H 1的孔径。
示例的，第二接触孔H 2的靠近第一接触孔H 1的部分的孔径沿靠近第一接触孔H 1的方向均匀增大(例如呈线性增大)，或者按照预设的变化规律增大(例如呈曲线增大)。
示例的，请继续参阅图4，以第二接触孔H 2中靠近第一接触孔H 1且孔径沿靠近第一接触孔H 1的方向逐渐增大的部分为第一部分，则第二接触孔H 2还包括位于其第一部分远离第一接触孔H 1一侧的第二部分，该第二部分的孔径可以保持不变，也可以沿靠近第一部分的方向逐渐增大。并且，在第二接触孔H 2的第二部分的孔径沿靠近其第一部分的方向逐渐增大的示例中，第二部分孔径沿靠近第一部分的方向增大的变化率小于第一部分孔径沿靠近第一接触孔H 1的方向增大的变化率。
上述第一接触孔H 1和第二接触孔H 2的深度，可以根据实际需求选择设置。基于第一接触孔H 1贯穿介质层12，介质层12的沉积厚度即为第一接触孔H 1的深度。
上述接触孔H中任一横截面在衬底10上的正投影形状可以为圆形、椭圆形、矩形或菱形等，本公开实施例对此不做限定。相应的，接触孔H的孔径是指：接触孔H在其横截面上的尺寸，该横截面为平行于衬底10的截面。
此外，前述第二接触孔H 2的最大孔径等于第一接触孔H 1的孔径，是指：第二接触孔H 2的上边缘与第一接触孔H 1的下边缘重合。第二接触孔H 2的最大孔径小于第一接触孔H 1的孔径，是指：第二接触孔H 2的上边缘与第一接触孔H 1的下边缘之间具有间隔，且可以通过平行于衬底10的平面衔接。
在一些实施例中，第一接触孔H 1的孔径沿远离第二接触孔H 2的方向逐渐增大或保持一致，均可。
在一些实施例中，步骤S300包括步骤如下。
S310，请参阅图5，在衬底10的有源区S A及介质层12中形成接触底孔H 0。
此处，接触底孔H 0通过一次构图工艺形成，即基于同一掩膜版，对介质层12和衬底10的有源区S A进行刻蚀，以形成接触底孔H 0。
可选的，接触底孔H 0与衬底10的有源区S A的源区和/或漏区一一对应地设置。
可以理解的是，接触底孔H 0的底部尺寸取决于半导体结构中允许设置接触孔的尺寸。在刻蚀形成接触底孔H 0后，按照接触底孔H 0尺寸的不同，接触底孔H 0的侧壁可以由衬底10构成，也可以由浅沟槽隔离结构11构成。
在一些实施例中，如图5中所示，接触底孔H 0暴露出部分浅沟槽隔离结构11，接触底孔H 0的侧壁由浅沟槽隔离结构11构成。
S320，请参阅图6～图9，去除接触底孔H 0的部分侧壁，以在介质层12内形成第一接触孔H 1，在衬底10内形成第二接触孔H 2。
可以理解，介质层12的材料、浅沟槽隔离结构11的材料和衬底10的材料均不同，第一接触孔H 1和第二接触孔H 2可以分别采用不同的刻蚀方式形成。
在一些实施例中，接触底孔H 0的侧壁由浅沟槽隔离结构11构成。步骤S320包括步骤如下所述。
S321，基于接触底孔H 0，回蚀去除部分介质层12，以形成第一接触孔H 1以及位于第一接触孔H 1底部的导引孔H 20，例如图6所示。
此处，导引孔H 20也就是接触底孔H 0位于衬底10内的部分，具体可以为低于有源区S A初始裸露表面或低于浅沟槽隔离结构11初始上表面的部分。
示例的，介质层12为氮化硅层，对氮化硅层进行回蚀，可以有效去除部分氮化硅材料，以增大氮化硅层中开口部分的关键尺寸，也即：可以增大接触底孔H 0位于介质层12中部分的孔径，以获得第一接触孔H 1。
示例的，介质层12的回蚀去除，可以通过对形成接触底孔H 0后所得的结构进行清洗来获得。
在一些实施例中，介质层12的回蚀去除采用湿法刻蚀。例如，使用氢氟酸溶液、磷酸溶液及标准清洗液对形成接触底孔H 0后所得的结构依次进行清洗，以回蚀去除部分介质层12，从而形成第一接触孔H 1。
S322，基于第一接触孔H 1及导引孔H 20，去除部分浅沟槽隔离结构11，以形成第二接触孔H 2。
在形成第一接触孔H 1之后，第一接触孔H 1的底部暴露出部分浅沟槽隔离结构11。在此基础上，自上而下去除接触底孔H 0位于衬底10内部分的上部分侧壁，可以形成第二接触孔H 2，并使第二接触孔H 2的部分孔径沿靠近第一接触孔H 1的方向增大。
在一些实施例中，接触底孔H 0的侧壁由浅沟槽隔离结构11构成，步骤S322包括步骤如下所述。
S3221，在导引孔H 20内形成硬掩膜13，以使浅沟槽隔离结构11待去除的部分暴露于硬掩膜13的上方。
示例的，硬掩膜13的制备方法如下所述。
首先，请参阅图7，在导引孔H 20内填充硬掩膜材料130。
此处，硬掩膜材料130可以根据实际需求选择设置，例如为光刻胶材料或旋涂硬掩膜(SOH，Spin on Hard mask)材料等。
在一些实施例中，硬掩膜材料130为SOH材料。硬掩膜材料130可以采用旋转涂覆工艺，涂覆于第一接触孔H 1及导引孔H 20内，但并不仅限于此。例如，硬掩膜材料130可以通过沉积工艺仅填充于接触底孔H 0位于衬底10内的部分内，即填充于导引孔H 20内。
此处，沉积工艺包括但不限于物理气相沉积(Physical Vapor Deposition，简称PVD)、化学气相沉积(Chemical Vapor Deposition，简称CVD)或原子层沉积(Atomic Layer Deposition，简称ALD)等。
然后，去除预设厚度T的硬掩膜材料130，以使保留于导引孔H 20内的硬掩膜材料形成硬掩膜13，例如图8中所示。
此处，预设厚度T可以根据硬掩膜材料130的成型厚度以及第二接触孔H 2中孔径变化部分的高度确定，以使得部分浅沟槽隔离结构11暴露于硬掩膜13上方为限。
S3222，基于第一接触孔H 1和硬掩膜13，去除部分浅沟槽隔离结构11。也即：去除导引孔H 20裸露于硬掩膜13上方的部分侧壁，例如图9中所示。
示例的，浅沟槽隔离结构11的去除可以采用刻蚀去除，例如湿法刻蚀。
在一些实施例中，浅沟槽隔离结构11为氧化硅(SiO 2)隔离结构，可以使用氢氟酸溶液对形成硬掩膜13后所得的结构进行湿法刻蚀。
S3223，去除硬掩膜13，以形成第二接触孔H 2，所得结构例如图4中所示。
此处，硬掩膜13例如可以采用等离子体刻蚀工艺去除。
在步骤S400中，请参阅图1中的S400及图10，在接触孔H内以及介质层12上形成沿第一方向延伸的接触结构14。
可以理解，接触结构14的结构不同，相应的制备方法不同。接触结构14例如为位线接触结构，但并不仅限于此。
在一些实施例中，请结合图10理解，接触结构14的制备方法如下所述。
S410，在接触孔H内以及介质层12上形成沿第一方向延伸的接触导电层141。
在一些实施例中，接触导电层141为多晶硅层，但并不仅限于此，其他与多晶硅具有相同或相似电学性能的可导电材料也均可用于形成接触导电层141。
在一些实施例中，接触导电层141采用沉积工艺形成，接触导电层141的部分填充于接触孔H内。
此处，沉积工艺包括但不限于物理气相沉积(Physical Vapor Deposition，简称PVD)、化学气相沉积(Chemical Vapor Deposition，简称CVD)或原子层沉积(Atomic Layer Deposition，简称ALD)等。
本公开实施例中，接触孔H采用相连通的第一接触孔H 1和第二接触孔H 2构成，并使第二接触孔H 2的部分孔径沿靠近第一接触孔H 1的方向增大，且第二接触孔H 2的最大孔径等于或小于第一接触孔H 1的孔径。这样可以利用第一接触孔H 1增大接触孔H的开口尺寸，并利用第二接触孔H 2连接第一接触孔H 1的孔径变化部分减缓台阶的坡度。在此基础上，在接触孔H内形成接触导电层141后，不仅可以避免在接触导电层141中形成不必要的孔隙，也可以确保接触导电层141具有良好的台阶覆盖率。
S420，形成覆盖接触导电层141的第一阻挡层142。
在一些实施例中，第一阻挡层142的材料包括钛。第一阻挡层142可以用于阻挡氮离子扩散。
在一些实施例中，第一阻挡层142采用沉积工艺形成，例如采用物理气相沉积(Physical Vapor Deposition，简称PVD)、化学气相沉积(Chemical Vapor Deposition，简称CVD)或 原子层沉积(Atomic Layer Deposition，简称ALD)等形成。
在一些实施例中，第一阻挡层142的厚度范围可以为5nm～10nm，例如第一阻挡层142的厚度可以为5nm、6nm、8nm或10nm。
S430，形成覆盖第一阻挡层142的第二阻挡层143。
在一些实施例中，如图11中所示，第二阻挡层143为由氮化钛层143A和氮化硅层143B交替层叠构成的层组(TSN)。其中，任一层氮化钛层143A或氮化硅层143B的厚度可以根据实际需求选择设置。并且，氮化钛层143A和氮化硅层143B的层叠顺序也可以根据实际需求调整。
在接触导电层141为多晶硅层的一些示例中，第二阻挡层143采用如上结构可以有效阻挡接触导电层141中的杂质元素(例如硼(B)和磷(P)等)扩散至接触结构14连接的导电结构中，以避免杂质元素对该导电结构的电性产生不良影响。在接触结构14为位线接触结构的示例中，接触结构14连接的导电结构为位线结构中的位线。在接触结构14为存储节点接触结构的示例中，接触结构14连接的导电结构为存储电容器。
由上，第二阻挡层143的制备步骤，包括：在第一阻挡层142上周期性的沉积氮化钛层143A和氮化硅层143B。
此处，周期性的沉积氮化钛层143A和氮化硅层143B是指：以沉积一层氮化钛层143A和一层氮化硅层143B为一个周期，并重复执行多个周期，以形成由氮化钛层143A和氮化硅层143B交替层叠构成的层组(TSN)。由于氮化硅的电阻大于钛和氮化钛，氮化硅的厚度增加，接触结构14的接触电阻也会随之增加，所以通过交替层叠氮化钛层143A和氮化硅层143B能有效降低氮化硅层143B的厚度，进而有利于降低层组(TSN)的电阻，提高接触结构14的导电性能。
此外，在制备第二阻挡层143的过程中，氮化钛层143A和氮化硅层143B不同形成周期内所对应的循环比可以不同。
示例的，第二阻挡层143采用先进连续流沉积(ASFD，Advanced Sequential Flow Deposition)工艺形成。
在一些实施例中，第一阻挡层142采用钛层。第二阻挡层143为由氮化钛层143A和氮化硅层143B交替层叠构成的层组。由于钛层的电阻低于氮化钛层的电阻。因此，将形成第二阻挡层143中氮化钛层143A和氮化硅层143B的原料质量比调低，有利于降低层组(TSN)的电阻，确保接触结构14的电学性能。
例如，形成第二阻挡层143中氮化钛层143A和氮化硅层143B的原料质量比的范围为10:1～20:1，例如该原料质量比可以为10:1，12:1，15:1，18:1或20:1。其中，形成氮化钛层143A所用的原料可以为氯化钛和氨气；形成氮化硅层143B所用的原料可以为硅和氨气，但并不仅限于此。
本公开实施例中，接触结构14包括接触导电层141、第一阻挡层142和第二阻挡层143，且接触导电层141为多晶硅层，第一阻挡层142为钛层，第二阻挡层143为氮化钛 层和氮化硅层交替层叠构成的层组。这样不仅可以利用第二阻挡层143有效阻挡接触导电层141中的杂质元素(例如硼(B)和磷(P)等)扩散至位线结构中，以避免杂质元素对位线结构的电性产生不良影响。并且，还可以利用第一阻挡层142有效隔绝第二阻挡层143中的氮离子扩散至接触导电层141，以避免氮离子对接触导电层141的电性产生不良影响。从而能够确保接触结构14及位线结构的电学性能良好。
综上，本公开实施例提供的接触结构的制备方法能够改善接触结构及接触结所在半导体结构的电学性能，以提升半导体结构的良率。
本公开一些实施例还提供了一种接触结构，采用上述一些实施例中的制备方法制备获得。
如图10所示，接触结构14形成于接触孔H内，接触孔H设置于衬底10的有源区及介质层12中，介质层12覆盖衬底10。
在一个示例中，衬底10包括但不仅限于硅衬底或硅基衬底。衬底10具有浅沟槽隔离结构11，浅沟槽隔离结构11在衬底10内隔离出多个有源区。
示例的，浅沟槽隔离结构11为氧化硅(SiO 2)隔离结构。
在一个示例中，介质层12覆盖衬底10及浅沟槽隔离结构11。介质层12的材料与浅沟槽隔离结构11的材料不同。示例的，介质层12可以为氮化硅层。
在一个示例中，请结合图4和图10理解，接触孔H包括：贯穿介质层12的第一接触孔H 1，以及位于第一接触孔H 1底部且形成于衬底10内的第二接触孔H 2。
示例的，第二接触孔H 2的靠近第一接触孔H 1的部分的孔径沿靠近第一接触孔H 1的方向逐渐增大，且第二接触孔H 2的最大孔径等于或小于第一接触孔H 1的孔径。
示例的，第二接触孔H 2的靠近第一接触孔H 1的部分的孔径沿靠近第一接触孔H 1的方向均匀增大(例如呈线性增大)，或者按照预设的变化规律增大(例如呈曲线增大)。
示例的，请继续参阅图4和图10，以第二接触孔H 2中靠近第一接触孔H 1且孔径沿靠近第一接触孔H 1的方向逐渐增大的部分为第一部分，则第二接触孔H 2还包括位于其第一部分远离第一接触孔H 1一侧的第二部分，该第二部分的孔径可以保持不变，也可以沿靠近第一部分的方向逐渐增大。并且，在第二接触孔H 2的第二部分的孔径沿靠近其第一部分的方向逐渐增大的示例中，第二部分孔径沿靠近第一部分的方向增大的变化率小于第一部分孔径沿靠近第一接触孔H 1的方向增大的变化率。
上述第一接触孔H 1和第二接触孔H 2的深度，可以根据实际需求选择设置。基于第一接触孔H 1贯穿介质层12，介质层12的厚度即为第一接触孔H 1的深度。
上述接触孔H中任一横截面在衬底10上的正投影形状可以为圆形、椭圆形、矩形或菱形等，本公开实施例对此不做限定。相应的，接触孔H的孔径是指：接触孔H在其横截面上的尺寸，该横截面为平行于衬底10的截面。
此外，第二接触孔H 2的最大孔径等于第一接触孔H 1的孔径，是指：第二接触孔H 2的上边缘与第一接触孔H 1的下边缘重合。第二接触孔H 2的最大孔径小于第一接触孔H 1 的孔径，是指：第二接触孔H 2的上边缘与第一接触孔H 1的下边缘之间具有间隔，且可以通过平行于衬底10的平面衔接。
在一些实施例中，第一接触孔H 1的孔径沿远离第二接触孔H 2的方向逐渐增大或保持一致，均可。
上述接触结构14形成于接触孔H内，接触结构14还包括位于介质层12上并沿第一方向延伸的部分。接触结构14例如为位线接触结构，但并不仅限于此。例如，接触结构14还可以为存储节点接触结构。
在一些实施例中，接触结构14包括：沿远离衬底10的方向层叠设置的接触导电层141、第一阻挡层142和第二阻挡层143。
示例的，接触导电层141为多晶硅层。多晶硅层的部分填充于接触孔H中，部分覆盖介质层12背离衬底10的表面且沿第一方向延伸。
示例的，第一阻挡层142为钛层。第一阻挡层142用于阻挡氮离子扩散。
在一些实施例中，钛层的厚度范围可以为5nm～10nm，例如钛层的厚度可以为：5nm、6nm、8nm或10nm。
在一些实施例中，第二阻挡层143为由氮化钛层143A和氮化硅层143B交替层叠构成的层组(TSN)。其中，任一层氮化钛层143A或氮化硅层143B的厚度可以根据实际需求选择设置。并且，氮化钛层143A和氮化硅层143B的层叠顺序也可以根据实际需求调整。第二阻挡层143可以有效阻挡接触导电层141中的杂质元素(例如硼(B)和磷(P)等)扩散至位线结构中，以避免杂质元素对位线结构的电性产生不良影响。
请参阅图12和图13，本公开一些实施例还提供了一种半导体结构，包括：如上一些实施例中所述的接触结构14，以及设置于接触结构14的背离衬底10的表面上的位线结构20或存储电容器30。
示例的，请参阅图12，衬底10的有源区包括源区和漏区。接触结构14可以为位线接触结构。位线结构20包括位线。如此，位线结构20中的位线可以通过对应的位线接触结构与有源区的源区相连接。
示例的，请参阅图13，衬底10的有源区包括源区和漏区。接触结构14可以为存储节点接触结构。存储电容器30包括相对设置的第一电极31和第二电极32，以及设置于第一电极31和第二电极32之间的电介质层33，其中，第一电极31与存储节点接触结构连接。此处，图13中的存储电容器30仅是一种示意性的表达，存储电容器30的结构还可以根据实际需求有其他的设置方式，而并不仅限于此。如此，存储电容器30的第一电极31可以通过对应的存储节点接触结构与有源区S A的漏区相连接。
需要补充的是，衬底10的有源区可以呈阵列状分布。并且，多个位线结构20平行间隔设置，且各位线结构20沿列方向延伸。基于此，每一列有源区S A的源区对应的接触结构14可以与一个位线结构20的位线对应连接，每一列有源区S A的漏区对应的接触结构14可以与一个存储电容器30对应连接。
在本公开实施例提供的接触结构14及半导体结构中，改良了接触孔H的形状，具体为：使接触孔H由位于介质层12中的第一接触孔H 1和位于衬底10内的第二接触孔H 2相连通构成，且使第二接触孔H 2的部分孔径沿靠近第一接触孔H 1的方向增大，第二接触孔H 2的最大孔径等于或小于第一接触孔H 1的孔径。这样可以在接触孔H底部尺寸较小的情况下确保接触孔H仍具有较大的开口尺寸，有利于减小接触孔H的深宽比，以及提升接触结构14的台阶覆盖率。从而可以避免在接触结构14(尤其是多晶硅层)中形成不必要的孔隙，进而可以避免出现因金属渗透并填充接触结构14中孔隙而导致半导体结构电性异常的问题。
此外，本公开实施例中，接触结构14的接触导电层141为多晶硅层，第一阻挡层142为钛层，第二阻挡层143为氮化钛层和氮化硅层交替层叠构成的层组。这样不仅可以利用第二阻挡层143有效阻挡接触导电层141中的杂质元素(例如硼(B)和磷(P)等)扩散至接触结构14连接的导电结构中，以避免杂质元素对导电结构的电性产生不良影响。并且，还可以利用第一阻挡层142有效隔绝第二阻挡层143中的氮离子扩散至接触导电层141，以避免氮离子对接触导电层141的电性产生不良影响。从而能够确保接触结构14及其相连的导电结构的电学性能良好。
综上，本公开实施例提供的接触结构14及半导体结构，能够改善接触结构14及半导体结构的电学性能，以提升半导体结构的良率。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本公开的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本公开构思的前提下，还可以做出若干变形和改进，这些都属于本公开的保护范围。因此，本公开专利的保护范围应以所附权利要求为准。

Claims (20)

  1. 一种接触结构的制备方法，包括：
    提供衬底，所述衬底具有浅沟槽隔离结构，所述浅沟槽隔离结构在所述衬底内隔离出有源区；
    形成覆盖所述衬底及所述浅沟槽隔离结构的介质层；
    在所述衬底的有源区及所述介质层中形成接触孔；
    所述接触孔包括：贯穿所述介质层的第一接触孔，以及位于所述第一接触孔底部且形成于所述衬底内的第二接触孔。
  2. 根据权利要求1所述的接触结构的制备方法，其中，所述第二接触孔的靠近所述第一接触孔的部分的孔径沿靠近所述第一接触孔的方向逐渐增大，且所述第二接触孔的最大孔径等于或小于所述第一接触孔的孔径。
  3. 根据权利要求1所述的接触结构的制备方法，其中，所述在所述衬底的有源区及所述介质层中形成接触孔，包括：
    在所述衬底的有源区及所述介质层中形成接触底孔；
    去除所述接触底孔的部分侧壁，以在所述介质层内形成第一接触孔，在所述衬底内形成所述第二接触孔。
  4. 根据权利要求3所述的接触结构的制备方法，其中，所述接触底孔的侧壁由所述浅沟槽隔离结构构成；所述去除所述接触底孔的部分侧壁，以在所述介质层中形成第一接触孔，在所述衬底的有源区内形成所述第二接触孔，包括：
    基于所述接触底孔，回蚀去除部分所述介质层，以形成所述第一接触孔以及位于所述第一接触孔底部的导引孔；
    基于所述第一接触孔及所述导引孔，去除部分所述浅沟槽隔离结构，以形成所述第二接触孔。
  5. 根据权利要求4所述的接触结构的制备方法，其中，所述回蚀去除部分所述介质层，包括：
    对形成所述接触底孔后所得的结构进行清洗，以回蚀去除部分所述介质层。
  6. 根据权利要求4所述的接触结构的制备方法，其中，所述基于所述第一接触孔及所述导引孔，去除部分所述浅沟槽隔离结构，以形成所述第二接触孔，包括：
    在所述导引孔内形成硬掩膜，以使所述浅沟槽隔离结构待去除的部分暴露于所述硬掩膜的上方；
    基于所述第一接触孔和所述硬掩膜，去除部分所述浅沟槽隔离结构；
    去除所述硬掩膜，以形成所述第二接触孔。
  7. 根据权利要求6所述的接触结构的制备方法，其中，所述在所述导引孔内形成硬掩膜，包括：
    在所述导引孔内填充硬掩膜材料；
    去除预设厚度的所述硬掩膜材料，以使保留于所述导引孔内的所述硬掩膜材料形成所述硬掩膜。
  8. 根据权利要求6所述的接触结构的制备方法，其中，所述去除部分所述浅沟槽隔离结构，包括：对形成所述硬掩膜后所得的结构进行刻蚀，以去除部分所述浅沟槽隔离结构。
  9. 根据权利要求1～8中任一项所述的接触结构的制备方法，其中，所述制备方法还包括：在所述接触孔内以及所述介质层上形成沿第一方向延伸的接触结构。
  10. 根据权利要求9所述的接触结构的制备方法，其中，所述在所述接触孔内以及所述介质层上形成沿第一方向延伸的接触结构，包括：
    在所述接触孔内以及所述介质层上形成沿第一方向延伸的接触导电层；
    形成覆盖所述接触导电层的第一阻挡层；
    形成覆盖所述第一阻挡层的第二阻挡层；
    其中，所述接触导电层、所述第一阻挡层和所述第二阻挡层共同构成所述接触结构。
  11. 根据权利要求10所述的接触结构的制备方法，其中，所述第一阻挡层的材料包括钛。
  12. 根据权利要求10所述的接触结构的制备方法，其中，所述第一阻挡层的厚度范围为5nm～10nm。
  13. 根据权利要求10所述的接触结构的制备方法，其中，所述第二阻挡层包括由氮化钛层和氮化硅层交替层叠构成的层组；
    所述形成覆盖所述第一阻挡层的第二阻挡层，包括：在所述第一阻挡层上周期性的沉积所述氮化钛层和所述氮化硅层。
  14. 根据权利要求13所述的接触结构的制备方法，其中，形成所述第二阻挡层中所述氮化钛层和所述氮化硅层的原料质量比的范围为10:1～20:1。
  15. 一种接触结构，形成于接触孔内；
    所述接触孔设置于衬底的有源区及介质层中；所述介质层覆盖所述衬底；所述接触孔包括：贯穿所述介质层的第一接触孔，以及位于所述第一接触孔的底部且位于所述衬底内的第二接触孔；
    所述接触结构还位于所述介质层上，并沿第一方向延伸。
  16. 根据权利要求15所述的接触结构，其中，所述第二接触孔的靠近所述第一接触孔的部分的孔径沿靠近所述第一接触孔的方向逐渐增大，且所述第二接触孔的最大孔径等于或小于所述第一接触孔的孔径。
  17. 根据权利要求15所述的接触结构，其中，所述接触结构包括：沿远离所述衬底的方向层叠设置的接触导电层、第一阻挡层和第二阻挡层。
  18. 根据权利要求17所述的接触结构，其中，
    所述第一阻挡层包括钛层；
    所述第二阻挡层包括由氮化钛层和氮化硅层交替层叠构成的层组；
    所述接触导电层包括多晶硅层。
  19. 根据权利要求18所述的接触结构，其中，所述钛层的厚度范围为5nm～10nm。
  20. 一种半导体结构，包括：
    如权利要求15～19中任一项所述的接触结构；
    以及，位线结构或存储电容器，设置于所述接触结构的背离所述衬底的表面上。
PCT/CN2022/081448 2022-02-17 2022-03-17 接触结构及其制备方法、半导体结构 Ceased WO2023155262A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/662,473 US20230262963A1 (en) 2022-02-17 2022-05-09 Contact structure, method of manufacturing contact structure, and semiconductor structure

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202210145921.1A CN116669416A (zh) 2022-02-17 2022-02-17 接触结构及其制备方法、半导体结构
CN202210145921.1 2022-02-17

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/662,473 Continuation US20230262963A1 (en) 2022-02-17 2022-05-09 Contact structure, method of manufacturing contact structure, and semiconductor structure

Publications (1)

Publication Number Publication Date
WO2023155262A1 true WO2023155262A1 (zh) 2023-08-24

Family

ID=87577414

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/081448 Ceased WO2023155262A1 (zh) 2022-02-17 2022-03-17 接触结构及其制备方法、半导体结构

Country Status (2)

Country Link
CN (1) CN116669416A (zh)
WO (1) WO2023155262A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN119133143A (zh) * 2024-09-03 2024-12-13 安徽长飞先进半导体股份有限公司 半导体器件及制备方法、功率模块、功率转换电路和车辆

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050003307A1 (en) * 2003-07-03 2005-01-06 Shih-Fan Kuan Method for forming DRAM cell bit-line contact
US20140061939A1 (en) * 2012-08-31 2014-03-06 SK Hynix Inc. Semiconductor devices having bit line contact plugs and methods of manufacturing the same
CN103779318A (zh) * 2012-10-25 2014-05-07 三星电子株式会社 包括凹陷有源区的半导体器件及形成该半导体器件的方法
CN107871742A (zh) * 2016-09-23 2018-04-03 联华电子股份有限公司 动态随机存取存储器元件
CN112018080A (zh) * 2020-09-04 2020-12-01 福建省晋华集成电路有限公司 存储器及其形成方法
CN113192892A (zh) * 2021-04-23 2021-07-30 长鑫存储技术有限公司 半导体结构及其制备方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108878352B (zh) * 2018-06-26 2021-01-12 武汉新芯集成电路制造有限公司 一种接触孔的外形结构

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050003307A1 (en) * 2003-07-03 2005-01-06 Shih-Fan Kuan Method for forming DRAM cell bit-line contact
US20140061939A1 (en) * 2012-08-31 2014-03-06 SK Hynix Inc. Semiconductor devices having bit line contact plugs and methods of manufacturing the same
CN103779318A (zh) * 2012-10-25 2014-05-07 三星电子株式会社 包括凹陷有源区的半导体器件及形成该半导体器件的方法
CN107871742A (zh) * 2016-09-23 2018-04-03 联华电子股份有限公司 动态随机存取存储器元件
CN112018080A (zh) * 2020-09-04 2020-12-01 福建省晋华集成电路有限公司 存储器及其形成方法
CN113192892A (zh) * 2021-04-23 2021-07-30 长鑫存储技术有限公司 半导体结构及其制备方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN119133143A (zh) * 2024-09-03 2024-12-13 安徽长飞先进半导体股份有限公司 半导体器件及制备方法、功率模块、功率转换电路和车辆

Also Published As

Publication number Publication date
CN116669416A (zh) 2023-08-29

Similar Documents

Publication Publication Date Title
US9917100B2 (en) Three-dimensional NAND device containing support pedestal structures for a buried source line and method of making the same
US9831266B2 (en) Three-dimensional NAND device containing support pedestal structures for a buried source line and method of making the same
US9799670B2 (en) Three dimensional NAND device containing dielectric pillars for a buried source line and method of making thereof
CN113035872B (zh) 半导体结构及其制作方法
CN108962894B (zh) 一种填充沟槽形成触点的方法
US12557272B2 (en) Semiconductor structure and method for manufacturing same
CN108389837A (zh) 晶体管结构、存储器结构及其制备方法
WO2022151697A1 (zh) 半导体结构及其制作方法
TWI854444B (zh) 一種半導體元件及其形成方法
WO2022222325A1 (zh) 半导体结构及其制备方法
CN109411472A (zh) 动态随机存取存储器及其制造方法
WO2022198959A1 (zh) 半导体结构及其形成方法
CN109920760B (zh) 半导体装置的形成方法
CN208189569U (zh) 晶体管结构及存储器结构
WO2022148067A1 (zh) 半导体结构及其制作方法
WO2023155262A1 (zh) 接触结构及其制备方法、半导体结构
CN209087833U (zh) 电容器阵列结构和包含它的半导体存储器
WO2022062717A1 (zh) 半导体结构形成方法以及半导体结构
CN113707659B (zh) 半导体器件中孔、半导体器件的制备方法及半导体器件
CN211480005U (zh) 半导体结构
JP2001053251A (ja) 半導体装置の製造方法
US20230262963A1 (en) Contact structure, method of manufacturing contact structure, and semiconductor structure
US20220359526A1 (en) Memory device, and semiconductor structure and forming method thereof
CN116546814A (zh) 半导体结构及其形成方法、存储器
JPH11330413A (ja) 半導体装置の製造方法

Legal Events

Date Code Title Description
NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 22926580

Country of ref document: EP

Kind code of ref document: A1