WO2023153317A1 - 基板補正装置、基板積層装置、基板処理システム、基板補正方法、基板処理方法、および半導体装置の製造方法 - Google Patents

基板補正装置、基板積層装置、基板処理システム、基板補正方法、基板処理方法、および半導体装置の製造方法 Download PDF

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WO2023153317A1
WO2023153317A1 PCT/JP2023/003482 JP2023003482W WO2023153317A1 WO 2023153317 A1 WO2023153317 A1 WO 2023153317A1 JP 2023003482 W JP2023003482 W JP 2023003482W WO 2023153317 A1 WO2023153317 A1 WO 2023153317A1
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Prior art keywords
substrate
information
wafer
correction
unit
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Ceased
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PCT/JP2023/003482
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English (en)
French (fr)
Japanese (ja)
Inventor
幹雄 牛島
創 三ッ石
義弘 前原
智弘 千葉
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Nikon Corp
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Nikon Corp
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Application filed by Nikon Corp filed Critical Nikon Corp
Priority to KR1020247029987A priority Critical patent/KR20240140173A/ko
Priority to CN202380021229.0A priority patent/CN118679551A/zh
Priority to JP2023580213A priority patent/JP7786482B2/ja
Publication of WO2023153317A1 publication Critical patent/WO2023153317A1/ja
Priority to US18/799,299 priority patent/US20240404859A1/en
Anticipated expiration legal-status Critical
Priority to JP2025226639A priority patent/JP2026035803A/ja
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/50—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for positioning, orientation or alignment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00—Bonding of wafers, substrates or parts of devices
    • H10P10/12—Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates
    • H10P10/128—Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates by direct semiconductor to semiconductor bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P54/00—Cutting or separating of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/04—Apparatus for manufacture or treatment
    • H10P72/0428—Apparatus for mechanical treatment or grinding or cutting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/06—Apparatus for monitoring, sorting, marking, testing or measuring
    • H10P72/0604—Process monitoring, e.g. flow or thickness monitoring
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/06—Apparatus for monitoring, sorting, marking, testing or measuring
    • H10P72/0606—Position monitoring, e.g. misposition detection or presence detection
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/06—Apparatus for monitoring, sorting, marking, testing or measuring
    • H10P72/0616—Monitoring of warpages, curvatures, damages, defects or the like
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/30—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for conveying, e.g. between different workstations
    • H10P72/32—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for conveying, e.g. between different workstations between different workstations
    • H10P72/3212—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for conveying, e.g. between different workstations between different workstations the substrates to be conveyed not being semiconductor wafers or large planar substrates, e.g. chips or lead frames
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/30—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for conveying, e.g. between different workstations
    • H10P72/32—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for conveying, e.g. between different workstations between different workstations
    • H10P72/3218—Conveying cassettes, containers or carriers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/76—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using mechanical means, e.g. clamps or pinches
    • H10P72/7604—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using mechanical means, e.g. clamps or pinches the wafers being placed on a susceptor, stage or support
    • H10P72/7611—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using mechanical means, e.g. clamps or pinches the wafers being placed on a susceptor, stage or support characterised by edge profile or support profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/76—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using mechanical means, e.g. clamps or pinches
    • H10P72/7604—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using mechanical means, e.g. clamps or pinches the wafers being placed on a susceptor, stage or support
    • H10P72/7624—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using mechanical means, e.g. clamps or pinches the wafers being placed on a susceptor, stage or support characterised by the mechanical construction of the susceptor, stage or support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/301—Marks applied to devices, e.g. for alignment or identification for alignment

Definitions

  • the present invention relates to a substrate correcting apparatus, a substrate stacking apparatus, a substrate processing system, a substrate correcting method, a substrate processing method, and a semiconductor device manufacturing method.
  • Japanese Patent Application Laid-Open No. 2002-200000 describes a measurement apparatus for measuring position information of a plurality of marks on a substrate, and an exposure apparatus for performing alignment measurement and exposure for measuring position information of some marks selected from the plurality of marks on the substrate.
  • a lithographic system is described comprising an apparatus.
  • a first aspect of the present invention provides a substrate correction device.
  • the substrate correction apparatus may include an acquisition unit that acquires the first information based on the positional information of the plurality of alignment marks on the first substrate measured outside.
  • the substrate correction device may include a stage that holds a second substrate bonded to the first substrate. The stage may have a deforming portion that deforms the second substrate. The deformation section may be controlled based on the first information.
  • a holding member having a holding surface for holding the first substrate may be provided.
  • the holding of the first substrate by the holding member may be released.
  • the deformation section may be capable of partially deforming the second substrate.
  • the deformation section may have a plurality of actuators arranged along the second substrate.
  • a fifth aspect of the present invention provides a substrate correction device.
  • the substrate correction apparatus may include an acquisition unit that acquires the first information based on the positional information of the plurality of alignment marks on the first substrate measured outside.
  • the substrate correction apparatus may include a measurement unit that measures position information of a plurality of alignment marks on the first substrate and outputs second information based on the position information.
  • the substrate correction device may include a stage that holds a second substrate bonded to the first substrate.
  • the substrate correction device may include a deformation section that deforms the second substrate held on the stage.
  • the substrate correcting apparatus may include a control unit that controls the deformation unit based on the first information and aligns the first substrate and the second substrate based on the second information.
  • a sixth aspect of the present invention provides a substrate correction device.
  • the substrate correction apparatus may include an acquisition unit that acquires the first information based on the positional information of the plurality of alignment marks on the substrate measured outside.
  • the substrate correction device may include a stage that holds the substrate.
  • the substrate correction device may include a correction unit that corrects positional deviation between the substrate held on the stage and another substrate bonded to the substrate.
  • the substrate correction device may include a control section that controls the correction section based on the first information.
  • the substrate correction apparatus measures position information of a plurality of alignment marks of the substrate while the substrate is placed on the stage, and performs second correction based on the measured position information.
  • a measuring unit that outputs information may be further provided.
  • the controller may align the substrate and the other substrate based on the second information.
  • the number of the plurality of alignment marks measured by the measuring section may be smaller than the number of the plurality of alignment marks measured externally.
  • control section may set parameters used for alignment of the substrate and the other substrate based on the second information measured by the measurement section.
  • the first information may include information on linear components and nonlinear components of distortion of the substrate.
  • control unit performs the correction based on third information regarding distortion occurring in at least one of the substrate and the other substrate when the substrate is laminated on the other substrate. You can control the part.
  • the first measurement unit performs alignment in a range of alignment marks on the substrate in which position deviation occurs due to distortion of a nonlinear component occurring in at least one of the substrate and the other substrate. Position information of the mark may be measured.
  • the thirteenth aspect of the present invention may further include a holding member having a holding surface for holding the substrate, and the holding surface may have a convex shape with a central portion protruding toward the substrate.
  • the fourteenth aspect of the present invention may further include a holding member having a holding surface for holding the substrate, and the holding surface may have regions with different heights in the circumferential direction.
  • the correction section may be a plurality of actuators arranged on one surface of the substrate.
  • a sixteenth aspect of the present invention provides a substrate processing system.
  • a substrate processing system may include the substrate correction apparatus according to the sixth aspect.
  • the substrate processing system may comprise a lamination section for laminating the substrate to another substrate.
  • a seventeenth aspect of the present invention provides a substrate processing system.
  • the substrate processing system may include a first measurement unit that measures position information of a plurality of alignment marks on the substrate placed on the first stage and outputs first information based on the measured position information.
  • the substrate processing system may include a correction section that corrects positional deviation between the substrate held on the second stage and another substrate bonded to the substrate.
  • the substrate processing system may include a control section that controls the correction section based on the first information.
  • the substrate processing system measures the position information of alignment marks less than the number of alignment marks measured by the first measurement unit, and measures the position information based on the measured position information.
  • a second measuring unit that outputs two pieces of information may be provided.
  • the control section may control the correction section based on the first information, and may control alignment between the substrate and another substrate based on the second information.
  • a nineteenth aspect of the present invention provides a substrate processing system.
  • the substrate processing system may include a first measurement unit that measures position information of a plurality of alignment marks on the substrate placed on the first stage and outputs first information based on the measured position information.
  • the substrate processing system may include a second measurement section that measures position information of a plurality of alignment marks on the substrate held by the second stage and outputs second information based on the position information.
  • the substrate processing system may include a correction section that corrects positional deviation between the substrate held on the second stage and another substrate bonded to the substrate.
  • the substrate processing system may include a control section that controls the correction section based on the first information.
  • the number of alignment marks measured by the second measuring section may be smaller than the number of alignment marks measured by the first measuring section.
  • a twentieth aspect of the present invention provides a substrate processing system.
  • the substrate processing system may include a measurement unit that measures position information of a plurality of alignment marks on the substrate placed on the first stage and outputs first information based on the measured position information.
  • the substrate processing system may include a correction section that corrects positional deviation between the substrate held on the second stage and another substrate bonded to the substrate.
  • the substrate processing system may include a control section that controls the correction section based on the first information.
  • the measurement section may have a reference coordinate system and measure the absolute coordinates of the alignment mark in the reference coordinate system.
  • a twenty-first aspect of the present invention provides a substrate correction method.
  • the substrate correction method may comprise obtaining first information based on positional information of a plurality of alignment marks on the substrate.
  • the substrate correction method may include a correction step of correcting a positional deviation between the substrate held on the stage and another substrate bonded to the substrate.
  • the substrate correction method may comprise a control step of controlling said correction step based on said first information.
  • the substrate correction method includes measuring positional information of a plurality of alignment marks of the substrate while the substrate is placed on the stage, and performing second correction based on the measured positional information.
  • a measuring step of outputting information may also be included.
  • the controlling step may align the substrate with the other substrate based on the second information.
  • the number of the plurality of alignment marks measured in the measuring step may be smaller than the number of the plurality of alignment marks measured outside.
  • a twenty-fourth aspect of the present invention provides a substrate processing method.
  • the substrate processing method may include a measuring step of measuring positional information of a plurality of alignment marks on the substrate placed on the first stage and outputting information based on the measured positional information.
  • the substrate processing method may include a correcting step of correcting a positional deviation between the substrate placed on the second stage and another substrate bonded to the substrate.
  • the substrate processing method may comprise a controlling step of controlling the correcting step based on the information obtained in the measuring step.
  • a twenty-fifth aspect of the present invention provides a method of manufacturing a semiconductor device.
  • the method for manufacturing a semiconductor device may include a substrate corrected by the substrate correction method according to any of the twenty-first to twenty-third aspects.
  • the method of manufacturing a semiconductor device may include an alignment step of aligning another substrate.
  • the method of manufacturing a semiconductor device may include a bonding step of bonding the substrate and the other substrate to form a laminate.
  • the method of manufacturing a semiconductor device may include a dicing step of separating a plurality of semiconductor devices by cutting the laminate.
  • a twenty-sixth aspect of the present invention provides a substrate correction device.
  • the substrate correction apparatus may include an acquisition unit that acquires the first information based on the positional information of the plurality of alignment marks on the substrate measured outside.
  • the substrate correction device may include a stage that holds the substrate.
  • the substrate correction device may include a deformation section that deforms the substrate held on the stage.
  • the substrate correction device may include a control section that controls the deformation section based on the first information.
  • FIG. 1 is a schematic plan view of a lamination device 200 in this embodiment.
  • FIG. FIG. 4 is a schematic diagram illustrating measurement of a wafer W using a part of the pre-aligner 500 in this embodiment;
  • FIG. 2 is a schematic cross-sectional view of a wafer holder WH that holds an upper wafer W of two wafers W stacked in a stacking apparatus 200 according to the present embodiment;
  • FIG. 3 is a schematic cross-sectional view of a wafer holder WH that holds a lower wafer W among two wafers W stacked in the stacking device 200 according to the present embodiment; 4 is a flow chart showing a procedure for stacking wafers W in the stacking apparatus 200 according to the present embodiment to fabricate a stack 230.
  • FIG. 3 is a view showing the structure of the stacking unit 300 according to the present embodiment and the state after the wafer holder WH holding the wafer W is loaded into the stacking unit 300.
  • FIG. It is a figure explaining operation
  • FIG. 3 is a schematic cross-sectional view of the lamination part 300 in a state where wafers W are aligned according to the present embodiment
  • FIG. 4 is a diagram showing the state of the wafer W and the wafer holder WH in the aligned state according to the present embodiment
  • FIG. 3 is a schematic cross-sectional view of the lamination unit 300 in a state where lamination of wafers W in this embodiment is started.
  • FIG. 3 is a diagram showing a state of a wafer W and a wafer holder WH in a state where lamination is started in the present embodiment;
  • FIG. 9 is a diagram showing a schematic configuration of a nonlinear vector diagram 901 showing nonlinear components of distortion of wafer W in this embodiment.
  • FIG. 9 is a diagram showing a schematic configuration of a three-dimensional view 902 for correcting nonlinear components of distortion of wafer W in this embodiment.
  • 4 is a flow chart showing a procedure for stacking wafers W in this embodiment.
  • FIG. 6 is a schematic cross-sectional view of a substrate correction device 601 that can be used to correct nonlinear components of distortion of wafer W in this embodiment.
  • FIG. 6 is a schematic plan view of the substrate correction device 601 according to the present embodiment, showing the layout of actuators 612 in the substrate correction device 601.
  • FIG. It is a figure explaining operation
  • 4 is a flow chart showing a method of manufacturing a stacked semiconductor device according to the present embodiment.
  • FIG. 1 is a diagram schematically showing the configuration of a substrate processing system 1000 according to this embodiment.
  • the substrate processing system 1000 includes a measuring device 100 and a stacking device 200 which are connected inline with each other.
  • the in-line connection means that different apparatuses are connected to each other while the transfer path of wafers, which is an example of substrates, is connected.
  • the measurement device 100 has a measurement control section 60 .
  • the lamination device 200 has a lamination control section 150 and a substrate correction device 601 .
  • the measurement control unit 60 of the measurement device 100 and the stacking control unit 150 of the stacking device 200 are connected to each other via a local area network (LAN) 800 and communicate with each other.
  • a controller 900 that controls the entire substrate processing system 1000 is connected to the LAN 800 .
  • the control device 900 has a storage section 910 .
  • a substrate processing system 1000 according to the present embodiment is an apparatus that stacks wafers by correcting positional deviation due to distortion occurring in the wafers.
  • FIG. 2 is a schematic plan view of wafers W stacked in the substrate processing system 1000.
  • FIG. Wafer W has a notch 214 , a plurality of circuit regions 216 and a plurality of alignment marks 218 .
  • the wafer W is, for example, a 300 mm wafer.
  • the circuit regions 216 are periodically arranged on the surface of the wafer W in the plane direction of the wafer W.
  • semiconductor devices, wirings, protective films, and the like are formed by photolithography or the like.
  • structures including connection portions such as pads and bumps that serve as connection terminals when electrically connecting the wafer W to other wafers W, lead frames, and the like are also arranged.
  • the alignment mark 218 is an example of a structure formed on the surface of the wafer W, and is arranged to overlap the scribe lines 212 arranged between the circuit regions 216 .
  • the alignment mark 218 is used as an index when aligning this wafer W with another wafer W to be stacked.
  • the alignment marks 218 include, for example, search alignment alignment marks and fine alignment alignment marks. In this embodiment, a two-dimensional mark shall be used as the alignment mark 218 .
  • the strain that occurs in the wafer W includes initial strain that occurs before the wafer W is stacked and strain that occurs during stacking of the wafer W.
  • the initial strain is the strain caused by processing the wafer W such as forming a structure on the surface of the wafer W
  • the strain during lamination is the strain caused during the lamination process in the lamination device 200 .
  • the distortion occurring in the wafer W is the displacement from the designed coordinates of the structure on the wafer W, that is, the designed position.
  • the distortion that occurs in the wafer W includes plane distortion and three-dimensional distortion.
  • the plane strain is the strain that occurs in the direction along the stacking surface of the wafer W.
  • the plane strain is a linear strain represented by a linear transformation of the position displaced with respect to the design position of each structure of the wafer W, and Non-linear distortions other than linear distortions that cannot be represented.
  • Linear strain includes magnification strain in which the amount of displacement increases at a constant rate along the radial direction from the center.
  • the magnification distortion is a value obtained by dividing the amount of deviation from the design value at the distance X from the center of the wafer W by X, and the unit is ppm.
  • the magnification distortion includes isotropic magnification distortion. Isotropic magnification distortion is distortion in which the X and Y components of the displacement vector from the design position are equal when the coordinates X and Y have the same value, that is, the magnification in the X direction is equal to the magnification in the Y direction.
  • Linear distortion includes anisotropic magnification distortion, which is distortion in which the displacement vector from the design position has different X and Y components, that is, the magnification in the X direction and the magnification in the Y direction are different.
  • Linear distortion includes orthogonal distortion.
  • Orthogonal distortion is a displacement parallel to the X-axis direction from the design position, which increases with the distance of the structure from the origin in the Y-axis direction, when the X-axis and Y-axis are set to be orthogonal to each other with the center of the wafer W as the origin. It is the distortion that is being done.
  • the amount of displacement is equal in each of a plurality of regions crossing the Y-axis parallel to the X-axis, and the absolute value of the amount of displacement increases with increasing distance from the X-axis.
  • the orthogonal strain is such that the direction of displacement on the positive side of the Y-axis and the direction of displacement on the negative side of the Y-axis are opposite to each other.
  • the three-dimensional distortion of the wafer W is displacement in a direction other than the direction along the stacking surface of the wafer W, that is, in a direction intersecting the stacking surface.
  • Stereoscopic distortion includes bending of the wafer W in whole or in part due to bending of the wafer W in whole or in part.
  • the bending of the wafer W means that the surface of the wafer W changes into a shape that includes a point that does not exist on the plane specified by the three points on the wafer W.
  • FIG. Stereoscopic distortion also includes linear distortion and nonlinear distortion.
  • the curvature is a distortion that causes the surface of the wafer W to form a curved surface, and includes warping of the wafer W, for example.
  • warpage refers to the distortion that remains in the wafer W when the influence of gravity is eliminated.
  • the distortion of the wafer W due to the warpage plus the effect of gravity is called deflection.
  • the warpage of the wafer W includes global warpage in which the entire wafer W is bent with a generally uniform curvature, and local warpage in which a portion of the wafer W is bent with a local curvature that changes.
  • Nonlinear distortion is caused by the mutual influence of a wide variety of factors, but the main factors are the crystal anisotropy in the silicon single crystal substrate and the wafer W manufacturing process.
  • the wafer W is formed with a plurality of structures.
  • a plurality of circuit regions 216, scribe lines 212, and a plurality of alignment marks 218 are formed on the wafer W as structures.
  • Each of the plurality of circuit regions 216 includes, as structures, wiring formed by a photolithography technique or the like, a protective film, and a connection terminal when electrically connecting the wafer W to another wafer W, a lead frame, or the like. Connection parts such as pads and bumps are also provided.
  • the structure and arrangement of these structures that is, the configuration of the structures, affects the in-plane stiffness distribution and in-plane stress distribution of the wafer W. Local curvature occurs.
  • the configuration of these structures may be different for each wafer W, or may be different for each type of wafer W such as a logic wafer, a CIS wafer, and a memory wafer. Further, even if the manufacturing process is the same, it is conceivable that the configuration of the structures may be slightly different depending on the manufacturing apparatus. In this way, the configuration of the plurality of structures formed on the wafer W may differ for each wafer W, each type of wafer W, each manufacturing lot of wafer W, or each manufacturing process of wafer W. FIG. Therefore, the in-plane stiffness distribution of the wafer W is also different. Therefore, the curved state of the wafer W caused in the manufacturing process and the stacking process is also different.
  • FIG. 3 is a flow chart showing the operation of the substrate processing system 1000 in this embodiment.
  • the measurement apparatus 100 measures the initial strain occurring in the stacked wafers W before stacking.
  • step S02 it is determined whether or not information on strain during stacking that occurs when wafers W are stacked is retained. If the distortion information during lamination of wafer W is not held (NO in step S02), the process proceeds to step S03, and the distortion during lamination of wafer W is measured. After step S03 is completed, the process advances to step S04 to calculate the amount of correction for wafer W.
  • step S02 of FIG. 3 if the stacking strain information of wafer W is held (YES in step S02), the process proceeds to step S04 without going through step S03. After step S04 is completed, the process proceeds to step S05, and wafers W are stacked.
  • FIG. 4 is a diagram schematically showing the configuration of the measuring device 100 according to this embodiment.
  • the measurement apparatus 100 is an apparatus that measures a plurality of alignment marks 218 on the wafer W to measure distortion of the wafer W.
  • FIG. The measuring apparatus 100 includes a measuring unit 101 having a mark detection system for detecting alignment marks 218 on the wafer W, and a wafer slider 102 which holds the wafer W and can move minutely with respect to a stage on which the wafer W is placed. Then, while controlling the drive system 103 that drives the wafer slider 102 and the drive of the wafer slider 102 by the drive system 103, measurement information is acquired by the measurement unit 101, and position information of the plurality of marks on the wafer W is calculated. and a measurement control unit 104 .
  • the measurement unit 101 detects one alignment mark 218 for each of a plurality of regions divided on the wafer using a mark detection system.
  • the measurement unit 101 detects the first number of alignment marks 218 .
  • the first number may be the number of all alignment marks 218 provided on the wafer W, for example. That is, the measurement unit 101 may measure the positions of all the alignment marks 218 provided on the wafer W.
  • FIG. A plurality of measurement units 101 may be provided.
  • the measurement control unit 104 calculates position information of each alignment mark 218 based on measurement information from the measurement unit 101 .
  • the measurement control unit 104 uses the position information of the alignment mark 218 measured by the measurement unit 101 to perform EGA (Enhanced Global Alignment) calculation.
  • EGA Enhanced Global Alignment
  • the EGA calculation means that after the alignment mark 218 is measured, the position of the alignment mark 218 is calculated using statistical calculation such as the least-squares method based on the information on the difference between the design value and the actual measurement value of the position coordinates of the alignment mark 218. It means a statistical operation for calculating the parameters of the model formula expressing the coordinate correction amount.
  • Measurement control unit 104 transmits information on the calculated linear component and nonlinear component of the initial strain of wafer W to control device 900 . Note that the measurement control unit 104 may transmit only the information on the nonlinear component of the initial distortion of the wafer W to the control device 900 .
  • FIG. 5 shows a schematic plan view of the lamination device 200 in this embodiment.
  • the stacking device 200 is a device for stacking one wafer W with another wafer W to form a stacked body 230.
  • the stacking device 200 includes a housing 110, wafer cassettes 120 and 130 arranged outside the housing 110, and a stacking device. It includes a control unit 150 , a transport unit 140 arranged inside the housing 110 , a stacking unit 300 , a holder stocker 400 , a pre-aligner 500 and an activation device 600 .
  • One wafer cassette 120 accommodates wafers W to be stacked from now on.
  • the other wafer cassette 130 accommodates a plurality of stacks 230 formed by stacking wafers W.
  • FIG. By using the wafer cassette 120, a plurality of wafers W can be loaded into the stacking device 200 at once. Moreover, by using the wafer cassette 130, the plurality of stacked bodies 230 can be collectively unloaded from the stacking device 200.
  • the transport unit 140 transports the wafer W and the wafer holder WH from the measuring device 100 into the stacking device 200 .
  • the holder stocker 400 accommodates a plurality of wafer holders WH.
  • the transport unit 140 loads and sets the wafer holder WH selected from the holder stocker 400 inside the stacking unit 300 in advance, and then transports the wafer W to be stacked inside the stacking unit 300 .
  • the transfer unit 140 may transfer the wafer holder WH holding the wafer W into the stacking unit 300 .
  • the wafer holder WH is an example of a wafer holding member, and is a disk-shaped member that is one size larger than the wafer W and has high rigidity.
  • Each wafer holder WH has a wafer chucking function such as an electrostatic chuck or a vacuum chuck, and holds the wafer W individually inside the stacking device 200 .
  • FIG. 6 is a schematic diagram illustrating measurement of the wafer W using part of the pre-aligner 500.
  • the pre-aligner 500 has a rotation drive section 510 , an edge detection section 520 and a distance measurement section 530 .
  • the rotation drive unit 510 rotates the mounted wafer W while supporting the vicinity of the center thereof against gravity.
  • the edge detector 520 continuously detects the position of the outer peripheral edge of the rotating wafer W.
  • the pre-aligner 500 detects the eccentricity of the wafer W with respect to the center of rotation, thereby detecting the geometric center of each wafer W.
  • the orientation of the wafer W is detected by detecting a notch or the like provided on the wafer W.
  • the pre-aligner 500 measures deformation of the wafer W using the distance measurement unit 530 .
  • the distance measuring unit 530 detects the distance from the rotating wafer W to the lower surface in the drawing in a direction parallel to the rotation axis. Thereby, the deformation of the wafer W in the thickness direction can be continuously detected in the circumferential direction based on the detected variation of the distance. Furthermore, by scanning the distance measuring unit 530 in the radial direction of the wafer W, the deformation of the wafer W as a whole can be measured.
  • Wafers W determined to be unsuitable for stacking may be transported to a predetermined position, for example, a specific accommodation position in the wafer cassette 130, and excluded from stacking.
  • a determination to exclude a certain wafer W from the stacking target may be made, for example, based on the fact that the amount of deformation of the wafer W exceeds a predetermined range.
  • exceeding the predetermined range means, for example, the case where the wafer W is deformed to such an extent that it cannot be brought into close contact with the holding surface of the wafer holder WH by the adsorption force of the wafer holder WH which is the holding member. is.
  • exceeding a predetermined range means, for example, the case where the deformation amount of the wafer W to be measured exceeds the limit of the correction amount by the correction described later. Furthermore, exceeding a predetermined range means that, for example, when the combination of the wafer W to be measured and the wafer W to be stacked thereon is already determined, the difference in the amount of deformation between the two wafers W is determined. This is a case where the positional deviation due to the .DELTA.
  • the amount of correction is the amount of deformation caused to at least one of the two wafers W so that the positional deviation of the two wafers W stacked on each other is equal to or less than a threshold value.
  • the stacking control unit 150 is composed of processors such as CPU, FPGA, ASIC, etc., and memories such as ROM, RAM, etc. Based on the control program, each unit of the stacking device 200 is interconnected and controlled comprehensively. In addition, the lamination control unit 150 receives user instructions from the outside and sets manufacturing conditions for manufacturing the laminated body 230 . Furthermore, the stacking control unit 150 also has a user interface that displays the operating state of the stacking device 200 to the outside.
  • the activation device 600 generates plasma that activates the upper surface of the wafer W.
  • the wafers W activated by the activation device 600 are stacked by contacting or approaching each other. It should be noted that stacking includes bonding wafers W to each other by autonomously attracting each other.
  • the activation device 600 cleans the surface of the wafer W with a chemical solution such as ammonia, alcohol, hydrochloric acid, or pure water.
  • the stacking unit 300 has a pair of stages that each hold a wafer W and face each other. After the wafers W held on the stages are aligned with each other, the wafers W are brought into contact with each other and stacked to form a stack 230 . .
  • the wafers W stacked in the stacking device 200 may be unprocessed silicon wafers, compound semiconductor wafers, glass wafers, etc., in addition to wafers W on which elements, circuits, terminals, etc. are formed.
  • the combination of wafers W to be stacked may be a circuit wafer and an unprocessed wafer, or may be unprocessed wafers.
  • the wafer W to be stacked may itself be a stack formed by stacking a plurality of wafers.
  • FIG. 7 is a schematic cross-sectional view of a wafer holder WH that holds the upper wafer W of the two wafers W stacked in the stacking device 200.
  • the wafer holder WH has a flat holding surface 225 and has a function of attracting and holding the wafer W, such as an electrostatic chuck or a vacuum chuck.
  • the wafer holder WH may have a convex holding surface with a raised center or a partially uneven holding surface.
  • One wafer W1 is released from being held by the wafer holder WH at the stage of being stacked on the other wafer W, as will be described later.
  • one wafer W is held by a wafer holder WH having a flat holding surface 225 .
  • FIG. 8 is a schematic cross-sectional view of the wafer holder WH that holds the lower wafer W of the two wafers W stacked in the stacking device 200. As shown in FIG. The holding surface 225 of the wafer holder WH has a convex shape with a raised center in the illustrated example.
  • the wafer holder WH has a function of attracting and holding the wafer W, such as an electrostatic chuck or a vacuum chuck. Therefore, the wafer W held by the wafer holder WH is curved along the shape of the holding surface 225, and is convexly deformed with the center of the wafer W as the vertex.
  • the linear distortion and nonlinear distortion produced in the wafer W as described above can be corrected by controlling the shape of the wafer holder WH that holds the wafer W.
  • a wafer holder WH having a holding surface 225 of a convex linear curved surface that is uniform in the circumferential direction is used as shown in FIG.
  • the nonlinear component of the distortion components generated in the wafer W can be corrected.
  • the wafer holder WH may have, for example, a shape in which the vicinity of the center is recessed, or a shape in which the curvature of the vicinity of the center is smaller than that of other regions.
  • FIG. 9 is a flow chart showing the procedure (S03) for measuring the strain during stacking of the wafer W in this embodiment.
  • the stacking control unit 150 selects a wafer holder WH from the holder stocker 400, and carries and sets the selected wafer holder WH inside the stacking unit 300 in advance by the transport unit 140 (step S11). Subsequently, the lamination control unit 150 measures deformation of the wafer W using the distance measurement unit 530 of the pre-aligner 500 (step S12). Subsequently, the stacking control unit 150 activates the stacking surface of the wafer W to be stacked, and cleans the stacking surface of the wafer W (step S13). The lamination controller 150 scans the surface of the wafer W with the plasma generated by the activation device 600 . As a result, each surface of the wafer W is cleaned and chemically active. Therefore, the wafers W are autonomously attracted and stacked by contacting or approaching each other.
  • the wafer W can be activated by sputter etching using an inert gas, an ion beam, a fast atom beam, etc., or a mechanical process such as polishing, in addition to the method of exposing it to plasma.
  • an ion beam or a fast atom beam it is possible to generate the laminated portion 300 under reduced pressure.
  • the wafer W can be activated by ultraviolet irradiation, ozone asher, or the like. Further activation may be achieved by chemically cleaning the surface of the wafer W using, for example, a liquid or gaseous etchant.
  • step S14 the wafers W to be stacked on each other are carried into the stacking section 300 (step S14).
  • FIG. 10 is a diagram showing the structure of the stacking section 300 in this embodiment and the state after the wafer W is carried into the stacking section 300.
  • a stacking unit 300 in the stacking apparatus 200 includes a frame 310, a fixed stage 322, and a moving stage 332 as a second stage.
  • the frame 310 has a bottom plate 312 and a top plate 316 parallel to the floor surface 301 and a plurality of supports 314 perpendicular to the floor surface 301 .
  • a fixed stage 322 fixed downward to the lower surface of the top plate 316 in the drawing has a function of holding a vacuum chuck, an electrostatic chuck, or the like. As shown, the fixed stage 322 holds a wafer W together with a wafer holder WH having a flat holding surface 225 .
  • a microscope 324 is fixed to the bottom surface of the top plate 316 .
  • the microscope 324 can observe the upper surface of the wafer W held on the moving stage 332 arranged to face the fixed stage 322 .
  • the moving stage 332 is mounted on a Y-direction driving section 333 that moves in the direction indicated by the arrow Y in the drawing.
  • the Y-direction driving portion 333 overlaps the X-direction driving portion 331 arranged on the bottom plate 312 .
  • the X-direction driving part 331 moves in the direction indicated by the arrow X in the figure, parallel to the bottom plate 312 . This allows the moving stage 332 to move two-dimensionally in the XY directions.
  • the illustrated moving stage 332 holds the wafer W held by the wafer holder WH.
  • the wafer holder WH has a curved holding surface 225 along which the wafer W is also held in a curved state.
  • the fixed stage 322 or the moving stage 332 on which the wafer W is mounted may directly hold the wafer W in the stacking section 300 of the stacking apparatus 200 without using the wafer holder WH. In this case, the fixed stage 322 or the moving stage 332 becomes the holding member.
  • the moving stage 332 is moved up and down with respect to the Y-direction drive section 333 by a Z-direction drive section 335 that moves up and down in the direction indicated by the arrow Z.
  • the amount of movement of the moving stage 332 by the X-direction driving section 331, Y-direction driving section 333, and Z-direction driving section 335 is precisely measured using an interferometer or the like.
  • the X-direction drive section 331 and the Y-direction drive section 333 may be configured in two stages, that is, a coarse movement section and a fine movement section. As a result, both high-precision alignment and high throughput can be achieved, and the movement of the wafers W mounted on the moving stage 332 can be stacked at high speed without lowering the control accuracy.
  • a microscope 334 is further mounted on the side of the moving stage 332 on the Y-direction driving unit 333 .
  • the microscope 334 can observe the lower surface of the downward facing wafer W held on the fixed stage 322 .
  • the stacking section 300 may further include a rotation driving section that rotates the moving stage 332 around a rotation axis perpendicular to the bottom plate 312 and a swinging driving section that swings the moving stage 332 .
  • the tilt angle of the moving stage 332 is adjusted to make the moving stage 332 parallel to the fixed stage 322, and the wafer W held by the moving stage 332 is rotated to improve the alignment accuracy of the wafer W.
  • the lamination control unit 150 mutually calibrates the microscopes 324 and 334 in advance by mutually focusing the microscopes 324 and 334 and observing a common index. Thereby, the relative positions of the pair of microscopes 324 and 334 in the stack 300 are measured.
  • the alignment marks 218 formed on each wafer W are detected (step S15).
  • FIG. 11 is a diagram explaining the operation of the lamination section 300 in step S15.
  • the stacking control unit 150 operates the X-direction driving unit 331 and the Y-direction driving unit 333 so that the second number of the alignment marks 218 provided on each wafer W by the microscopes 324 and 334 are aligned. Alignment mark 218 is detected.
  • the second number may be, for example, 10 or less.
  • the linear distortion and non-linear distortion of the wafer W can be grasped in advance from the positional information of the alignment marks 218 of the wafer W measured by the measurement apparatus 100 .
  • step S15 only the number of measurement points necessary for grasping the position of wafer W with respect to the coordinate system of stacking unit 30, that is, shift and rotation, should be secured. may be less than the first number of alignment marks 218 on wafer W measured by measuring apparatus 100 .
  • the lamination control unit 150 calculates the relative position of the wafer W, is calculated (step S16). That is, in the stacked section 300, the amount of movement of the moving stage 332 is calculated so that the corresponding circuit regions 216 overlap each other. Note that the lamination control unit 150 also calculates the adjustment amount of the tilt angle when the movable stage 332 is tilted and the tilt angle needs to be adjusted.
  • the microscopes 324 and 334 in this embodiment function as a second measurement unit that outputs second information indicating the amount of movement of the moving stage 332 for aligning the wafer W.
  • the movement amount of the moving stage 332 calculated in step S16 can be calculated by measuring the positions of the plurality of alignment marks 218 on the wafer W at multiple points and executing an EGA calculation for statistical processing.
  • FIG. 13 is a diagram showing the state of the wafer W and the wafer holder WH in the aligned state.
  • FIG. 15 is a diagram showing the state of the wafer W and the wafer holder WH after lamination has started.
  • step S18 As shown in FIG. 15, at the time of contact in step S18, one flat wafer W and the other curved wafer W partially contact each other. As a result, as indicated by a dotted line C in the drawing, a starting point of lamination is formed at approximately the center of the wafer W, where the wafer W is partially laminated.
  • the stacking control unit 150 releases the holding of the wafer W by the wafer holder WH on the fixed stage 322 .
  • the upper wafer W which is freed in the figure, expands the stacked area autonomously due to its own weight and the intermolecular force of the activated wafer W itself, and eventually the entire surface is stacked. be done. In this way, the stacked body 230 of the wafers W is formed in the stacking section 300 .
  • the wafer W on the lower side in the drawing continues to be held by the wafer holder WH having the curved holding surface 225 throughout the stacking process after step S18. Therefore, since the wafers W are stacked in a state corrected by the wafer holder WH, the magnification difference between the wafers W can be corrected.
  • the stacking control section 150 may partially or completely release the holding of the wafer W by the wafer holder WH. Also, the holding of the wafer holder WH by the fixed stage 322 may be released.
  • the lower wafer W lifts from the wafer holder WH and bends due to the pulling force from the upper wafer W in the process of enlarging the contact area. As a result, the shape is changed so that the surface of the lower wafer W is elongated, so that the difference from the amount of elongation of the surface of the upper wafer W is reduced by this amount of elongation.
  • the wafer W may be stacked by releasing the wafer W held by the moving stage 332 without releasing the wafer W held by the fixed stage 322 . Furthermore, the wafers W may be stacked by bringing the fixed stage 322 and the moving stage 332 closer together while holding the wafer W on both of the fixed stage 322 and the moving stage 332 .
  • the multiple alignment marks 218 formed on the wafer W forming the stacked body 230 are detected by the microscopes 324 and 334, and the positional information of the alignment mark 218 is acquired.
  • the linear component and the nonlinear component of the distortion during lamination of the wafer W can be calculated (step S19). Since the position information of the alignment mark 218 observed at this time includes the initial distortion component and the lamination distortion component of the wafer W, by subtracting the initial distortion component of the wafer W measured by the measurement apparatus 100, , the components of the strain during lamination of the wafer W can be calculated.
  • the stacking control unit 150 transmits the information of the calculated linear component and nonlinear component of the strain during stacking of the wafer W to the control device 900 as the third information. As described above, the step of measuring the strain during stacking of the wafer W in step S03 of FIG. 3 is completed.
  • step S04 calculates the correction amount of the wafer W.
  • step S04 calculates the correction amount of the wafer W.
  • FIG. 17 is a flow chart showing the procedure for calculating the correction amount of the wafer W in this embodiment.
  • FIG. 17 shows details of step S04 in FIG.
  • the control device 900 receives information on the linear and nonlinear components of the initial distortion of the wafer W from the measurement control section 60 .
  • the control device 900 receives the information on the linear component and the non-linear component of the distortion during lamination of the wafer W from the lamination control section 150 .
  • step S23 the control device 900 uses the information on the nonlinear component of the initial distortion of the wafer W, the information on the nonlinear component of the distortion during lamination, and the design information indicating the size of the wafer W, etc. Generate information that integrates the nonlinear components of the distortion of W.
  • FIG. 18 is a nonlinear vector diagram 901 schematically showing information obtained by integrating the nonlinear components of the distortion of the wafer W in this embodiment. In FIG. 18, it is shown that the wafer W is distorted in the direction of the arrow with a magnitude corresponding to the length of the arrow.
  • step S24 the control device 900 generates shape information indicating the shape of the wafer W to be corrected based on the information integrating the nonlinear components.
  • FIG. 19 is a stereogram 902 schematically showing shape information for correcting the nonlinear component of the distortion of the wafer W in this embodiment.
  • the three-dimensional view 902 shows the magnitude of distortion of the wafer W in the Z direction (direction perpendicular to the plane of the wafer W).
  • step S25 the control device 900 calculates the drive amount of the actuator to be driven to correct the nonlinear component of the distortion of the wafer W based on the generated shape information.
  • the details of the operation of the actuator for correcting the nonlinear component of the distortion of wafer W will be described later.
  • the step of calculating the correction amount of the wafer W in step S04 in FIG. 3 is completed.
  • the process proceeds to the step of stacking the wafers W in step S05 in FIG.
  • FIG. 20 is a flowchart showing the procedure for stacking wafers W in this embodiment.
  • FIG. 20 shows details of the step of stacking the wafers W in step S05 in FIG. Since steps S12 to S18 in FIG. 20 are the same as steps S12 to S18 in FIG. 9, description thereof is omitted.
  • the stacking control unit 150 selects a wafer holder WH from the holder stocker 400, and carries the selected wafer holder WH into the stacking unit 300 by the transport unit 140 in advance.
  • the wafer holder WH selected at this time is selected for the purpose of correcting the positional deviation between the wafers W due to the linear distortion of the wafers W.
  • FIG. The lamination control unit 150 receives the information of the linear component of the initial strain of the wafer W measured in step S01 and the information of the linear component of the strain during lamination from the control device 900, and based on the information, A wafer holder WH suitable for correcting the distortion of the linear component of W is selected from holder stocker 400 . Thereby, the linear component of the distortion of the wafer W can be corrected by the wafer holder WH.
  • step S32 of FIG. 20 the actuator is driven based on the actuator driving amount calculated in step S25 of FIG. 17 to correct the nonlinear component of the distortion of wafer W.
  • FIG. Step S32 in FIG. 20 is performed between steps S14 and S15 in FIG.
  • FIG. 21 is a schematic cross-sectional view of a substrate correction device 601 that can be used to correct the nonlinear component of distortion of the wafer W in this embodiment.
  • the substrate correction device 601 is incorporated in the moving stage 332 of the stacking section 300 and used to correct one of the wafers W in the stacking device 200 .
  • the substrate correction device 601 deforms the wafer W by sucking the wafer W in a state where the shape of the chucking surface for deforming the wafer W is created, thereby correcting the nonlinear component of the distortion of the wafer W.
  • FIG. 21 is a schematic cross-sectional view of a substrate correction device 601 that can be used to correct the nonlinear component of distortion of the wafer W in this embodiment.
  • the substrate correction device 601 is incorporated in the moving stage 332 of the stacking section 300 and used to correct one of the wafers W in the stacking device 200 .
  • the substrate correction device 601 deforms the wafer W by sucking the wafer
  • the substrate correction device 601 has a base portion 611 , a plurality of actuators 612 and a suction portion 613 .
  • the base portion 611 supports the adsorption portion 613 via the actuator 612 .
  • the adsorption unit 613 has an adsorption mechanism such as a vacuum chuck or an electrostatic chuck, and forms the upper surface of the moving stage 332 .
  • the suction unit 613 sucks and holds the loaded wafer holder WH.
  • the wafer holder WH holding the lower wafer W has a convex shape as shown in FIG.
  • a plurality of actuators 612 are arranged below the suction portion 613 along the lower surface of the suction portion 613 .
  • the plurality of actuators 612 are individually driven by external supply of working fluid through pumps 615 and valves 616 under the control of the stack control unit 150 .
  • the plurality of actuators 612 expands and contracts in the thickness direction of the moving stage 332, that is, in the overlapping direction of the wafers W, with different expansion and contraction amounts, thereby raising or lowering the joined area of the adsorption section 613.
  • the plurality of actuators 612 are coupled to the suction portion 613 via links, respectively.
  • a center portion of the adsorption portion 613 is coupled to the base portion 611 by a support 614 .
  • the actuator 612 operates in the substrate correction device 601
  • the surface of the adsorption portion 613 is displaced in the thickness direction for each region where the actuator 612 is coupled.
  • FIG. 22 is a schematic plan view of the substrate correction device 601 in this embodiment, showing the layout of the actuators 612 in the substrate correction device 601.
  • the actuators 612 are arranged radially around the column 614 .
  • the arrangement of the actuators 612 can be regarded as a concentric circle centering on the support 614 .
  • the arrangement of the actuators 612 is not limited to that shown in the figure, and may be arranged, for example, in a grid pattern, a spiral pattern, or the like. As a result, the shape of the wafer W can be changed concentrically, radially, spirally, or the like for correction.
  • FIG. 23 is a diagram for explaining the operation of the substrate correction device 601 in this embodiment.
  • the actuators 612 can be expanded and contracted to change the shape of the adsorption section 613 . Therefore, when the suction portion 613 is suctioning the wafer holder WH and the wafer holder WH is holding the wafer W, the shapes of the wafer holder WH and the wafer W can be changed by changing the shape of the suction portion 613. It can change and bend.
  • the actuators 612 can be considered to be arranged concentrically, that is, in the circumferential direction of the moving stage 332 . Therefore, as indicated by the dotted line M in FIG. 22, by grouping the actuators 612 for each circumference and increasing the driving amount toward the circumference, the center of the surface of the adsorption portion 613 is raised to form a spherical or parabolic surface. It can be changed to a shape such as a surface, a cylindrical surface, or the like.
  • the actuators 612 indicated by the dotted line N in FIG. 22 may be grouped and the drive amount may be controlled so that the drive amount increases as the actuators approach the periphery.
  • the wafer W can be curved by changing its shape following a spherical surface, a parabolic surface, or the like, similar to the case where the wafer W is held by the curved wafer holder WH. Therefore, in the substrate correcting apparatus 601, the surface of the wafer W is enlarged in the planar direction at the upper surface of the wafer W in the drawing as compared with the central portion B in the thickness direction of the wafer W indicated by the dashed line in FIG. change shape to
  • the shape of the lower surface of the wafer W in the drawing is changed so that the surface of the wafer W is reduced in the planar direction.
  • the shape of the wafer W can be changed and curved in a non-linear shape including a plurality of uneven portions in addition to other shapes such as a cylindrical surface.
  • the nonlinear component of the distortion of the wafer W can be corrected by individually controlling the driving amount of the actuator 612 of the substrate correction device 601 .
  • the step of correcting the nonlinear component of the distortion of the wafer W in step S31 of FIG. 20 is completed. Wafers W corrected for the nonlinear component of distortion are then stacked (S18).
  • the wafer W is initialized by measuring the first number of alignment marks 218 of the wafer W before the wafer W is loaded into the stacking apparatus 200 . Measure strain. Then, based on the information on the initial distortion of the wafer W and the information on the distortion during lamination, the correction amount for the distortion of the wafer W or the positional deviation caused by the distortion between the wafers W is calculated. The positional deviation between the wafers W caused by is corrected.
  • the stacking apparatus 200 does not need to measure the distortion of the wafer W, and the stacking apparatus 200 only needs to measure the second number of alignment marks 218, which is smaller than the first number, in order to align the wafer W. , the number of alignment marks 218 of the wafer W to be measured in the stacking apparatus 200 can be reduced.
  • the linear component of the distortion of the wafer W is corrected using the wafer holder WH, and the nonlinear component of the distortion of the wafer W is corrected by controlling the actuator 612.
  • the distortion of the wafer W is not limited to this. Both linear and nonlinear components may be corrected using the wafer holder WH.
  • the actuator 612 of the substrate correction device 601 may be used to supplementally correct the distortion of the nonlinear component of the wafer W that cannot be corrected by the wafer holder WH.
  • the distortion of the linear component of wafer W may be additionally corrected using actuator 612 of substrate correction device 601 .
  • Actuator 612 and wafer holder WH each serve as a correcting section for correcting positional deviation between wafers W, and are also a deforming section for deforming wafer W. As shown in FIG.
  • the distortion during lamination of the wafer W was measured by observing the alignment marks 218 of the wafer W of the laminate 230 actually laminated with the microscopes 324 and 334. Based on the information on the initial strain of the wafer obtained, the strain during stacking of the wafer W may be estimated by simulation. This makes it possible to omit the process of actually measuring the distortion of the wafer W during stacking. Further, in the distortion correction at the time of initial bonding of the wafer W (bonding for measuring the distortion at the time of stacking), the accumulated past data may be referred to for correction.
  • the measuring device 100 measures the first number of alignment marks 218 .
  • the alignment marks 218 on the wafer W only the alignment marks 218 within the range where the distortion of the nonlinear component occurs may be measured.
  • the range in which the distortion of the nonlinear component occurs on the wafer W may be calculated in advance and machine-learned.
  • only the alignment marks 218 at locations on the wafer W where the reproducibility of nonlinear distortion is poor locations on the wafer W that need to be checked each time) may be measured.
  • the alignment mark 218 to be measured may be selected according to the correction capability of the substrate correction device 601 (for example, a shape that can be corrected by an actuator type).
  • Alignment marks 218 to be measured may be determined according to the number and positions of actuators 612 and suction portions 613 of substrate correction device 601 . In this case, the center and surroundings of the actuator 612 and the adsorption portion 613, the range affected by the driving of the actuator 612, and the like may be taken into consideration for determination. Furthermore, the number of alignment marks 218 to be measured may be evenly thinned out on the wafer.
  • the correction amount for the distortion of the wafer W is calculated based on the information on the initial distortion of the wafer W and the information on the distortion during stacking.
  • the correction amount for the distortion of the wafer W may be calculated by Further, the amount of correction for the distortion of the wafer W is calculated by using the expected fluctuation amount of the distortion during lamination (predicting the fluctuation amount of the distortion during lamination from the wafer W manufacturing information in advance and the amount of warpage of the wafer W). may be calculated.
  • the distortion component to be corrected may be an orthogonal component (linear component) other than the magnification nonlinear component.
  • the stacking control unit 150 may consider the shape of the wafer holder WH selected in step S31 of FIG. 20 when calculating the amount of movement of the moving stage 332.
  • the order of driving the substrate correction device 601, loading the wafer holder WH into the stacking device 200, loading the wafer W into the stacking device 200, and suction-holding by the substrate correction device 601 may be performed in various orders.
  • the following order may be performed. 1.
  • the wafer holder WH is sucked and held on the substrate correction device 601 while the suction surface of the substrate correction device 601 is flat.
  • the wafer holder WH is deformed by the frictional force between the attraction surface of the wafer holder WH and the wafer holder WH. It may be transformed by imitating it. 2.
  • the substrate correction device 601 is driven in advance to create the shape of the suction surface, and the wafer holder WH is carried into the stacking device 200 and held by suction so that the wafer holder WH is deformed following the shape of the suction surface. is carried in and sucked by the wafer holder WH, the wafer W may be deformed following the shape of the wafer holder WH. 3.
  • the substrate correction device 601 is driven in advance to create the shape of the attraction surface
  • the wafer W attracted by the wafer holder WH is carried into the stacking device 200 at the same time, and the substrate correction device 601 attracts and holds the wafer holder WH. Both W and wafer holder WH may be deformed following the shape of the attraction surface. 4.
  • the wafer W sucked by the wafer holder WH is loaded into the stacking device 200, the wafer holder WH is sucked and held by the substrate correction device 601, and then the substrate correction device 601 is driven.
  • the wafer W and the wafer holder WH may be deformed by the frictional force between the attraction surface of the substrate correction device 601 and the wafer holder WH, and the shapes of the wafer holder WH and the wafer W may be corrected.
  • the wafer W may be released from the wafer holder WH, and the wafer W may be once again adsorbed to the wafer holder WH.
  • the above 2. and 3. When the wafer W is carried into the stacking apparatus 200 in a state where the attraction surface of the substrate correction apparatus 601 has been shaped as described above, the information on the nonlinear component of the distortion of the wafer W measured by the measuring apparatus 100 and the information in the stacking apparatus 200 EGA calculation may be performed based on the positional information of the plurality of alignment marks 218 of the wafer W measured in .
  • a distortion correction amount for the wafer W of the first set is calculated.
  • the non-linear component of the strain during stacking of the wafer W is estimated, and using both, the strain of the first set of wafers W is estimated. A distortion correction amount is calculated.
  • FIG. 24 is a flow chart showing a method for manufacturing a stacked semiconductor device.
  • This manufacturing method has steps S100, S102, S104, S106, and S108.
  • the semiconductor device is, for example, an electronic component such as an imaging device such as a backside illuminated imaging device or a memory such as a flash memory.
  • a semiconductor device is, for example, a chip part obtained by dicing a laminate in which a pixel substrate on which pixels are arranged and a processing substrate on which processing circuits such as an amplifier circuit, an image processing circuit, and a control circuit are arranged are laminated. (electronic parts).
  • the stacked semiconductor device is not limited to the back-illuminated imaging device, and may be, for example, an arithmetic processing device obtained by stacking and dicing a memory substrate and a logic substrate.
  • the semiconductor exposure apparatus is used to project the circuit pattern on the mask onto a wafer coated with a resist in a reduced scale. After the resist is developed, etching and thermal diffusion of impurities are performed. A wafer W on which circuit elements are formed is obtained.
  • the correction described with reference to FIGS. 3 to 23 is performed. For example, steps S01 to S04 in FIG. 3, steps S21 to S25 in FIG. 17, and steps S31 to S32 in FIG. 20 are performed.
  • S104 This is an alignment process for aligning the wafers W to be superimposed on each other. In this step, the alignment described with reference to FIGS. 3 to 23 is performed. For example, steps S05 in FIG. 3 and steps S15 to S17 in FIG. 20 are performed.
  • S106 This is a stacking step of stacking the aligned wafers W.
  • the lamination described with reference to FIGS. 3 to 23 is performed to obtain the laminated body 230 .
  • S05 in FIG. 3 and S18 in FIG. 20 are performed.
  • the laminate 230 is transported from the lamination apparatus 200 to an electrode joining section (not shown) by a robot arm.
  • step S108 This is an electrode bonding step for bonding the connection terminals on the wafers that are superimposed on each other.
  • the laminated body 230 that has been aligned and laminated is carried into an annealing furnace and heat-treated. By applying predetermined heat for a predetermined time, the connection terminals (metal bumps and pads, metal bumps and metal bumps) on the wafer W are bonded.
  • steps S106 and S108 may be collectively called a bonding step. Also, if sufficient bonding strength and electrical connection are obtained in step S106, step S108 may be omitted.
  • the above correction step (S012), alignment step (S104), stacking step (S106), and electrode bonding step (S108) are repeated the same number of times as the number of wafers W to be stacked (predetermined number of wafers described above).
  • a step of thinning the laminate 230 by grinding, polishing, or etching is added. As a result, a laminate 230 formed by laminating a predetermined number of wafers is obtained.
  • the wafer W laminated and bonded at the wafer level is cut along the scribe lines 212 to cut out chips for each circuit region 216 .
  • a dicing saw method for cutting using a dicing blade, a method for breaking the wafer surface by melting it with a laser beam, and a method for breaking by drawing a cutting line with a diamond cutter are adopted.
  • the dicing saw method is particularly preferable as a method for separating the laminate 230 into chips. Each chip thus cut out is a stacked semiconductor device.
  • the measuring apparatus 100 may have a reference coordinate system, and the absolute coordinates of the alignment marks 218 of the wafer W may be measured in the reference coordinate system. Measuring apparatus 100 may detect the absolute coordinates of other marks on wafer W in addition to alignment mark 218 .
  • the measuring apparatus 100 may measure the absolute coordinates of the alignment mark 218 of at least one of the wafers W constituting the laminate to calculate the position information.
  • the measurement apparatus 100 may send the calculated position information of the alignment mark 218 to an exposure apparatus that exposes a pattern on at least one wafer W of the stack, and the exposure apparatus performs exposure processing based on the received position information.
  • Information on the measurement results of the laminate measured by the measurement apparatus 100 may be sent from the measurement apparatus 100 to an exposure apparatus that exposes a pattern on at least one of a plurality of other wafers W to be bonded later.
  • the wafer W may be subjected to exposure processing based on the obtained information.
  • the measurement apparatus 100 The information to be sent from to the exposure apparatus is not limited to the positional information of the alignment mark 218, but also includes positional deviation information of the mark from the design value, positional deviation information between a plurality of stacked wafers W, and stacked wafers W.
  • Information on at least one distortion, warp, or the like of the plurality of wafers W may be included.
  • 60 measurement control unit 100 measurement device, 101 measurement unit, 102 wafer slider, 103 drive system, 104 measurement control unit, 110 housing, 120, 130 wafer cassette, 140 transfer unit, 150 control unit, 200 stacking device, 212 scribe Line, 214 Notch, 216 Circuit area, 218 Alignment mark, 225 Holding surface, 230 Laminated body, 300 Laminated part, 301 Floor surface, 310 Frame body, 312 Bottom plate, 314 Column, 316 Top plate, 322 Fixed stage, 324, 334 microscope, 331 X-direction drive unit, 332 movement stage, 333 Y-direction drive unit, 335 Z-direction drive unit, 400 holder stocker, 500 pre-aligner, 600 activation device, 601 correction device, 611 base, 612 actuator, 613 adsorption unit, 614 column, 615 pump, 616 valve, 1000 substrate processing system, W wafer, WH wafer holder

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PCT/JP2023/003482 2022-02-10 2023-02-02 基板補正装置、基板積層装置、基板処理システム、基板補正方法、基板処理方法、および半導体装置の製造方法 Ceased WO2023153317A1 (ja)

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CN202380021229.0A CN118679551A (zh) 2022-02-10 2023-02-02 基板修正装置、基板层叠装置、基板处理系统、基板修正方法、基板处理方法以及半导体装置的制造方法
JP2023580213A JP7786482B2 (ja) 2022-02-10 2023-02-02 基板補正装置、基板積層装置、基板処理システム、基板補正方法、基板処理方法、および半導体装置の製造方法
US18/799,299 US20240404859A1 (en) 2022-02-10 2024-08-09 Substrate correction device, substrate lamination device, substrate processing system, substrate correction method, substrate processing method, and semiconductor device manufacturing method
JP2025226639A JP2026035803A (ja) 2022-02-10 2025-12-03 基板補正装置、基板積層装置、基板処理システム、基板補正方法、基板処理方法、および半導体装置の製造方法

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WO2017217431A1 (ja) * 2016-06-16 2017-12-21 株式会社ニコン 積層装置および積層方法
WO2018012300A1 (ja) * 2016-07-12 2018-01-18 株式会社ニコン 積層基板製造方法、積層基板製造装置、積層基板製造システム、および基板処理装置
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WO2017217431A1 (ja) * 2016-06-16 2017-12-21 株式会社ニコン 積層装置および積層方法
WO2018012300A1 (ja) * 2016-07-12 2018-01-18 株式会社ニコン 積層基板製造方法、積層基板製造装置、積層基板製造システム、および基板処理装置
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