WO2023153108A1 - 固体撮像装置 - Google Patents

固体撮像装置 Download PDF

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Publication number
WO2023153108A1
WO2023153108A1 PCT/JP2022/048317 JP2022048317W WO2023153108A1 WO 2023153108 A1 WO2023153108 A1 WO 2023153108A1 JP 2022048317 W JP2022048317 W JP 2022048317W WO 2023153108 A1 WO2023153108 A1 WO 2023153108A1
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WIPO (PCT)
Prior art keywords
pixel
transistor
solid
imaging device
state imaging
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
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PCT/JP2022/048317
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English (en)
French (fr)
Japanese (ja)
Inventor
良昭 北野
秀俊 大石
直広 高橋
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Sony Semiconductor Solutions Corp
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Sony Semiconductor Solutions Corp
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Application filed by Sony Semiconductor Solutions Corp filed Critical Sony Semiconductor Solutions Corp
Priority to KR1020247028548A priority Critical patent/KR20240148850A/ko
Priority to EP22926122.7A priority patent/EP4481824A4/en
Priority to US18/835,910 priority patent/US20250151430A1/en
Priority to CN202280091196.2A priority patent/CN118715616A/zh
Priority to JP2023580111A priority patent/JPWO2023153108A1/ja
Publication of WO2023153108A1 publication Critical patent/WO2023153108A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/803—Pixels having integrated switching, control, storage or amplification elements
    • H10F39/8037—Pixels having integrated switching, control, storage or amplification elements the integrated elements comprising a transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/803—Pixels having integrated switching, control, storage or amplification elements
    • H10F39/8037—Pixels having integrated switching, control, storage or amplification elements the integrated elements comprising a transistor
    • H10F39/80373—Pixels having integrated switching, control, storage or amplification elements the integrated elements comprising a transistor characterised by the gate of the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/12—Image sensors
    • H10F39/199—Back-illuminated image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/011—Manufacture or treatment of image sensors covered by group H10F39/12
    • H10F39/014—Manufacture or treatment of image sensors covered by group H10F39/12 of CMOS image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/802—Geometry or disposition of elements in pixels, e.g. address-lines or gate electrodes
    • H10F39/8023—Disposition of the elements in pixels, e.g. smaller elements in the centre of the imager compared to larger elements at the periphery
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/802—Geometry or disposition of elements in pixels, e.g. address-lines or gate electrodes
    • H10F39/8027—Geometry of the photosensitive area
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/807—Pixel isolation structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/813—Electronic components shared by multiple pixels, e.g. one amplifier shared by two pixels

Definitions

  • the present disclosure relates to a solid-state imaging device.
  • Patent Document 1 discloses a solid-state imaging device.
  • one pixel is formed in a region surrounded by inter-pixel light shielding walls.
  • a photodiode is formed on the back side of the semiconductor substrate, and a pixel circuit is formed on the front side of the semiconductor substrate.
  • a pixel circuit is composed of an amplification transistor, a selection transistor, a floating diffusion conversion gain switching transistor, and a reset transistor.
  • a solid-state imaging device at a position corresponding to one pixel, the area of an element isolation section that isolates a plurality of transistors forming a pixel circuit, a floating diffusion region, a transfer transistor, and a well contact is large. For this reason, it becomes difficult to secure an area for arranging a transistor as pixels are miniaturized. Therefore, in a solid-state imaging device, it is desired to increase the area for arranging transistors and improve the performance of the transistors.
  • a solid-state imaging device includes first pixels disposed on a first surface side of a substrate, which is a light incident side, and having a first photoelectric conversion element that converts light into electric charge; formed in the thickness direction and extending in the first direction and in the second direction intersecting the first direction when viewed from the side of the second surface opposite to the first surface of the substrate to form the side periphery of the first pixel; and electrically and optically isolate the first pixels from other regions; and the gate length direction of the first transistor is oblique to the first direction or the second direction, and the gate width direction of the first transistor on the second surface side of the substrate at the position corresponding to the first pixel and a first transfer gate electrode of a first transfer transistor for transferring charges from the first pixel to the first floating diffusion region, or a first substrate connection portion for supplying a voltage to the substrate. ing.
  • a solid-state imaging device includes a first pixel disposed on a first surface side of a substrate, which is a light incident side, and having a first photoelectric conversion element that converts light into electric charge; formed in the thickness direction and extending in the first direction and in the second direction intersecting the first direction when viewed from the side of the second surface opposite to the first surface of the substrate to form the side periphery of the first pixel; and electrically and optically isolate the first pixels from other regions; a first transistor having a gate length direction slanted with respect to the first direction or the second direction; a second transistor disposed on the side of the substrate, the gate length direction of which is slanted with respect to the first direction or the second direction, and electrically connected in series with the first transistor; a first floating diffusion region disposed in the gate width direction of the first transistor and the second transistor on the second surface side of the second surface of the first transfer transistor for transferring charges from the first pixel to the first floating diffusion region; and a first substrate
  • a solid-state imaging device includes pixels arranged on a first surface side, which is a light incident side of a substrate, having a photoelectric conversion element that converts light into an electric charge, and a plurality of arranged pixels; A pixel isolation region formed in the thickness direction of a substrate, surrounding the side surfaces of a plurality of pixels, and electrically and optically isolating the plurality of pixels, and a pixel isolation region having a periphery at a position corresponding to the pixel.
  • Transistors arranged on the second surface side of the surrounded substrate, the gate length direction of which is slanted with respect to the arrangement direction of the pixels, and the gate width direction of the transistors on the second surface side of the substrate at positions corresponding to the pixels. and a transfer gate electrode of a transfer transistor that transfers charges from a pixel to the floating diffusion region, or a first substrate connection portion that supplies a voltage to the substrate.
  • a solid-state imaging device includes a first pixel provided on a first surface side, which is a light incident side, of a substrate and having a first photoelectric conversion element that converts light into electric charge; a second pixel adjacent to the pixel, arranged on the first surface side of the substrate and having a second photoelectric conversion element for converting light into electric charge; and a pixel separation region formed in the thickness direction of the substrate for electrically and optically separating the first pixel and the second pixel from each other; provided on the second surface side of the substrate at a position corresponding to the first transistor whose gate length direction is oblique to the arrangement direction of the first and second pixels, and the second pixel; A second transistor having a gate length direction oblique to the arrangement direction of the pixels and the second pixel, and electrically direct to one of the pair of main electrodes of the first transistor and one of the pair of main electrodes of the second transistor. and a shared connection for supplying the power supply voltage.
  • FIG. 1 is a circuit diagram showing pixels and pixel circuits of a solid-state imaging device according to a first embodiment of the present disclosure
  • FIG. 2 is a plan configuration diagram illustrating the basic configuration of a transistor that constructs the pixel circuit shown in FIG. 1.
  • FIG. 2 is a specific plan view of the pixel circuit shown in FIG. 1
  • FIG. 3 is a vertical cross-sectional view (a cross-sectional view taken along the line AA shown in FIG. 3) of part of the pixel and pixel circuit shown in FIG. 1
  • FIG. 4 is a specific plan configuration diagram for explaining a wiring connection state in the pixel circuit shown in FIG. 3
  • FIG. 5 is a cross-sectional view of the first process corresponding to FIG.
  • FIG. 15 is a specific planar configuration diagram corresponding to FIG. 3 of the pixel circuit shown in FIG. 14;
  • FIG. FIG. 11 is a specific planar configuration diagram corresponding to FIG. 3 of a portion of the pixel circuit of the solid-state imaging device according to the fourth embodiment of the present disclosure;
  • FIG. 17 is a vertical cross-sectional configuration diagram of part of the pixel circuit shown in FIG. 16 (a cross-sectional view cut along the CC cutting line shown in FIG. 16);
  • FIG. 17 is a vertical cross-sectional configuration diagram of part of the pixel circuit shown in FIG. 16 (a cross-sectional view cut along the DD cutting line shown in FIG. 16);
  • FIG. 15 is a specific planar configuration diagram corresponding to FIG. 3 of the pixel circuit shown in FIG. 14;
  • FIG. FIG. 11 is a specific planar configuration diagram corresponding to FIG. 3 of a portion of the pixel circuit of the solid-state imaging device according to the fourth embodiment of the present disclosure;
  • FIG. 17 is a
  • FIG. 17 is a specific planar configuration diagram corresponding to FIG. 16 of part of the pixel circuit of the solid-state imaging device according to the first modification of the fourth embodiment;
  • FIG. 20 is a vertical cross-sectional configuration diagram of part of the pixel circuit shown in FIG. 19 (a cross-sectional view cut along the EE cutting line shown in FIG. 19);
  • FIG. 20 is a vertical cross-sectional configuration diagram of part of the pixel circuit shown in FIG. 19 (a cross-sectional view cut along the FF cutting line shown in FIG. 19);
  • FIG. 17 is a specific planar configuration diagram corresponding to FIG. 16 of part of the pixel circuit of the solid-state imaging device according to the second modification of the fourth embodiment;
  • FIG. 20 is a vertical cross-sectional configuration diagram of part of the pixel circuit shown in FIG. 19 (a cross-sectional view cut along the EE cutting line shown in FIG. 19);
  • FIG. 20 is a vertical cross-sectional configuration diagram of part of the pixel circuit shown in FIG. 19 (a
  • FIG. 23 is a vertical cross-sectional configuration diagram of part of the pixel circuit shown in FIG. 22 (a cross-sectional view cut along the GG cutting line shown in FIG. 22);
  • FIG. 23 is a vertical cross-sectional view of part of the pixel circuit shown in FIG. 22 (a cross-sectional view taken along the line HH shown in FIG. 22);
  • FIG. 12 is a specific planar configuration diagram corresponding to FIG. 3 of a portion of the pixel circuit of the solid-state imaging device according to the fifth embodiment of the present disclosure;
  • FIG. 26 is a vertical cross-sectional configuration diagram of part of the pixel circuit shown in FIG. 25 (a cross-sectional view cut along the II cutting line shown in FIG. 25);
  • FIG. 10 is a specific planar configuration diagram corresponding to FIG.
  • FIG. 11 is a specific planar configuration diagram corresponding to FIG. 5 , explaining a pixel circuit and a wiring connection state of a solid-state imaging device according to a seventh embodiment of the present disclosure
  • FIG. 20 is a specific planar configuration diagram corresponding to FIG. 3 of the pixel circuit of the solid-state imaging device according to the eighth embodiment of the present disclosure
  • FIG. 30 is a vertical cross-sectional view of part of the pixel and pixel circuit shown in FIG. 29 (a cross-sectional view cut along the JJ cutting line shown in FIG. 29);
  • FIG. 30 is a specific plan configuration diagram corresponding to FIG.
  • FIG. 20 is a specific planar configuration diagram corresponding to FIG. 3 of the pixel circuit of the solid-state imaging device according to the ninth embodiment of the present disclosure
  • FIG. 33 is a vertical cross-sectional configuration diagram of a part of the pixel and pixel circuit shown in FIG. 32 (a cross-sectional view cut along the KK cutting line shown in FIG. 32)
  • FIG. 34 is a plan configuration diagram corresponding to FIG. 33 for explaining an arrangement layout of pixels and pixel circuits of a solid-state imaging device according to a first modified example of the tenth embodiment
  • FIG. 34 is a plan configuration diagram corresponding to FIG.
  • FIG. 34 is a plan configuration diagram corresponding to FIG. 33 for explaining an arrangement layout of pixels and pixel circuits of a solid-state imaging device according to a second modified example of the tenth embodiment
  • FIG. 34 is a plan configuration diagram corresponding to FIG. 33 for explaining an arrangement layout of pixels and pixel circuits of a solid-state imaging device according to a third modified example of the tenth embodiment
  • FIG. 34 is a plan configuration diagram corresponding to FIG. 33 for explaining an arrangement layout of pixels and pixel circuits of a solid-state imaging device according to a fourth modified example of the tenth embodiment
  • FIG. 12 is a vertical cross-sectional configuration diagram corresponding to FIG. 4 of part of a pixel and a pixel circuit according to an eleventh embodiment of the present disclosure
  • FIG. 22 is a circuit diagram showing pixels and pixel circuits of a solid-state imaging device according to a twelfth embodiment of the present disclosure
  • 40 is a specific planar configuration diagram of the pixel circuit shown in FIG. 39.
  • FIG. FIG. 41 is a vertical cross-sectional configuration diagram of part of the pixel and pixel circuit shown in FIG. 40 (a cross-sectional view cut along the LL cutting line shown in FIG. 40);
  • FIG. 42 is a first process cross-sectional view schematically showing FIG. 41 for explaining the method of manufacturing the solid-state imaging device according to the twelfth embodiment; It is a 2nd process sectional drawing. It is a 3rd process sectional drawing. It is a 4th process sectional drawing. It is a 5th process sectional drawing.
  • FIG. 43 is a vertical cross-sectional configuration diagram corresponding to FIG. 42 of part of the pixels and pixel circuits of the solid-state imaging device according to the thirteenth embodiment of the present disclosure;
  • FIG. 43 is a cross-sectional view of the first step corresponding to FIG. 42 for explaining the manufacturing method of the solid-state imaging device according to the thirteenth embodiment;
  • It is a 2nd process sectional drawing.
  • 41 is a specific planar configuration diagram corresponding to FIG. 40 of the pixel circuit of the solid-state imaging device according to the fourteenth embodiment of the present disclosure;
  • FIG. 41 is a specific planar configuration diagram corresponding to FIG.
  • FIG. 41 is a specific planar configuration diagram corresponding to FIG. 40 of the pixel circuit of the solid-state imaging device according to the sixteenth embodiment of the present disclosure
  • FIG. 41 is a plan configuration diagram showing a basic arrangement configuration corresponding to FIG. 40 of the pixel circuits of the solid-state imaging device according to the seventeenth embodiment of the present disclosure
  • FIG. 56 is a plan configuration diagram showing a specific arrangement configuration corresponding to FIG. 55 of the pixel circuits of the solid-state imaging device according to the seventeenth embodiment
  • FIG. 56 is a plan configuration diagram showing a specific arrangement configuration corresponding to FIG.
  • FIG. 20 is a plan configuration diagram showing a specific arrangement configuration of pixels, color filters, and optical lenses of a solid-state imaging device according to an eighteenth embodiment of the present disclosure
  • FIG. 20 is a plan configuration diagram showing pixels, pixel circuits, and wiring connection states of a solid-state imaging device according to an eighteenth embodiment
  • FIG. 20 is a plan configuration diagram showing pixels in which color filters of a specific color are arranged, pixel circuits, and wiring connection states in a solid-state imaging device according to an eighteenth embodiment
  • 1 is a block diagram showing an example of a schematic configuration of a vehicle control system, which is a first application example according to an embodiment of the present disclosure
  • FIG. FIG. 4 is an explanatory diagram showing an example of installation positions of an outside information detection unit and an imaging unit;
  • First Embodiment A first embodiment describes an example in which the present technology is applied to a solid-state imaging device.
  • 1st Embodiment demonstrates in detail the circuit structure of the pixel of a solid-state imaging device, a pixel circuit, a plane structure, a longitudinal cross-sectional structure, and the manufacturing method of a solid-state imaging device.
  • Second Embodiment A second embodiment describes a first example in which the structure of the transistor of the pixel circuit is changed in the solid-state imaging device according to the first embodiment. 3.
  • Third Embodiment A third embodiment will explain a second example in which the configuration of the transistor of the pixel circuit is changed in the solid-state imaging device according to the first embodiment. 4.
  • Fourth Embodiment A fourth embodiment describes an example in which the configuration of the gate electrode of the transfer transistor of the pixel is changed in any one of the solid-state imaging devices according to the first to third embodiments. The fourth embodiment further describes some modifications. 5.
  • Fifth Embodiment A fifth embodiment describes a first example in which the planar layout configuration of the transistors of the pixel circuit is changed in any one of the solid-state imaging devices according to the first to fourth embodiments. . 6.
  • Sixth Embodiment A sixth embodiment describes a second example in which the planar layout configuration of the transistors of the pixel circuit is changed in any one of the solid-state imaging devices according to the first to fourth embodiments. . 7. Seventh Embodiment A seventh embodiment describes a third example in which the planar layout configuration of the transistors of the pixel circuit is changed in any one of the solid-state imaging devices according to the first to fourth embodiments. . 8. Eighth Embodiment In the eighth embodiment, in any one of the solid-state imaging devices according to the first to seventh embodiments, an example will be described in which the configuration of the shared connection portion of the pixel circuit is changed. 9.
  • Ninth Embodiment A ninth embodiment describes an example in which the connection configuration of the wiring of the pixel circuit is changed in any one of the solid-state imaging devices according to the first to seventh embodiments. 10.
  • Tenth Embodiment A tenth embodiment will explain a fourth example in which the planar layout configuration of the transistors of the pixel circuit is changed in the solid-state imaging device according to the fifth embodiment. The tenth embodiment further describes some modifications.
  • Eleventh Embodiment An eleventh embodiment describes an example in which the configuration of the element isolation region of the pixel circuit is changed in any one of the solid-state imaging devices according to the first to tenth embodiments. 12.
  • Twelfth Embodiment A twelfth embodiment describes an example in which the power supply voltage supply configuration is changed in any one of the solid-state imaging devices according to the first to eleventh embodiments.
  • the twelfth embodiment will describe in detail the circuit configuration, planar configuration, vertical cross-sectional configuration of pixels and pixel circuits of a solid-state imaging device, and a method for manufacturing a solid-state imaging device.
  • Thirteenth Embodiment A thirteenth embodiment will explain an example in which the configuration of the shared connection portion of the pixel circuit is changed in the solid-state imaging device according to the twelfth embodiment.
  • the thirteenth embodiment also describes a method for manufacturing a solid-state imaging device. 14.
  • 14th Embodiment A 14th embodiment describes a first example in which the arrangement layout configuration of the shared connection portion of the pixel circuit is changed in the solid-state imaging device according to the 12th or 13th embodiment.
  • 15 Fifteenth Embodiment A fifteenth embodiment describes a second example in which the arrangement layout configuration of the shared connection portion of the pixel circuit is changed in the solid-state imaging device according to the twelfth or thirteenth embodiment.
  • 16. 16th Embodiment A 16th embodiment will explain a third example in which the arrangement layout configuration of the shared connection portion of the pixel circuit is changed in the solid-state imaging device according to the 12th or 13th embodiment. 17.
  • the 17th embodiment describes a fourth example in which the arrangement layout configuration of the shared connection portion of the pixel circuit is changed in the solid-state imaging device according to the 12th or 13th embodiment.
  • the seventeenth embodiment also describes a modification.
  • Eighteenth Embodiment An eighteenth embodiment describes an application example of the solid-state imaging device according to the twelfth embodiment or the thirteenth embodiment. In the eighteenth embodiment, a planar layout configuration of pixels and pixel circuits, a planar layout configuration of color filters, and a planar layout configuration of optical lenses will be described. 19.
  • Example of Application to Moving Body An example in which the present technology is applied to a vehicle control system, which is an example of a moving body control system, will be described. 20. Other embodiments
  • FIG. 1 A solid-state imaging device 1 according to a first embodiment of the present disclosure will be described with reference to FIGS. 1 to 11.
  • FIG. 1 A solid-state imaging device 1 according to a first embodiment of the present disclosure will be described with reference to FIGS. 1 to 11.
  • FIG. 1 A solid-state imaging device 1 according to a first embodiment of the present disclosure will be described with reference to FIGS. 1 to 11.
  • FIG. 1 A solid-state imaging device 1 according to a first embodiment of the present disclosure will be described with reference to FIGS. 1 to 11.
  • the arrow X direction shown as appropriate indicates one plane direction of the solid-state imaging device 1 placed on a plane for convenience.
  • the arrow Y direction indicates another planar direction perpendicular to the arrow X direction.
  • the arrow Z direction indicates an upward direction orthogonal to the arrow X direction and the arrow Y direction. That is, the arrow X direction, the arrow Y direction, and the arrow Z direction exactly match the X-axis direction, the Y-axis direction, and the Z-axis direction of the three-dimensional coordinate system, respectively. It should be noted that each of these directions is shown to aid understanding of the description and is not intended to limit the direction of the present technology.
  • FIG. 1 shows an example of the circuit configuration of the pixel 10 and the pixel circuit 20 that construct the solid-state imaging device 1 according to the first embodiment. .
  • One pixel 10 is composed of a series circuit of a photoelectric conversion element (photodiode) 11 and a transfer transistor 12 .
  • the photoelectric conversion element 11 converts light incident from the outside of the solid-state imaging device 1 into electric charge (electrical signal).
  • the transfer transistor 12 has a transfer gate electrode and a pair of main electrodes. One of the pair of main electrodes is connected to the photoelectric conversion element 11 .
  • the other main electrode is connected to the pixel circuit 20 through a floating diffusion region (hereinafter simply referred to as “FD region”) 25 .
  • the transfer gate electrodes are connected to horizontal signal lines (not shown).
  • a control signal TG is input to the transfer gate electrode from the horizontal signal line.
  • the pixel circuit 20 is arranged here for each unit pixel. That is, one pixel circuit 20 is arranged for four pixels 10 .
  • the pixel circuit 20 performs signal processing on charges converted from light in the pixel 10 .
  • the pixel circuit 20 is constructed with four transistors, first to fourth transistors.
  • the first transistor is an amplification transistor 21 having a gate electrode and a pair of main electrodes.
  • the second transistor is a selection transistor 22 having a gate electrode and a pair of main electrodes.
  • the third transistor is a floating diffusion conversion gain switching transistor (hereinafter simply referred to as "FD conversion gain switching transistor") 23 having a gate electrode and a pair of main electrodes.
  • a fourth transistor is a reset transistor 24 having a gate electrode and a pair of main electrodes.
  • a gate electrode of the amplification transistor 21 is connected to the FD region 25 .
  • One main electrode of the amplification transistor 21 is connected to the power supply voltage terminal VDD, and the other main electrode is connected to one main electrode of the selection transistor 22 .
  • the power supply voltage is, for example, 2.8 [V].
  • the power supply voltage may be, for example, 2.2 [V].
  • a gate electrode of the select transistor 22 is connected to a select signal line SEL.
  • the other main electrode of the select transistor 22 is connected to the vertical signal line VSL and current source load LC.
  • a current source load LC is connected to the reference voltage terminal GND.
  • a gate electrode of the FD conversion gain switching transistor 23 is connected to the floating diffusion control signal line FDG.
  • One main electrode of the FD conversion gain switching transistor 23 is connected to the FD region 25 and the other main electrode is connected to one main electrode of the reset transistor 24 .
  • a gate electrode of the reset transistor 24 is connected to the reset signal line RST.
  • the other main electrode of the reset transistor 24 is connected to the power supply voltage terminal VDD.
  • the pixel circuit 20 is further connected to an image processing circuit (not shown).
  • the image processing circuit includes, for example, an analog-to-digital converter (ADC) and a digital signal processor (DSP).
  • ADC analog-to-digital converter
  • DSP digital signal processor
  • the charge converted from light by pixel 10 is an analog signal. This analog signal is amplified in the pixel circuit 20 .
  • the ADC converts an analog signal output from the pixel circuit 20 into a digital signal.
  • DSPs perform functional processing of digital signals. That is, the image processing circuit performs signal processing for image creation.
  • FIG. 1 (2) Basic Layout Configuration of Transistor 200 Constructing Pixel 10 and Pixel Circuit 20
  • the transistors 200 forming one pixel 10 and pixel circuit 20 are arranged in a region surrounded by the pixel isolation region 16. ing.
  • the side opposite to the arrow Z direction is configured as a light incident surface.
  • Photoelectric conversion elements 11 forming pixels 10 are arranged on the light incident surface side.
  • the pixel isolation regions 16 extend in the arrow X direction with a constant width dimension, and are arranged in plurality in the arrow Y direction with a constant spacing dimension. Furthermore, the pixel isolation regions 16 are similarly extended in the arrow Y direction with a constant width dimension, and are arranged in plurality in the arrow X direction with a constant spacing dimension. In other words, the pixel isolation region 16 is arranged in a lattice shape in plan view, and the pixels 10 and the transistors 200 are arranged in the regions partitioned by the pixel isolation region 16 .
  • the pixels 10 and the transistors 200 are arranged in a square area partitioned by the pixel separation area 16 in plan view.
  • one pixel 10 is arranged in one region partitioned by the pixel isolation region 16 .
  • One transistor 200 constituting the pixel circuit 20 is arranged in one region partitioned by the pixel isolation region 16 . Note that vertical cross-sectional structures of the pixel isolation region 16 and the transistor 200 will be described later.
  • the transistor 200 is a first transistor, a second transistor, a third transistor or a fourth transistor. That is, the transistor 200 is any one of the amplification transistor 21 , the selection transistor 22 , the FD conversion gain switching transistor 23 , and the reset transistor 24 .
  • the transistor 200 is surrounded by an element isolation region 26 and electrically and optically isolated from other regions.
  • the transistor 200 includes a channel forming region 201 , a gate insulating film 202 , a gate electrode 203 and a pair of main electrodes 204 .
  • the main electrode 204 is formed of an n-type semiconductor region as the first conductivity type and used as a source electrode or a drain electrode.
  • transistor 200 is an n-channel insulated gate field effect transistor (IGFET).
  • IGFETs include Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) and Metal Insulator Semiconductor Field Effect Transistors (MISFETs). .
  • the transistors 200 are arranged diagonally with respect to the extending direction of the pixel isolation regions 16 in the regions corresponding to the pixels 10 .
  • the transistor 200 has a gate length of 100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
  • the gate width Wg is the length in the direction orthogonal to the direction of the gate length Lg and in the direction corresponding to the diagonal line D2-D2 extending from the lower left side to the upper right side shown as a virtual line.
  • the minimum angle ⁇ 1 between the pixel isolation region 16 extending in the direction of the arrow X and the diagonal line D1-D1 is 45 degrees.
  • the maximum angle will be 135 degrees.
  • the minimum angle ⁇ 2 formed by the pixel isolation region 16 extending in the arrow Y direction and the diagonal line D1-D1 is naturally 45 degrees.
  • the angle ⁇ 1 is set to 45 degrees, the gate length Lg dimension and the gate width Wg dimension of the transistor 200 can be maximized.
  • the angle ⁇ 1 can be appropriately set at an angle of 15 degrees or more and less than 75 degrees.
  • the gate length Lg and the gate width Wg of the transistor 200 can be increased compared to when the transistor 200 is not arranged diagonally.
  • the FD area 25 and the substrate connecting portion 27 are arranged in the area partitioned by the pixel separation area 16 so as to be aligned with the diagonal line D2-D2.
  • the FD area 25 is arranged at the lower left corner where the pixel isolation area 16 extending in the arrow X direction and the pixel isolation area 16 extending in the arrow Y direction intersect.
  • the FD region 25 is made of an n-type semiconductor region.
  • the FD region 25 is arranged with the element isolation region 26 interposed with respect to the transistor 200 .
  • a transfer gate electrode (vertical gate electrode) 205 is arranged at a position spaced apart on the right side of the FD region 25 .
  • the transfer gate electrode 205 is a gate electrode of the transfer transistor 200, and extends on the base 15 with the thickness direction of the base 15 as the gate length Lg direction.
  • the base connecting portion 27 is arranged at the upper right corner where the pixel isolation region 16 extending in the arrow X direction and the pixel isolation region 16 extending in the arrow Y direction intersect.
  • the base connecting portion 27 is formed of a p-type semiconductor region as the second conductivity type.
  • substrate 15 is formed as a p-type well region. That is, the substrate 15 is connected to the reference voltage terminal GND with the substrate connecting portion 27 interposed therebetween.
  • the base connection portion 27 is arranged with the element isolation region 26 interposed with respect to the transistor 200 , similarly to the FD region 25 .
  • the portion indicated by the black circle is the connection region (contact region) with the wiring arranged in the upper layer on the side opposite to the photoelectric conversion element 11 of the transistor 200 .
  • the wiring is, for example, the wiring 7 shown in FIG.
  • wiring for example, copper (Cu) wiring is used.
  • the connection area is, for example, the connection hole 6H shown in FIG.
  • the shared connection section 31 is provided here between the transistor 200 of the pixel 10 and the transistor 200 of another pixel 10 (not shown) adjacent in the arrow Y direction. More specifically, the shared connection 31 has one end electrically directly connected to one main electrode 204 of the transistor 200 and the other end electrically connected across the pixel isolation region 16 to one main electrode of the other transistor 200 . directly connected. In other words, the shared connection portion 31 is connected to the main portion of the transistor 200 across the pixel isolation region 16 without forming the wiring on the transistor 200 and the connection hole formed in the interlayer insulating film between the transistor 200 and the wiring. The electrodes 204 are directly connected.
  • the shared connection portion 32 is provided here between the FD region 25 of the pixel 10 and the FD region 25 of another pixel 10 (not shown) adjacent in the arrow X direction and the arrow Y direction. Specifically, the shared connection portion 32 is formed over a total of four FD regions 25 of the pixels 10 adjacent in the arrow X direction and the arrow Y direction, and is electrically directly connected to the total of four FD regions 25. .
  • the shared connection portion 33 is provided here between the base connection portion 27 of the pixel 10 and the base connection portion 27 of another pixel 10 (not shown) adjacent in the arrow X direction and the arrow Y direction. Similarly to the shared connection portion 32, the shared connection portion 33 is formed over the substrate connection portions 27 of a total of four pixels 10 adjacent in the arrow X direction and the arrow Y direction, and is electrically connected to the substrate connection portions 27 in total. Directly connected.
  • FIG. 3 shows an example of a specific planar configuration of the pixel 10 and pixel circuit 20 .
  • FIG. 4 shows a vertical cross-sectional configuration of part of the pixel 10 and the pixel circuit 20 (a cross section cut along the line AA shown in FIG. 3).
  • FIG. 5 shows an arrangement layout configuration of the unit pixel BP shown in FIG. 3 and the surrounding pixels 10 (or unit pixel BP).
  • one pixel circuit 20 is arranged for four pixels 10 in the first embodiment.
  • the four pixels 10 are two pixels 10A and 10B that are adjacent in the direction of the arrow X, and two pixels that are adjacent in the direction of the arrow X and are adjacent to the pixels 10A and 10B in the direction of the arrow Y.
  • Pixel 10C and pixel 10D are adjacent to the pixels 10A and 10B in the direction of the arrow Y.
  • Pixel 10C and pixel 10D form a unit pixel BP.
  • a selection transistor 22 of the pixel circuit 20 is arranged at a position corresponding to the pixel 10D.
  • the select transistor 22 is arranged in a region partitioned by the pixel isolation region 16 with the gate length Lg direction aligned with the diagonal line D1-D1.
  • the selection transistor 22 is arranged on the main surface portion of the substrate 15 opposite to the light incident side (the second surface as the upper surface of the substrate 15 in FIG. 4).
  • a semiconductor substrate is used as the base 15 .
  • a single crystal silicon substrate having a p-type semiconductor region (or p-type well region) 151 is used.
  • a photoelectric conversion element 11 is arranged on the light incident side of the substrate 15 (the first surface side as the lower surface of the substrate 15 in FIG. 4). The photoelectric conversion element 11 is formed at the pn junction between the p-type semiconductor region 151 and the n-type semiconductor region (not denoted by reference numeral).
  • the pixel isolation region 16 has a first groove 161 and a first embedding member 162 .
  • the first groove 161 is formed as a deep groove penetrating through the substrate 15 from the upper surface to the lower surface in the thickness direction.
  • the first embedding member 162 is embedded in the first groove 161 .
  • the first embedded member 162 is formed of an insulator 162A provided along the inner wall of the first groove 161 and an embedded member 162B embedded in the first groove 161 with the insulator 162A interposed therebetween.
  • a silicon oxide film, a silicon nitride film, or the like, for example, is used for the insulator 162A.
  • a silicon oxide film or a polycrystalline silicon film, for example, is used for the embedded member 162B.
  • the pixel isolation region 16 is configured with a trench isolation structure. Although detailed illustration and description are omitted here, a pinning region is arranged between the photoelectric conversion element 11 inside the base 15 and the pixel separation region 16 in the region corresponding to the photoelectric conversion element 11 .
  • the selection transistor 22 includes a channel formation region 201, a gate insulating film 202, a gate electrode 203, and a pair of main electrodes 204, as described for the transistor 200 described above.
  • a channel forming region 201 is formed by the p-type semiconductor region 151 of the substrate 15 .
  • a gate insulating film 202 is formed on the surface of the channel forming region 201 .
  • a single layer film such as a silicon oxide film, a silicon nitride film, an oxynitride film, or a composite film thereof is used for the gate insulating film 202 .
  • the gate electrode 203 is formed on the surface of the gate insulating film 202 opposite to the channel formation region 201 .
  • the gate electrode 203 is a single layer film of a gate electrode material such as a polycrystalline silicon film, a high melting point metal film, a high melting point metal silicide film which is a compound of polycrystalline silicon and a high melting point metal, or a composite film thereof. It is used.
  • the main electrodes 204 are arranged in pairs on the main surface of the substrate 15 in the direction of the gate length Lg with the gate electrode 203 at the center, and are formed of n-type semiconductor regions.
  • the FD region 25 and the substrate connecting portion 27 are arranged at positions corresponding to the diagonal line D2-D2 and facing each other with the selection transistor 22 as the center. .
  • An element isolation region 26 is formed between the FD region 25 and the select transistor 22 and between the base connecting portion 27 and the select transistor 22, respectively.
  • the FD region 25 is arranged on the main surface portion of the substrate 15 and is formed of an n-type semiconductor region like the main electrode 204 of the select transistor 22 .
  • the base connecting portion 27 is arranged on the main surface portion of the base 15 and is formed of a p-type semiconductor region having a higher impurity density than the p-type semiconductor region 151 of the base 15 .
  • the element isolation region 26 has a second trench 261 and a second embedding member 262 .
  • the second groove 261 is a groove formed in the thickness direction from the upper surface of the base 15 toward the lower surface.
  • the second groove 261 is a groove that does not reach the photoelectric conversion element 11 , and the depth of the second groove 261 is shallower than the depth of the first groove 161 .
  • the second embedding member 262 is embedded inside the second groove 261 .
  • the second embedded member 262 is made of, for example, a silicon oxide film or the like, like the insulator 162A.
  • the amplification transistor 21 of the pixel circuit 20 is arranged at the position corresponding to the pixel 10B.
  • the amplifying transistor 21 is arranged in a region partitioned by the pixel isolation region 16 with the gate length Lg direction aligned with the diagonal line D2-D2.
  • the amplification transistor 21 is arranged on the main surface portion of the substrate 15 in the same manner as the selection transistor 22 .
  • the amplification transistor 21 includes a channel forming region 201 , a gate insulating film 202 , a gate electrode 203 , and a pair of main electrodes 204 like the selection transistor 22 .
  • the FD region 25 and the substrate connection portion 27 are arranged at positions corresponding to the diagonal line D1-D1 and facing each other with the amplification transistor 21 at the center.
  • An element isolation region 26 is formed between the FD region 25 and the amplification transistor 21 and between the substrate connecting portion 27 and the amplification transistor 21, respectively.
  • the amplification transistor 21 is formed in a line-symmetrical shape with respect to the selection transistor 22 with the pixel isolation region 16 extending in the direction of the arrow X as the center. For this reason, one main electrode 204 of the selection transistor 22 is arranged close to one of the main electrodes 204 of the amplification transistor 21 in the direction of the arrow Y with the pixel isolation region 16 interposed therebetween.
  • One main electrode (input electrode or drain electrode) 204 of the selection transistor 22 and one main electrode (output electrode or source electrode) 204 of the amplification transistor 21 are electrically connected by a shared connection portion 31 .
  • the FD conversion gain switching transistor 23 of the pixel circuit 20 is arranged at the position corresponding to the pixel 10A.
  • the FD conversion gain switching transistor 23 is arranged in a region partitioned by the pixel separation region 16 with the gate length Lg direction aligned with the diagonal line D1-D1, similarly to the selection transistor 22 .
  • the FD conversion gain switching transistor 23 is arranged on the main surface portion of the substrate 15 .
  • the FD conversion gain switching transistor 23 includes a channel forming region 201 , a gate insulating film 202 , a gate electrode 203 and a pair of main electrodes 204 , like the selection transistor 22 .
  • the FD region 25 and the substrate connection portion 27 are arranged at positions corresponding to the diagonal line D2-D2 and opposed to each other with the FD conversion gain switching transistor 23 at the center.
  • Element isolation regions 26 are formed between the FD region 25 and the FD conversion gain switching transistor 23, and between the substrate connecting portion 27 and the FD conversion gain switching transistor 23, respectively.
  • the FD conversion gain switching transistor 23 is formed line-symmetrically with respect to the amplification transistor 21 with the pixel isolation region 16 extending in the arrow Y direction as the center.
  • a reset transistor 24 of the pixel circuit 20 is arranged at a position corresponding to the pixel 10C.
  • the reset transistor 24 is arranged in a region partitioned by the pixel isolation region 16 with the gate length Lg direction aligned with the diagonal line D2-D2, similarly to the amplification transistor 21 .
  • the reset transistor 24 is arranged on the main surface portion of the substrate 15 in the same manner as the selection transistor 22 .
  • the reset transistor 24 includes a channel forming region 201 , a gate insulating film 202 , a gate electrode 203 and a pair of main electrodes 204 , similarly to the selection transistor 22 .
  • the FD region 25 and the substrate connecting portion 27 are arranged at positions corresponding to the diagonal line D1-D1 and opposed to each other with the reset transistor 24 at the center.
  • An element isolation region 26 is formed between the FD region 25 and the reset transistor 24 and between the substrate connecting portion 27 and the reset transistor 24, respectively.
  • the reset transistor 24 is formed in a line-symmetrical shape with respect to the FD conversion gain switching transistor 23 with the pixel isolation region 16 extending in the arrow X direction as the center. Therefore, one main electrode 204 of the reset transistor 24 is arranged close to one main electrode 204 of the FD conversion gain switching transistor 23 in the direction of the arrow Y, with the pixel isolation region 16 interposed therebetween. .
  • One main electrode (input electrode or drain electrode) 204 of the reset transistor 24 and one main electrode (output electrode or source electrode) 204 of the FD conversion gain switching transistor 23 are electrically connected by a shared connection section 31. .
  • the reset transistor 24 is formed in a line-symmetrical shape with respect to the selection transistor 22 with the pixel isolation region 16 extending in the arrow Y direction as the center.
  • the shared connection portion 32 is made of a gate electrode material such as a polycrystalline silicon film.
  • This polycrystalline silicon film contains impurities at a high impurity density which reduce the resistance value. Phosphorus, which is an n-type impurity, can be practically used as the impurity.
  • the shared connection section 31 electrically connects one main electrode 204 of the FD conversion gain switching transistor 23 of the pixel 10A and one main electrode 204 of the reset transistor 24 of the pixel 10C. That is, one end of the shared connection portion 31 is directly connected to the surface of one main electrode 204 of the FD conversion gain switching transistor 23 . The other end of the shared connection portion 31 is directly connected to the surface of one main electrode 204 of the reset transistor 24 across the pixel isolation region 16 .
  • the shared connection portion 31 electrically connects one main electrode 204 of the amplification transistor 21 of the pixel 10B and one main electrode 204 of the selection transistor 22 of the pixel 10D. That is, one end of the shared connection portion 31 is directly connected to the surface of one main electrode 204 of the amplification transistor 21 . The other end of the shared connection portion 31 is directly connected to the surface of one main electrode 204 of the select transistor 22 across the pixel isolation region 16 .
  • Planar view WHEREIN The shared connection part 31 is formed in rectangular shape here. Specifically, the shared connection portion 31 is formed in a rectangular shape. Like the shared connection portion 32, the shared connection portion 31 is made of, for example, the gate electrode material.
  • a total of four substrate connection portions 27 arranged in each of the pixel 10A, pixel 10B, pixel 10C, and pixel 10D are arranged in four corners of the unit pixel BP.
  • the base connection portion 27 is electrically connected to the base connection portion 27 of another unit pixel BP adjacent to the unit pixel BP by the shared connection portion 33 .
  • the shared connection portion 33 is formed with the same configuration as the shared connection portion 32 that connects the four FD areas 25 .
  • the wiring 7 is arranged above the amplifying transistor 21 and the like of the pixel circuit 20 with an interlayer insulating film 6 interposed therebetween.
  • the wiring 7 is connected to the gate electrode 203, the main electrode 204, the shared connection portion 31, the shared connection portion 32, the shared connection portion 33 and the like through the connection hole 6H formed in the interlayer insulating film 6.
  • FIG. 7 for example, copper wiring is used as described above.
  • a substrate 15 is prepared. As shown in FIG. 6, a p-type semiconductor region (p-type well region) 151 is formed in the substrate 15, and the photoelectric conversion element 11 is formed in the pixel formation region. Each of the p-type semiconductor region 151 and the photoelectric conversion element 11 is formed by, for example, introducing an impurity and activating the introduced impurity.
  • pixel isolation regions 16 and element isolation regions 26 are formed.
  • the pixel isolation region 16 is formed in a region between the pixels 10 of the substrate 15 .
  • the pixel isolation region 16 is formed, for example, by forming a first groove 161 penetrating from the upper surface to the lower surface of the substrate 15 and embedding a first embedding member 162 in the first groove 161 .
  • Anisotropic etching such as reactive ion etching (RIE) is used to form the first grooves 161 .
  • RIE reactive ion etching
  • CVD chemical vapor deposition
  • the element isolation region 26 is formed in part of the pixel isolation region 16 and part of the p-type semiconductor region 151 on the main surface side of the substrate 15 .
  • the element isolation region 26 is formed by forming a second groove 261 from the upper surface to the lower surface of the substrate 15 and embedding a second embedding member 262 in the second groove 261 .
  • the second groove 261 is formed shallower than the first groove 161 .
  • Anisotropic etching such as RIE, for example, is used to form the second grooves 261 .
  • the CVD method or the like is used to form the second embedded member 262 .
  • a transfer gate electrode 205 is formed in a region surrounded by the pixel isolation region 16 and the element isolation region 26 and in the formation region of the transfer transistor 12 .
  • the transfer gate electrode 205 is connected to a groove (not numbered) formed from the upper surface to the bottom surface of the substrate 15, an embedded member (not numbered) embedded in the groove with a gate insulating film interposed therebetween, and the embedded member. and a gate electrode.
  • a gate insulating film 202 and a gate electrode 203 are formed on the surface of the substrate 15 in respective formation regions of the amplification transistor 21 , the selection transistor 22 , the FD conversion gain switching transistor 23 and the reset transistor 24 .
  • each of the FD regions 25 is formed.
  • the base connecting portion 27 is formed by implanting p-type impurities using photolithography and ion implantation.
  • the FD region 25 is formed by implanting n-type impurities using photolithography and ion implantation.
  • main electrodes 204 of the amplification transistor 21, the selection transistor 22, the FD conversion gain switching transistor 23, and the reset transistor 24 are formed in the same step as the step of forming the FD region 25. be done. By forming the main electrode 204, the amplification transistor 21, the selection transistor 22, the FD conversion gain switching transistor 23, and the reset transistor 24 are formed. Note that the impurity may be introduced by a solid phase diffusion method.
  • a shared connection portion 33 that connects between the substrate connection portions 27 and a shared connection portion 32 that connects between the FD regions 25 are formed.
  • the shared connection portion 33 is formed of, for example, a polycrystalline silicon film as a gate electrode material.
  • the polycrystalline silicon film is formed by, for example, the CVD method, and p-type impurities are introduced into the polycrystalline silicon film.
  • the p-type impurity is introduced by ion implantation or solid phase diffusion.
  • the shared connection portion 32 is formed by the same process as that for forming the shared connection portion 33, for example, a polycrystalline silicon film. An n-type impurity is introduced into this polycrystalline silicon film.
  • the shared connection portion 31 that connects the main electrodes 204 is formed in the same process as the shared connection portion 32 is formed.
  • An interlayer insulating film 6 is formed covering the amplification transistor 21, the selection transistor 22, the FD conversion gain switching transistor 23, the reset transistor 24, the shared connection portion 31, the shared connection portion 32, and the shared connection portion 33 (see FIG. 11). ). Subsequently, as shown in FIG. 11, a contact hole 6H is formed in the interlayer insulating film 6. Then, as shown in FIG.
  • wiring 7 is formed in interlayer insulating film 6 .
  • a wiring 7 is connected to each region through a connection hole 6H.
  • the solid-state imaging device 1 according to the first embodiment is completed, and the manufacturing method is finished.
  • the shared connection portion 31 and the shared connection portion 32 or the shared connection portion 33 may be doped with an impurity during the formation of the polycrystalline silicon film, for example.
  • the solid-state imaging device 1 includes pixels 10, pixel isolation regions 16, transistors 200, FD regions 25, transfer gate electrodes 205, or substrate connection portions 27.
  • the pixel 10 has a photoelectric conversion element 11 that is arranged on the first surface side of the substrate 15, which is the light incident side, and converts light into charge.
  • the pixel 10 is a "first pixel” according to the present technology, and is any one of the pixel 10A, the pixel 10B, the pixel 10C, and the pixel 10D.
  • the photoelectric conversion element is the "first photoelectric conversion element" according to the present technology.
  • the pixel separation region 16 is formed in the thickness direction of the substrate 15 and extends in the first direction and in the second direction crossing the first direction when viewed from the second surface side opposite to the first surface of the substrate 15 . Extending around the sides of pixel 10, it electrically and optically isolates pixel 10 from other regions.
  • the first direction is, for example, the arrow X direction.
  • the second direction is, for example, the arrow Y direction.
  • Each of the first direction and the second direction is the extending direction of the pixel isolation region 16 or the arrangement direction of the pixels 10 .
  • the transistor 200 is arranged on the second surface side of the substrate 15 surrounded by the pixel isolation region 16 at a position corresponding to the pixel 10, and the gate length direction is slanted with respect to the first direction or the second direction. are placed. Transistor 200 processes the converted charge. Transistor 200 is the "first transistor" according to the present disclosure. In the first embodiment, the "first transistor” is the FD conversion gain switching transistor 23 arranged at the position corresponding to the pixel 10A, but it may be any of the amplification transistor 21, the selection transistor 22, and the reset transistor 24. may The FD region 25 is arranged in the gate width Wg direction of the transistor 200 on the second surface of the substrate 15 at a position corresponding to the pixel 10 .
  • the FD area 25 is the "first FD area” according to the present technology.
  • the transfer gate electrode 205 is arranged in the gate width Wg direction of the transistor 200 on the second surface side of the substrate 15 at the position corresponding to the pixel 10 .
  • a transfer gate electrode 205 is a gate electrode of the transfer transistor 12 that transfers charges from the pixel 10 to the FD region 25 .
  • the transfer transistor 12 and the transfer gate electrode 205 are the "first transfer transistor” and the "first transfer gate electrode” according to the present technology.
  • the base connecting portion 27 supplies voltage to the base 15 .
  • the base connecting portion 27 is the “first base connecting portion” according to the present technology. Note that the first substrate connecting portion is a well contact region.
  • the transistor 200 is arranged diagonally in the direction of the gate length Lg in a region corresponding to the pixel 10 and surrounded by the pixel isolation region 16.
  • a sufficient layout area can be secured. Specifically, the lengths of the transistor 200 in the gate length Lg direction and the gate width Wg direction can be sufficiently secured. Therefore, the transistor 200 having excellent noise immunity can be constructed, so that the electrical reliability of the solid-state imaging device 1 can be improved.
  • the pair of main electrodes 204 are not formed in the gate width Wg direction of the transistor 200 . This area can be utilized as an empty space.
  • the FD region 25, the transfer gate electrode 205, or the substrate connecting portion 27 is arranged in this empty space. Although all of these are provided in the first embodiment, at least one may be provided. Therefore, the area corresponding to the pixel 10 can be effectively utilized.
  • the FD region 25, the transfer gate electrode 205, or the substrate connection portion 27 is arranged with the element isolation region 26 interposed with respect to the transistor 200. be. Therefore, the isolation capability between the transistor 200 and the FD region 25, the transfer gate electrode 205, or the substrate connecting portion 27 can be improved as compared with the case where the element isolation region 26 is not interposed.
  • the element isolation region 26 is formed from the second surface of the substrate 15 toward the first surface, and includes a second groove 261 deeper than the first groove 161 and a second embedding member 262 embedded in the second groove 261 . and Therefore, in the element isolation region 26, the isolation distance between the elements can be increased in the thickness direction of the substrate 15, so that the isolation ability between the transistor 200 and the FD region 25, the transfer gate electrode 205, or the substrate connection portion 27 can be improved. It can be improved further.
  • the pixels 10 are partitioned by the pixel isolation regions 16 and formed in a rectangular shape when viewed from the second surface side.
  • a pair of main electrodes 204 of the transistor 200 are arranged so as to coincide with, for example, diagonal lines D1-D1 of the rectangular shape of the pixel 10 .
  • the FD region 25, the transfer gate electrode 205, or the substrate connecting portion 27 is arranged in alignment with another diagonal line D2-D2 intersecting the diagonal line D1-D1 or along the diagonal line D2-D2. Therefore, the gate length Lg and the gate width Wg of the transistor 200 are longer than when the gate length Lg direction is aligned with the extending direction of the pixel isolation region 16 . Accordingly, in the transistor 200, noise resistance performance is improved, and electrical characteristics can be improved.
  • the gate length Lg direction of the transistor 200 has an inclination of 45 degrees with respect to the first direction or the second direction. Therefore, the gate length Lg and the gate width Wg of the transistor 200 are the longest.
  • the solid-state imaging device 1 includes pixels 10, pixel isolation regions 16, transistors 200, FD regions 25, transfer gate electrodes 205, or substrates. and a connecting portion 27 .
  • the pixel 10 is adjacent to the "first pixel” according to the present technology in the first direction, is arranged on the first surface side of the substrate 15 with the pixel separation region 16 interposed therebetween, and converts light into electric charge. It has a photoelectric conversion element 11 that The pixel 10 is a "second pixel” according to the present technology. For example, if the "first pixel" is the pixel 10A, the "second pixel” is the pixel 10B.
  • the photoelectric conversion element is the "second photoelectric conversion element” according to the present technology.
  • the pixel separation region 16 is formed in the thickness direction of the substrate 15 and extends in the first direction and in the second direction crossing the first direction when viewed from the second surface side opposite to the first surface of the substrate 15 . Extending around the sides of pixel 10, it electrically and optically isolates pixel 10 from other regions.
  • the transistor 200 is arranged on the second surface side of the substrate 15 surrounded by the pixel isolation region 16 at a position corresponding to the pixel 10, and the gate length direction is slanted with respect to the first direction or the second direction. , to process the converted charge.
  • Transistor 200 is the "second transistor" according to the present disclosure.
  • the “second transistor” is the amplification transistor 21 .
  • the “second transistor” is formed in a line-symmetrical shape with respect to the "first transistor” centering on the pixel isolation region 16 between the "first pixel” and the “second pixel”.
  • the FD region 25 is arranged in the gate width Wg direction of the transistor 200 on the second surface side of the substrate 15 at a position corresponding to the pixel 10 .
  • the FD area 25 is the "second FD area” according to the present technology.
  • the transfer gate electrode 205 is arranged in the gate width Wg direction of the transistor 200 on the second surface of the substrate 15 at the position corresponding to the pixel 10 .
  • a transfer gate electrode 205 is a gate electrode of the transfer transistor 12 that transfers charges from the pixel 10 to the FD region 25 .
  • the transfer transistor 12 and the transfer gate electrode 205 are the “second transfer transistor” and the “second transfer gate electrode” according to the present technology.
  • the base connecting portion 27 supplies voltage to the base 15 .
  • the base connecting portion 27 is the “second base connecting portion” according to the present technology.
  • the transistor 200 is arranged diagonally in the direction of the gate length Lg in a region corresponding to the pixel 10 and surrounded by the pixel isolation region 16. A sufficient layout area can be secured. Specifically, the lengths of the transistor 200 in the gate length Lg direction and the gate width Wg direction can be sufficiently secured.
  • the transistor 200 having excellent noise immunity can be constructed, so that the electrical reliability of the solid-state imaging device 1 can be improved.
  • the pair of main electrodes 204 are not formed in the gate width Wg direction of the transistor 200 .
  • This area can be utilized as an empty space.
  • the FD region 25, the transfer gate electrode 205, or the substrate connecting portion 27 is arranged in this empty space. Although all of these are provided in the first embodiment, at least one may be provided. Therefore, the area corresponding to the pixel 10 can be effectively utilized.
  • the "second transistor" is formed in a line-symmetrical shape with respect to the "first transistor", the arrangement layout of the pixels 10 and the transistors 200 can be easily realized.
  • both FD regions 25 or between substrate connecting portions 27 can be arranged close to each other. Therefore, a shared connection using the shared connection portion 32 or the shared connection portion 33 becomes possible, and a sufficient area for arranging the transistor 200 in the pixel 10 can be secured.
  • a “third pixel” and a “third transistor” are, for example, the pixel 10C and the reset transistor 24 .
  • the “fourth pixel” and the “fourth transistor” are the pixel 10D and the selection transistor 22, for example.
  • one of the pair of main electrodes 204 of the transistor 200 and one of the pair of main electrodes 204 of the other adjacent transistor 200 are connected by the shared connection portion 31, as shown in FIGS. be shared.
  • the main electrode 204 of the FD conversion gain switching transistor 23 and the main electrode 204 of the reset transistor 24 are shared by the shared connection section 31 .
  • the main electrode 204 of the amplification transistor 21 and the main electrode 204 of the selection transistor 22 are shared by the shared connection 31 .
  • the shared connection 31 is directly connected to the surface of the main electrode 204 .
  • the main electrodes 204 of the transistors 200 can be electrically connected to each other by the shared connection portion 31 without forming wiring and connection holes that cross over the pixel isolation region 16 .
  • the shared connection portion 31 is arranged so as to overlap the main electrode 204, and the connection between the two does not require an alignment margin dimension such as a connection hole. Therefore, the area on the main surface of the substrate 15 that connects the main electrodes 204 does not increase, so that a sufficient area for disposing the transistor 200 in the pixel 10 can be secured.
  • the gate length Lg dimension and the gate width Wg dimension of the transistor 200 can be increased. Therefore, the transistor 200 having excellent noise immunity can be constructed, so that the electrical reliability of the solid-state imaging device 1 can be improved.
  • the adjacent FD regions 25 are shared by the shared connection portion 32
  • the adjacent substrate connection portions 27 are shared by the shared connection portion 33 .
  • the shared connection portion 32 is directly connected to the surface of the FD region 25
  • the shared connection portion 33 is directly connected to the surface of the substrate connection portion 27 .
  • the parasitic capacitance added to the FD region 25 can be reduced because the connection is not made by the wiring 7 .
  • the substrate connecting portions 27 can be electrically connected to each other by the shared connecting portion 33 without forming wiring and connecting holes that cross over the pixel isolation region 16 .
  • the shared connection portion 33 is arranged so as to overlap the base connection portion 27, and the connection between the two does not require an alignment margin dimension such as a connection hole. Therefore, the area on the main surface of the substrate 15 that connects the substrate connection portions 27 does not increase. Therefore, in the pixel 10, a sufficient area is secured for arranging the transistor 200, so that the gate length Lg dimension and the gate width Wg dimension of the transistor 200 can be increased. That is, since the transistor 200 having excellent noise resistance can be constructed, the electrical reliability of the solid-state imaging device 1 can be improved.
  • one transistor 200 is arranged in one pixel 10, as shown in FIGS.
  • One FD region 25 is provided for a plurality of pixels 10 and the FD region 25 is shared (shared) by the plurality of pixels 10 .
  • Second Embodiment> A solid-state imaging device 1 according to a second embodiment of the present disclosure will be described with reference to FIGS. 12 and 13.
  • FIG. 12 shows an example of a specific planar configuration of the pixels 10 and pixel circuits 20 of the solid-state imaging device 1 according to the second embodiment.
  • FIG. 13 shows a vertical cross-sectional configuration of part of the pixel 10 and the pixel circuit 20 (a cross section cut along the BB cutting line shown in FIG. 12).
  • a fin (FIN) structure is adopted for the transistor 200 in the solid-state imaging device 1 according to the first embodiment.
  • the amplification transistor 21, the selection transistor 22, the FD conversion gain switching transistor 23, and the reset transistor 24 have a fin structure.
  • the fin structure is a structure in which the end of the gate electrode 203 in the direction of the gate width Wg extends from the second surface of the substrate 15 toward the first surface.
  • both ends of the gate electrode 203 in the gate width Wg direction are embedded in grooves formed in the substrate 15 and extend into the substrate 15 .
  • Both ends of the gate electrode 203 in the direction of the gate width Wg are formed exactly along the element isolation region 26 , and the gate width Wg of the gate electrode 203 is defined by the element isolation region 26 .
  • the fin structure may be employed for one selected from the amplification transistor 21, the selection transistor 22, the FD conversion gain switching transistor 23, and the reset transistor 24.
  • FIG. the fin structure may be adopted only for the amplification transistor 21 .
  • the transistor 200 extends the end of the gate electrode 203 in the gate width Wg direction from the second surface of the substrate 15 toward the first surface. It has a fin-type structure.
  • the gate width Wg dimension can be secured in the thickness direction of the base 15 in the transistor 200 .
  • the transistor 200 since the direction of the gate length Lg is arranged obliquely, the dimension of the gate length Lg is increased, and the occurrence of the short channel effect or the occurrence of noise can be effectively suppressed or prevented. be able to.
  • the transistor 200 can effectively suppress or prevent generation of RTN (Random Telegraph Signal) noise.
  • the gate width Wg dimension of transistor 200 can be extended to improve transconductance (gm). Also, since the mutual conductance of the transistor 200 is improved, the operation speed of the pixel circuit 200 can be increased.
  • FIG. 14 shows an example of a circuit configuration of the pixel 10 and the pixel circuit 20 that construct the solid-state imaging device 1 according to the third embodiment. .
  • the amplification transistor 21 includes amplification transistors 21A and 21B
  • the selection transistor 22 includes selection transistors 22A and 22B.
  • the amplification transistor 21A and the amplification transistor 21B are electrically connected in parallel.
  • the selection transistor 22A and the selection transistor 22B are electrically connected in parallel.
  • the amplification transistor 21A and the selection transistor 22A are electrically connected in series.
  • the amplification transistor 21B and the selection transistor 22B are electrically connected in series.
  • FIG. 15 shows an example of a specific planar configuration of the pixel 10 and pixel circuit 20 .
  • an amplification transistor 21B of the amplification transistor 21 and a selection transistor 22B of the selection transistor 22 are arranged at a position corresponding to the pixel 10A.
  • the amplification transistor 21B and the selection transistor 22B are arranged along the diagonal line D1-D1 (see FIG. 2). Further, the gate length Lg dimension of the amplification transistor 21B is formed longer than the gate length Lg dimension of the selection transistor 22B.
  • an amplification transistor 21A of the amplification transistor 21 and a selection transistor 22A of the selection transistor 22 are arranged at a position corresponding to the pixel 10B.
  • the amplification transistor 21A and the selection transistor 22A are arranged along a diagonal line D2-D2 (see FIG. 2). Further, the gate length Lg dimension of the amplification transistor 21A is formed longer than the gate length Lg dimension of the selection transistor 22A.
  • the amplification transistor 21A and the selection transistor 22A are formed in a line-symmetrical shape with respect to the amplification transistor 21B and the selection transistor 22B, centering on the pixel isolation region 16 arranged between the pixel 10A and the pixel 10B. .
  • a reset transistor 24 is arranged at a position corresponding to the pixel 10C.
  • the reset transistor 24 is arranged along the diagonal line D2-D2 (see FIG. 2).
  • An FD conversion gain switching transistor 23 is arranged at a position corresponding to the pixel 10D.
  • the FD conversion gain switching transistor 23 is arranged along the diagonal line D1-D1 (see FIG. 2).
  • the FD conversion gain switching transistor 23 is formed in a line-symmetrical shape with respect to the reset transistor 24 centering on the pixel isolation region 16 arranged between the pixel 10C and the pixel 10D.
  • the FD conversion gain switching transistor 23 is arranged in a substantially line-symmetrical shape with respect to the amplification transistor 21B and the selection transistor 22B, centering on the pixel isolation region 16 arranged between the pixel 10A and the pixel 10C. formed.
  • the reset transistor 24 is formed substantially line-symmetrically with respect to the amplification transistor 21A and the selection transistor 22A, with the pixel separation region 16 provided between the pixel 10B and the pixel 10D as the center. ing.
  • the main electrode 204 of the FD conversion gain switching transistor 23 and the main electrode 204 of the reset transistor 24 are connected by the wiring 7 (see FIG. 4).
  • a parasitic capacitance is positively formed by the wiring 7 .
  • Components other than the components described above are the same or substantially the same as the components of the solid-state imaging device 1 according to the first embodiment.
  • the amplification transistor 21 of the pixel circuit 20 is constructed by an amplification transistor 21A and an amplification transistor 21B electrically connected in parallel.
  • the select transistor 22 of the pixel circuit 20 is constructed by a select transistor 22A and a select transistor 22B electrically connected in parallel.
  • the amplification transistor 21A and the selection transistor 22A are arranged at positions corresponding to the pixels 10B.
  • the amplification transistor 21B and the selection transistor 22B are arranged at positions corresponding to the pixels 10A.
  • the gate length Lg of the amplification transistor 21A and the amplification transistor 21B is formed longer than the gate length Lg of the selection transistor 22A and the selection transistor 22B. Therefore, the noise resistance of the amplification transistor 21 constructed by the amplification transistor 21A and the amplification transistor 21B can be improved.
  • FIG. 16 shows an example of a specific planar configuration of the pixel 10 and the pixel circuit 20.
  • FIG. 17 shows a vertical cross-sectional configuration of part of the pixel 10 and the pixel circuit 20 (a cross section taken along the CC cutting line shown in FIG. 16).
  • FIG. 18 shows the vertical cross-sectional configuration of another part of the pixel 10 and the pixel circuit 20 (cross section taken along the DD cutting line shown in FIG. 16).
  • a plurality of transfer gate electrodes 205 of the transfer transistor 12 are arranged. More specifically, a transistor 200 is provided at a position corresponding to one pixel 10, and two transfer gate electrodes 205 are provided here. In plan view, the two transfer gate electrodes 205 are arranged along a diagonal line D2-D2 with the FD region 25 interposed therebetween.
  • the planar shape of the transfer gate electrode 205 is rectangular, specifically square.
  • the pixel 10 is the pixel 10A, the pixel 10B, the pixel 10C, or the pixel 10D.
  • a transistor 200 is an amplification transistor 21 , a selection transistor 22 , an FD conversion gain switching transistor 23 or a reset transistor 24 .
  • Components other than the components described above are the same or substantially the same as the components of the solid-state imaging device 1 according to the first embodiment.
  • a plurality of transfer gate electrodes 205 are arranged at positions corresponding to the pixels 10, as shown in FIGS.
  • the effective gate width Wg dimension of the transfer gate electrode 205 of the transfer transistor 12 is increased, so that the charge reading efficiency from the pixel 10 to the pixel circuit 20 can be improved.
  • FIG. 19 shows an example of a specific planar configuration of the pixel 10 and the pixel circuit 20.
  • FIG. 20 shows a vertical cross-sectional configuration of part of the pixel 10 and the pixel circuit 20 (a cross section cut along the EE cutting line shown in FIG. 19).
  • FIG. 21 shows the vertical cross-sectional configuration of another part of the pixel 10 and the pixel circuit 20 (a cross section cut along the FF cutting line shown in FIG. 19).
  • the transfer gate electrode 205 of the transfer transistor 12 has a rectangular shape in plan view. is formed in More specifically, a transistor 200 is provided at a position corresponding to one pixel 10, and one transfer gate electrode 205 is provided here. In plan view, the transfer gate electrode 205 is formed in a rectangular shape with long sides along the diagonal line D2-D2 and short sides along the diagonal line D1-D1. An FD region 25 is arranged to face the central portion of the transfer gate electrode 205 .
  • Components other than the components described above are the same or substantially the same as the components of the solid-state imaging device 1 according to the fourth embodiment.
  • transfer gate electrodes 205 having a rectangular shape in plan view are arranged at positions corresponding to the pixels 10.
  • FIG. As a result, the effective gate width Wg dimension of the transfer gate electrode 205 of the transfer transistor 12 is increased, so that the charge reading efficiency from the pixel 10 to the pixel circuit 20 can be improved.
  • FIG. 22 shows an example of a specific planar configuration of the pixel 10 and the pixel circuit 20.
  • FIG. 23 shows a vertical cross-sectional configuration of part of the pixel 10 and the pixel circuit 20 (a cross section cut along the GG cutting line shown in FIG. 22).
  • FIG. 24 shows a vertical cross-sectional configuration of another part of the pixel 10 and the pixel circuit 20 (a cross section taken along the HH cutting line shown in FIG. 22).
  • a plurality of transfer gate electrodes 205 of the transfer transistor 12 are arranged. . More specifically, a transistor 200 is provided at a position corresponding to one pixel 10, and two transfer gate electrodes 205 are provided here. In plan view, the two transfer gate electrodes 205 are arranged along a diagonal line D2-D2 with the FD region 25 interposed therebetween. Here, the planar shape of the transfer gate electrode 205 is triangular. One of the two transfer gate electrodes 205 is formed line-symmetrically with respect to the other of the transfer gate electrodes 205 about the diagonal line D1-D1.
  • planar shape of the transfer gate electrode 205 may be circular, elliptical, or a polygonal shape having a pentagon or more, other than the above.
  • a plurality of transfer gate electrodes 205 are arranged at positions corresponding to the pixels 10, as shown in FIGS.
  • the effective gate width Wg dimension of the transfer gate electrode 205 of the transfer transistor 12 is increased, so that the charge reading efficiency from the pixel 10 to the pixel circuit 20 can be improved.
  • FIG. 25 shows an example of a specific planar configuration of the pixel 10 and the pixel circuit 20.
  • FIG. 26 shows a vertical cross-sectional configuration of part of the pixel 10 and the pixel circuit 20 (a cross section taken along the II cutting line shown in FIG. 25).
  • the wiring 7 electrically connects between the main electrodes 204 of the transistor 200, between the FD regions 25, and between the substrate connecting portions 27, respectively.
  • the shared connection portion 31, the shared connection portion 32, and the shared connection portion 33 of the solid-state imaging device 1 according to the first embodiment are not formed.
  • Components other than the components described above are the same or substantially the same as the components of the solid-state imaging device 1 according to the first embodiment. Note that a plurality of pixels 10 may be arranged with the gate length Lg direction of the transistor 200 aligned with the diagonal line D2-D2.
  • the transistors 200 having the gate lengths Lg aligned in the same direction are arranged in each of the plurality of pixels 10 arranged.
  • Wirings 7 electrically connect the main electrodes 204 of the transistor 200, the FD regions 25, and the substrate connection portions 27.
  • FIG. With such a configuration, the shared connection portion 31 connecting between the main electrodes 204, the shared connection portion 32 connecting between the FD regions 25, and the shared connection portion 33 connecting between the substrate connection portions 27 are omitted. be able to. Therefore, the manufacturing process of the shared connection portion 31, the shared connection portion 32, and the shared connection portion 33 can be simplified.
  • FIG. 27 shows an example of a specific planar configuration of the pixel 10 and the pixel circuit 20.
  • the pixel circuit 20 includes two amplification transistors 21 electrically connected in parallel, a selection transistor 22, and a reset transistor 24. It has
  • One of the two amplification transistors 21 is arranged at a position corresponding to the pixel 10A.
  • the other of the two amplification transistors 21 is arranged at a position corresponding to the pixel 10B adjacent to the pixel 10A in the arrow X direction.
  • the other amplifying transistor 21 is formed in a line symmetrical shape with respect to the one amplifying transistor 21 with the pixel isolation region 16 between the pixel 10A and the pixel 10B as the center.
  • a reset transistor 24 is arranged at a position corresponding to the pixel 10C adjacent to the pixel 10A in the arrow Y direction.
  • the reset transistor 24 is formed in a line-symmetrical shape with respect to one amplification transistor 21 centering on the pixel isolation region 16 between the pixel 10A and the pixel 10C.
  • a selection transistor 22 is provided at a position corresponding to the pixel 10D adjacent to the pixel 10B in the direction opposite to the arrow Y direction.
  • the selection transistor 22 is formed in a line-symmetrical shape with respect to the other amplification transistor 21 centering on the pixel isolation region 16 between the pixel 10B and the pixel 10D.
  • a wiring 7 electrically connects between the FD region 25 and the gate electrode 203 of the amplification transistor 21, between the main electrode 204 of the amplification transistor 21 and the main electrode 204 of the selection transistor 22, and the like.
  • Components other than the components described above are the same or substantially the same as the components of the solid-state imaging device 1 according to the first embodiment.
  • amplification transistors 21 electrically connected in parallel are arranged at positions corresponding to the pixels 10A and 10B.
  • a reset transistor 24 is provided at a position corresponding to the pixel 10C arranged adjacent to the pixel 10A.
  • a selection transistor 22 is provided at a position corresponding to the pixel 10D arranged adjacent to the pixel 10B. Therefore, since the pixels 10 and the transistors 200 are arranged at positions suitable for connection points, connection using the wiring 7 is facilitated. In addition, since the wiring length of the wiring 7 is shortened, the parasitic capacitance added to the wiring 7 can be reduced.
  • FIG. 28 shows an example of a specific planar configuration of the pixel 10 and the pixel circuit 20.
  • the pixel circuit 20 includes two pixels electrically connected in parallel. It has an amplification transistor 21 , a selection transistor 22 and a reset transistor 24 .
  • One of the two amplification transistors 21 is arranged at a position corresponding to the pixel 10A.
  • the other of the two amplification transistors 21 is arranged at a position corresponding to the pixel 10B adjacent to the pixel 10A in the arrow X direction.
  • the other amplifying transistor 21 is formed in a line symmetrical shape with respect to the one amplifying transistor 21 with the pixel isolation region 16 between the pixel 10A and the pixel 10B as the center.
  • a reset transistor 24 is arranged at a position corresponding to the pixel 10C adjacent to the pixel 10A in the arrow Y direction.
  • the reset transistor 24 is formed in a line-symmetrical shape with respect to one amplification transistor 21 centering on the pixel isolation region 16 between the pixel 10A and the pixel 10C.
  • a selection transistor 22 is arranged at a position corresponding to the pixel 10D adjacent to the pixel 10B in the arrow Y direction.
  • the selection transistor 22 is formed in a line-symmetrical shape with respect to the other amplification transistor 21 centering on the pixel isolation region 16 between the pixel 10B and the pixel 10D.
  • a wiring 7 electrically connects between the FD region 25 and the gate electrode 203 of the amplification transistor 21, between the main electrode 204 of the amplification transistor 21 and the main electrode 204 of the selection transistor 22, and the like.
  • Components other than the components described above are the same or substantially the same as the components of the solid-state imaging device 1 according to the sixth embodiment.
  • FIG. 29 shows an example of a specific planar configuration of the pixel 10 and the pixel circuit 20.
  • FIG. 30 shows a vertical cross-sectional configuration of part of the pixel 10 and the pixel circuit 20 (a cross section cut along the JJ cutting line shown in FIG. 29).
  • FIG. 31 shows an arrangement layout configuration of the unit pixel BP shown in FIG. 29 and the surrounding pixels 10 (or unit pixel BP).
  • the unit pixel BP includes the pixel 10A, the pixel 10B, It has a pixel 10C and a pixel 10D.
  • An FD conversion gain switching transistor 23 is arranged at a position corresponding to the pixel 10A.
  • An amplification transistor 21 is arranged at a position corresponding to the pixel 10B.
  • a reset transistor 24 is provided at a position corresponding to the pixel 10C.
  • a selection transistor 22 is arranged at a position corresponding to the pixel 10D.
  • the main electrode 204 of the amplification transistor 21 and the main electrode of the selection transistor 22 are electrically connected by a shared connection portion 31 .
  • a shared connection section 31 electrically connects the main electrode 204 of the FD conversion gain switching transistor 23 and the main electrode 204 of the reset transistor 204 .
  • shared connection portion 31 includes shared groove 311 and connection conductor 312 .
  • the shared trench 311 is formed as a blind hole between the main electrodes 204 by digging from the upper surface (second surface) of the pixel isolation region 16 toward the lower surface (first surface).
  • the depth of the shared trench 311 is formed to be approximately the same as the junction depth of the main electrode 204, for example.
  • the depth of the shared trench 311 is formed shallower than the depth of the second trench 261 of the isolation region 26 .
  • a connection conductor 312 is embedded in the shared groove 311 .
  • the connection conductor 312 is directly connected to the side surface of the main electrode 204 .
  • the connection conductor 312 is made of a gate electrode material such as a polycrystalline silicon film. This polycrystalline silicon film contains impurities at a high impurity density which reduce the resistance value. Phosphorus, which is an n-type impurity, can be practically used as the impurity.
  • the shared connection portion 32 includes a shared groove 321 and a connection conductor 322, similar to the shared connection portion 31. As shown in FIG.
  • the shared connection portion 33 includes a shared groove 331 and a connection conductor 332 in the same manner as the shared connection portion 31 .
  • the connection conductor 332 is formed of, for example, a polycrystalline silicon film
  • the polycrystalline silicon film contains p-type impurities at a high impurity density that reduce the resistance value.
  • Components other than the components described above are the same or substantially the same as the components of the solid-state imaging device 1 according to the first embodiment.
  • the solid-state imaging device 1 also includes a shared connection section 31 as shown in FIGS. 29 to 31.
  • FIG. The shared connection portion 31 includes a shared groove 311 and a connection conductor 312 embedded in the shared groove 311 .
  • the main electrodes 204 of the transistor 200 can be electrically connected without forming a wiring and a connection hole over the pixel isolation region 16 . Therefore, the area on the main surface of the substrate 15 that connects the main electrodes 204 is effectively eliminated, so that a sufficient area for arranging the transistor 200 in the pixel 10 can be secured.
  • shared connection 31 is directly connected to the side of main electrode 204 of transistor 200 .
  • the area for connecting the shared connection portion 31 and the main electrode 204 is secured in the direction of the arrow Z, and is not substantially required on the main surface of the substrate 15 .
  • the solid-state imaging device 1 includes a shared connection portion 32 that connects between the FD regions 25 and a shared connection portion 33 that connects between the substrate connection portions 27, similarly to the shared connection portion 31. FIG. Therefore, the same effects as those obtained by the shared connection portion 31 can be obtained.
  • FIG. 32 shows an example of a specific planar configuration of the pixel 10 and the pixel circuit 20.
  • FIG. 33 shows a vertical cross-sectional configuration of part of the pixel 10 and the pixel circuit 20 (a cross section cut along the KK cutting line shown in FIG. 30).
  • the solid-state imaging device 1 according to the ninth embodiment includes a shared connection section 31, a shared connection section 32, and a shared connection section 31 provided in the solid-state imaging device 1 according to the eighth embodiment.
  • the connecting part 33 is not provided.
  • the wiring 7 is directly connected to the main electrode 204 of the transistor 200, the FD region 25, the substrate connecting portion 27, and the like.
  • Components other than the components described above are the same or substantially the same as the components of the solid-state imaging device 1 according to the first embodiment.
  • the wiring 7 is connected to the main electrode 204 of the transistor 200, the FD region 25, the substrate connecting portion 27, and the like.
  • each of the FD regions 25 gathered at the central portion of the plurality of pixels 10 is individually connected to the wiring 7 without disposing the shared connection portion 32 of the solid-state imaging device 1 according to the eighth embodiment. , not shared. Therefore, the parasitic capacitance generated between the FD region 25 and, for example, the transfer gate electrode 205 can be reduced, so that the charge readout efficiency from the pixel 10 to the pixel circuit 20 can be improved.
  • FIG. 10 A solid-state imaging device 1 according to the tenth embodiment of the present disclosure will be described with reference to FIGS. 34 to 37.
  • FIG. The tenth embodiment describes a construction example of the unit pixel BP of the solid-state imaging device 1 .
  • FIG. 34 shows an example of a specific planar configuration of the pixel 10 and the pixel circuit 20.
  • the solid-state imaging device 1 according to the tenth embodiment is different from the solid-state imaging device 1 according to the fifth embodiment in that the pixels 10A, 10B, and 10C arranged in the arrow Y direction are
  • a unit pixel BP is constructed by a total of three pixels 10 .
  • a reset transistor 24 is provided at a position corresponding to the pixel 10A.
  • An amplification transistor 21 is arranged at a position corresponding to the pixel 10B.
  • a selection transistor 22 is arranged at a position corresponding to the pixel 10C.
  • the reset transistor 24, amplification transistor 21, and selection transistor 22 are arranged with their gate lengths Lg aligned with the diagonal line D1-D1 (see FIG. 2).
  • each of the pixels 10A, 10B, and 10C forming the unit pixel BP is repeatedly arranged in the arrow X direction.
  • the unit pixels BP are repeatedly arranged in the arrow X direction and the arrow Y direction.
  • Components other than the components described above are the same or substantially the same as the components of the solid-state imaging device 1 according to the fifth embodiment.
  • FIG. 35 shows an example of a specific planar configuration of the pixel 10 and the pixel circuit 20 of the solid-state imaging device 1 according to the first modified example of the tenth embodiment.
  • a unit pixel BP is constructed by a total of four pixels 10, that is, a pixel 10A, a pixel 10B, a pixel 10C, and a pixel 10D arranged in the arrow Y direction.
  • a reset transistor 24 is provided at a position corresponding to the pixel 10A.
  • An FD conversion gain switching transistor 23 is arranged at a position corresponding to the pixel 10B.
  • An amplification transistor 21 is arranged at a position corresponding to the pixel 10C.
  • a selection transistor 22 is arranged at a position corresponding to the pixel 10D.
  • the reset transistor 24, the FD conversion gain switching transistor 23, the amplification transistor 21, and the selection transistor 22 are arranged with their gate lengths Lg aligned with the diagonal line D1-D1 (see FIG. 2).
  • each of the pixels 10A, 10B, 10C, and 10D forming the unit pixel BP is repeatedly arranged in the arrow X direction.
  • the unit pixels BP are repeatedly arranged in the arrow X direction and the arrow Y direction.
  • Components other than the components described above are the same or substantially the same as the components of the solid-state imaging device 1 according to the fifth embodiment.
  • FIG. 36 shows an example of a specific planar configuration of the pixel 10 and the pixel circuit 20 of the solid-state imaging device 1 according to the second modification of the tenth embodiment.
  • a unit pixel BP is constructed by a total of eight pixels 10, pixels 10A to 10H arranged in the arrow X direction and the arrow Y direction.
  • the pixels 10A and 10B are arranged adjacent to each other in the arrow X direction.
  • a reset transistor 24 is arranged at a position corresponding to each of the pixels 10A and 10B.
  • the pixels 10C and 10D are arranged adjacent to each other in the direction of the arrow X, and the pixels 10A and 10B are arranged adjacent to each other in the direction of the arrow Y.
  • FD conversion gain switching transistors 23 are provided at positions corresponding to the pixels 10C and 10D, respectively.
  • the pixels 10E and 10F are arranged adjacent to each other in the direction of the arrow X, and the pixels 10C and 10D are arranged adjacent to each other in the direction of the arrow Y.
  • Amplification transistors 21 are arranged at positions corresponding to the pixels 10E and 10F, respectively.
  • the pixels 10G and 10H are arranged adjacent to each other in the direction of the arrow X, and the pixels 10E and 10F are arranged adjacent to each other in the direction of the arrow Y.
  • Selection transistors 22 are arranged at positions corresponding to the pixels 10G and 10H, respectively.
  • the reset transistor 24, the FD conversion gain switching transistor 23, the amplification transistor 21, and the selection transistor 22 are arranged with their gate lengths Lg aligned with the diagonal line D1-D1 (see FIG. 2).
  • each of the pixels 10A to 10H forming the unit pixel BP is repeatedly arranged in the arrow X direction.
  • the unit pixels BP are repeatedly arranged in the arrow X direction and the arrow Y direction.
  • Components other than the components described above are the same or substantially the same as the components of the solid-state imaging device 1 according to the fifth embodiment.
  • FIG. 37 shows an example of a specific planar configuration of the pixel 10 and the pixel circuit 20 of the solid-state imaging device 1 according to the third modification of the tenth embodiment.
  • the solid-state imaging device 1 according to the third modification has pixels 10A, 10B, 10C, and 10A, 10B, 10C, and 10B arranged in the direction of the arrow Y in the same manner as the solid-state imaging device 1 according to the first modification.
  • a unit pixel BP is constructed by a total of four pixels 10 including the pixel 10D.
  • a reset transistor 24 is provided at a position corresponding to the pixel 10A.
  • An FD conversion gain switching transistor 23 is arranged at a position corresponding to the pixel 10B.
  • the FD conversion gain switching transistor 23 is formed in a line-symmetrical shape with respect to the reset transistor 24 .
  • An amplification transistor 21 is arranged at a position corresponding to the pixel 10C.
  • the amplification transistor 21 is formed line-symmetrically with respect to the FD conversion gain switching transistor 23 .
  • a selection transistor 22 is arranged at a position corresponding to the pixel 10D.
  • the selection transistor 22 is formed line-symmetrically with respect to the amplification transistor 21 .
  • each of the pixels 10A, 10B, 10C, and 10D forming the unit pixel BP is formed in a line-symmetrical shape.
  • the unit pixel BP is formed in a line-symmetrical shape in the arrow X direction and the arrow Y direction.
  • Components other than the components described above are the same or substantially the same as the components of the solid-state imaging device 1 according to the fifth embodiment.
  • FIG. 38 shows a vertical cross-sectional configuration of part of the pixel 10 and the pixel circuit 20 (longitudinal cross-sectional configuration corresponding to FIG. 4 described above).
  • the solid-state imaging device 1 according to the eleventh embodiment includes element isolation regions 26P instead of the element isolation regions 26 of the solid-state imaging device 1 according to the first embodiment.
  • the element isolation region 26 ⁇ /b>P is formed of a semiconductor region that is the same p-type as the base 15 and has an impurity density higher than that of the p-type semiconductor region 151 of the base 15 .
  • the element isolation region 26P is formed using, for example, an ion implantation method, a solid phase diffusion method, or the like.
  • the element isolation region 26P is also formed in part of the pixel isolation region 16 on the second surface side, and the pixel isolation region 16 is configured including the element isolation region 26P.
  • Components other than the components described above are the same or substantially the same as the components of the solid-state imaging device 1 according to the first embodiment.
  • the solid-state imaging device 1 also includes an element isolation region 26P, as shown in FIG. It is not necessary to form the second groove 261 and the second embedded member 262 of the element isolation region 26P in the element isolation region 26P. Therefore, the solid-state imaging device 1 can be constructed easily.
  • FIG. 39 A solid-state imaging device 1 according to the twelfth embodiment of the present disclosure will be described with reference to FIGS. 39 to 48.
  • FIG. 39 A solid-state imaging device 1 according to the twelfth embodiment of the present disclosure will be described with reference to FIGS. 39 to 48.
  • FIG. 39 A solid-state imaging device 1 according to the twelfth embodiment of the present disclosure will be described with reference to FIGS. 39 to 48.
  • FIG. 39 shows an example of a circuit configuration of the pixel 10 and the pixel circuit 20 that construct the solid-state imaging device 1 according to the twelfth embodiment. .
  • the basic configurations of the pixels 10 and the pixel circuits 20 of the solid-state imaging device 1 are the same as the configurations of the pixels 10 and the pixel circuits 20 of the solid-state imaging device 1 according to the first embodiment. .
  • the power supply voltage terminal VDD connected to each of the amplification transistor 21 and the reset transistor 24 of the pixel circuit 20 forming the unit pixel BP1 is shared.
  • the power supply voltage terminal VDD connected to each of the amplification transistor 21 and the reset transistor 24 of the pixel circuit 20 constructing the unit pixel BP2 arranged adjacent to the unit pixel BP1 is shared.
  • the unit pixel BP1 and the unit pixel BP2 share the power supply voltage terminal VDD.
  • FIG. 40 shows an example of a specific planar configuration of the pixel 10 and pixel circuit 20 .
  • FIG. 41 shows a vertical cross-sectional configuration of part of the pixel 10 and the pixel circuit 20 (a cross section cut along the LL cutting line shown in FIG. 40).
  • one pixel circuit 20 is provided for four pixels 10, like the solid-state imaging device 1 according to the first embodiment.
  • the four pixels 10 are two pixels 10A and 10B that are adjacent in the direction of the arrow X, and two pixels that are adjacent in the direction of the arrow X and are adjacent to the pixels 10A and 10B in the direction of the arrow Y.
  • These four pixels 10A, 10B, 10C and 10D form a unit pixel BP1.
  • a reset transistor 24 of the pixel circuit 20 is arranged at a position corresponding to the pixel 10D.
  • the reset transistor 24 is arranged in a region partitioned by the pixel isolation region 16 so that the gate length Lg direction is aligned with the diagonal line D1-D1 (see FIG. 2).
  • An amplification transistor 21 of the pixel circuit 20 is arranged at a position corresponding to the pixel 10B.
  • the amplifying transistor 21 is arranged in a region partitioned by the pixel isolation region 16 with the gate length Lg direction aligned with the diagonal line D2-D2.
  • a selection transistor 22 of the pixel circuit 20 is arranged at a position corresponding to the pixel 10A.
  • the select transistor 22 is arranged in a region partitioned by the pixel isolation region 16 so that the gate length Lg direction is aligned with the diagonal line D1-D1 (see FIG. 2).
  • An FD conversion gain switching transistor 23 of the pixel circuit 20 is arranged at a position corresponding to the pixel 10C.
  • the FD conversion gain switching transistor 23 is arranged in the region partitioned by the pixel isolation region 16 so that the gate length Lg direction is aligned with the diagonal line D2-D2.
  • the amplification transistor 21 is formed in a line-symmetrical shape with respect to the selection transistor 22 with the pixel isolation region 16 between the pixel 10A and the pixel 10B as the center.
  • the reset transistor 24 is formed in a line-symmetrical shape with respect to the FD conversion gain switching transistor 23 centering on the pixel separation region 16 between the pixel 10C and the pixel 10BD. Further, the reset transistor 24 and the FD conversion gain switching transistor 23 are line symmetrical with respect to the amplification transistor 21 and the selection transistor 22, centering on the pixel isolation region 16 between the pixels 10A and 10B and the pixels 10C and 10D. formed into a shape.
  • the unit pixel BP2 is arranged adjacent to the unit pixel BP1 in the arrow X direction.
  • the unit pixel BP2 is formed in a line-symmetrical shape with respect to the unit pixel BP1, centering on the pixel separation region 16 between the unit pixel BP1 and the unit pixel BP2.
  • the pixel 10B of the unit pixel BP1 and the pixel 10B of the unit pixel BP2 are arranged close to each other.
  • the pixel 10D of the unit pixel BP1 and the pixel 10D of the unit pixel BP2 are arranged close to each other. That is, the main electrodes 204 of the amplification transistor 21 and the reset transistor 24 of the unit pixel BP1 and the main electrodes 204 of the amplification transistor 21 and the reset transistor 24 of the unit pixel BP2 are gathered at one place.
  • the four main electrodes 204 gathered at one place are electrically connected to each other by the shared connection portion 34 and shared.
  • the shared connection portion 34 is electrically directly connected to the surface of the main electrode 204 in the same manner as the shared connection portion 31 and the shared connection portion 32 of the solid-state imaging device 1 according to the first embodiment described above. . Specifically, one end of the shared connection portion 34 is connected to, for example, the main electrode 204 of the amplification transistor 21 of the unit pixel BP1. The other end of the shared connection portion 34 is connected across the pixel isolation region 16 to the main electrodes 204 of the reset transistor 24 of the unit pixel BP1 and the amplification transistor 21 and reset transistor 24 of the unit pixel BP2. The shared connection portion 34 is connected to the power supply voltage terminal VDD through the wiring 7 (see FIG. 39).
  • Components other than the components described above are the same or substantially the same as the components of the solid-state imaging device 1 according to the first embodiment.
  • a substrate 15 is prepared. As shown in FIG. 42, a first groove 161 is formed in the substrate 15 in the formation region of the pixel isolation region 16 . Anisotropic etching such as RIE, for example, is used to form the first grooves 161 .
  • a mask 165 is formed on the inner wall of the first groove 161 on the second surface side. The mask 165 is used as an anti-impurity mask.
  • a mask 165 is used to introduce, for example, a p-type impurity into the substrate 15 from the inner wall of the first groove 161 to form a pinning region 166 . After this, the mask 165 is removed. As shown in FIG. 44, a first embedding member 162 is embedded in the first trench 161 to form the pixel isolation region 16 .
  • element isolation regions 26 are formed.
  • the element isolation region 26 is formed between each of the transistor 200, the FD region 25, and the substrate connection portion 27, and is also formed in a part of the pixel isolation region 16 on the second surface side here.
  • the element isolation region 26 is formed by forming a second groove 261 from the upper surface to the lower surface of the substrate 15 and embedding a second embedding member 262 in the second groove 261 .
  • the second groove 261 is formed shallower than the first groove 161 .
  • Anisotropic etching such as RIE, for example, is used to form the second grooves 261 .
  • the CVD method or the like is used to form the second embedded member 262 .
  • a gate insulating film 202 and a gate electrode 203 are sequentially formed on the second surface of the substrate 15 within the region surrounded by the pixel isolation region 16 and the element isolation region 26 (see FIG. 8). ). Subsequently, main electrode 204 of transistor 200 is formed, as shown in FIG. Once the main electrode 204 is formed, the transistor 200 is completed.
  • a shared connection portion 34 is formed to connect between the main electrodes 204 of the transistor 200 across the pixel isolation region 16 .
  • the shared connection portion 34 is formed by the same process as that for forming the shared connection portion 31 and the shared connection portion 32 (not shown).
  • An interlayer insulating film 6 and a connection hole 6H are sequentially formed, and wiring 7 is formed as shown in FIG.
  • the wiring 7 shown in FIG. 48 connects the shared connection portion 34 to the power supply voltage terminal VDD.
  • the solid-state imaging device 1 according to the twelfth embodiment is completed, and the manufacturing method is completed.
  • the solid-state imaging device 1 includes pixels 10, transistors 200, pixel isolation regions 16, and shared connection portions 34.
  • the pixel 10 has a photoelectric conversion element 11 that is arranged on the first surface side of the substrate 15, which is the light incident side, and converts light into charge.
  • the pixel 10 is each of a “first pixel” and a “second pixel” according to the present technology.
  • the "first pixel” is, for example, the pixel 10B or the pixel 10D of the unit pixel BP1.
  • a “second pixel” is, for example, the pixel 10A or the pixel 10C of the unit pixel BP2.
  • the pixel separation regions 16 are arranged between the pixels 10 and formed in the thickness direction of the substrate 15 to electrically and optically separate the pixels 10 from each other.
  • the transistor 200 is arranged on the second surface side of the substrate 15 at a position corresponding to the pixel 10, and the gate length Lg direction is slanted with respect to the arrangement direction of the pixel 10, and processes converted charges.
  • the transistor 200 is each of a “first transistor” and a “second transistor” according to the present technology. For example, when the “first transistor” is arranged at the position corresponding to the pixel 10B of the unit pixel BP1, the “first transistor” is the amplification transistor 21 .
  • the “second transistor” When the “second transistor” is arranged at the position corresponding to the pixel 10A of the unit pixel BP2, the “second transistor” is the amplification transistor 21. FIG. Further, when the “first transistor” is arranged at the position corresponding to the pixel 10 ⁇ /b>D of the unit pixel BP ⁇ b>1 , the “first transistor” is the reset transistor 24 . When the “second transistor” is arranged at the position corresponding to the pixel 10 ⁇ /b>D of the unit pixel BP ⁇ b>2 , the “second transistor” is the reset transistor 24 .
  • the shared connection 34 provides a direct electrical connection between the main electrodes 204 of the transistor 200 and supplies a power supply voltage.
  • the power supply voltage can be supplied to the main electrodes 204 of the plurality of transistors 200 at one point without forming wiring and connection holes that cross over the pixel isolation region 16 . Therefore, it is possible to reduce the number of connection points between the main electrode 204 and the power supply voltage terminal VDD, so that a sufficient area for disposing the transistor 200 in the pixel 10 can be secured. Here, four connection points become one connection point. In addition, for example, in the pixel 10, since a sufficient area is secured for arranging the transistor 200, the transistor 200 having excellent noise resistance can be constructed, and the electrical reliability of the solid-state imaging device 1 can be improved. can be done.
  • the shared connection section 34 is connected to the power supply voltage terminal VDD through the wiring 7 at the position overlapping the pixel isolation region 16.
  • FIG. Therefore, the distance between the wiring 7 and the transfer gate electrode 205 or the FD region 25 can be increased, so that the electric field strength from the wiring 7 to the transfer gate electrode 205 or the FD region 25 can be weakened.
  • the shared connection section 34 is connected to the surface of the main electrode 204 of the transistor 200, as in the solid-state imaging device 1 according to the first embodiment.
  • FIG. 49 shows a vertical cross-sectional configuration of part of the pixel 10 and the pixel circuit 20 (longitudinal cross-sectional configuration corresponding to FIG. 48 described above).
  • the structure of the shared connection section 34 of the solid-state imaging device 1 according to the twelfth embodiment is replaced with that of the solid-state imaging device according to the eighth embodiment. It has the same structure as the shared connection section 31 and the shared connection section 32 of the device 1 .
  • the shared connection portion 34 includes a shared groove 341 and a connection conductor 342 .
  • the shared groove 341 has the same configuration as the shared groove 311 of the shared connection portion 31 of the solid-state imaging device according to the eighth embodiment
  • the connection conductor 342 has the same configuration as the connection conductor 312 .
  • each of the shared connection portion 31, the shared connection portion 32, and the shared connection portion 33 has the same structure as the shared connection portion .
  • Components other than the components described above are the same or substantially the same as the components of the solid-state imaging device 1 according to the eighth embodiment.
  • a shared groove 341 is formed in a part of the second surface side of the pixel isolation region 16 (see FIG. 50). .
  • the shared groove 341 is formed by the same process as the shared groove 311 of the shared connection portion 31 (not shown).
  • connection conductors 342 are formed in shared trenches 341 .
  • the connection conductor 341 is formed in the same process as the connection conductor 312 of the shared connection portion 31 (not shown).
  • connection conductor 342 As shown in FIG. 51, an n-type impurity is introduced into the connection conductor 342 to form the shared connection portion 34 .
  • the shared connection portion 34 is formed by the same process as the shared connection portion 31 .
  • the interlayer insulating film 6 and the connection hole 6H are formed in sequence, and the wiring 7 is formed as shown in FIG. 49 described above.
  • the wiring 7 shown in FIG. 49 connects the shared connection portion 34 to the power supply voltage terminal VDD.
  • the solid-state imaging device 1 according to the thirteenth embodiment is completed, and the manufacturing method is completed.
  • the solid-state imaging device 1 according to the thirteenth embodiment it is possible to obtain the same effects as those obtained by the solid-state imaging device 1 according to the twelfth embodiment. Furthermore, according to the solid-state imaging device 1 according to the thirteenth embodiment, it is possible to obtain the effects obtained by combining the solid-state imaging device 1 according to the twelfth embodiment and the solid-state imaging device 1 according to the eighth embodiment. can.
  • FIG. 52 shows an example of a specific planar configuration of the pixel 10 and the pixel circuit 20. As shown in FIG.
  • one pixel circuit 20 is arranged for four pixels 10, like the solid-state imaging device 1 according to the twelfth embodiment.
  • the four pixels 10 are two pixels 10A and 10B that are adjacent in the direction of the arrow X, and two pixels that are adjacent in the direction of the arrow X and are adjacent to the pixels 10A and 10B in the direction of the arrow Y.
  • These four pixels 10A, 10B, 10C and 10D form a unit pixel BP1.
  • a reset transistor 24 of the pixel circuit 20 is arranged at a position corresponding to the pixel 10C.
  • the reset transistor 24 is arranged in a region partitioned by the pixel isolation region 16 with the gate length Lg direction aligned with the diagonal line D2-D2 (see FIG. 2).
  • An amplification transistor 21 of the pixel circuit 20 is arranged at a position corresponding to the pixel 10D.
  • the amplifying transistor 21 is arranged in a region partitioned by the pixel isolation region 16 with the gate length Lg direction aligned with the diagonal line D1-D1.
  • An FD conversion gain switching transistor 23 of the pixel circuit 20 is arranged at a position corresponding to the pixel 10A.
  • the FD conversion gain switching transistor 23 is arranged in the region partitioned by the pixel separation region 16 so that the gate length Lg direction is aligned with the diagonal line D1-D1.
  • a selection transistor 22 of the pixel circuit 20 is arranged at a position corresponding to the pixel 10B.
  • the select transistor 22 is arranged in a region partitioned by the pixel isolation region 16 with the gate length Lg direction aligned with the diagonal line D2-D2 (see FIG. 2).
  • the selection transistor 22 is formed in a line-symmetrical shape with respect to the FD conversion gain switching transistor 23 with the pixel isolation region 16 between the pixel 10A and the pixel 10B as the center.
  • the amplification transistor 21 is formed in a line-symmetrical shape with respect to the reset transistor 24 with the pixel isolation region 16 between the pixel 10C and the pixel 10D as the center. Further, the reset transistor 24 and the amplification transistor 21 are line-symmetrical with respect to the FD conversion gain switching transistor 23 and the selection transistor 22, centering on the pixel isolation region 16 between the pixels 10A and 10B and the pixels 10C and 10BD. formed into a shape.
  • the unit pixel BP2 is arranged adjacent to the unit pixel BP1 in the arrow Y direction.
  • the unit pixel BP2 is formed in a line-symmetrical shape with respect to the unit pixel BP1, centering on the pixel separation region 16 between the unit pixel BP1 and the unit pixel BP2.
  • Components other than the components described above are the same or substantially the same as the components of the solid-state imaging device 1 according to the twelfth embodiment.
  • FIG. 53 shows an example of a specific planar configuration of the pixel 10 and the pixel circuit 20. As shown in FIG.
  • the shared connection section 34 is arranged over two pixels 10 in the solid-state imaging device 1 according to the twelfth embodiment. More specifically, the shared connection portion 34 is arranged at a position corresponding to the main electrode 204 of the amplifying transistor 21 corresponding to the pixel 10B of the unit pixel BP2 and the pixel 10D of the same unit pixel BP2. and the main electrode 204 of the reset transistor 24 are electrically connected. That is, the shared connection portion 34 is formed in a rectangular shape that is elongated in the arrow Y direction in plan view.
  • the main electrode 204 of the amplification transistor 21 arranged at the position corresponding to the pixel 10B of the unit pixel BP1, and the main electrode 204 of the reset transistor 24 arranged at the position corresponding to the pixel 10D of the same unit pixel BP1. are configured to be connected to the wiring 7 .
  • Components other than the components described above are the same or substantially the same as the components of the solid-state imaging device 1 according to the twelfth embodiment.
  • FIG. 54 shows an example of a specific planar configuration of the pixel 10 and the pixel circuit 20. As shown in FIG.
  • the shared connection section 34 is arranged over two pixels 10 in the solid-state imaging device 1 according to the twelfth embodiment. More specifically, the common connection section 34 includes the main electrode 204 of the reset transistor 24 arranged at a position corresponding to the pixel 10D of the unit pixel BP1 and the reset transistor 204 arranged at a position corresponding to the pixel 10D of the unit pixel BP2. It is electrically connected to the main electrode 204 of the transistor 24 . That is, the shared connection portion 34 is formed in a rectangular shape elongated in the arrow X direction in plan view.
  • Each of the main electrode 204 of the amplification transistor 21 arranged at the position corresponding to the pixel 10B of the unit pixel BP1 and the main electrode 204 of the amplification transistor 21 arranged at the position corresponding to the pixel 10B of the unit pixel BP2 has A wiring 7 is connected.
  • Components other than the components described above are the same or substantially the same as the components of the solid-state imaging device 1 according to the twelfth embodiment.
  • the main electrodes 204 of two adjacent reset transistors 24 are connected by the shared connection portion 34.
  • the wiring 7 connects between the main electrodes 204 of two adjacent amplifying transistors 21 .
  • FIG. 55 shows an example of a specific planar configuration of the pixel 10 and the pixel circuit 20. As shown in FIG.
  • the 16 pixels 10 are pixels 10A to 10P.
  • the four pixels 10A to 10D are adjacent in the arrow X direction.
  • the four pixels 10E to 10H are adjacent in the arrow X direction, and adjacent to the pixels 10A to 10D in the arrow Y direction.
  • the four pixels 10I to 10L are adjacent in the arrow X direction, and adjacent to the pixels 10E to 10H in the arrow Y direction.
  • the four pixels 10M to 10P are adjacent in the arrow X direction and adjacent to the pixels 10I to 10L in the arrow Y direction.
  • These 16 pixels 10A to 10P constitute a unit pixel BP3.
  • a unit pixel BP3 shown in FIG. 55 is a basic array that can be expanded into several modifications.
  • Selection transistors 22 of the pixel circuit 20 are arranged at positions corresponding to the pixels 10A and 10D. Similar to the selection transistor 22 of the solid-state imaging device 1 according to the twelfth embodiment, the selection transistor 22 and the like are arranged with the gate length Lg direction aligned with the diagonal line D1-D1 or the diagonal line D2-D2 ( See Figure 2). Amplifying transistors 21 of the pixel circuit 20 are arranged at positions corresponding to the pixels 10B and 10C. An amplification transistor 21 or a selection transistor 22 of the pixel circuit 20 is arranged at positions corresponding to the pixels 10E to 10H, the pixels 10I, and the pixels 10L.
  • Amplifying transistors 21 of the pixel circuit 20 are arranged at positions corresponding to the pixels 10J and 10K.
  • FD conversion gain switching transistors 23 of the pixel circuit 20 are arranged at positions corresponding to the pixels 10M and 10P.
  • a reset transistor 24 of the pixel circuit 20 is arranged at a position corresponding to the pixel 10N and the pixel 10O.
  • the unit pixels BP3 configured in this manner are sequentially arranged in a line-symmetrical shape in the arrow X direction and the arrow Y direction.
  • FIG. 56 shows an example of a specific planar configuration of the pixel 10 and the pixel circuit 20.
  • amplification transistors 21 of the pixel circuit 20 are arranged at positions corresponding to the pixels 10E to 10H, the pixels 10I, and the pixels 10L.
  • the main electrodes 204 of the amplification transistors 21 arranged at positions corresponding to the pixels 10B, 10C, 10F, and 10G are gathered in one place. This allows the plurality of main electrodes 204 to be connected to the power supply voltage terminal VDD through the shared connection portion 34 and the wiring 7 .
  • Components other than the components described above are the same or substantially the same as the components of the solid-state imaging device 1 according to the twelfth embodiment.
  • FIG. 57 shows an example of a specific planar configuration of the pixel 10 and the pixel circuit 20 of the solid-state imaging device 1 according to the modification of the seventeenth embodiment.
  • selection transistors 22 of the pixel circuit 20 are arranged at positions corresponding to the pixels 10E, 10H, 10I, and 10L.
  • amplification transistors 21 of the pixel circuit 20 are arranged at positions corresponding to the pixels 10F and 10G.
  • the main electrodes 204 of the amplification transistors 21 arranged at positions corresponding to the pixels 10B, 10C, 10F, and 10G are gathered in one place. This allows the plurality of main electrodes 204 to be connected to the power supply voltage terminal VDD through the shared connection portion 34 and the wiring 7 .
  • Components other than the components described above are the same or substantially the same as the components of the solid-state imaging device 1 according to the seventeenth embodiment.
  • FIG. 18 A solid-state imaging device 1 according to the eighteenth embodiment of the present disclosure will be described with reference to FIGS. 58 to 60.
  • FIG. 18 A solid-state imaging device 1 according to the eighteenth embodiment of the present disclosure will be described with reference to FIGS. 58 to 60.
  • FIG. 18 A solid-state imaging device 1 according to the eighteenth embodiment of the present disclosure will be described with reference to FIGS. 58 to 60.
  • the color filter 4 is arranged in the pixel 10 .
  • the color filter 4 is arranged on the first surface side of the substrate 15, although the description of the longitudinal section is omitted.
  • the color filter 4 includes a red filter 41, a green filter 42, a green filter 43, and a blue filter 44.
  • red filters 41 and green filters 43 are alternately arranged in the arrow X direction.
  • green filters 42 are arranged in the arrow Y direction and on the opposite side.
  • blue filters 44 are arranged in the arrow Y direction and on the opposite side. That is, the green filters 42 and the blue filters 44 are alternately arranged in the arrow X direction.
  • FIG. 59 shows an example of a planar layout configuration of the pixel 10 and the pixel circuit 20 .
  • a total of eight pixels 10 are constructed as one unit pixel BPR, and a red filter 41 is arranged in this unit pixel BPR.
  • the amplification transistor 21 is arranged at the position corresponding to the pixel 10A.
  • a selection transistor 22 is arranged at a position corresponding to the pixel 10B.
  • An FD conversion gain switching transistor 23 is arranged at a position corresponding to the pixel 10C.
  • a reset transistor 24 is provided at a position corresponding to the pixel 10D.
  • the unit pixel BPR includes a pixel 10D and a pixel 10C arranged adjacent in the arrow X direction, and a pixel 10B and a pixel 10A arranged adjacent in the arrow Y direction and also adjacent in the arrow X direction. , a pixel 10D and a pixel 10C, and a pixel 10B and a pixel 10A arranged adjacent to each other in the arrow Y direction and the arrow X direction.
  • a total of eight pixels 10 are constructed as one unit pixel BPB, and a blue filter 44 is arranged in this unit pixel BPB.
  • the unit pixel BPB includes a pixel 10D and a pixel 10C arranged adjacently in the arrow X direction, and a pixel 10B, a pixel 10A, a pixel 10D and a pixel 10D arranged adjacently in the arrow Y direction and also adjacently arranged in the arrow X direction. It includes a pixel 10C, and pixels 10B and 10A that are arranged adjacent to each other in the arrow Y direction and adjacent to each other in the arrow X direction.
  • FIG. 60 shows an example of the planar layout configuration of the pixels 10 in which the green filters 43 are arranged.
  • a total of 10 pixels 10 are constructed as one unit pixel BPGb, and a green filter 43 is arranged in this unit pixel BPGb.
  • the unit pixel BPGb includes a pixel 10, a pixel 10C, a pixel 10B, and a pixel 10A arranged adjacently in the arrow X direction, and a pixel 10D and a pixel 10D arranged adjacently in the arrow X direction. It includes a pixel 10A, and a pixel 10A, a pixel 10B, a pixel 10D, and a pixel 10C arranged adjacent in the arrow Y direction and adjacent in the arrow X direction.
  • a total of 10 pixels 10 are constructed as one unit pixel BPGr, and a green filter 42 is arranged in this unit pixel BPGr.
  • the unit pixel BPGr includes a pixel 10, a pixel 10C, a pixel 10B, and a pixel 10A arranged adjacently in the arrow X direction, and a pixel 10D and a pixel 10D arranged adjacently in the arrow X direction. It includes a pixel 10A, and a pixel 10A, a pixel 10B, a pixel 10D, and a pixel 10C arranged adjacent in the arrow Y direction and adjacent in the arrow X direction.
  • the optical lens 5 is arranged on the first surface of the substrate 15 with the color filter 4 interposed therebetween.
  • the optical lens 5 is formed in the direction of the arrow X with a length corresponding to two pixels, and is formed in the direction of the arrow Y with a length corresponding to one pixel ten. That is, the optical lens 5 is formed in an elliptical shape with different aspect ratios in plan view.
  • One optical lens 5 is arranged corresponding to each unit pixel BP.
  • the unit pixel BPGb two pixels 10D and 10A adjacent in the direction of the arrow X and one pixel 10D adjacent in the direction of the arrow Y share the main electrodes 204 of the amplification transistor 21 and the reset transistor 24. It is shared by the connecting section 34 . That is, the shared connection section 34 is arranged over a total of three pixels 10 .
  • the gap between the main electrodes 204 of the amplification transistor 21 and the reset transistor 24 is It is shared by the shared connection section 34 .
  • the shared connection portion 34 is connected to the power supply voltage terminal VDD through the wiring 7 .
  • Components other than the components described above are the same or substantially the same as the components of the solid-state imaging device 1 according to the twelfth embodiment.
  • the technology (the present technology) according to the present disclosure can be applied to various products.
  • the technology according to the present disclosure can be realized as a device mounted on any type of moving body such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility, airplanes, drones, ships, and robots. may
  • FIG. 61 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology according to the present disclosure can be applied.
  • a vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001.
  • the vehicle control system 12000 includes a driving system control unit 12010, a body system control unit 12020, a vehicle exterior information detection unit 12030, a vehicle interior information detection unit 12040, and an integrated control unit 12050.
  • a microcomputer 12051, an audio/image output unit 12052, and an in-vehicle network I/F (Interface) 12053 are illustrated.
  • the drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs.
  • the driving system control unit 12010 includes a driving force generator for generating driving force of the vehicle such as an internal combustion engine or a driving motor, a driving force transmission mechanism for transmitting the driving force to the wheels, and a steering angle of the vehicle. It functions as a control device such as a steering mechanism to adjust and a brake device to generate braking force of the vehicle.
  • the body system control unit 12020 controls the operation of various devices equipped on the vehicle body according to various programs.
  • the body system control unit 12020 functions as a keyless entry system, a smart key system, a power window device, or a control device for various lamps such as headlamps, back lamps, brake lamps, winkers or fog lamps.
  • body system control unit 12020 can receive radio waves transmitted from a portable device that substitutes for a key or signals from various switches.
  • the body system control unit 12020 receives the input of these radio waves or signals and controls the door lock device, power window device, lamps, etc. of the vehicle.
  • the vehicle exterior information detection unit 12030 detects information outside the vehicle in which the vehicle control system 12000 is installed.
  • the vehicle exterior information detection unit 12030 is connected with an imaging section 12031 .
  • the vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image of the exterior of the vehicle, and receives the captured image.
  • the vehicle exterior information detection unit 12030 may perform object detection processing or distance detection processing such as people, vehicles, obstacles, signs, or characters on the road surface based on the received image.
  • the imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of received light.
  • the imaging unit 12031 can output the electric signal as an image, and can also output it as distance measurement information.
  • the light received by the imaging unit 12031 may be visible light or non-visible light such as infrared rays.
  • the in-vehicle information detection unit 12040 detects in-vehicle information.
  • the in-vehicle information detection unit 12040 is connected to, for example, a driver state detection section 12041 that detects the state of the driver.
  • the driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 detects the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041. It may be calculated, or it may be determined whether the driver is dozing off.
  • the microcomputer 12051 calculates control target values for the driving force generator, the steering mechanism, or the braking device based on the information inside and outside the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and controls the drive system control unit.
  • a control command can be output to 12010 .
  • the microcomputer 12051 realizes the functions of ADAS (Advanced Driver Assistance System) including collision avoidance or shock mitigation, follow-up driving based on inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, or vehicle lane deviation warning. Cooperative control can be performed for the purpose of ADAS (Advanced Driver Assistance System) including collision avoidance or shock mitigation, follow-up driving based on inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, or vehicle lane deviation warning. Cooperative control can be performed for the purpose of ADAS (Advanced Driver Assistance System) including collision avoidance or shock mitigation, follow-up driving based on inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, or vehicle
  • the microcomputer 12051 controls the driving force generator, the steering mechanism, the braking device, etc. based on the information about the vehicle surroundings acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, so that the driver's Cooperative control can be performed for the purpose of autonomous driving, etc., in which vehicles autonomously travel without depending on operation.
  • the microcomputer 12051 can output a control command to the body system control unit 12030 based on the information outside the vehicle acquired by the information detection unit 12030 outside the vehicle.
  • the microcomputer 12051 controls the headlamps according to the position of the preceding vehicle or the oncoming vehicle detected by the vehicle exterior information detection unit 12030, and performs cooperative control aimed at anti-glare such as switching from high beam to low beam. It can be carried out.
  • the audio/image output unit 12052 transmits at least one of audio and/or image output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle.
  • an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are illustrated as output devices.
  • the display unit 12062 may include at least one of an on-board display and a head-up display, for example.
  • FIG. 62 is a diagram showing an example of the installation position of the imaging unit 12031.
  • the imaging unit 12031 has imaging units 12101, 12102, 12103, 12104, and 12105.
  • the imaging units 12101, 12102, 12103, 12104, and 12105 are provided at positions such as the front nose, side mirrors, rear bumper, back door, and windshield of the vehicle 12100, for example.
  • An image pickup unit 12101 provided in the front nose and an image pickup unit 12105 provided above the windshield in the passenger compartment mainly acquire images in front of the vehicle 12100 .
  • Imaging units 12102 and 12103 provided in the side mirrors mainly acquire side images of the vehicle 12100 .
  • An imaging unit 12104 provided in the rear bumper or back door mainly acquires an image behind the vehicle 12100 .
  • the imaging unit 12105 provided above the windshield in the passenger compartment is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, and the like.
  • FIG. 62 shows an example of the imaging range of the imaging units 12101 to 12104.
  • FIG. The imaging range 12111 indicates the imaging range of the imaging unit 12101 provided in the front nose
  • the imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided in the side mirrors, respectively
  • the imaging range 12114 The imaging range of an imaging unit 12104 provided on the rear bumper or back door is shown. For example, by superimposing the image data captured by the imaging units 12101 to 12104, a bird's-eye view image of the vehicle 12100 viewed from above can be obtained.
  • At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information.
  • at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.
  • the microcomputer 12051 determines the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and changes in this distance over time (relative velocity with respect to the vehicle 12100). , it is possible to extract, as the preceding vehicle, the closest three-dimensional object on the traveling path of the vehicle 12100, which runs at a predetermined speed (for example, 0 km/h or more) in substantially the same direction as the vehicle 12100. can. Furthermore, the microcomputer 12051 can set the inter-vehicle distance to be secured in advance in front of the preceding vehicle, and perform automatic brake control (including following stop control) and automatic acceleration control (including following start control). In this way, cooperative control can be performed for the purpose of automatic driving in which the vehicle runs autonomously without relying on the operation of the driver.
  • automatic brake control including following stop control
  • automatic acceleration control including following start control
  • the microcomputer 12051 converts three-dimensional object data related to three-dimensional objects to other three-dimensional objects such as motorcycles, ordinary vehicles, large vehicles, pedestrians, and utility poles. It can be classified and extracted and used for automatic avoidance of obstacles. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into those that are visible to the driver of the vehicle 12100 and those that are difficult to see. Then, the microcomputer 12051 judges the collision risk indicating the degree of danger of collision with each obstacle, and when the collision risk is equal to or higher than the set value and there is a possibility of collision, an audio speaker 12061 and a display unit 12062 are displayed. By outputting an alarm to the driver via the drive system control unit 12010 and performing forced deceleration and avoidance steering via the drive system control unit 12010, driving support for collision avoidance can be performed.
  • At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays.
  • the microcomputer 12051 can recognize a pedestrian by determining whether or not the pedestrian exists in the captured images of the imaging units 12101 to 12104 .
  • recognition of a pedestrian is performed by, for example, a procedure for extracting feature points in images captured by the imaging units 12101 to 12104 as infrared cameras, and performing pattern matching processing on a series of feature points indicating the outline of an object to determine whether or not the pedestrian is a pedestrian.
  • the audio image output unit 12052 outputs a rectangular outline for emphasis to the recognized pedestrian. is superimposed on the display unit 12062 . Also, the audio/image output unit 12052 may control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.
  • the technology according to the present disclosure can be applied to the imaging unit 12031 among the configurations described above.
  • the imaging unit 12031 By applying the technology according to the present disclosure to the imaging unit 12031, the imaging unit 12031 with a simpler configuration can be realized.
  • the present technology is not limited to the above embodiments, and can be modified in various ways without departing from the scope of the present technology.
  • two or more of the solid-state imaging devices according to the embodiments may be combined.
  • the present technology for example, in the solid-state imaging device according to the eighteenth embodiment, the number of groups of pixels forming a unit pixel and the arrangement layout of the unit pixels can be changed as appropriate.
  • this technology is not limited to imaging applications, and can be widely applied to light receiving devices, photoelectric conversion devices, light detection devices, etc. used for sensing applications.
  • the solid-state imaging device is not limited to incident light of visible light, and incident light such as infrared light, ultraviolet light, and electromagnetic waves may be used.
  • the present technology may be configured such that a bandpass filter or the like is arbitrarily provided above the light incident side of the photoelectric conversion element to receive desired incident light.
  • a solid-state imaging device includes a first pixel, a pixel isolation region, a first transistor, a first floating diffusion region, a first transfer gate electrode, or a first substrate connecting portion.
  • the first pixel is arranged on the first surface side, which is the light incident side of the substrate, and has a first photoelectric conversion element that converts light into charge.
  • the pixel separation region is formed in the thickness direction of the substrate and extends in the first direction and the second direction crossing the first direction when viewed from the second surface side opposite to the first surface of the substrate. surrounds the sides of the first pixel to electrically and optically isolate the first pixel from other regions.
  • the first transistor is disposed on a second surface of the substrate surrounded by the pixel isolation region at a position corresponding to the first pixel, and has a gate length direction slanted with respect to the first direction or the second direction; Process the converted charge.
  • the first floating diffusion region, the first transfer gate electrode, or the first substrate connecting portion is arranged in the gate width direction of the first transistor on the second surface of the substrate at a position corresponding to the first pixel.
  • the first transfer gate electrode is the gate electrode of the first transfer transistor that transfers charges from the first pixel to the first floating diffusion region.
  • the first substrate connection supplies a voltage to the substrate.
  • a solid-state imaging device includes a first pixel, a pixel isolation region, a first transistor, a second transistor, a first floating diffusion region, a first transfer gate electrode, or a first substrate connection. and a part.
  • the first pixel is arranged on the first surface side, which is the light incident side of the substrate, and has a first photoelectric conversion element that converts light into charge.
  • the pixel separation region is formed in the thickness direction of the substrate and extends in the first direction and the second direction crossing the first direction when viewed from the second surface side opposite to the first surface of the substrate. surrounds the sides of the first pixel to electrically and optically isolate the first pixel from other regions.
  • the first transistor is disposed on a second surface of the substrate surrounded by the pixel isolation region at a position corresponding to the first pixel, and has a gate length direction slanted with respect to the first direction or the second direction; Process the converted charge.
  • the second transistor is disposed on the second surface of the substrate surrounded by the pixel isolation region at a position corresponding to the first pixel, and has a gate length direction slanted with respect to the first direction or the second direction; It is electrically connected in series with the first transistor.
  • the first floating diffusion region, the first transfer gate electrode, or the first substrate connecting portion is arranged in the gate width direction of the first transistor and the second transistor on the second surface of the substrate at a position corresponding to the first pixel. .
  • the first transfer gate electrode is the gate electrode of the first transfer transistor that transfers charges from the first pixel to the first floating diffusion region.
  • the first substrate connection supplies a voltage to the substrate.
  • a solid-state imaging device includes pixels, pixel separation regions, transistors, floating diffusion regions, transfer gate electrodes, or first substrate connection portions.
  • the pixels are arranged on the first surface side of the substrate, which is the light incident side, and have photoelectric conversion elements that convert light into electric charges.
  • the pixel isolation region is formed in the thickness direction of the substrate, surrounds the side surfaces of the plurality of pixels, and electrically and optically isolates the plurality of pixels.
  • the transistor is arranged on the second surface of the substrate surrounded by the pixel isolation region at a position corresponding to the pixel, and the gate length direction is slanted with respect to the pixel arrangement direction, and the converted charge is processed. .
  • a floating diffusion region, a transfer gate electrode, or a first substrate connecting portion is arranged in the gate width direction of the transistor on the second surface of the substrate at a position corresponding to the pixel.
  • a transfer gate electrode is a gate electrode of a transfer transistor that transfers charges from a pixel to a floating diffusion region.
  • the first substrate connection supplies a voltage to the substrate.
  • a solid-state imaging device includes a first pixel, a second pixel, a pixel isolation region, a first transistor, a second transistor, and a shared connection section.
  • the first pixel is arranged on the first surface side, which is the light incident side of the substrate, and has a first photoelectric conversion element that converts light into charge.
  • the second pixel is adjacent to the first pixel, is arranged on the first surface side of the substrate, and has a second photoelectric conversion element that converts light into charge.
  • the pixel isolation region is disposed between the first pixel and the second pixel, is formed in the thickness direction of the substrate, and electrically and optically isolates the first pixel and the second pixel.
  • the first transistor is disposed on the second surface of the substrate at a position corresponding to the first pixel, has a gate length direction slanted with respect to the arrangement direction of the first pixel and the second pixel, and processes converted charges.
  • the second transistor is arranged on the second surface of the substrate at a position corresponding to the second pixel, has a gate length direction slanted with respect to the arrangement direction of the first pixel and the second pixel, and processes converted charges. do.
  • the shared connection is electrically directly connected to one of the pair of main electrodes of the first transistor and one of the pair of main electrodes of the second transistor to supply a power supply voltage.
  • the present technology has the following configuration. According to the present technology having the following configuration, it is possible to increase the area for arranging transistors and improve the performance of the transistors in the solid-state imaging device.
  • a first pixel having a first photoelectric conversion element disposed on the first surface side of the substrate, which is the light incident side, for converting light into electric charge; formed in the thickness direction of the base body and extending in a first direction and a second direction crossing the first direction when viewed from the side of a second surface opposite to the first surface of the base body; a pixel isolation region surrounding a side periphery of a first pixel and electrically and optically isolating the first pixel from other regions; It is disposed on the second surface side of the substrate surrounded by the pixel isolation region at a position corresponding to the first pixel, and the gate length direction is slanted with respect to the first direction or the second direction.
  • a solid-state imaging device with The solid-state imaging device according to (1), wherein the first floating diffusion region, the first transfer gate electrode, or the first substrate connection portion is disposed with an element isolation region interposed with respect to the first transistor.
  • the pixel isolation region includes a first groove formed from the second surface of the substrate toward the first surface, and a first embedding member embedded in the first groove.
  • the element isolation region is formed from the second surface of the base to the first surface, and includes a second groove shallower than the first groove, and a second buried buried in the second groove.
  • the first pixels are partitioned by the pixel isolation regions and formed in a rectangular shape when viewed from the second surface side, a pair of main electrodes of the first transistor are arranged so as to coincide with diagonal lines of the rectangular shape of the first pixel;
  • the first floating diffusion region, the first transfer gate electrode, or the first base connecting portion are arranged in alignment with or along another diagonal line that intersects the diagonal line.
  • a second transistor formed in a line-symmetrical shape with respect to the first transistor, with At a position corresponding to the second pixel, the first floating diffusion region, the first transfer gate electrode, or the first substrate connection centering on the pixel isolation region between the first pixel and the second pixel A voltage is supplied to a second floating diffusion region formed in a line-symmetrical shape with respect to the part, a second transfer gate electrode of a second transfer transistor that transfers charges from the second pixel to the second floating diffusion region, or the substrate.
  • the solid-state imaging device according to any one of (1) to (5) above, further comprising a second base connecting portion that connects to the second substrate.
  • One of a pair of main electrodes of the first transistor and one of a pair of main electrodes of the second transistor, the first floating diffusion region and the second floating diffusion region, the first substrate connection portion and the second substrate connection The solid-state imaging device according to (7), wherein at least one of the portions is shared by a shared connection portion that is disposed across the pixel isolation region and electrically directly connected.
  • One end of the shared connection portion is directly connected to a side surface of one of the main electrodes of the first transistor, a side surface of the first floating diffusion region, or a side surface of the first substrate connection portion.
  • Imaging device (10) The solid-state imaging device according to (8) or (9), wherein the shared connection portion is embedded in a shared groove formed from the second surface of the pixel isolation region toward the first surface.
  • one end of the shared connection portion is directly connected to the surface of one of the main electrodes of the first transistor, the surface of the first floating diffusion region, or the surface of the first substrate connection portion; The other end of the shared connection portion is directly connected to the surface of one of the main electrodes of the second transistor, the surface of the second floating diffusion region, or the surface of the second substrate connection portion.
  • the solid-state imaging device according to any one of (8) to (11), wherein the shared connection portion is a gate electrode material.
  • the third photoelectric conversion element is disposed on the first surface side of the base with the pixel isolation region interposed therebetween, and converts light into electric charge.
  • a third pixel The pixel isolation region is disposed on the second surface side of the substrate surrounded by the pixel isolation region at a position corresponding to the third pixel and between the first pixel and the third pixel.
  • a third transistor formed in a line-symmetrical shape with respect to the first transistor, At a position corresponding to the third pixel, the first floating diffusion region, the first transfer gate electrode, or the first substrate connection centering on the pixel separation region between the first pixel and the third pixel
  • a voltage is supplied to a third floating diffusion region formed in a line-symmetrical shape with respect to the part, a third transfer gate electrode of a third transfer transistor that transfers charges from the third pixel to the third floating diffusion region, or the substrate.
  • the solid-state imaging device further comprising a third base connecting portion that (14) Adjacent to the third pixel in the first direction and arranged on the first surface side of the base with the pixel isolation region interposed therebetween, a fourth photoelectric conversion element for converting light into electric charge is provided.
  • a fourth pixel Adjacent to the third pixel in the first direction and arranged on the first surface side of the base with the pixel isolation region interposed therebetween, a fourth photoelectric conversion element for converting light into electric charge is provided.
  • a fourth pixel Adjacent to the third pixel in the first direction and arranged on the first surface side of the base with the pixel isolation region interposed therebetween, a fourth photoelectric conversion element for converting light into electric charge is provided.
  • a fourth pixel Adjacent to the third pixel in the first direction and arranged on the first surface side of the base with the pixel isolation region interposed therebetween, a fourth photoelectric conversion element for converting light into electric charge is provided.
  • a fourth pixel Adjacent to
  • a fourth transistor formed in a line-symmetrical shape with respect to the third transistor, with At a position corresponding to the fourth pixel, the third floating diffusion region, the third transfer gate electrode, or the third substrate connection centering on the pixel isolation region between the third pixel and the fourth pixel A voltage is supplied to a fourth floating diffusion region formed in a line-symmetrical shape with respect to the part, a fourth transfer gate electrode of a fourth transfer transistor that transfers charges from the fourth pixel to the fourth floating diffusion region, or the substrate.
  • the first transistor, the second transistor, the third transistor, and the fourth transistor are any one of an amplification transistor, a selection transistor, a floating diffusion conversion gain switching transistor, and a reset transistor, which constitute a pixel circuit.
  • (17) Adjacent to the first pixel in the first direction and arranged on the first surface side of the substrate with the pixel isolation region interposed therebetween, a second photoelectric conversion element for converting light into electric charge is provided.
  • a second pixel a second transistor disposed on the second surface side of the substrate surrounded by the pixel isolation region at a position corresponding to the second pixel and formed in the same shape as the first transistor; , a second floating diffusion region formed in the same shape as the first floating diffusion region, the first transfer gate electrode, or the first substrate connecting portion at a position corresponding to the second pixel;
  • the solid-state imaging device according to (1) further comprising a second transfer gate electrode of a second transfer transistor that transfers charge to a second floating diffusion region or a second substrate connection portion that supplies a voltage to the substrate.
  • At least one of the first transistor, the second transistor, the third transistor, and the fourth transistor extends the end portion of the gate electrode in the gate width direction from the second surface of the substrate toward the first surface.
  • the solid-state imaging device according to (15) above which has a fin-shaped structure provided with a fin.
  • the planar shape of the first transfer gate electrode is circular, elliptical, triangular, rectangular, or polygonal with pentagons or more.
  • a solid-state imaging device comprising: a first transfer gate electrode of a first transfer transistor that transfers charge to a floating diffusion region; or a first substrate connecting portion that supplies a voltage to the substrate.
  • (22) a plurality of pixels arranged on the first surface side of the substrate, which is the light incident side, and having a photoelectric conversion element that converts light into an electric charge; and a pixel isolation region formed in the thickness direction of the base, surrounding side surfaces of the plurality of pixels, and electrically and optically isolating the plurality of pixels; a transistor disposed on the second surface side of the substrate surrounded by the pixel isolation region at a position corresponding to the pixel, and having a gate length direction oblique to the pixel arrangement direction; a floating diffusion region disposed in a gate width direction of the transistor on the second surface side of the substrate at a position corresponding to the pixel; and a transfer gate electrode of a transfer transistor that transfers charges from the pixel to the floating diffusion region.
  • a first pixel having a first photoelectric conversion element disposed on the first surface side of the substrate, which is the light incident side, for converting light into electric charge; a second pixel adjacent to the first pixel, disposed on the first surface side of the substrate, and having a second photoelectric conversion element that converts light into electric charge; a pixel disposed between the first pixel and the second pixel, formed in the thickness direction of the substrate, and electrically and optically separating the first pixel and the second pixel from each other; an isolation region; a first transistor disposed on the second surface side of the substrate at a position corresponding to the first pixel and having a gate length direction oblique to an arrangement direction of the first pixel and the second pixel; a second transistor disposed on the second surface side of the substrate at a position corresponding to the second pixel and having a gate length direction oblique to the arrangement direction of the first pixel and the second pixel; A solid-state imaging
  • One end of the shared connection is connected to one side of the main electrode of the first transistor, and the other end of the shared connection is connected to one of the main electrodes of the second transistor.
  • the solid-state imaging device according to (23). The solid-state imaging device according to (23) or (24), wherein the shared connection portion is embedded in a shared groove formed from the second surface of the pixel isolation region toward the first surface.
  • One end of the shared connection is connected to the surface of one of the main electrodes of the first transistor, and the other end of the shared connection is connected to the surface of one of the main electrodes of the second transistor.
  • the second transistor is formed in a line-symmetrical shape with respect to the first transistor, centering on the pixel isolation region between the first pixel and the second pixel; one main electrode of the first transistor and one main electrode of the second transistor are closer than the other main electrode of the first transistor and the other main electrode of the second transistor;
  • the other first pixel and the other second pixel adjacent to the first pixel and the second pixel in a direction crossing the arrangement direction of the first pixel and the second pixel are arranged in the arrangement direction

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EP22926122.7A EP4481824A4 (en) 2022-02-14 2022-12-27 SEMICONDUCTOR IMAGING DEVICE
US18/835,910 US20250151430A1 (en) 2022-02-14 2022-12-27 Solid-state imaging device
CN202280091196.2A CN118715616A (zh) 2022-02-14 2022-12-27 固态摄像装置
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