WO2023144999A1

WO2023144999A1 - Topological insulator, quantum bit, method for producing topological insulator, and method for producing quantum bit

Info

Publication number: WO2023144999A1
Application number: PCT/JP2022/003313
Authority: WO
Inventors: 大伴真名歩
Original assignee: 富士通株式会社
Priority date: 2022-01-28
Filing date: 2022-01-28
Publication date: 2023-08-03
Also published as: JPWO2023144999A1

Abstract

A topological insulator according to the present invention contains a first material, the electrical properties of which change in accordance with the width, while having a first region that extends in a first direction and a second region that is provided on the surface of the first region and contains an oxide of the first material; and the first region has such a width that the electrical properties of the first region are those of a semiconductor. A quantum bit according to the present invention is provided with a first Majorana particle carrier that contains a topological insulator and extends in a first direction, and a superconductor that is in contact with the first Majorana particle carrier; the first Majorana particle carrier contains a first material, the electrical properties of which change in accordance with the width, while having a first region that extends in the first direction and a second region that is provided on the surface of the first region and contains an oxide of the first material; and the first region has such a width that the electrical properties of the first region are those of a semiconductor.　

Description

Topological insulator, qubit, method of manufacturing topological insulator, and method of manufacturing qubit

The present invention relates to a topological insulator, a qubit, a method for manufacturing a topological insulator, and a method for manufacturing a qubit.

Research is being conducted on quantum computers using Majorana particles. Various techniques have been proposed as methods for expressing Majorana particles. For example, a technique has been proposed to express Majorana particles using a nanowire structure such as a semiconductor (for example, Patent Documents 1 to 3).

JP 2020-96107 A U.S. Patent Application Publication No. 2014/0221059 U.S. Patent Application Publication No. 2013/0299783

Topological superconductors are known as substances that express Majorana particles. However, at present, no good candidates for topological superconductors have been found, so research is being conducted to bring s-wave superconductors into contact with topological insulators and induce superconductivity by the proximity effect. As a topological insulator, it is desired that a gapless state appears on the surface and edges, while the inside has an insulating or semiconducting property so that a conduction mode is difficult to form.

One aspect aims to achieve both the emergence of a gapless state and the suppression of the generation of internal conduction modes.

In one aspect, a first region including a first material whose electrical properties change according to width and extending in a first direction; and an oxide of the first material provided on a surface of the first region. wherein the first region is a topological insulator having a width such that the electrical properties of the first region are semiconductor properties.

As one aspect, it is possible to achieve both the emergence of a gapless state and the suppression of the generation of internal conduction modes.

FIG. 1(a) is a plan view showing the appearance position of the gapless state of a single tungsten ditelluride (WTe ₂ ) layer, and FIG. 1(b) shows the appearance position of the gapless state of a multilayer WTe ₂ layer. It is a perspective view. Fig. 2(a) is a plan view showing the positions of Majorana grains expressed in the single _WTe bilayer, and Fig. ₂ (b) is a perspective view showing the positions of Majorana grains expressed in the multilayer WTe bilayer. is. FIG. 3(a) is a perspective view showing a bulk single crystal WTe ₂ layer, and FIG. 3(b) is a perspective view showing a nanowire-like WTe ₂ layer. FIG. 4 shows simulation results of the band structure of bulk _single crystal WTe bilayer. FIG. 5 shows the widthwise crystal structure of the nanowire-like WTe ₂ layer. 6(a) and 6(b) are diagrams (part 1) showing simulation results of the band structure of the nanowire-like WTe _bilayer . 7(a) and 7(b) are diagrams (part ₂ ) showing simulation results of the band structure of the nanowire-like WTe bilayer. 8(a) and 8(b) are diagrams (part 3) showing simulation results of the band structure of the nanowire-like WTe _bilayer . 9(a) and 9(b) are diagrams (part 4) showing simulation results of the band structure of the nanowire-like WTe _bilayer . FIG. 10 is a diagram showing the relationship between the number of unit cells in the width direction and the bandgap obtained from the simulation results of FIGS. 6(a) to 9(b). FIG. 11(a) is a transparent perspective view showing a topological insulator according to Example 1, FIG. 11(b) is a cross-sectional view along line AA in FIG. 11(a), and FIG. It is a BB sectional view of a). 12(a) to 12(c) are perspective views showing a method for manufacturing a topological insulator according to Example 1. FIG. FIG. 13 is a perspective view showing a quantum bit according to Example 2. FIG. FIGS. 14A to 14C are perspective views (part 1) showing the method of manufacturing the quantum bit according to the second embodiment. 15A and 15B are perspective views (part 2) showing the method of manufacturing the quantum bit according to the second embodiment. 16A to 16C are perspective views showing another method of manufacturing a quantum bit according to Example 2. FIG. FIG. 17 is a perspective view of a quantum bit according to a modification of the second embodiment;

Tungsten di-telluride (WTe ₂ ) is a material that is expected to produce Majorana grains. Therefore, first, the appearance position of the gapless state (metallic state) of the single WTe ₂ layer and the multilayer WTe ₂ layer and the appearance position of the Majorana grains will be described. FIG. 1(a) is a plan view showing the appearance position of the gapless state 20 of the single _WTe2 layer 500, and FIG. 1(b) is a perspective view showing the appearance position of the gapless state 20 of the multilayer _WTe2 layer 600. is. In FIGS. 1(a) and 1(b), the length of the WTe _two layers in the lateral direction of the paper surface is assumed to be infinite. As shown in FIG. 1(a), a single _WTe2 layer 500 is called a two-dimensional primary topological insulator, and a one-dimensional gapless state 20 appears at the edge. As shown in FIG. 1(b), the multi-layered _WTe2 layer 600 is what is called a three-dimensional second-order topological insulator, and a one-dimensional gapless state 20 appears at the ridgeline.

FIG. 2(a) is a plan view showing the positions where the Majorana particles 22 appear in the single WTe ₂ layer 500, and FIG. 2(b) shows the positions where the Majorana particles 22 appear in the multilayer WTe ₂ layer 600. It is a perspective view showing the. As shown in FIG. 2( a ), when the s-wave superconductor 30 is brought into contact with the single _WTe2 layer 500 , the s-wave superconductor 30 in the gapless state 20 appears at the edge of the _WTe2 layer 500 . Majorana grains 22 appear in the vicinity. As shown in FIG. 2(b), when the s-wave superconductor 30 is brought into contact with the multi-layered _WTe2 layer 600, Majorana grains appear in the vicinity of the s-wave superconductor 30 in the gapless state 20 appearing on the ridgeline of the _WTe2 layer 600. 22 is expressed. In FIG. 2(b), the gapless state did not appear on the upper right ridgeline in the simulation, so it is not shown here.

A single WTe ₂ layer is easily totally oxidized by natural oxidation. In this case, the gapless state 20 will not appear. In order to suppress oxidation, it is necessary to fabricate the device in an inert gas atmosphere or in a vacuum, and to protect it with a film that suppresses oxygen permeation, which increases the difficulty of the process and makes it difficult to handle. . Multilayered WTe ₂ layers are therefore considered below.

[Multilayer WTe ₂ layers]
3(a) is a perspective view of a bulk single crystal WTe ₂ layer 700, and FIG. 3(b) is a perspective view of a nanowire-like WTe ₂ layer 800. FIG. As shown in FIG. 3A, the bulk single crystal WTe ₂ layer 700 is not particularly limited in size, but for example, the width W and length L are about several tens of μm, and the thickness T is about several tens of nm. . As shown in FIG. 3(b), the nanowire-like WTe ₂ layer 800 has a width W of several nanometers. Although the length L and thickness T are not particularly limited, for example, the length L is several tens of μm and the thickness T is several tens of nm.

The band structures of the bulk single-crystal _WTe2 layer 700 and the nanowire-like _WTe2 layer 800 were calculated by simulation. The simulation was performed by the density functional theory. In the density functional theory, the exchange-correlation potential is treated under the generalized gradient approximation using the PBE (Perdew-Burke-Ernzerhof) exchange energy. Electron-ion interactions are described by norm-conserving pseudopotentials with partial core correction. A pseudo-atomic orbital centered on an atomic site is used as the basis function, and a semi-empirical DFT-D2 method is used for the van der Waals interaction. The structure optimization is performed under three-dimensional periodic boundary conditions, and the convergence condition is that the force acting on each atom is 0.01 eV/Å or less.

FIG. 4 shows simulation results of the band structure of bulk single crystal WTe ₂ layer 700 . G, Y, S, X, and Z on the horizontal axis of FIG. 4 correspond to the G point, Y point, S point, X point, and Z point of the Brillouin zone, respectively. The vertical axis in FIG. 4 is the bandgap. In the simulation of FIG. 4, the direction of the width W of the WTe ₂ layer 700 is taken as the a-axis direction of the crystal, the direction of the length L as the b-axis direction, and the direction of the thickness T as the c-axis direction. The a-axis, b-axis, and c-axis directions were all modeled assuming periodic boundary conditions, and the width W, length L, and thickness T of the WTe2 layer ₇₀₀ were assumed to be infinite. As shown in FIG. 4, the bulk single crystal _WTe2 layer 700 can be confirmed to have a semi-metallic electronic state. In the _WTe2 layer 700, which exhibits semi-metallic properties, conduction modes occur inside the bulk in addition to the gapless states 20 appearing at the ridges. In this case, if the Andreev coupling state occurs via the conduction mode inside the bulk, it becomes difficult to separate it from the development of the Majorana grain 22 . That is, when some kind of signal appears, it becomes difficult to distinguish whether it is caused by Majorana particles or other quasiparticles. For this reason, it is not preferable to use a bulk single-crystal _WTe2 layer as the material for the topological insulator.

FIG. 5 shows the crystal structure along the width W of the nanowire-like WTe ₂ layer 800 . In FIG. 5, the unit cells 40 in the direction of the width W of the _WTe2 layer 800 are illustrated by dotted lines, and the number of the unit cells 40 is nine. As shown in FIG. 5, in the simulation, the direction of the width W of the nanowire-like WTe ₂ layer 800 is taken as the a-axis direction of the crystal, the direction of the length L as the b-axis direction, and the direction of the thickness T as the c-axis direction. The crystal lattice constant in the a-axis direction is about 0.348 nm, the crystal lattice constant in the b-axis direction is about 0.625 nm, and the crystal lattice constant in the c-axis direction is about 1.405 nm. In other words, in this specification, the direction of the smallest lattice constant in the _WTe2 crystal is defined as the a-axis direction, the direction with the second smallest lattice constant as the b-axis direction, and the direction with the largest lattice constant as the c-axis direction.

6(a) to 9(b) show simulation results of the band structure of the nanowire-like _WTe2 layer 800. FIG. G, Y, S, X, and Z on the horizontal axes of FIGS. 6A to 9B correspond to G point, Y point, S point, X point, and Z point of the Brillouin zone, respectively. The vertical axis in FIGS. 6A to 9B is the bandgap. In the simulations of FIGS. 6(a) to 9(b), the width dependence of the band structure was investigated by changing the number N of the unit cells 40 in the direction of the width W (a-axis direction) between 4 and 13. . The b-axis and c-axis directions were modeled assuming periodic boundary conditions, and the length L and thickness T of the _WTe2 layer 800 were assumed to be infinite.

As shown in FIGS. 6(a), 6(b), 7(a), 7(b), and 8(b), the number N of unit cells 40 in the direction of width W (a-axis direction) is 4, 5, 6, 7, 9, it can be confirmed that the nanowire-like WTe2 layer ₈₀₀ has semiconducting properties. As shown in FIGS. 8(a), 9(a), and 9(b), when the number N of the unit cells 40 in the direction of the width W (a-axis direction) is 8, 10, or 13, the nanowire-like It can be seen that the _WTe2 layer 800 has semi-metallic properties. The bandgap was 34 meV in FIG. 6(a), 10 meV in FIG. 6(b), 14 meV in FIG. 7(a), 17 meV in FIG. 7(b), and 8 meV in FIG. 8(b).

FIG. 10 is a diagram showing the relationship between the number N of unit cells 40 in the width direction and the bandgap obtained from the simulation results of FIGS. 6(a) to 9(b). As shown in FIG. 10, the bandgap tends to be large in a series in which the number N of the unit cells 40 is 3n+1 (n is a positive integer) (that is, N=4, 7). On the other hand, in the series where the number N of the unit cells 40 is 3n+2 (n is a positive integer) (that is, N=5, 8), the bandgap tends to be small, and when the number N is 8, the bandgap is closed. In addition, even in a series in which the number N is 3n+1, the bandgap is closed when the number N is 10. From these facts, it can be said that by setting the number N of the unit cells 40 in the a-axis direction to 9 or less, the bandgap can be widened and the properties of a semiconductor can be obtained. It can be said that when the number N of the unit cells 40 in the a-axis direction is 10 or more, the bandgap is closed and the material has semimetal properties.

From this result, when using a nanowire-shaped multilayer _WTe2 layer as a material for a topological insulator, by setting the width W direction of the nanowire as the a-axis direction of the _WTe2 crystal and controlling the number of unit cells in the a-axis direction, It can be said that the occurrence of conduction modes other than the gapless state 20 appearing on the ridgeline can be suppressed, and the occurrence of the Majorana grains 22 can be separated. In addition, since the natural oxidation stops at a few layers on the surface and the inside is not oxidized, it can be said that the use of the nanowire-like multilayer WTe ₂ layer makes it less susceptible to oxidation. Therefore, it can be said that the nanowire-like multilayer WTe ₂ layer is suitable as a material for the topological insulator. Example 1 below provides an example of a topological insulator using nanowire-like multilayer WTe ₂ layers.

11(a) is a see-through perspective view showing the topological insulator 100 according to Example 1, FIG. 11(b) is a cross-sectional view along line AA of FIG. 11(a), and FIG. 11(c) is a cross-sectional view of FIG. It is a BB sectional view of (a). As shown in FIGS. 11( a ) to 11 ( c ), the topological insulator 100 includes a first region 10 that is a nanowire-shaped WTe ₂ layer and a second region 10 that is an oxide layer formed on the surface of the first region 10 . 2 regions 12; The first region 10 extends in a first direction that is the direction of length L, and a second direction that intersects (for example, is perpendicular to) the first direction is the direction of width W. As shown in FIG. The direction of the width W of the first region 10 is the a-axis direction of the _WTe2 crystal, and the direction of the length L is the b-axis direction. The second region 12 is formed by naturally oxidizing the surface of the first region 10 . The second region 12 is made of tungsten oxide (WO ₃ ) and/or tellurium oxide (TeO ₂ ), for example. By using multiple layers of WTe ₂ layers, the native oxidation remains only on the surface and the interior retains the WTe ₂ layers. Therefore, the topological insulator 100 is obtained in which the inside becomes the first region 10 containing WTe ₂ and the second region 12 containing the oxide of WTe ₂ is formed on the surface of the first region 10 . The second region 12 is not limited to being formed on all of the top surface, bottom surface, and side surfaces of the first region 10, and may not be formed on any of the surfaces.

The electrical properties of the first region 10 containing WTe ₂ change according to the width W, as shown in the simulation results of FIGS. 6(a) to 9(b). From the simulation results of FIGS. 6A to 9B, the width W of the first region 10 is preferably such that the number of unit cells 40 in the a-axis direction is 9 or less. Since the length is 3.1 nm when the number of unit cells 40 in the a-axis direction is nine, the width W of the first region 10 is preferably 3.1 nm or less. By having such a width W, the first region 10 exhibits properties of a semiconductor. The thickness of the second region 12 is approximately 2 to 3 nm on all of the top surface, bottom surface and side surfaces of the first region 10 . Therefore, by manufacturing a WTe ₂ layer having a width of about 7 to 9 nm or less, the first region 10 including WTe ₂ and having a width W of 3.1 nm or less and provided on the surface of the first region 10, WTe ₂ and a second region 12 having a thickness of the order of 2-3 nm. That is, the width of the topological insulator 100 is about 7 to 9 nm or less.

The thickness T of the first region 10 may be equal to or greater than the thickness of one layer of WTe ₂ , and may be equal to or greater than 7.07 Å. Therefore, the thickness of the topological insulator 100 is about 4.1 to 6.1 nm or more when the second region 12 is formed on both the upper surface and the lower surface of the first region 10, and is formed only on one side. If there is, it will be about 2.1 to 3.1 nm or more. The upper limit of the thickness T of the first region 10 may be within a range in which manufacturing is possible. For example, when a film containing hydrogen silsesquioxane as a main component is used as a resist film for patterning, as in the manufacturing method described later, the aspect ratio of patterning is about 50:1. In this case, the upper limit of the thickness T of the first region 10 is approximately 500 nm. The length L of the first region 10 is not particularly limited.

[Production method]
12A to 12C are perspective views showing a method of manufacturing the topological insulator 100 according to the first embodiment. As shown in FIG. 12(a), the WTe ₂ single crystal is thinned by repeating tape peeling under an inert atmosphere, and is temporarily attached to a holding substrate. A WTe ₂ film 86 having desired crystals is picked up from the WTe ₂ stuck on the holding substrate by the glass substrate 82 using, for example, a polycarbonate film 84 as an adhesive layer.

As shown in FIG. 12B, a WTe ₂ film 86 picked up using a glass substrate 82 is adhered onto an insulating substrate 80 . At this time, the WTe ₂ crystal is attached so that the crystal orientation matches the desired direction by utilizing the property that the longitudinal direction of the WTe 2 crystal tends to be parallel to the a-axis. The formation of the WTe ₂ film 86 on the substrate 80 may be performed using a molecular beam epitaxy method, a pulsed laser deposition method, or the like.

As shown in FIG. 12C, the _WTe2 film 86 is patterned to form a pattern 87 by photolithography using electron beam exposure and etching using reactive ion etching. The pattern 87 extends in the first direction and the second direction is the width direction. In the photolithography method, for example, a resist film containing hydrogen silsesquioxane as a main component is used, and in the reactive ion etching method, for example, a fluorocarbon gas is used as an etching gas. At this time, patterning is performed so that the width of the pattern 87 is 7 to 9 nm or less. The surface of pattern 87 is naturally oxidized. As a result, as shown in FIG. 11A, a first region 10 having a nanowire shape with a width W of 3.1 nm or less and containing WTe ₂ and an oxide of WTe ₂ formed on the surface of the first region 10 A topological insulator 100 is formed having a second region 12 comprising: In attaching the _WTe2 film 86 to the substrate 80 in FIG. 12(b), the direction of the length L of the topological insulator 100 is the b-axis direction of the crystallographic orientation of _WTe2 , and the direction of the width W is the a-axis direction. so that

According to Example 1, the topological insulator 100 includes a material whose electrical properties change according to the width, the first region 10 extending in the first direction, and provided on the surface of the first region 10, and a second region 12 comprising an oxide of the material contained in the first region 10 . The first region 10 has a width W such that the electrical properties of the first region 10 are those of a semiconductor. As a result, the first region 10 suppresses the occurrence of conduction modes other than the gapless state appearing on the ridgeline. Further, since the influence of natural oxidation stops at the second region 12, the influence of oxidation on the first region 10 is suppressed. Therefore, it is possible to achieve both the emergence of a gapless state and the suppression of the occurrence of internal conduction modes.

Further, in Example 1, the material included in the first region 10 whose electrical properties change according to the width is _WTe2 . As shown in the simulation results of FIGS. 6(a) to 9(b), the electrical properties of WTe ₂ change according to the width, exhibiting the properties of a semiconductor at a given width. Therefore, by using WTe ₂ as the material contained in the first region 10 whose electrical properties change according to the width, it is possible to realize the appearance of the gapless state and the suppression of the occurrence of the internal conduction mode.

Further, in Example 1, the width W of the first region 10 containing WTe ₂ is 3.1 nm or less. At this time, the direction of the width W of the first region 10 is the a-axis direction of WTe ₂ , and the number of unit cells 40 of WTe ₂ in the a-axis direction is 9 or less. As a result, the first region 10 exhibiting semiconductor properties can be obtained as shown in the simulation results of FIGS. 6(a) to 9(b). From the point that the first region 10 exhibits semiconductor properties, as shown in _FIG . is preferred, and 4 or less is more preferred. The length is 2.41 nm when the number of WTe ₂ unit cells 40 in the a-axis direction is seven, and the length is 1.38 nm when the number is four. Therefore, the width W of the first region 10 is preferably 2.41 nm or less, more preferably 1.38 nm or less.

In addition, in Example 1, the thickness T of the first region 10 is equal to or greater than the thickness of one layer of WTe ₂ and equal to or greater than 7.07 Å. As a result, it is possible to realize the appearance of the gapless state and the suppression of the occurrence of the internal conduction mode.

In Example 1, the direction of the length L of the first region 10 is the b-axis direction of the crystal orientation of _WTe2 . In the nanowire-like _WTe2 , a gapless state appears at the ridgeline in the b-axis direction of the crystal orientation. Therefore, by setting the direction of the length L of the first region 10 to the b-axis direction of the crystal orientation of WTe ₂ , it becomes easier to contact the s-wave superconductor layer for developing Majorana grains.

According to the manufacturing method of Example 1, the _WTe2 film 86, which is a material whose electrical properties change according to the width, is formed on the substrate 80 (FIG. 12(b)). The _WTe2 film 86 is patterned to form a pattern 87 extending in the first direction (FIG. 12(c)). The surface of pattern 87 is oxidized to form an oxide of _WTe2 . When forming this oxide, the width W of the region where the WTe ₂ is not oxidized (the first region 10 in FIG. 11(a)) is the width where the electrical properties of the WTe ₂ are those of a semiconductor. As a result, the topological insulator 100 in which the gapless state appears and the generation of the internal conduction mode is suppressed is obtained.

FIG. 13 is a perspective view showing a quantum bit 200 according to Example 2. FIG. As shown in FIG. 13, a qubit 200 includes a nanowire-like Majorana particle carrier layer 50 extending in a first direction, a bulk Majorana particle carrier layer 52 having a longitudinal direction in a second direction, and an s-wave superconducting It includes body layers 60-64 and magnetic layers 70-76. The first direction and the second direction intersect, for example, orthogonally. The s-wave superconductor layers 60-64 are, for example, aluminum (Al) or niobium (Nb) layers with a thickness of 30-50 nm. The magnetic layers 70-76 are, for example, iron (Fe) layers, nickel (Ni) layers, or cobalt (Co) layers with a thickness of 30-50 nm. Although these are provided on a substrate, illustration of the substrate is omitted for clarity of the drawing.

The Majorana particle carrier layer 50 is a nanowire-shaped topological insulator, contains WTe ₂ and extends in a first direction, and has a nanowire-shaped first region 10 provided on the surface of the first region 10 and containing WTe ₂ . and a second region 12 comprising oxide. The second region 12 is formed on the side and top surfaces of the first region 10 . The first region 10, as described in Example 1, has a width exhibiting semiconductor properties. That is, in the first region 10, the width direction (second direction) is the a-axis direction of the crystal orientation of WTe ₂ , the number of unit cells 40 in the a-axis direction is 9 or less, and the width is 3.1 nm or less. have width. As described in Example 1, the thickness of the first region 10 may be equal to or greater than the thickness of one layer of WTe ₂ , and may be equal to or greater than 7.07 Å. In the Majorana grain carrier layer 50, the first direction, which is the length direction, is the b-axis direction of the crystal orientation of WTe ₂ , and the second direction, which is the width direction, is the a-axis direction. A one-dimensional gapless state appears on the ridge extending in one direction.

The s-wave superconductor layer 60 and the magnetic layer 70 are provided in contact with the lower surface of the Majorana particle carrier layer 50 . The width of the s-wave superconductor layer 60 and the magnetic layer 70 is greater than the width of the Majorana grain carrier layer 50 . As a result, as shown in FIG. 2B, Majorana grains appear in the vicinity of the s-wave superconductor layer 60 in the gapless state appearing on the ridgeline of the first region 10 . For example, the on and off of a switch connecting the s-wave superconductor layer 60 to ground can control the development of Majorana particles. The magnetic layer 70 is provided to suppress the influence of the Majorana grains on the Majorana grains appearing at other positions.

The Majorana grain carrier layer 52 is a bulk topological insulator, and is a bulk single crystal WTe ₂ layer having a length direction in the second direction and a third region 54 provided on the surface of the third region 54 . , and a fourth region 56 comprising an oxide of _WTe2 . The fourth region 56 is formed on the side and top surfaces of the third region 54 . One end of the Majorana particle carrier layer 50 is connected to the side surface of the Majorana particle carrier layer 52 extending in the second direction. In the Majorana grain carrier layer 52, the second longitudinal direction is the a-axis direction of the crystal orientation of _WTe2 . In bulk single crystal WTe ₂ , a one-dimensional gapless state appears on the ridge extending in the a-axis direction of the crystal orientation of WTe ₂ . Therefore, a one-dimensional gapless state appears on the ridge extending in the second direction of the third region 54 .

The s-wave superconductor layers 62 and 64 and the magnetic layers 72 to 76 are provided in contact with the lower surface of the Majorana particle carrier layer 52 . The s-wave superconductor layers 62 and 64 and the

magnetic layers

72 and 74 are provided so as to protrude outward from the side surfaces of the Majorana particle carrier layer 52 . Therefore, as shown in FIG. 2(b), Majorana grains appear in the vicinity of the s-wave superconductor layers 62 and 64 in the gapless state appearing on the ridgeline extending in the second direction of the third region 54. FIG. For example, the on and off of switches connecting the s-wave superconductor layers 62, 64 to ground can control the development of Majorana particles. The s-wave superconductor layer 62 and the s-wave superconductor layer 64 are provided, for example, so as to sandwich the portion where the Majorana particle carrier layer 50 connects to the Majorana particle carrier layer 52 in the second direction. The magnetic layers 72 to 76, like the magnetic layer 70, are provided to suppress the influence of the Majorana grains on the Majorana grains appearing at other positions.

[Production method]
14(a) to 15(b) are perspective views showing a method of manufacturing the quantum bit 200 according to the second embodiment. As shown in FIG. 14A, magnetic layers 70 to 76 are formed on an insulating substrate 80 using, for example, a lift-off method. As shown in FIG. 14B, s-wave superconductor layers 60 to 64 are formed on a substrate 80 using, for example, a lift-off method.

As shown in FIG. 14(c), the WTe ₂ single crystal is thinned by repeating tape peeling under an inert atmosphere, and is temporarily attached to a holding substrate. A WTe ₂ film 86 having desired crystals is picked up from the WTe ₂ stuck on the holding substrate by the glass substrate 82 using, for example, a polycarbonate film 84 as an adhesive layer.

As shown in FIG. 15(a), a WTe ₂ film 86 picked up using a glass substrate 82 is adhered onto the substrate 80 so as to cover the s-wave superconductor layers 60-64 and the magnetic layers 70-76. At this time, the crystal orientations of the _WTe2 crystals are matched so that the b-axis direction is the first direction and the a-axis direction is the second direction. The _WTe2 crystal utilizes the property that the longitudinal direction tends to be parallel to the a-axis.

As shown in FIG. 15B, the _WTe2 film 86 is patterned by photolithography using electron beam exposure and etching using reactive ion etching. At this time, the WTe ₂ film 86 is patterned so that the width of the Majorana particle carrier layer 50 is 7 to 9 nm or less. The surface of the _WTe2 film 86 after patterning is naturally oxidized. As a result, a nanowire-shaped first region 10 containing WTe ₂ and extending in the first direction and having a width of 3.1 nm or less, and a second region provided on the surface of the first region 10 and containing an oxide of WTe ₂ 12 and a Majorana grain carrier layer 50 is formed (see also FIG. 13). Further, it has a third region 54 which is bulk single crystal WTe ₂ having a length direction in the second direction, and a fourth region 56 provided on the surface of the third region 54 and containing an oxide of WTe ₂ . A Majorana grain carrier layer 52 is formed (see also FIG. 13). The first direction is the b-axis direction of the crystal orientation of WTe ₂ and the second direction is the a-axis direction.

16(a) to 16(c) are perspective views showing another manufacturing method of the quantum bit 200 according to the second embodiment. As shown in FIG. 16A, s-wave superconductor layers 60 to 64 and magnetic layers 70 to 76 are formed on an insulating substrate 80 by using, for example, a lift-off method. A substrate on which WTe ₂ can be epitaxially grown, such as a magnesium oxide (MgO) substrate, is used as the substrate 80 .

As shown in FIG. 16(b), a _WTe2 film 86 is deposited on the substrate 80 using, for example, molecular beam epitaxy or pulsed laser deposition to cover the s-wave superconductor layers 60-64 and the magnetic layers 70-76. to form As a result, a WTe ₂ film 86 having the crystal orientation b-axis direction in the first direction and the crystal orientation a-axis direction in the second direction is obtained.

As shown in FIG. 16C, the _WTe2 film 86 is patterned by photolithography using electron beam exposure and etching using reactive ion etching. At this time, the WTe ₂ film 86 is patterned so that the width of the Majorana particle carrier layer 50 is 7 to 9 nm or less. The surface of the _WTe2 film 86 after patterning is naturally oxidized. As a result, a nanowire-shaped first region 10 containing WTe ₂ and extending in the first direction and having a width of 3.1 nm or less, and a second region provided on the surface of the first region 10 and containing an oxide of WTe ₂ 12 and a Majorana grain carrier layer 50 is formed (see also FIG. 13). Further, it has a third region 54 which is bulk single crystal WTe ₂ having a length direction in the second direction, and a fourth region 56 provided on the surface of the third region 54 and containing an oxide of WTe ₂ . A Majorana grain carrier layer 52 is formed (see also FIG. 13).

According to the second embodiment, it includes a Majorana particle carrier layer 50 that includes a topological insulator and extends in the first direction, and an s-wave superconductor layer 60 that is in contact with the Majorana particle carrier layer 50 . The Majorana grain carrier layer 50 includes a material whose electrical properties change depending on the width, and includes a first region 10 extending in the first direction, and a material provided on the surface of the first region 10 and included in the first region 10 . and a second region 12 comprising an oxide of a material that can be deposited. The first region 10 has a width such that the electrical properties of the first region 10 are those of a semiconductor. As a result, the first region 10 suppresses the occurrence of conduction modes other than the gapless state appearing on the ridgeline. Further, since the influence of natural oxidation stops at the second region 12, the influence of oxidation on the first region 10 is suppressed. Therefore, in the Majorana grain carrier layer 50, a gapless state appears and the generation of internal conduction mode is suppressed. Therefore, the emergence of the gapless state enables the development of Majorana particles, and the suppression of the occurrence of the internal conduction mode makes it possible to distinguish whether Majorana particles are occurring or not.

In addition, in Example 2, a bulk Majorana particle carrier layer 52 which is a topological insulator connected to the nanowire Majorana particle carrier layer 50, an s-wave superconductor layer 62 in contact with the Majorana

particle carrier layer

52, 64 and. The nanowire-like Majorana particle carrier layer 50 extends in a first direction, and the longitudinal direction of the bulk Majorana particle carrier layer 52 is a second direction that intersects (eg, is perpendicular to) the first direction. The bulk Majorana particle carrier layer 52 includes a bulk third region 54 made of the same material as the first region 10 of the nanowire Majorana particle carrier layer 50, and provided on the surface of the third region 54. and a fourth region 56 comprising an oxide of the material contained in the third region 54 . Thereby, in addition to the nanowire-like Majorana particle carrier layer 50, it is possible to express Majorana particles in the bulk Majorana particle carrier layer 52 as well. For example, the first region 10 and the third region 54 both contain WTe ₂ , the first direction in which the Majorana grain carrier layer 50 extends is the b-axis direction of the crystal orientation of WTe ₂ , and the length of the Majorana grain carrier layer 52 The second direction, which is the longitudinal direction, is the a-axis direction. In this case, a gapless state appears on the ridgeline of the Majorana particle carrier layer 50 extending in the first direction, and a gapless state appears on the ridgeline of the Majorana particle carrier layer 52 extending in the second direction.

Further, according to the manufacturing method of Example 2, the patterned s-wave superconductor layers 60 to 62 are formed on the substrate 80 (FIGS. 14(b) and 16(a)). A WTe ₂ film 86, which is a material whose electrical properties change depending on the width, is formed on the substrate 80 so as to cover the s-wave superconductor layers 60 to 62 (FIGS. 15(a) and 16(b)). ). The _WTe2 film 86 is patterned to form the Majorana grain carrier layer 50, which is a topological insulator in contact with the s-wave superconductor layer 60 (FIGS. 15(b) and 16(c)). The Majorana grain carrier layer 50 includes a first region 10 that includes WTe ₂ , a material whose electrical properties vary according to width, has a width that is semiconducting, and extends in a first direction; a second region 12 provided on the surface of the region 10 and comprising an oxide of _WTe2 (FIG. 13). Thereby, a gapless state appears and the Majorana grain carrier layer 50 in which the generation of the internal conduction mode is suppressed is obtained. Therefore, it becomes possible to express Majorana particles, and it is also possible to distinguish whether Majorana particles are expressed or not.

[Modification]
FIG. 17 is a perspective view showing a quantum bit 210 according to a modified example of the second embodiment. As shown in FIG. 17, a qubit 210 includes a nanowire-shaped Majorana particle carrier layer 50 extending in a first direction and a nanowire-shaped Majorana particle carrier layer 50 extending in a third direction that intersects (for example, is perpendicular to) the first direction. It includes a carrier layer 50a, s-wave superconductor layers 60-66, and magnetic layers 70-76. Although these are provided on a substrate, illustration of the substrate is omitted for clarity of the drawing. Also, the third direction may be the same as or different from the second direction in the second embodiment.

As described above, the Majorana particle _carrier layer 50 is a topological insulator containing WTe ₂ and extending in the first direction. and a second region 12 comprising oxide. _The Majorana particle carrier layer 50a is also a topological insulator and contains WTe ₂ and extends in the third direction. and a second region 12a including. The

first regions

10, 10a, as described in Example 1, have widths that are semiconductor in nature. That is, the

first regions

10 and 10a have 9 or less unit cells 40 in the width direction and have a width of 3.1 nm or less. As described in the first embodiment, the thickness of the

first regions

10 and 10a should be equal to or greater than the thickness of one layer of WTe ₂ , and may be equal to or greater than 7.07 Å.

The s-wave superconductor layers 60 and 66 and the

magnetic layers

70 and 76 are provided in contact with the lower surface of the Majorana particle carrier layer 50 . The widths of the s-wave superconductor layers 60 , 66 and the

magnetic layers

70 , 76 are greater than the width of the Majorana grain carrier layer 50 . Similarly, s-wave superconductor layers 62, 64 and

magnetic layers

72, 74 are provided in contact with the lower surface of Majorana grain carrier layer 50a. The widths of the s-wave superconductor layers 62, 64 and the

magnetic layers

72, 74 are greater than the width of the Majorana grain carrier layer 50a. As a result, Majorana grains appear in the vicinity of the s-wave superconductor layers 60 to 66 in the gapless state appearing on the ridgelines of the

first regions

10 and 10a.

The quantum bit 210 of the modification of Example 2 can be manufactured by the same method as the quantum bit 200 of Example 2 described in FIGS. 14(a) to 16(c).

In the modification of the second embodiment, the nanowire-shaped Majorana particle carrier layer 50 extending in the first direction and the nanowire-shaped Majorana particle carrier layer 50a extending in the third direction crossing the Majorana particle carrier layer 50 are provided. , provided. Even in this case, the Majorana particle carrier layers 50 and 50a exhibit a gapless state and suppress the generation of the internal conduction mode, so that the Majorana particles can be developed and whether or not the Majorana particles are generated can be determined. It is possible to distinguish.

In Examples 1 and 2 and their modifications, if the

first regions

10 and 10a are made of a material whose electrical properties change according to the width and have semiconductor properties at a predetermined width, It may be formed of a material other than _WTe2 .

Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and variations can be made within the scope of the gist of the present invention described in the scope of claims. Change is possible.

10, 10a

first region

12, 12a second region 20 gapless state 22 Majorana particles 30 s-wave superconductor 40

unit lattice

50, 50a Majorana particle carrier layer 52 Majorana particle carrier layer 54 third region 56 fourth region 60-64 S-wave superconductor layer 70-76 Magnetic layer 80 Substrate 82 Glass substrate 84 Polycarbonate film 86 WTe ₂ film 100

Topological insulator

200, 210 Qubit 500 Single layer WTe ₂ layer 600 Multilayer WTe ₂ layer 700 Bulk single crystal WTe _bilayer of 800 Nanowire-like WTe _bilayer

Claims

a first region that includes a first material whose electrical properties vary with width and that extends in a first direction;
a second region provided on the surface of the first region and containing an oxide of the first material;
The first region is a topological insulator having a width such that the electrical properties of the first region are those of a semiconductor.
The topological insulator according to claim 1, wherein the first material is tungsten ditelluride.
The topological insulator according to claim 2, wherein the width of the first region is 3.1 nm or less.
4. The direction of the width of the first region is the a-axis direction of the crystal orientation of the tungsten ditelluride, and the unit cell number of the tungsten ditelluride in the a-axis direction is 9 or less. The topological insulator described in .
The topological insulator according to any one of claims 2 to 4, wherein the first region has a thickness of 7.07 Å or more.
The topological insulator according to any one of claims 2 to 5, wherein the first direction is the b-axis direction of the crystal orientation of the tungsten ditelluride.
a first Majorana-grain carrier comprising a topological insulator and extending in a first direction;
a superconductor in contact with the first Majorana particle carrier;
The first Majorana particle carrier is
a first region including a first material whose electrical properties vary with width and extending in the first direction;
a second region provided on the surface of the first region and containing an oxide of the first material;
The first region has a width such that the electrical property of the first region is a property of a semiconductor.
The qubit according to claim 7, wherein the first material is tungsten ditelluride.
a second Majorana-particle carrier including a topological insulator connected to the first Majorana-particle carrier and extending in a second direction intersecting the first direction;
a superconductor in contact with the second Majorana particle carrier;
The second Majorana particle carrier is
a third region formed of the first material;
9. A qubit according to claim 7 or 8, comprising a fourth region provided on the surface of said third region and comprising an oxide of said first material.
the first material is tungsten ditelluride;
The first direction is the b-axis direction of the crystal orientation of the tungsten ditelluride,
10. The qubit of claim 9, wherein the second direction is the crystal orientation a-axis direction of the tungsten ditelluride.
a third Majorana particle carrier extending across the first Majorana particle carrier in a third direction that intersects the first direction;
The third Majorana particle carrier is
a fifth region including the first material and extending in the third direction;
a sixth region provided on the surface of the fifth region and containing an oxide of the first material;
9. The qubit according to claim 7 or 8, wherein the fifth region has a width such that the electrical properties of the fifth region are semiconductor properties.
forming on a substrate a film containing a first material whose electrical properties vary according to width;
patterning the film to form a first pattern extending in a first direction;
oxidizing the surface of the first pattern to form an oxide of the first material;
The method of manufacturing a topological insulator, wherein in the step of forming the oxide, the width of the region where the first material is not oxidized is the width at which the electrical properties of the first material are those of a semiconductor.
A method of fabricating a qubit comprising Majorana particle carriers that are topological insulators extending in a first direction over a substrate, comprising:
forming a patterned superconductor on the substrate;
forming a film comprising a first material whose electrical properties vary according to width on the substrate so as to cover the superconductor;
A first region is formed by patterning the film to contact the superconductor and includes the first material having a width such that the electrical property is that of a semiconductor; and forming said Majorana particle carrier being a topological insulator having a second region comprising an oxide of a first material.