WO2023047460A1

WO2023047460A1 - Majorana quantum bit and quantum computer

Info

Publication number: WO2023047460A1
Application number: PCT/JP2021/034577
Authority: WO
Inventors: 真名歩大伴; 研一河口
Original assignee: 富士通株式会社
Priority date: 2021-09-21
Filing date: 2021-09-21
Publication date: 2023-03-30
Also published as: JPWO2023047460A1

Abstract

This Majorana quantum bit has a first topological insulator layer comprising a first edge; a first s-wave superconductor layer; and a first layer that is disposed between the first edge and the first s-wave superconductor layer and that enables the penetration of Cooper pairs via a proximity effect from the first s-wave superconductor layer to the first edge.

Description

Majorana qubits and quantum computers

This disclosure relates to Majorana qubits and quantum computers.

Research is being conducted on quantum computers using Majorana particles. A technique using a two-dimensional topological insulator has been proposed as a technique for generating Majorana particles. In this technique, an s-wave superconductor is brought into contact with a topological insulator, and Majorana particles are generated by tunneling Cooper pairs from the s-wave superconductor to the topological insulator.

Japanese Patent Publication No. 2020-511780 U.S. Patent Application Publication No. 2020/0098990

　In the conventional technology using a two-dimensional topological insulator, the electronic state of the topological insulator may be damaged, and Majorana particles may not occur.

The purpose of the present disclosure is to provide a Majorana qubit and a quantum computer that can stably generate Majorana particles.

According to one aspect of the present disclosure, a first topological insulator layer with a first edge, a first s-wave superconductor layer, and between said first edge and said first s-wave superconductor layer: and a first layer capable of penetration of Cooper pairs from said first s-wave superconductor layer to said first edge by proximity effect.

According to the present disclosure, Majorana particles can be stably generated.

FIG. 1 is a top view showing a quantum bit according to the first embodiment. FIG. FIG. 2 is a cross-sectional view showing the quantum bit according to the first embodiment. FIG. 3 shows the density of states of h-BN in contact with Nb. FIG. 4 is a top view showing a quantum bit according to a reference example. FIG. 5 is a cross-sectional view showing a quantum bit according to a reference example. FIG. 6 is a diagram showing an intensity map of spectral weights of WTe ₂ in the reference example. FIG. 7 is a diagram showing band structures of WTe ₂ and Nb in the reference example. FIG. 8 shows the band structure of WTe ₂ without external influences. FIG. 9 is a perspective view showing a quantum bit according to the second embodiment. FIG. 10 is a top view showing a quantum bit according to the second embodiment. FIG. 11 is a cross-sectional view (No. 1) showing the quantum bit according to the second embodiment. FIG. 12 is a cross-sectional view (Part 2) showing the quantum bit according to the second embodiment. FIG. 13 is a top view (No. 1) showing the manufacturing method of the quantum bit 2 according to the second embodiment. FIG. 14 is a top view (No. 2) showing the manufacturing method of the quantum bit 2 according to the second embodiment. FIG. 15 is a top view (No. 3) showing the manufacturing method of the quantum bit 2 according to the second embodiment. FIG. 16 is a top view (No. 4) showing the manufacturing method of the quantum bit 2 according to the second embodiment. FIG. 17 is a top view (No. 5) showing the manufacturing method of the quantum bit 2 according to the second embodiment. FIG. 18 is a top view (No. 6) showing the manufacturing method of the quantum bit 2 according to the second embodiment. FIG. 19 is a top view (No. 7) showing the manufacturing method of the quantum bit 2 according to the second embodiment. FIG. 20 is a top view (No. 8) showing the manufacturing method of the quantum bit 2 according to the second embodiment. FIG. 21 is a top view (No. 9) showing the manufacturing method of the quantum bit 2 according to the second embodiment. FIG. 22 is a top view (No. 10) showing the manufacturing method of the quantum bit 2 according to the second embodiment. FIG. 23 is a top view (No. 11) showing the manufacturing method of the quantum bit 2 according to the second embodiment. FIG. 24 is a schematic diagram (Part 1) showing a method of manufacturing a quantum bit according to the third embodiment. FIG. 25 is a schematic diagram (Part 2) showing the method of manufacturing the quantum bit according to the third embodiment. FIG. 26 is a schematic diagram (No. 3) showing the method of manufacturing the quantum bit according to the third embodiment. FIG. 27 is a schematic diagram (part 4) showing the method of manufacturing the quantum bit according to the third embodiment. FIG. 28 is a schematic diagram (No. 5) showing the method of manufacturing the quantum bit according to the third embodiment. FIG. 29 is a schematic diagram showing a quantum bit according to the fourth embodiment. FIG. 30 is a diagram showing a quantum computer according to the fifth embodiment; FIG. 31 is a schematic diagram showing a qubit including a higher topological insulator layer.

Hereinafter, embodiments of the present disclosure will be specifically described with reference to the attached drawings. In the present specification and drawings, constituent elements having substantially the same functional configuration may be denoted by the same reference numerals, thereby omitting redundant description.

(First embodiment)
First, the first embodiment will be described. A first embodiment relates to a qubit containing a two-dimensional topological insulator. FIG. 1 is a top view showing a quantum bit according to the first embodiment. FIG. FIG. 2 is a cross-sectional view showing the quantum bit according to the first embodiment. FIG. 2 corresponds to a cross-sectional view taken along line II-II in FIG.

The quantum bit 1 according to the first embodiment has a topological insulator layer 10, an s-wave superconductor layer 20, and a cap layer 30, as shown in FIGS.

Topological insulator layer 10 comprises edge 11 . The material of the topological insulator layer 10 is tungsten ditelluride (WTe ₂ ). The material of the s-wave superconductor layer 20 is Nb. The material of the cap layer 30 is hexagonal boron nitride (h-BN). A cap layer 30 is provided between the edge 11 and the s-wave superconductor layer 20 . Cooper pair penetration from the s-wave superconductor layer 20 to the edge 11 is possible through the cap layer 30 due to the proximity effect. That is, it is possible for Cooper pairs from the s-wave superconductor layer 20 to tunnel through the cap layer 30 and into the edge 11 . When the Cooper pairs encroach on the edge 11, the topological insulator layer 10 becomes functional as a topological superconductor layer. Cap layer 30 directly contacts both topological insulator layer 10 and s-wave superconductor layer 20 . The cap layer 30 is an example of the first layer.

h-BN itself, which is the material of the cap layer 30, is an insulator with a bandgap of about 6 eV. However, when the cap layer 30 contacts the s-wave superconductor layer 20 made of Nb, a chemical bond occurs between h-BN and Nb, and the electronic state of h-BN changes to a metallic electronic state. become. According to the inventor's simulation, when the cap layer 30 is in direct contact with the s-wave superconductor layer 20, the shortest distance between Nb and h-BN is about 2.4 Å. FIG. 3 shows the density of state (DOS) of h-BN in contact with Nb. As shown in FIG. 3, h-BN in contact with Nb has a density of states at the Fermi surface and does not act as a barrier to Cooper pairs.

Further, according to the inventor's simulation, when the cap layer 30 is in direct contact with the topological insulator layer 10, the shortest distance between WTe ₂ and h-BN is about 3.0 Å. Therefore, there is no chemical bond between the cap layer 30 and the topological insulator layer 10 , and the cap layer 30 is physically adsorbed to the topological insulator layer 10 . The cap layer 30 and the topological insulator layer 10 may be van der Waals coupled to each other.

In the first embodiment, a suitable cap layer 30 is provided between the edge 11 of the topological insulator layer 10 and the s-wave superconductor layer 20, so that the topological insulator layer by the s-wave superconductor layer 20 Disturbance of the 10 electronic states can be suppressed, and Majorana particles can be stably generated. In the first embodiment, the shortest distance between Nb and _WTe2 is about 5.4 Å.

The generated Majorana particles can be replaced, for example, by grounding or floating the s-wave superconductor layer 20 .

Here, a reference example will be described for comparison with the first embodiment. FIG. 4 is a top view showing a quantum bit according to a reference example. FIG. 5 is a cross-sectional view showing a quantum bit according to a reference example. FIG. 5 corresponds to a cross-sectional view taken along line V-V in FIG.

As shown in FIGS. 4 and 5, the quantum bit 9 according to the reference example does not have the cap layer 30, and the edge 11 of the topological insulator layer 10 and the s-wave superconductor layer 20 are in direct contact with each other. are doing. Other configurations are the same as those of the first embodiment.

According to the inventors' simulations, when the s-wave superconductor layer 20 is in direct contact with the topological insulator layer 10, the shortest distance between Nb and _WTe2 is only about 1.6 Å, so the topological insulator A chemical bond is formed between layer 10 and s-wave superconductor layer 20 . As a result, the electronic state of the topological insulator layer 10 is affected by the s-wave superconductor layer 20 . FIG. 6 is a diagram showing an intensity map of spectral weights of WTe ₂ in the reference example. FIG. 7 is a diagram showing band structures of WTe ₂ and Nb in the reference example. FIG. 6 corresponds to extracting the contribution of WTe ₂ in FIG. 7 as a weighting map. FIG. 8 shows the band structure of WTe ₂ without external influences.

As shown in FIG. 8, the energy difference between the upper end of the valence band and the lower end of the conduction band is small in the pure _WTe2 , which is free from external influences. Therefore, in this state, WTe ₂ can stably function as a topological insulator. However, as shown in FIGS. 6 and 7, when Nb and _WTe2 are in direct contact with each other, the band structure of _WTe2 is disturbed. Therefore, WTe ₂ may not be able to function as a topological insulator. Therefore, in the quantum bit 9 according to the reference example, the electronic state of the topological insulator layer 10 may be damaged, and Majorana particles may not be generated.

In contrast, in the first embodiment, as described above, since the appropriate cap layer 30 is provided, it is possible to suppress the disturbance of the electronic state of the topological insulator layer 10 due to the s-wave superconductor layer 20. It can generate Majorana Particles stably. If a layer serving as a barrier against the Cooper pairs is provided instead of the cap layer 30, the Cooper pairs cannot enter the topological insulator layer 10 and the Majorana particles cannot be generated.

(Second embodiment)
Next, a second embodiment will be described. The second embodiment relates to a quantum bit including a two-dimensional topological insulator to which the first embodiment is applied. FIG. 9 is a perspective view showing a quantum bit according to the second embodiment. FIG. 10 is a top view showing a quantum bit according to the second embodiment. 11 and 12 are cross-sectional views showing a quantum bit according to the second embodiment. FIG. 11 corresponds to a cross-sectional view taken along line XI-XI in FIG. FIG. 12 corresponds to a cross-sectional view taken along line XII-XII in FIG.

9 to 12, the qubit 2 according to the second embodiment includes a substrate 110, a lower topological insulator layer 121 extending in the Y-axis direction, and an upper topological insulator layer 122 extending in the X-axis direction. have The substrate 110 is an insulating substrate such as an alumina substrate or a sapphire substrate. The X-axis direction and the Y-axis direction are directions orthogonal to the Z-axis direction perpendicular to the surface of the substrate 110 . The Y-axis direction intersects the X-axis direction, for example, the X-axis direction and the Y-axis direction are orthogonal to each other. In the present disclosure, viewing an object from the Z-axis direction may be referred to as planar viewing. The Y-axis direction is an example of a first direction, and the X-axis direction is an example of a second direction.

The lower topological insulator layer 121 is, for example, a two-dimensional topological insulator layer and has a first edge 161 and a third edge 163 extending in the Y-axis direction. The first edge 161 is located on the +X side of the third edge 163 . The lower topological insulator layer 121 may be composed of a single two-dimensional topological insulator, or may be composed of a plurality of stacked two-dimensional topological insulators. The material of the lower topological insulator layer 121 is, for example, tungsten ditelluride (WTe ₂ ). Although not shown, a plurality of lower topological insulator layers 121 may be arranged side by side in the X-axis direction. The lower topological insulator layer 121 is an example of a first topological insulator layer.

The upper topological insulator layer 122 is, for example, a two-dimensional topological insulator layer and has a second edge 162 and a fourth edge 164 extending in the X-axis direction. The second edge 162 is located on the +Y side of the fourth edge 164 . The upper topological insulator layer 122 may be composed of a single two-dimensional topological insulator, or may be composed of a plurality of stacked two-dimensional topological insulators. The material of the upper topological insulator layer 122 is, for example, tungsten ditelluride (WTe ₂ ). Although not shown, a plurality of upper topological insulator layers 122 may be arranged side by side in the Y-axis direction. Upper topological insulator layer 122 is an example of a second topological insulator layer.

A plurality of lower s-wave superconductor layers 131 are provided below the lower topological insulator layer 121 . The lower s-wave superconductor layer 131 is provided along the first edge 161 and the third edge 163 . The Y-axis direction end of each lower s-wave superconductor layer 131 is separated from the second edge 162 and the fourth edge 164 of the upper topological insulator layer 122 in plan view. The lower s-wave superconductor layer 131 is, for example, a Nb layer. The lower s-wave superconductor layer 131 is an example of a first s-wave superconductor layer.

A cap layer 151 is provided on the upper surface of each lower s-wave superconductor layer 131 . The cap layer 151 directly contacts the upper surface of the lower s-wave superconductor layer 131 and the lower surface of the lower topological insulator layer 121 . The cap layer 151 is, for example, an h-BN layer. The h-BN layer includes one or more h-BN layers stacked together. Cap layer 151 is provided between first edge 161 or third edge 163 and lower s-wave superconductor layer 131 . There is no chemical bond between the cap layer 151 and the lower topological insulator layer 121 , and the cap layer 151 is physically adsorbed to the lower topological insulator layer 121 . The cap layer 151 and the lower topological insulator layer 121 may be van der Waals coupled to each other. Cooper pair penetration from the lower s-wave superconductor layer 131 to the first edge 161 or the third edge 163 is possible through the cap layer 151 due to the proximity effect. That is, it is possible for Cooper pairs from the lower s-wave superconductor layer 131 to tunnel through the cap layer 151 and enter the first edge 161 or the third edge 163 . When the Cooper pair penetrates the first edge 161 or the third edge 163, the lower topological insulator layer 121 will act as a topological superconductor layer. The cap layer 151 is an example of the first layer.

A plurality of upper s-wave superconductor layers 132 are provided below the upper topological insulator layer 122 . Upper s-wave superconductor layer 132 is provided along second edge 162 and fourth edge 164 . The X-axis direction end of each upper s-wave superconductor layer 132 is separated from the first edge 161 and the third edge 163 of the lower topological insulator layer 121 in plan view. The upper s-wave superconductor layer 132 is, for example, a Nb layer. The upper s-wave superconductor layer 132 is an example of a second s-wave superconductor layer.

A cap layer 152 is provided on the upper surface of each upper s-wave superconductor layer 132 . Cap layer 152 directly contacts the top surface of upper s-wave superconductor layer 132 and the bottom surface of upper topological insulator layer 122 . Cap layer 152 is, for example, an h-BN layer. The h-BN layer includes one or more h-BN layers stacked together. Cap layer 152 is provided between second edge 162 or fourth edge 164 and upper s-wave superconductor layer 132 . There is no chemical bond between the cap layer 152 and the upper topological insulator layer 122 , and the cap layer 152 is physically adsorbed to the upper topological insulator layer 122 . The cap layer 152 and the upper topological insulator layer 122 may be van der Waals coupled to each other. Cooper pair penetration from the upper s-wave superconductor layer 132 to the second edge 162 or the fourth edge 164 is possible through the cap layer 152 due to the proximity effect. That is, it is possible for Cooper pairs from the upper s-wave superconductor layer 132 to tunnel through the cap layer 152 and penetrate the second edge 162 or the fourth edge 164 . When Cooper pairs penetrate second edge 162 or fourth edge 164, upper topological insulator layer 122 becomes functional as a topological superconductor layer. Cap layer 152 is an example of a second layer.

A plurality of upper s-wave superconductor layers 133 are provided above the upper topological insulator layer 122 . The upper s-wave superconductor layer 133 is provided along the second edge 162 and the fourth edge 164 . The X-axis direction end of each upper s-wave superconductor layer 133 is separated from the first edge 161 and the third edge 163 of the lower topological insulator layer 121 in plan view. The upper s-wave superconductor layer 133 is, for example, a Nb layer. The upper s-wave superconductor layer 133 is an example of a second s-wave superconductor layer.

A cap layer 153 is provided on the lower surface of each upper s-wave superconductor layer 133 . Cap layer 153 directly contacts the bottom surface of upper s-wave superconductor layer 133 and the top surface of upper topological insulator layer 122 . Cap layer 153 is, for example, an h-BN layer. The h-BN layer includes one or more h-BN layers stacked together. Cap layer 153 is provided between second edge 162 or fourth edge 164 and upper s-wave superconductor layer 133 . There is no chemical bond between the cap layer 153 and the upper topological insulator layer 122 , and the cap layer 153 is physically adsorbed to the upper topological insulator layer 122 . The cap layer 153 and the upper topological insulator layer 122 may be van der Waals coupled to each other. Cooper pair penetration from the upper s-wave superconductor layer 133 to the second edge 162 or the fourth edge 164 is possible through the cap layer 153 due to the proximity effect. That is, it is possible for Cooper pairs from the upper s-wave superconductor layer 133 to tunnel through the cap layer 153 and penetrate the second edge 162 or the fourth edge 164 . When Cooper pairs penetrate second edge 162 or fourth edge 164, upper topological insulator layer 122 becomes functional as a topological superconductor layer. Cap layer 153 is an example of a second layer.

For example, in plan view, the upper s-wave superconductor layer 133 and the cap layer 153 are provided in a region overlapping the lower topological insulator layer 121 of the upper topological insulator layer 122, and the upper s-wave superconductor layer 132 And the cap layer 152 is provided in a region away from the lower topological insulator layer 121 .

An etching stopper 140 is provided between the lower topological insulator layer 121 and the upper topological insulator layer 122 . The material of the etching stopper 140 is graphene or graphite, for example. When the material of the etching stopper 140 is graphite, the thinner the thickness, the better, for example, 5 nm or less. This is because the Majorana grains tunnel through the etching stopper 140 between the lower topological insulator layer 121 and the upper topological insulator layer 122 .

A plurality of magnetic electrodes 141 are provided on the upper topological insulator layer 122 . For example, in plan view, the magnetic electrode 141 is located between the upper s-wave superconductor layer 133 and the second edge 162 and between the upper s-wave superconductor layer 133 and the upper topological insulator layer 122 within the range where the lower topological insulator layer 121 and the upper topological insulator layer 122 overlap. It is provided between the s-wave superconductor layer 133 and the fourth edge 164 . The magnetic electrode 141 generates a magnetic field across the upper topological insulator layer 122 and the lower topological insulator layer 121 . The material of the magnetic electrode 141 is Fe, Co or Ni, for example. The magnetic electrode 141 is an example of the first magnetic layer and the second magnetic layer.

In the qubit 2, a portion of the first edge 161 between two adjacent lower s-wave superconductor layers 131 in plan view, and a portion of the third edge 163 between two adjacent lower s-wave superconductor layers in plan view. Majorana grains can be present in the portion between 131 and . Then, for example, of the portions where these Majorana particles can exist, the portion of the first edge 161 that overlaps the second edge 162 functions as the first region 171, and the portion of the third edge 163 that overlaps the second edge 162 functions as the first region 171. functions as the third region 173 . Further, for example, among the portions where these Majorana particles can exist, the portion of the first edge 161 that overlaps the fourth edge 164 functions as a fifth region 175, and the portion of the third edge 163 that overlaps the fourth edge 164 functions as a fifth region 175. functions as the seventh region 177 .

Similarly, the portion between the upper s-wave superconductor layer 132 and the upper s-wave superconductor layer 133 that are adjacent in plan view of the second edge 162 and the upper s-wave superconductor layer that is adjacent in plan view of the fourth edge 164 Majorana grains can be present in the conductor layer 132 and in the portion between the upper s-wave superconductor layer 133 . Then, for example, among the portions where these Majorana particles can exist, the portion of the second edge 162 that overlaps the first edge 161 functions as the second region 172, and the portion of the fourth edge 164 that overlaps the first edge 161 functions as the second region 172. functions as the sixth region 176 . Further, among the portions where these Majorana particles can exist, the portion of the second edge 162 that overlaps the third edge 163 functions as a fourth region 174, and the portion of the fourth edge 164 that overlaps the third edge 163 functions as the fourth region 174. 8 region 178.

The Majorana particles existing in the first region 171 and the Majorana particles existing in the second region 172 can tunnel through the etching stopper 140 and interact with each other. Therefore, both Majorana particles can be regarded as a single Majorana particle. The same applies to the set of the third area 173 and the fourth area 174, the set of the fifth area 175 and the sixth area 176, and the set of the seventh area 177 and the eighth area 178.

Thus, in the qubit 2, the Majorana particles generated in the lower topological insulator layer 121 and the Majorana particles generated in the upper topological insulator layer 122 can easily interact.

A cap layer 151 is provided on the upper surface of each lower s-wave superconductor layer 131 , a cap layer 152 is provided on the upper surface of each upper s-wave superconductor layer 132 , and a cap layer 152 is provided on the upper surface of each upper s-wave superconductor layer 133 . A cap layer 153 is provided on the bottom surface. Therefore, similarly to the first embodiment, disturbance of the electronic states of the lower topological insulator layer 121 and the upper topological insulator layer 122 can be suppressed, and Majorana particles can be stably generated. The generated Majorana grains can be replaced, for example, by grounding or floating the s-wave superconductor layers 131-133.

Next, a method for manufacturing the quantum bit 2 according to the second embodiment will be described. 13 to 23 are top views showing the manufacturing method of the quantum bit 2 according to the second embodiment.

First, as shown in FIG. 13, the Nb layer 181 is formed on the substrate 110. Then, as shown in FIG. The Nb layer 181 can be formed, for example, by vapor deposition.

Then, an h-BN layer 182 is formed on the Nb layer 181, as shown in FIG. The h-BN layer 182 can be formed by chemical vapor deposition (CVD), for example.

Thereafter, as shown in FIG. 15, by processing the laminate of the Nb layer 181 and the h-BN layer 182, the laminate of the lower s-wave superconductor layer 131 and the cap layer 151 and the upper s-wave superconductor A stack of layer 132 and cap layer 152 is formed (see FIGS. 11 and 12). The cap layers 151, 152 can function as protective layers for the lower s-wave superconductor layer 131 and the upper s-wave superconductor layer 132, respectively, and during subsequent processing, the lower s-wave superconductor layer 131, Oxidation of the surface of the upper s-wave superconductor layer 132 can be suppressed.

Subsequently, as shown in FIG. 16, a laminate of the lower s-wave superconductor layer 131 and the cap layer 151 and a laminate of the upper s-wave superconductor layer 132 and the cap layer 152 are formed on the substrate 110. A two-dimensional topological insulator layer 121X is provided so as to cover it. The two-dimensional topological insulator layer 121X can be provided, for example, by separately growing it on a growth substrate (not shown) and transferring it from the growth substrate.

Next, as shown in FIG. 17, a plurality of lower topological insulator layers 121 are formed by processing the two-dimensional topological insulator layer 121X. In the processing of the two-dimensional topological insulator layer 121X, for example, reactive ion etching (RIE) is performed. As an etching gas, for example, a fluorocarbon-based gas is used.

After that, as shown in FIG. 18, an etching stopper 140X is provided above the substrate 110 so as to cover the lower topological insulator layer 121. Then, as shown in FIG. The etching stopper 140X can be provided, for example, by separately growing it on a growth substrate (not shown) and transferring it from the growth substrate.

Subsequently, as shown in FIG. 19, a two-dimensional topological insulator layer 122X is provided on the etching stopper 140X. The two-dimensional topological insulator layer 122X can be provided, for example, by separately growing it on a growth substrate (not shown) and transferring it from the growth substrate.

Next, as shown in FIG. 20, a plurality of upper topological insulator layers 122 are formed by processing the two-dimensional topological insulator layer 122X. For processing the two-dimensional topological insulator layer 122X, for example, RIE is performed. As an etching gas, for example, a fluorocarbon-based gas is used. At this time, the lower topological insulator layer is protected by the etching stopper 140X.

Thereafter, as shown in FIG. 21, the etching stopper 140X is processed to remove the exposed portion of the etching stopper 140X from the upper topological insulator layer 122, thereby forming the lower topological insulator layer 121 and the upper topological insulator layer. 122, an etching stopper 140 is left (see FIGS. 11 and 12). In processing the etching stopper 140X, for example, RIE is performed. Oxygen gas, for example, is used as the etching gas.

Subsequently, as shown in FIG. 22, a laminate of a cap layer 153 and an upper s-wave superconductor layer 133 is formed on the upper topological insulator layer 122 (see FIG. 11).

Next, as shown in FIG. 23, a plurality of magnetic electrodes 141 are formed on the upper topological insulator layer 122 .

In this way, the quantum bit 2 according to the second embodiment can be manufactured.

(Third embodiment)
Next, a third embodiment will be described. The third embodiment relates to a method of manufacturing a quantum bit. 24 to 28 are schematic diagrams showing a method of manufacturing a quantum bit according to the third embodiment.

First, as shown in FIG. 24, the h-BN layer 301 is formed on the growth substrate 41, and the h-BN layer 301 is adhered to the transparent polymer block 52 provided on the slide glass 51. Then, as shown in FIG.

A WTe ₂ layer 302 is then formed on the growth substrate 42 and the WTe ₂ layer 302 is attached to the h-BN layer 301, as shown in FIG. The _WTe2 layer 302 can be formed, for example, by pulsed laser deposition (PLD) or molecular beam epitaxy. A WTe ₂ layer 302 exfoliated from single crystal WTe ₂ may also be used.

Thereafter, an h-BN layer 303 is formed on the growth substrate 43 and the h-BN layer 303 is attached to the _WTe2 layer 302, as shown in FIG.

Subsequently, as shown in FIG. 27, an s-wave superconductor layer 310 is formed on the substrate 44, and a laminate of the h-BN layer 301, the _WTe2 layer 302 and the h-BN layer 303 is formed as an s-wave superconductor. Press against layer 310 .

The transparent polymer mass 52 is then removed from the h-BN layer 301, as shown in FIG. As a result, a stack of h-BN layer 301 , WTe ₂ layer 302 and h-BN layer 303 is transferred onto substrate 44 .

In this manner, a qubit 3 having an h-BN layer 301 sandwiched between an s-wave superconductor layer 310 and a topological insulator _WTe2 layer 302 can be fabricated.

(Fourth embodiment)
Next, a fourth embodiment will be described. FIG. 29 is a schematic diagram showing a quantum bit according to the fourth embodiment.

As shown in FIG. 29, the quantum bit 4 according to the fourth embodiment has a topological insulator layer 421 with a rectangular planar shape and a topological insulator layer 422 with a rectangular planar shape. One vertex of the topological insulator layer 421 and one vertex of the topological insulator layer 422 are connected. If the topological insulator layers 421 and 422 are regarded as one topological insulator layer, there is a constriction at the connecting portion 423 between the topological insulator layers 421 and 422 .

The topological insulator layer 421 is, for example, a two-dimensional topological insulator layer and has a first edge 461 and a third edge 463 extending from the connecting portion 423 . The topological insulator layer 421 may be configured from a single two-dimensional topological insulator, or may be configured by stacking a plurality of two-dimensional topological insulators. The material of the topological insulator layer 421 is _WTe2 , for example.

The topological insulator layer 422 is, for example, a two-dimensional topological insulator layer and has a second edge 462 and a fourth edge 464 extending from the connecting portion 423 . The topological insulator layer 422 may be configured from a single two-dimensional topological insulator, or may be configured by stacking a plurality of two-dimensional topological insulators. The material of the topological insulator layer 422 is _WTe2 , for example.

An s-wave superconductor layer 431 is provided above the first edge 461 of the topological insulator layer 421 . An s-wave superconductor layer 433 is provided above the third edge 463 of the topological insulator layer 421 . The s-wave superconductor layers 431 and 433 are, for example, Nb layers.

A cap layer 451 is provided on the lower surface of the s-wave superconductor layer 431 . Cap layer 451 directly contacts the bottom surface of s-wave superconductor layer 431 and the top surface of topological insulator layer 421 . Cap layer 451 is, for example, an h-BN layer. A cap layer 451 is provided between the first edge 461 and the s-wave superconductor layer 431 . There is no chemical bond between the cap layer 451 and the topological insulator layer 421 , and the cap layer 451 is physically adsorbed to the topological insulator layer 421 . The cap layer 451 and the topological insulator layer 421 may be van der Waals coupled to each other. Cooper pair penetration from the s-wave superconductor layer 431 to the first edge 461 is possible through the cap layer 451 due to the proximity effect. That is, it is possible for Cooper pairs from the s-wave superconductor layer 431 to tunnel through the cap layer 451 and enter the first edge 461 . Once the Cooper pair penetrates the first edge 461, the topological insulator layer 421 will act as a topological superconductor layer.

A cap layer 453 is provided on the lower surface of the s-wave superconductor layer 433 . Cap layer 453 directly contacts the bottom surface of s-wave superconductor layer 433 and the top surface of topological insulator layer 421 . Cap layer 453 is, for example, an h-BN layer. A cap layer 453 is provided between the third edge 463 and the s-wave superconductor layer 433 . There is no chemical bond between the cap layer 453 and the topological insulator layer 421 , and the cap layer 453 is physically adsorbed to the topological insulator layer 421 . The cap layer 453 and the topological insulator layer 421 may be van der Waals coupled to each other. Cooper pair penetration from the s-wave superconductor layer 433 to the third edge 463 is possible through the cap layer 453 due to the proximity effect. That is, it is possible for Cooper pairs from the s-wave superconductor layer 433 to tunnel through the cap layer 453 and enter the third edge 463 . Once the Cooper pair penetrates the third edge 463, the topological insulator layer 421 will act as a topological superconductor layer.

A cap layer 452 is provided on the lower surface of the s-wave superconductor layer 432 . Cap layer 452 directly contacts the bottom surface of s-wave superconductor layer 432 and the top surface of topological insulator layer 422 . Cap layer 452 is, for example, an h-BN layer. A cap layer 452 is provided between the second edge 462 and the s-wave superconductor layer 432 . There is no chemical bond between the cap layer 452 and the topological insulator layer 422 , and the cap layer 452 is physically adsorbed to the topological insulator layer 422 . Cap layer 452 and topological insulator layer 422 may be van der Waals coupled to each other. Cooper pair penetration from the s-wave superconductor layer 432 to the second edge 462 is possible through the cap layer 452 due to the proximity effect. That is, it is possible for Cooper pairs from the s-wave superconductor layer 432 to tunnel through the cap layer 452 and enter the second edge 462 . When the Cooper pair penetrates the second edge 462, the topological insulator layer 422 becomes functional as a topological superconductor layer.

Magnetic layers

441 and 443 are provided on the topological insulator layer 421 . The magnetic layer 441 is provided at the end of the first edge 461 opposite to the connecting portion 423 . The magnetic layer 443 is provided at the end of the third edge 463 opposite to the connecting portion 423 . In plan view, there is a laminate of the s-wave superconductor layer 431 and the cap layer 451 between the magnetic layer 441 and the coupling portion 423, and the s-wave superconductor is between the magnetic layer 443 and the coupling portion 423. There is a stack of layer 433 and cap layer 453 .

Magnetic layers

441 and 443 generate a magnetic field across topological insulator layer 421 . The material of the

magnetic layers

441 and 443 is Fe, Co or Ni, for example.

Magnetic layers

442 and 444 are provided on the topological insulator layer 422 . The magnetic layer 442 is provided at the end of the second edge 462 opposite to the connecting portion 423 . A magnetic layer 444 is provided on the fourth edge 464 . In plan view, there is a laminate of the s-wave superconductor layer 432 and the cap layer 452 between the magnetic layer 442 and the connecting portion 423 . The material of the

magnetic layers

442 and 444 is Fe, Co or Ni, for example.

In the qubit 4 , the portion between the magnetic layer 441 and the stack of the s-wave superconductor layer 431 and the cap layer 451 in plan view of the first edge 461 is the first region where Majorana particles can exist. 471 functions. A portion of the second edge 462 between the magnetic layer 442 and the lamination of the s-wave superconductor layer 432 and the cap layer 452 in plan view functions as a second region 472 in which Majorana grains can exist. A portion of the third edge 463 between the magnetic layer 443 and the lamination of the s-wave superconductor layer 433 and the cap layer 453 in plan view functions as a third region 473 in which Majorana grains can exist. Furthermore, the connecting portion 423 functions as a fourth region 474 in which Majorana particles can exist.

In the fourth embodiment, a cap layer 451 is provided on the lower surface of the s-wave superconductor layer 431, a cap layer 452 is provided on the lower surface of the s-wave superconductor layer 432, and a cap layer 452 is provided on the lower surface of the s-wave superconductor layer 433. A cap layer 453 is provided. Therefore, as in the first embodiment, disturbance of the electronic states of the topological insulator layers 421 and 422 can be suppressed, and Majorana particles can be stably generated.

(Fifth embodiment)
Next, a fifth embodiment will be described. The fifth embodiment relates to quantum computers. FIG. 30 is a diagram showing a quantum computer according to the fifth embodiment;

A quantum computer 5 according to the fifth embodiment has a general-purpose computer 501, a control unit 502, and a quantum bit 503. Control unit 502 controls quantum bit 503 based on a control signal from general-purpose computer 501 . As the quantum bit 503, the quantum bit according to any one of the first to fourth embodiments is used. Control unit 502 and qubit 503 are housed in cryostat 504 .

　The quantum computer 5 can perform stable quantum operations.

Note that in the present disclosure, the material of the first layer, that is, the cap layer in the embodiment is not limited to h-BN. When the material of the first layer is h-BN, the thickness of the first layer is preferably 1 nm or less.

For example, the first layer may be an oxide layer such as Nb ₂ O ₅ layer, Nb ₂ O ₃ layer, NbO ₂ layer. When the first layer is an oxide layer, the thickness of the first layer is preferably 1 nm or less. The oxide layer may be deposited on the Nb layer used as the s-wave superconductor layer or may be formed by oxidation of the Nb layer. When the Nb layer is oxidized, the surface of the Nb layer is terminated with O atoms.

For example, the first layer may be a nitride layer such as an NbN layer or a TiN layer. Since the NbN layer functions as a superconductor, it can be relatively thick. Also, part of the NbN layer may function as the first s-wave superconductor layer. The nitride layer may be deposited on the Nb layer used as the s-wave superconductor layer, may be formed by nitridation of the Nb layer, or may be formed directly on the substrate. When the Nb layer is nitrided, the surface of the Nb layer is terminated with N atoms.

For example, the first layer may be a graphene layer or graphite. When the first layer is a graphene layer or graphite, the thickness of the first layer is preferably 1 nm or less. The graphene layer or graphite may be provided by transfer or the like on the Nb layer used as the s-wave superconductor layer. good too. A graphene layer includes one or more graphenes stacked together.

For example, the first layer may be a normal-conducting metal layer such as an Au layer or a Pt layer. When the first layer is a normal metal layer, the thickness of the first layer is preferably 5 nm or less. A normal metal layer may be deposited over the Nb layer which is used as an s-wave superconductor layer.

The first layer may contain a combination of these multiple types.

Also, the first topological insulator layer is not limited to a two-dimensional topological insulator layer, and may be a higher-order topological insulator layer. FIG. 31 is a schematic diagram showing a qubit including a higher topological insulator layer.

A quantum bit 6 shown in FIG. 31 has a rectangular parallelepiped high-order topological insulator layer 610 , an s-wave superconductor layer 620 , a cap layer 630 , and a magnetic layer 640 . A cap layer 630 covers a portion of the higher topological insulator layer 610 and an s-wave superconductor layer 620 covers the cap layer 630 . Cap layer 630 directly contacts high-order topological insulator layer 610 and s-wave superconductor layer 620 . Materials of the higher-order topological insulator layer 610, the s-wave superconductor layer 620, and the cap layer 630 are WTe ₂ , Nb, h-BN, for example. A magnetic layer 640 covers a portion of the high-order topological insulator layer 610 away from the cap layer 630 . In the portion between the cap layer 630 and the magnetic layer 640 of the high-order topological insulator layer 610 , Majorana grains can be present at two hinges (ridge lines) located diagonally.

In the qubit 6 as well, since an appropriate cap layer 630 is provided between the s-wave superconductor layer 620 and the high-order topological insulator layer 610, disturbance of the electronic state of the high-order topological insulator layer 610 can be suppressed. It can be suppressed, and Majorana particles can be stably generated.

Also, the material of the topological insulator layer is not limited to _WTe2 . For example, other topological insulators, Weyl semimetals, or the like may be used as the material of the topological insulator layer.

Although the preferred embodiments and the like have been described in detail above, the present invention is not limited to the above-described embodiments and the like, and various modifications can be made to the above-described embodiments and the like without departing from the scope of the claims. and substitutions can be added.

1, 2, 3, 4, 6: qubits 5:

quantum computer

10, 121, 122, 421, 422: topological insulator layers 11, 161, 162, 163, 164, 461, 462, 463, 464:

edges

20 , 131, 132, 133, 310, 431, 432, 433, 620: s-

wave superconductor layer

30, 151, 152, 153, 451, 452, 453, 630: cap layer 141: magnetic electrode 301, 303: h -BN layer 302: WTe ₂ layers 441, 442, 443, 444, 640: magnetic layer 610: higher topological insulator layer

Claims

a first topological insulator layer having a first edge;
a first s-wave superconductor layer;
a first layer provided between the first edge and the first s-wave superconductor layer and capable of penetration of Cooper pairs from the first s-wave superconductor layer to the first edge by proximity effect;
A Majorana qubit characterized by having:
The Majorana qubit according to claim 1, wherein the first layer is physically adsorbed to the first topological insulator layer.
The Majorana qubit according to claim 1 or 2, wherein the first layer has a density of states on the Fermi surface.
The first layer is Nb2O5 layer , Nb2O3 layer, NbO2 layer, NbN layer, TiN layer, hexagonal boron nitride layer, graphene layer, graphite, Au layer or Pt layer or any combination thereof. The Majorana qubit according to any one of claims 1 to 3, comprising:
The Majorana qubit according to any one of claims 1 to 4, wherein the first topological insulator layer includes a two-dimensional topological insulator or a higher-order topological insulator.
The Majorana qubit according to any one of claims 1 to 5, comprising a first magnetic layer that generates a magnetic field that reaches the first topological insulator layer.
The Majorana qubit according to any one of claims 1 to 6, wherein the first layer and the first topological insulator layer are van der Waals coupled to each other.
the first topological insulator layer extends in a first direction;
a second topological insulator layer having a second edge and extending in a second direction intersecting the first direction;
a second s-wave superconductor layer;
a second layer provided between the second edge and the second s-wave superconductor layer to allow penetration of Cooper pairs from the second s-wave superconductor layer to the second edge by proximity effect;
has
The first topological insulator layer includes a first region where Majorana grains can exist in a portion of the first edge that overlaps the second edge in plan view,
The second topological insulator layer includes a second region where Majorana grains can exist in a portion of the second edge that overlaps the first edge in plan view,
The Majorana qubit according to any one of claims 1 to 6, wherein the Majorana particles in the first region and the Majorana particles in the second region are interchangeable.
The Majorana qubit according to claim 8, wherein the second layer is physically adsorbed to the second topological insulator layer.
The Majorana qubit according to claim 8 or 9, wherein the second layer has a density of states on the Fermi surface.
The second layer is Nb2O5 layer , Nb2O3 layer, NbO2 layer, NbN layer, TiN layer, hexagonal boron nitride layer, graphene layer, graphite, Au layer or Pt layer or any combination thereof. 11. The Majorana qubit according to any one of claims 8 to 10, comprising:
The Majorana qubit according to any one of claims 8 to 11, wherein the second topological insulator layer includes a two-dimensional topological insulator or a higher-order topological insulator.
The Majorana qubit according to any one of claims 8 to 12, further comprising a second magnetic layer that generates a magnetic field that reaches the second topological insulator layer.
The Majorana qubit according to any one of claims 8 to 13, wherein the second layer and the second topological insulator layer are van der Waals coupled to each other.
A quantum computer comprising the Majorana qubit according to any one of claims 1 to 14.