WO2023140042A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2023140042A1
WO2023140042A1 PCT/JP2022/047430 JP2022047430W WO2023140042A1 WO 2023140042 A1 WO2023140042 A1 WO 2023140042A1 JP 2022047430 W JP2022047430 W JP 2022047430W WO 2023140042 A1 WO2023140042 A1 WO 2023140042A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor device
region
die pad
resin
main surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2022/047430
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English (en)
French (fr)
Japanese (ja)
Inventor
嘉蔵 大角
太郎 西岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP2023575156A priority Critical patent/JPWO2023140042A1/ja
Priority to DE112022006100.6T priority patent/DE112022006100T5/de
Priority to CN202280089355.5A priority patent/CN118633155A/zh
Publication of WO2023140042A1 publication Critical patent/WO2023140042A1/ja
Priority to US18/777,194 priority patent/US20240379574A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/80—Arrangements for protection of devices protecting against overcurrent or overload, e.g. fuses or shunts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H10W44/501—Inductive arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/411—Chip-supporting parts, e.g. die pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/421—Shapes or dispositions
    • H10W70/424—Cross-sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/481—Leadframes for devices being provided for in groups H10D8/00 - H10D48/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/811—Multiple chips on leadframes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/755—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a laterally-adjacent insulating package substrate, interpose or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Definitions

  • the present disclosure relates to semiconductor devices.
  • inverter devices have been used in electric vehicles (including hybrid vehicles) and home appliances.
  • a semiconductor device equipped with an insulating element is used in such an inverter device.
  • the inverter device includes, for example, a plurality (eg, six) of power semiconductors such as IGBTs (Insulated Gate Bipolar Transistors) and MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) in addition to the semiconductor device.
  • the semiconductor device includes a control element, an isolation element, and a drive element.
  • a control signal output from an ECU (Engine Control Unit) is input to a control element of the semiconductor device.
  • ECU Engine Control Unit
  • the control element converts the control signal into a PWM (Pulse Width Modulation) control signal and transmits it to the driving element via the isolation element.
  • the drive element causes the power semiconductor to switch at desired timing based on the PWM control signal.
  • Three-phase AC power for driving a motor is generated from the DC power of the on-vehicle battery by the six power semiconductors switching at desired timings.
  • Patent Literature 1 discloses an example of a semiconductor device equipped with an insulating element.
  • the insulating element transmits an electric signal such as a control signal while maintaining an insulating state between the relatively low-potential control element and the relatively high-potential driving element.
  • the insulating element is mounted on the die pad and covered with a sealing resin.
  • the repeated thermal stress due to the difference in linear expansion coefficient between the sealing resin and the die pad may cause the sealing resin to separate from the die pad. If the delamination extends to the insulating element, dielectric breakdown will occur between the low and high potential portions of the insulating element. In addition, peeling may cause cracks in the sealing resin. When the crack reaches a die pad on which an insulating element is mounted and another die pad having a larger potential difference than the die pad, dielectric breakdown occurs between these two die pads. If dielectric breakdown occurs, the insulating element will no longer function, and eventually the semiconductor device will no longer function.
  • An object of the present disclosure is to provide a semiconductor device that is improved over conventional semiconductor devices.
  • an object of the present disclosure is to provide a semiconductor device that can suppress the occurrence of dielectric breakdown.
  • a semiconductor device provided by one aspect of the present disclosure includes an insulating element, a conductive member on which the insulating element is mounted, and a sealing resin covering the insulating element, and the conductive member includes an uneven portion covered with the sealing resin.
  • FIG. 1 is a plan view showing a semiconductor device according to a first embodiment of the present disclosure
  • FIG. FIG. 2 is a plan view showing the semiconductor device of FIG. 1, and is a view through a sealing resin.
  • 3 is a front view showing the semiconductor device of FIG. 1.
  • FIG. 4 is a left side view of the semiconductor device of FIG. 1.
  • FIG. 5 is a cross-sectional view along line VV in FIG. 6 is a partially enlarged view of FIG. 5.
  • FIG. FIG. 7 is a cross-sectional view along line VII-VII of FIG. 8 is a partially enlarged view of FIG. 7.
  • FIG. FIG. 9 is a perspective view showing the first die pad.
  • 10A and 10B are plan views showing steps related to the method of manufacturing the semiconductor device of FIG.
  • FIG. 11A and 11B are plan views showing steps related to the method of manufacturing the semiconductor device of FIG.
  • FIG. 12 is a perspective view showing the first die pad 3 according to the first modified example of the first embodiment.
  • FIG. 13 is a perspective view showing the first die pad 3 according to the second modification of the first embodiment.
  • FIG. 14 is a perspective view showing a first die pad 3 according to a third modified example of the first embodiment.
  • FIG. 15 is a perspective view showing a first die pad 3 according to a fourth modified example of the first embodiment.
  • FIG. 16 is a plan view showing a semiconductor device according to a second embodiment of the present disclosure, and is a view through a sealing resin.
  • FIG. 17 is a plan view showing a semiconductor device according to a third embodiment of the present disclosure, and is a view through a sealing resin.
  • 18 is a perspective view showing the first die pad 3 of the semiconductor device shown in FIG. 17.
  • FIG. 19 is a perspective view showing the first die pad 3 according to the first modified example of the third embodiment.
  • FIG. 20 is a plan view showing a semiconductor device according to a fourth embodiment of the present disclosure, and is a view through a sealing resin.
  • FIG. 21 is a plan view showing a semiconductor device according to a fifth embodiment of the present disclosure, and is a view through a sealing resin.
  • FIG. 22 is a plan view showing a semiconductor device according to a sixth embodiment of the present disclosure, and is a view through a sealing resin.
  • First embodiment: 1 to 9 show an example of a semiconductor device according to the present disclosure.
  • the semiconductor device A10 of this embodiment includes a first semiconductor element 11, a second semiconductor element 12, an insulating element 13, a conductive member 2, a plurality of wires 61 to 64, and a sealing resin .
  • the conductive member 2 includes a first die pad 3 , a second die pad 4 , a plurality of first terminals 51 , a plurality of second terminals 52 , a plurality of pad portions 53 and 55 , a pair of connection portions 54 and a pair of connection portions 56 .
  • the semiconductor device A10 is surface-mounted, for example, on a wiring board of an inverter device such as an electric vehicle (or hybrid vehicle).
  • the application and function of the semiconductor device A10 are not limited.
  • the package format of the semiconductor device A10 is SOP (Small Outline Package). However, the package format of the semiconductor device A10 is not limited to SOP.
  • FIG. 1 is a plan view showing the semiconductor device A10.
  • FIG. 2 is a plan view showing the semiconductor device A10.
  • the outer shape of the sealing resin 7 is shown by an imaginary line (chain double-dashed line) through the sealing resin 7 .
  • FIG. 3 is a front view showing the semiconductor device A10.
  • FIG. 4 is a left side view showing the semiconductor device A10.
  • FIG. 5 is a cross-sectional view along line VV in FIG. 6 is a partially enlarged view of FIG. 5.
  • FIG. FIG. 7 is a cross-sectional view along line VII-VII of FIG. 8 is a partially enlarged view of FIG. 7.
  • FIG. FIG. 9 is a perspective view showing the first die pad 3.
  • the semiconductor device A10 has a rectangular shape when viewed in the thickness direction (planar view).
  • the thickness direction of the semiconductor device A10 is defined as the z direction
  • the direction along one side of the semiconductor device A10 orthogonal to the z direction (horizontal direction in FIGS. 1 and 2) is defined as the x direction
  • the direction orthogonal to the z direction and the x direction (vertical direction in FIGS. 1 and 2) is defined as the y direction.
  • the shape and dimensions of the semiconductor device A10 are not limited.
  • the first semiconductor element 11, the second semiconductor element 12, and the insulating element 13 are elements that serve as functional centers of the semiconductor device A10.
  • the first semiconductor element 11 is mounted on a part of the conductive member 2 (the first die pad 3 to be described later), and is arranged in the center of the semiconductor device A10 in the y direction and closer to the x1 side in the x direction.
  • the first semiconductor element 11 has a rectangular shape elongated in the y direction when viewed in the z direction.
  • the first semiconductor element 11 is a control element.
  • the first semiconductor element 11 has a circuit that converts a control signal input from an ECU or the like into a PWM control signal, a transmission circuit that transmits the PWM control signal to the second semiconductor element 12, and a reception circuit that receives an electric signal from the second semiconductor element 12.
  • the second semiconductor element 12 is mounted on a part of the conductive member 2 (a second die pad 4 described later), and is arranged in the center of the semiconductor device A10 in the y direction and closer to the x2 side in the x direction.
  • the second semiconductor element 12 has a rectangular shape elongated in the y direction when viewed in the z direction.
  • the second semiconductor element 12 is a driving element.
  • the second semiconductor element 12 has a receiving circuit for receiving the PWM control signal transmitted from the first semiconductor element 11, a circuit (gate driver) for generating and outputting a driving signal for a switching element (for example, IGBT or MOSFET) based on the received PWM control signal, and a transmitting circuit for transmitting an electrical signal to the first semiconductor element 11.
  • a switching element for example, IGBT or MOSFET
  • the insulating element 13 is mounted on a portion of the conductive member 2 (the first die pad 3) and arranged in the center of the semiconductor device A10 in the y direction.
  • the insulating element 13 is located on the x-direction x2 side with respect to the first semiconductor element 11 and is located on the x-direction x1 side with respect to the second semiconductor element 12 . That is, the insulating element 13 is positioned between the first semiconductor element 11 and the second semiconductor element 12 in the x-direction.
  • the insulating element 13 has a rectangular shape elongated in the y direction when viewed in the z direction.
  • the isolation element 13 is an element for transmitting the PWM control signal and other electrical signals in an isolated state.
  • the isolation element 13 receives the PWM control signal from the first semiconductor element 11 via the wire 63 and transmits the received PWM control signal to the second semiconductor element 12 via the wire 64 in an insulated state. Also, the insulating element 13 receives an electrical signal from the second semiconductor element 12 via the wire 64 and transmits the received electrical signal to the first semiconductor element 11 via the wire 63 in an insulated state. That is, the insulating element 13 relays signals between the first semiconductor element 11 and the second semiconductor element 12 and insulates the first semiconductor element 11 and the second semiconductor element 12 from each other.
  • the isolation element 13 is an inductive isolation element.
  • An inductive insulating element transmits an electrical signal by inductively coupling two inductors (coils).
  • the insulating element 13 has a substrate made of Si, and an inductor made of Cu is formed on the substrate.
  • the inductors include a transmitting side inductor and a receiving side inductor, and these inductors are stacked together in the thickness direction (z direction) of the insulating element 13 .
  • a dielectric layer made of SiO 2 or the like is interposed between the transmitting side inductor and the receiving side inductor. The dielectric layer electrically insulates the transmitting inductor from the receiving inductor.
  • the insulating element 13 is of the inductive type in this embodiment, the insulating element 13 may be of the capacitive type.
  • An example of a capacitive isolation element is a capacitor.
  • the first semiconductor element 11 transmits the PWM control signal to the second semiconductor element 12 via the insulating element 13 .
  • the first semiconductor element 11 may also transmit signals other than the PWM control signal to the second semiconductor element 12 .
  • the second semiconductor element 12 transmits electrical signals to the first semiconductor element 11 via the insulating element 13 .
  • Information indicated by the electrical signal transmitted from the second semiconductor element 12 to the first semiconductor element 11 is not limited.
  • a half-bridge circuit in which a low-side switching element and a high-side switching element are connected like a totem pole is generally used for a motor driver circuit in an inverter device such as a hybrid vehicle.
  • an isolated gate driver only one of the low-side switching element and the high-side switching element is turned on at any given time.
  • the source of the low-side switching element and the reference potential of the insulated gate driver that drives the switching element are grounded, so the gate-source voltage operates with the ground as the reference.
  • the source of the high-side switching element and the reference potential of the insulated gate driver that drives the switching element are connected to the output node of the half-bridge circuit.
  • the reference potential of the insulated gate driver that drives the high-side switching element changes.
  • the high-side switching element is on, the reference potential becomes a voltage (for example, 600 V or higher) equivalent to the voltage applied to the drain of the high-side switching element.
  • Grounds are separated between the first semiconductor element 11 and the second semiconductor element 12 to ensure insulation.
  • the semiconductor device A10 is used as an insulated gate driver that drives a high-side switching element, a voltage of 600 V or more is transiently applied to the second semiconductor element 12 compared to the ground of the first semiconductor element 11.
  • the isolation element 13 isolates the input side circuit, which has a relatively low potential, from the output side circuit, which has a relatively high potential.
  • a plurality of electrodes 11A are provided on the upper surface of the first semiconductor element 11 (the surface facing the z1 side).
  • a plurality of electrodes 11 ⁇ /b>A are electrically connected to the circuit configured in the first semiconductor element 11 .
  • a plurality of electrodes 12A are provided on the upper surface of the second semiconductor element 12 (the surface facing the z1 side).
  • a plurality of electrodes 12A are electrically connected to the circuit configured in the second semiconductor element 12 .
  • a plurality of first electrodes 13A and a plurality of second electrodes 13B are provided on the upper surface of the insulating element 13 (the surface facing the z1 side).
  • Each of the plurality of first electrodes 13A and the plurality of second electrodes 13B is electrically connected to either the transmitting side inductor or the receiving side inductor.
  • the plurality of first electrodes 13A are arranged along the y direction near the x1 side in the x direction.
  • the plurality of second electrodes 13B are arranged along the y direction near the center in the x direction.
  • the conductive member 2 is a member that constitutes a conductive path between the first semiconductor element 11 and the second semiconductor element 12 and the wiring board of the inverter device in the semiconductor device A10.
  • the conductive member 2 is made of an alloy containing Cu in its composition, for example.
  • the conductive member 2 is formed from a lead frame 81 which will be described later.
  • Conductive member 2 mounts first semiconductor element 11 , second semiconductor element 12 , and insulating element 13 .
  • the conductive member 2 includes a first die pad 3, a second die pad 4, a plurality of first terminals 51, a plurality of second terminals 52, a plurality of pad portions 53 and 55, a pair of connection portions 54, and a pair of connection portions 56.
  • the first die pad 3 is arranged in the center of the semiconductor device A10 in the y direction and closer to the x1 side in the x direction.
  • the second die pad 4 is arranged away from the first die pad 3 on the x2 side in the x direction with respect to the first die pad 3 .
  • a first semiconductor element 11 and an insulating element 13 are mounted on the first die pad 3, as shown in FIGS.
  • the first die pad 3 is electrically connected to the first semiconductor element 11 and is one element of the input side circuit described above.
  • the first die pad 3 has, for example, a rectangular shape (or a substantially rectangular shape) when viewed in the z direction.
  • First die pad 3 has main surface 31 and back surface 32 .
  • the major surface 31 and the back surface 32 are positioned apart from each other in the z-direction, as shown in FIGS.
  • the main surface 31 faces the z1 side, and the back surface 32 faces the z2 side.
  • the first semiconductor element 11 and the insulating element 13 are mounted on the main surface 31 .
  • the first die pad 3 also has side surfaces 33-36.
  • Each of the side surfaces 33 to 36 is connected to the main surface 31 and the back surface 32 and is sandwiched between the main surface 31 and the back surface 32 in the z-direction.
  • Sides 33 and 35 are spaced apart from each other in the y-direction as shown in FIGS.
  • the side surface 33 faces the y2 side
  • the side surface 35 faces the y1 side.
  • Sides 34 and 36 are spaced from each other in the x-direction and join side 33 and side 35, as shown in FIGS.
  • Side 34 faces the x2 side and side 36 faces the x1 side.
  • the main surface 31, the back surface 32, and the side surfaces 33 to 36 are not limited to flat surfaces, and may include curved surfaces.
  • the four corners of the main surface 31 and the back surface 32 are curved rather than right-angled, so that both ends of the side surfaces 33 to 36 in the x direction or the y direction are curved.
  • the first die pad 3 has corner portions 39a to 39h, as shown in FIG.
  • Corner portion 39a is a portion where main surface 31, side surface 33, and side surface 34 are connected to each other.
  • Corner portion 39b is a portion where main surface 31, side surface 34, and side surface 35 are connected to each other.
  • the corner portion 39c is a portion where the back surface 32, the side surface 33, and the side surface 34 are connected to each other.
  • the corner portion 39d is a portion where the back surface 32, the side surface 34, and the side surface 35 are connected to each other.
  • Corner portion 39e is a portion where main surface 31, side surface 33, and side surface 36 are connected to each other.
  • angular parts are parts which the main surface 31, the side surface 35, and the side surface 36 are connected with each other.
  • the corner portion 39g is a portion where the back surface 32, the side surface 33, and the side surface 36 are connected to each other.
  • a corner portion 39h is a portion where the back surface 32, the
  • the uneven portion 21 is arranged on the first die pad 3 .
  • the uneven portion 21 is a portion in which fine unevenness is formed, and has a larger surface roughness than a portion of the conductive member 2 in which the uneven portion 21 is not formed.
  • the uneven portion 21 is covered with the sealing resin 7 .
  • the concave-convex portion 21 is formed by irregularly forming a plurality of fine concave portions.
  • the area where the uneven portion 21 is formed is stippled.
  • the uneven portion 21 is arranged on the entire surfaces of the main surface 31, the back surface 32, and the side surfaces 33 to 36 of the first die pad 3.
  • the concave-convex portion 21 is formed by etching as described in the manufacturing method described later.
  • the method for forming the uneven portion 21 is not limited.
  • the uneven portion 21 may be formed by shot blasting or the like.
  • the uneven portion 21 may not be arranged on the entire surface of each surface (may be arranged only partially), and may not be arranged on all of the main surface 31, the back surface 32, and the side surfaces 33 to 36 (may be arranged only on some surfaces).
  • the first semiconductor element 11 and the insulating element 13 are bonded to the main surface 31 of the first die pad 3 with a conductive bonding material 19, as shown in FIGS.
  • the conductive bonding material 19 is solder, for example.
  • the conductive bonding material 19 is not limited, and may be metal paste, sintered metal, or the like.
  • a second semiconductor element 12 is mounted on the second die pad 4, as shown in FIGS.
  • the second die pad 4 is electrically connected to the second semiconductor element 12 and is one element of the output side circuit described above.
  • the second die pad 4 has, for example, a rectangular shape (or a substantially rectangular shape) when viewed in the z direction.
  • the second die pad 4 has a main surface 41 and a back surface 42 .
  • the major surface 41 and the back surface 42 are located apart from each other in the z-direction as shown in FIG.
  • the main surface 41 faces the z1 side, and the back surface 42 faces the z2 side.
  • the second semiconductor element 12 is mounted on the main surface 41 .
  • the second die pad 4 also has side surfaces 43-45.
  • Each of the side surfaces 43 to 46 is connected to the main surface 41 and the back surface 42 and is sandwiched between the main surface 41 and the back surface 42 in the z-direction.
  • Sides 43 and 45 are spaced apart in the y-direction as shown in FIG.
  • the side surface 43 faces the y2 side
  • the side surface 45 faces the y1 side.
  • Sides 44 and 46 are spaced from each other in the x-direction and join side 43 and side 45, as shown in FIGS.
  • the side 44 faces the x1 side and the side 46 faces the x2 side.
  • the main surface 41, the back surface 42, and the side surfaces 43 to 46 are not limited to flat surfaces, and may include curved surfaces. In the present embodiment, the four corners of the main surface 41 and the back surface 42 are curved rather than right-angled, so that both ends of the side surfaces 43 to 46 in the x direction or the y direction are curved.
  • the second semiconductor element 12 is bonded to the main surface 41 of the second die pad 4 with a conductive bonding material 19 .
  • the plurality of first terminals 51 are members that form a conductive path between the semiconductor device A10 and the wiring board by being joined to the wiring board of the inverter device. Each first terminal 51 is appropriately conducted to the first semiconductor element 11 and is one element of the input side circuit described above. As shown in FIGS. 1, 2, and 4, the plurality of first terminals 51 are spaced apart from each other and arranged at regular intervals along the y direction. The plurality of first terminals 51 are all positioned on the x1 side in the x direction with respect to the first die pad 3 and protrude from the sealing resin 7 (resin side surface 73 described later) on the x1 side in the x direction.
  • the plurality of first terminals 51 include a power supply terminal to which a voltage is supplied, a ground terminal, an input terminal to which a control signal is input, an input terminal to which other electrical signals are input, and an output terminal to output other electrical signals.
  • the semiconductor device A10 has ten first terminals 51 . Note that the number of first terminals 51 is not limited. Further, the signals input/output to/from each first terminal 51 are not limited.
  • Each first terminal 51 has an elongated rectangular shape extending along the x direction, and includes a portion exposed from the sealing resin 7 and a portion covered with the sealing resin 7 . As shown in FIGS. 3 and 5, the portion of the first terminal 51 exposed from the sealing resin 7 is bent into a gull-wing shape. A portion of the first terminal 51 exposed from the sealing resin 7 may be plated.
  • the plating layer formed by the plating process is made of an alloy containing Sn, such as solder, and covers the portion exposed from the sealing resin 7 .
  • the multiple first terminals 51 include a first terminal 51a and a first terminal 51b.
  • the first terminal 51a is arranged closest to the y1 side in the y direction.
  • the first terminal 51b is arranged closest to the y2 side in the y direction.
  • the plurality of pad portions 53 are connected to the x-direction x2 side of the plurality of first terminals 51 other than the first terminals 51a and 51b.
  • the shape of each pad portion 53 when viewed in the z direction is not limited.
  • the upper surface (the surface facing the z1 side) of each pad portion 53 is flat (or substantially flat), and a wire 61, which will be described later, is joined.
  • the upper surface of each pad portion 53 may be plated.
  • the plated layer formed by the plating process is made of a metal containing Ag, for example, and covers the upper surface of the pad portion 53 .
  • the plating layer increases the bonding strength of the wires 61 and protects the lead frame 81 (described later) from impacts during wire bonding of the wires 61 .
  • the pad portion 53 is entirely covered with the sealing resin 7 .
  • a pair of connecting portions 54 are connected to the first terminal 51a or the first terminal 51b and the first die pad 3 respectively.
  • the connection portion 54 connected to the first terminal 51a extends in the y direction, and the end on the y2 side of the first die pad 3 connects to the center of the first die pad 3 on the y1 side in the y direction.
  • the connection portion 54 connected to the first terminal 51b extends in the y direction, and the end portion on the y direction y1 side is connected to the end portion on the y direction y2 side of the first die pad 3 near the center in the x direction.
  • the first terminal 51a and the first terminal 51b are connected to the first die pad 3 via the pair of connecting portions 54 and support the first die pad 3 .
  • each connecting portion 54 is flat (or substantially flat), and a wire 61, which will be described later, is joined thereto.
  • the upper surface of each connection portion 54 may be covered with a plating layer (for example, a metal containing Ag) similarly to the upper surface of the pad portion 53 .
  • the connection portion 54 is entirely covered with the sealing resin 7 .
  • the plurality of second terminals 52 are members that form a conductive path between the semiconductor device A10 and the wiring board by being joined to the wiring board of the inverter device. Each second terminal 52 is appropriately connected to the second semiconductor element 12 and is one element of the output side circuit described above. As shown in FIGS. 1 and 2, the plurality of second terminals 52 are spaced apart from each other and arranged at regular intervals along the y direction. The plurality of second terminals 52 are all positioned on the x2 side in the x direction with respect to the second die pad 4 and protrude from the sealing resin 7 (a resin side surface 74 described later) on the x2 side in the x direction.
  • the plurality of second terminals 52 includes a power supply terminal to which voltage is supplied, a ground terminal, an output terminal to output a drive signal, an input terminal to which other electrical signals are input, and an output terminal to output other electrical signals.
  • the semiconductor device A10 has ten second terminals 52 . Note that the number of second terminals 52 is not limited. Further, the signals input/output to/from each second terminal 52 are not limited.
  • Each second terminal 52 has an elongated rectangular shape extending along the x direction, and includes a portion exposed from the sealing resin 7 and a portion covered with the sealing resin 7 . As shown in FIGS. 3 and 5, the portion of the second terminal 52 exposed from the sealing resin 7 is subjected to a gull-wing bending process. A plated layer (for example, an alloy containing Sn such as solder) may be formed on the portions of the second terminals 52 exposed from the sealing resin 7 , as in the case of the first terminals 51 .
  • the plurality of second terminals 52 includes second terminals 52a and second terminals 52b.
  • the second terminal 52a is arranged second from the y-direction y1 side among the plurality of second terminals 52 .
  • the second terminal 52b is arranged second from the y-direction y2 side among the plurality of second terminals 52 .
  • the plurality of pad portions 55 are connected to the x-direction x1 side of the plurality of second terminals 52 other than the second terminals 52a and 52b.
  • the shape of each pad portion 55 when viewed in the z direction is not limited.
  • the upper surface (the surface facing the z1 side) of each pad portion 55 is flat (or substantially flat), and a wire 62, which will be described later, is joined.
  • the upper surface of each pad portion 55 may be covered with a plating layer (for example, metal containing Ag), like the upper surface of pad portion 53 .
  • the pad portion 55 is entirely covered with the sealing resin 7 .
  • the pair of connection portions 56 are connected to the second terminal 52a or the second terminal 52b and the second die pad 4, respectively.
  • the connecting portion 56 connected to the second terminal 52a has an end on the y2 side connected to the center of the second die pad 4 on the y1 side in the y direction near the center in the x direction.
  • the connection portion 56 connected to the second terminal 52b has an end portion on the y-direction y1 side connected to an end portion on the y-direction y2 side of the second die pad 4 near the center in the x-direction.
  • the second terminal 52a and the second terminal 52b are connected to the second die pad 4 via the pair of connecting portions 56 and support the second die pad 4. As shown in FIG.
  • each connecting portion 56 is flat (or substantially flat), and a wire 62, which will be described later, is joined.
  • the upper surface of each connection portion 56 may be covered with a plating layer (for example, metal containing Ag), like the upper surface of pad portion 53 .
  • the connection portion 56 is entirely covered with the sealing resin 7 .
  • the shape of the conductive member 2 is not limited to the above.
  • the first die pad 3 may be supported by any first terminal 51 . That is, the pair of connecting portions 54 may be connected to the first die pad 3 and any first terminal 51 .
  • the second die pad 4 may be supported by any second terminal 52 . That is, the pair of connecting portions 56 may be connected to any second terminal 52 and second die pad 4 .
  • the plurality of wires 61 to 64, together with the conductive member 2, constitute a conductive path for the first semiconductor element 11, the second semiconductor element 12, and the insulating element 13 to perform their predetermined functions.
  • the material of each of the plurality of wires 61-64 is metal including Au, Cu, or Al, for example.
  • the plurality of wires 61 constitute conduction paths between the first semiconductor element 11 and the plurality of first terminals 51, as shown in FIGS.
  • the plurality of wires 61 electrically connect the first semiconductor element 11 to at least one of the plurality of first terminals 51 .
  • a plurality of wires 61 is one element of the input side circuit described above. As shown in FIG. 2, each of the plurality of wires 61 has one end conductively joined to one of the electrodes 11A of the first semiconductor element 11, and the other end conductively joined to one of the plurality of pad portions 53 and the pair of connection portions 54.
  • the number of wires 61 joined to each pad portion 53 and each connection portion 54 is not limited.
  • the plurality of wires 62 constitute conduction paths between the second semiconductor element 12 and the plurality of second terminals 52, as shown in FIGS.
  • the plurality of wires 62 electrically connect the second semiconductor element 12 to at least one of the plurality of second terminals 52 .
  • a plurality of wires 62 is one element of the output side circuit described above. As shown in FIG. 2, each of the plurality of wires 62 has one end conductively joined to one of the electrodes 12A of the second semiconductor element 12, and the other end conductively joined to one of the plurality of pad portions 55 and the pair of connection portions 56.
  • the number of wires 62 joined to each pad portion 55 and each connection portion 54 is not limited.
  • the plurality of wires 63 constitute a conductive path between the first semiconductor element 11 and the insulating element 13, as shown in FIGS.
  • the plurality of wires 63 electrically connect the first semiconductor element 11 and the insulating element 13 to each other.
  • a plurality of wires 63 is one element of the input side circuit described above.
  • Each of the plurality of wires 63 is electrically connected to one of the electrodes 11A of the first semiconductor element 11 and one of the first electrodes 13A of the insulating element 13, as shown in FIG.
  • a plurality of wires 64 constitute a conductive path between the second semiconductor element 12 and the insulating element 13, as shown in FIGS.
  • the wires 64 electrically connect the second semiconductor element 12 and the insulating element 13 to each other.
  • a plurality of wires 64 is one element of the output side circuitry previously described.
  • Each of the plurality of wires 64 is conductively joined to one of the electrodes 12A of the second semiconductor element 12 and one of the second electrodes 13B of the insulating element 13, as shown in FIG.
  • the sealing resin 7 covers the first semiconductor element 11, the second semiconductor element 12, the insulating element 13, the first die pad 3, the second die pad 4, the pair of connection portions 54, the pair of connection portions 56, the plurality of pad portions 53 and 55, the plurality of wires 61 to 64, and a portion of each of the plurality of first terminals 51 and the second terminals 52.
  • the sealing resin 7 has electrical insulation.
  • Sealing resin 7 is made of a material containing, for example, black epoxy resin.
  • the sealing resin 7 has a rectangular shape when viewed in the z direction.
  • the sealing resin 7 has a resin top surface 71, a resin bottom surface 72, and resin side surfaces 73-76.
  • the resin top surface 71 and the resin bottom surface 72 are located apart from each other in the z direction.
  • the resin top surface 71 and the resin bottom surface 72 face opposite sides in the z-direction.
  • the resin top surface 71 is positioned on the z1 side in the z direction and faces the z1 side like the main surface 31 of the first die pad 3 .
  • the resin bottom surface 72 is positioned on the z2 side in the z direction and, like the back surface 32 of the first die pad 3, faces the z2 side.
  • Each of resin top surface 71 and resin bottom surface 72 is flat (or substantially flat).
  • Each of the resin side surfaces 73 to 76 is connected to the resin top surface 71 and the resin bottom surface 72, and is sandwiched between the resin top surface 71 and the resin bottom surface 72 in the z-direction.
  • the resin side surface 73 and the resin side surface 74 are positioned apart from each other in the x direction.
  • the resin side surface 73 and the resin side surface 74 face opposite sides in the x direction.
  • the resin side surface 73 is positioned on the x1 side in the x direction, and the resin side surface 74 is positioned on the x2 side in the x direction.
  • the resin side surfaces 75 and 76 are separated from each other in the y-direction and connected to the resin side surfaces 73 and 74 .
  • the resin side surface 75 and the resin side surface 76 face opposite sides in the y direction.
  • the resin side surface 75 is positioned on the y1 side in the y direction, and the resin side surface 76 is positioned on the y2 side in the y direction.
  • a portion of each of the plurality of first terminals 51 protrudes from the resin side surface 73 .
  • a part of each of the plurality of second terminals 52 protrudes from the resin side surface 74 .
  • the resin side surface 73 includes a first resin area 731, a second resin area 732, and a third resin area 733.
  • the first resin region 731 has one end in the z direction connected to the resin top surface 71 and the other end in the z direction connected to the third resin region 733 .
  • the resin first region 731 is inclined with respect to the resin top surface 71 and the yz plane.
  • the second resin region 732 has one end in the z direction connected to the resin bottom surface 72 and the other end in the z direction connected to the third resin region 733 .
  • the resin second region 732 is inclined with respect to the resin bottom surface 72 and the yz plane.
  • the third resin region 733 has one end in the z direction connected to the first resin region 731 and the other end in the z direction connected to the second resin region 732 .
  • the resin third region 733 extends along the yz plane.
  • the third resin region 733 is located outside the resin top surface 71 and the resin bottom surface 72 when viewed in the z direction. A portion of each of the plurality of first terminals 51 is exposed from the resin third region 733 .
  • the resin side surface 74 includes a fourth resin area 741 , a fifth resin area 742 and a sixth resin area 743 .
  • the fourth resin region 741 has one end in the z direction connected to the resin top surface 71 and the other end in the z direction connected to the sixth resin region 743 .
  • the fourth resin region 741 is inclined with respect to the resin top surface 71 and the yz plane.
  • the fifth resin region 742 has one end in the z direction connected to the resin bottom surface 72 and the other end in the z direction connected to the sixth resin region 743 .
  • the fifth resin region 742 is inclined with respect to the resin bottom surface 72 and the yz plane.
  • the sixth resin region 743 has one end in the z direction connected to the fourth resin region 741 and the other end in the z direction connected to the fifth resin region 742 .
  • the sixth resin region 743 extends along the yz plane. As viewed in the z-direction, the sixth resin region 743 is located outside the resin top surface 71 and the resin bottom surface 72 . A portion of each of the plurality of second terminals 52 is exposed from the sixth resin region 743 .
  • the resin side surface 75 includes a seventh resin area 751 , an eighth resin area 752 and a ninth resin area 753 .
  • the seventh resin region 751 has one end in the z direction connected to the resin top surface 71 and the other end in the z direction connected to the ninth resin region 753 .
  • the resin seventh region 751 is inclined with respect to the resin top surface 71 and the xz plane.
  • the eighth resin region 752 connects to the resin bottom surface 72 at one end in the z direction, and connects to the ninth resin region 753 at the other end in the z direction.
  • the eighth resin region 752 is inclined with respect to the resin bottom surface 72 and the xz plane.
  • the ninth resin region 753 has one end in the z direction connected to the seventh resin region 751 and the other end in the z direction connected to the eighth resin region 752 .
  • the ninth resin region 753 extends along the xz plane.
  • the ninth resin region 753 is located outside the resin top surface 71 and the resin bottom surface 72 when viewed in the z direction.
  • the resin side surface 76 includes a tenth resin area 761 , an eleventh resin area 762 and a twelfth resin area 763 .
  • the tenth resin region 761 has one end in the z direction connected to the resin top surface 71 and the other end in the z direction connected to the twelfth resin region 763 .
  • the resin tenth region 761 is inclined with respect to the resin top surface 71 and the xz plane.
  • the eleventh resin region 762 has one end in the z direction connected to the resin bottom surface 72 and the other end in the z direction connected to the twelfth resin region 763 .
  • the eleventh resin region 762 is inclined with respect to the resin bottom surface 72 and the xz plane.
  • the twelfth resin region 763 has one end in the z direction connected to the tenth resin region 761 and the other end in the z direction connected to the eleventh resin region 762 .
  • the twelfth resin region 763 extends along the xz plane. As viewed in the z-direction, the twelfth resin region 763 is located outside the resin top surface 71 and the resin bottom surface 72 .
  • FIGS. 10 and 11 are plan views showing steps related to the method of manufacturing the semiconductor device A10.
  • the lead frame 81 is a plate-shaped material.
  • the base material of the lead frame 81 is made of Cu.
  • the lead frame 81 may be formed by etching a metal plate or the like, or may be formed by punching a metal plate. In this embodiment, the lead frame 81 is formed by etching.
  • the lead frame 81 has a main surface 81A and a back surface 81B spaced apart in the z-direction.
  • the lead frame 81 also includes an outer frame 811 , a first die pad 812 A, a second die pad 812 B, a plurality of first leads 813 , a plurality of second leads 814 , a plurality of connection portions 815 and dam bars 816 .
  • the outer frame 811 and the dam bar 816 do not constitute the semiconductor device A10.
  • the first die pad 812A is a portion that becomes the first die pad 3 later.
  • the second die pad 812B is a portion that will become the second die pad 4 later.
  • the multiple first leads 813 are sites that will later become the multiple first terminals 51 and the pad section 53 .
  • the plurality of second leads 814 are portions that later become the plurality of second terminals 52 and the pad section 55 .
  • the plurality of connecting portions 815 are portions that will later become the pair of connecting portions 54 and the pair of connecting portions 56 .
  • uneven portions 21 are formed in predetermined portions of the lead frame 81 .
  • the uneven portion 21 is formed over the entire first die pad 812A. That is, the uneven portion 21 is formed on the entire surface of the first die pad 812A portion of the main surface 81A (the stippled portion in FIG. 10), the first die pad 812A portion of the back surface 81B, and the side surface of the first die pad 812A (the surface connecting the main surface 81A and the back surface 81B).
  • a mask is formed on a portion of the lead frame 81 where the concave-convex portion 21 is not formed.
  • the lead frame 81 with the mask formed thereon is immersed in an etchant.
  • the portions of the lead frame 81 where the mask is not formed are eroded by the etchant, and the uneven portions 21 having fine irregular unevenness are formed.
  • the uneven portion 21 may be formed by dry etching.
  • the first semiconductor element 11 and the insulating element 13 are bonded to the first die pad 812A by die bonding, and the second semiconductor element 12 is bonded to the second die pad 812B by die bonding.
  • each of the plurality of wires 61-64 is formed by wire bonding.
  • a sealing resin 7 is formed.
  • the sealing resin 7 is formed by transfer molding.
  • the lead frame 81 is housed in a mold having a plurality of cavities.
  • the portion of the lead frame 81 that will become the conductive member 2 covered with the sealing resin 7 in the semiconductor device A10 is accommodated in one of the plurality of cavities.
  • the fluidized resin is poured from the pot into each of the plurality of cavities through runners.
  • resin burrs located outside each of the plurality of cavities are removed with high-pressure water or the like. Formation of the sealing resin 7 is thus completed.
  • the semiconductor device A10 is manufactured.
  • the first die pad 3 is provided with the uneven portion 21 .
  • the concave-convex portion 21 is formed with a plurality of fine concave portions and is covered with the sealing resin 7 . Since the encapsulating resin 7 enters the fine recesses and is solidified, the anchoring effect improves the adhesion with the first die pad 3 . Therefore, peeling of the sealing resin 7 from the first die pad 3 is suppressed. Thereby, the semiconductor device A10 can suppress dielectric breakdown caused by peeling of the sealing resin 7 .
  • the uneven portion 21 is arranged over the entire main surface 31 of the first die pad 3 . Since the first semiconductor element 11 is mounted on the main surface 31, thermal stress is more likely to act on the main surface 31 than other surfaces, and peeling is likely to occur. By arranging the uneven portion 21 on the main surface 31 , peeling of the sealing resin 7 on the main surface 31 can be suppressed. In addition, even if the sealing resin 7 is peeled off from the first die pad 3 , it is possible to prevent the peeling from spreading to the insulating element 13 . Further, according to the present embodiment, the uneven portion 21 is also arranged on the entire surfaces of the side surfaces 33 to 36 connected to the main surface 31 .
  • the uneven portions 21 are also arranged at the corner portions 39a to 39h. Therefore, it is possible to suppress the peeling of the sealing resin 7 at the corner portions 39a to 39h, which tend to be starting points of peeling.
  • the uneven portion 21 is formed by etching. This is advantageous when forming the uneven portion 21 over a wide range. In addition, fine and irregular unevenness can be formed on the uneven portion 21 .
  • FIG. 12 is a diagram for explaining the semiconductor device A11 according to the first modification of the first embodiment.
  • FIG. 12 is a perspective view showing the first die pad 3 of the semiconductor device A11, corresponding to FIG.
  • the concave-convex portion 21 according to the first modified example is formed by regularly arranging a plurality of fine concave portions.
  • the uneven portion 21 is formed by laser processing.
  • the concave-convex portion 21 is formed with a plurality of concave portions extending in the x-direction and arranged side by side in the y-direction.
  • the uneven portion 21 is formed with a plurality of recesses extending in the z-direction and arranged side by side in the x-direction or the y-direction. This is formed by irradiating a laser beam to scan in the z-direction, and repeating scanning in the x-direction while moving the laser irradiation position in the x-direction or the y-direction.
  • the scanning direction of the laser on each surface is not limited.
  • the concave-convex portion 21 may be formed by overlapping concave portions extending in a plurality of directions.
  • the concave-convex portion 21 may be formed by forming a plurality of concave portions extending in the x direction and arranged side by side in the y direction on the main surface 31, and forming a plurality of concave portions extending in the y direction and arranged side by side in the x direction.
  • the method of forming the concave-convex portion 21 is not limited, and for example, it may be formed by stamping.
  • the lead frame 81 may be formed by punching a metal plate, and in the following step, the concave-convex portion 21 may be formed by crushing using a mold having concave-convex inner surfaces.
  • the method of forming the uneven portion 21 is not limited at all.
  • FIG. 13 is a diagram for explaining the semiconductor device A12 according to the second modification of the first embodiment.
  • FIG. 13 is a perspective view showing the first die pad 3 of the semiconductor device A12, corresponding to FIG.
  • the first die pad 3 according to the second modification includes a region 22 in which the uneven portion 21 is not arranged on the main surface 31 .
  • the uneven portion 21 is arranged not on the entire surface of the main surface 31 but only on a part of the main surface 31 .
  • the region 22 of the main surface 31 is indicated by an imaginary line (chain double-dashed line).
  • a region 22 is a region where the first semiconductor element 11 and the insulating element 13 are mounted.
  • the area 22 does not come into contact with the sealing resin 7, so it is not necessary to form the uneven portion 21 thereon.
  • the uneven portion 21 is formed by laser, the area for forming the uneven portion 21 can be reduced, so the time for forming the uneven portion 21 can be shortened.
  • the irregularities 21 may not be arranged on the entire surface of each surface, and may be arranged only partially.
  • FIG. 14 is a diagram for explaining the semiconductor device A13 according to the third modification of the first embodiment.
  • FIG. 14 is a perspective view showing the first die pad 3 of the semiconductor device A13, corresponding to FIG.
  • the uneven portion 21 is arranged only on the main surface 31 . That is, the uneven portion 21 is not arranged on the back surface 32 and the side surfaces 33 to 36 .
  • the uneven portion 21 is arranged on the main surface 31 of the first die pad 3 , peeling of the sealing resin 7 on the main surface 31 can be suppressed. Moreover, even if peeling occurs, it is possible to suppress the peeling from spreading to the insulating element 13 .
  • FIG. 15 is a diagram for explaining a semiconductor device A14 according to the fourth modification of the first embodiment.
  • FIG. 15 is a perspective view showing the first die pad 3 of the semiconductor device A14, corresponding to FIG.
  • the uneven portions 21 are arranged only on the main surface 31 and the side surfaces 34 . That is, the uneven portion 21 is not arranged on the back surface 32 and the side surfaces 33 , 35 , 36 .
  • peeling of the sealing resin 7 at the boundary between the main surface 31 and the side surface 34 can be suppressed. Since the boundary portion is closer to the insulating element 13 than other boundary portions, it is possible to effectively prevent the peeling from spreading to the insulating element 13 by suppressing the peeling. In addition, since the boundary portion is closer to the second die pad 4 than the other boundary portions, it is possible to effectively suppress cracks caused by peeling from reaching the second die pad 4 and causing dielectric breakdown.
  • the uneven portion 21 may not be arranged on all of the main surface 31, the back surface 32, and the side surfaces 33 to 36, and may be arranged only on some surfaces. Note that the surface on which the uneven portion 21 is arranged is not limited. However, it is desirable that the uneven portion 21 is formed at least on the main surface 31 .
  • FIG. 16 is a diagram for explaining the semiconductor device A20 according to the second embodiment of the present disclosure.
  • FIG. 16 is a plan view showing the semiconductor device A20, corresponding to FIG. In FIG. 16 , for convenience of understanding, the outer shape of the sealing resin 7 is shown by an imaginary line (chain double-dashed line) through the sealing resin 7 .
  • the semiconductor device A20 of this embodiment differs from that of the first embodiment in that the second die pad 4 is also formed with an uneven portion 21 .
  • the configuration and operation of other portions of this embodiment are the same as those of the first embodiment.
  • each part of said 1st Embodiment and each modification may be combined arbitrarily.
  • the uneven portion 21 is also arranged on the entire surface of the main surface 41, the back surface 42, and the side surfaces 43 to 46 of the second die pad 4. As shown in FIG.
  • the uneven portion 21 may not be arranged on the entire surface of each surface of the second die pad 4 (may be arranged only on a part), and may not be arranged on all of the main surface 41, the back surface 42, and the side surfaces 43 to 46 (may be arranged on only a part). Variations similar to those of the first die pad 3 shown in each variation of the first embodiment can be applied to the uneven portion 21 arranged on the second die pad 4 as well.
  • the uneven portion 21 is arranged on the first die pad 3, the adhesion between the sealing resin 7 and the first die pad 3 is improved, and peeling of the sealing resin 7 can be suppressed.
  • the semiconductor device A20 can suppress dielectric breakdown caused by peeling of the sealing resin 7 .
  • the semiconductor device A20 has the same effect as the semiconductor device A10 due to the configuration common to the semiconductor device A10.
  • the uneven portion 21 is also formed on the second die pad 4, peeling of the sealing resin 7 on the second die pad 4 can be suppressed. As a result, it is possible to prevent cracks caused by peeling from reaching the first die pad 3 and causing dielectric breakdown.
  • the uneven portion 21 may be formed not only on the first die pad 3 and the second die pad 4 but also on the entire conductive member 2 . In this case, if the uneven portion 21 is formed by etching or the like, it is not necessary to form a mask on the lead frame 81, so the manufacturing process can be simplified.
  • FIG. 17 and 18 are diagrams for explaining the semiconductor device A30 according to the third embodiment of the present disclosure.
  • FIG. 17 is a plan view showing the semiconductor device A30, corresponding to FIG.
  • the outer shape of the sealing resin 7 is shown by an imaginary line (chain double-dashed line) through the sealing resin 7 .
  • FIG. 18 is a perspective view showing the first die pad 3 of the semiconductor device A30, corresponding to FIG.
  • the semiconductor device A30 of the present embodiment differs from the first embodiment in that the uneven portion 21 is arranged only at each corner portion of the first die pad 3 .
  • the configuration and operation of other portions of this embodiment are the same as those of the first embodiment. It should be noted that each part of the above-described first and second embodiments and modifications may be combined arbitrarily.
  • the uneven portions 21 are arranged only at the respective corner portions 39a to 39h of the first die pad 3. As shown in FIG. In FIGS. 17 and 18, each uneven portion 21 is surrounded by an imaginary line (a chain double-dashed line) and dotted. As shown in FIG. 18, the main surface 31, the back surface 32, and the side surfaces 33 to 36 are provided with the uneven portions 21 spaced apart from each other at the four corners. The uneven portions 21 arranged at the respective corner portions 39a to 39h are arranged apart from each other.
  • the uneven portion 21 is arranged on the first die pad 3, the adhesion between the sealing resin 7 and the first die pad 3 is improved, and peeling of the sealing resin 7 can be suppressed.
  • the semiconductor device A30 can suppress dielectric breakdown caused by peeling of the sealing resin 7 .
  • the semiconductor device A30 has the same effect as the semiconductor device A10 due to the configuration common to the semiconductor device A10.
  • the area for arranging the uneven portion 21 can be minimized while suppressing the peeling of the sealing resin 7 at the corner portions 39a to 39h where peeling tends to occur.
  • the uneven portions 21 are arranged at all the corner portions 39a to 39h, but the present invention is not limited to this.
  • the uneven portion 21 may be arranged only on one of the corner portions 39a to 39h.
  • the uneven portion 21 may be arranged only at the corner portions 39a, 39b, 39e, 39f on the main surface 31 side, or may be arranged only at the corner portions 39a, 39b, 39c, 39d on the side surface 34 side. In these cases, it is possible to further reduce the area in which the concave-convex portion 21 is arranged while suppressing the peeling of the portion where peeling is likely to occur or where problems are more likely to occur if peeling occurs.
  • FIG. 19 is a diagram for explaining a semiconductor device A31 according to the first modification of the third embodiment.
  • FIG. 19 is a perspective view showing the first die pad 3 of the semiconductor device A31, corresponding to FIG.
  • the uneven portion 21 arranged at the corner portion 39a and the uneven portion 21 arranged at the corner portion 39c are connected.
  • the uneven portion 21 arranged at the corner portion 39b and the uneven portion 21 arranged at the corner portion 39d are connected.
  • the uneven portion 21 arranged at the corner portion 39e and the uneven portion 21 arranged at the corner portion 39g are connected.
  • the uneven portion 21 arranged at the corner portion 39f and the uneven portion 21 arranged at the corner portion 39h are connected.
  • the uneven portions 21 arranged at the corner portions 39a to 39h may not all be separated from each other.
  • FIG. 20 is a diagram for explaining a semiconductor device A40 according to the fourth embodiment of the present disclosure.
  • FIG. 20 is a plan view showing the semiconductor device A40, corresponding to FIG. In FIG. 20, for convenience of understanding, the outer shape of the sealing resin 7 is shown by an imaginary line (double-dot chain line) through the sealing resin 7 .
  • the semiconductor device A40 of this embodiment differs from that of the first embodiment in that the insulating element 13 is mounted on the second die pad 4 .
  • the configuration and operation of other portions of this embodiment are the same as those of the first embodiment. It should be noted that each part of the above-described first to third embodiments and modifications may be arbitrarily combined.
  • the second die pad 4 has a larger dimension in the x direction than in the first embodiment.
  • the first die pad 3 has a smaller dimension in the x direction than in the first embodiment.
  • the insulating element 13 is mounted on the second die pad 4 .
  • the first die pad 3 is not formed with the concave-convex portion 21, and the second die pad 4 on which the insulating element 13 is mounted is formed with the concave-convex portion 21.
  • the semiconductor device A40 since the semiconductor device A40 has the uneven portion 21 arranged on the second die pad 4, the adhesion between the sealing resin 7 and the second die pad 4 is improved, and peeling of the sealing resin 7 can be suppressed. Thereby, the semiconductor device A40 can suppress dielectric breakdown caused by peeling of the sealing resin 7 . In addition, the semiconductor device A40 has the same effect as the semiconductor device A10 due to the configuration common to the semiconductor device A10.
  • FIG. 21 is a diagram for explaining a semiconductor device A50 according to the fifth embodiment of the present disclosure.
  • FIG. 21 is a plan view showing the semiconductor device A50, corresponding to FIG. In FIG. 21, for convenience of understanding, the outer shape of the sealing resin 7 is shown by an imaginary line (double-dot chain line) through the sealing resin 7 .
  • the semiconductor device A50 of this embodiment is different from that of the first embodiment in that it further includes a third die pad 9 and the first semiconductor element 11 is mounted on the third die pad 9 .
  • the configuration and operation of other portions of this embodiment are the same as those of the first embodiment. It should be noted that each part of the above-described first to fourth embodiments and modifications may be combined arbitrarily.
  • the first die pad 3 is arranged in the center of the semiconductor device A50 in the x direction.
  • the first die pad 3 extends to both ends of the sealing resin 7 in the y direction, and has an end portion on the y direction y1 side exposed from the resin side surface 75 and an end portion on the y direction y2 side exposed from the resin side surface 76 .
  • the conductive member 2 further includes a third die pad 9 .
  • the third die pad 9 is arranged away from the first die pad 3 on the x-direction x1 side of the first die pad 3 .
  • the first semiconductor element 11 is mounted on the third die pad 9 .
  • the semiconductor device A50 can suppress dielectric breakdown caused by peeling of the sealing resin 7 . Further, the semiconductor device A50 has the same effect as the semiconductor device A10 due to the configuration common to the semiconductor device A10.
  • FIG. 22 is a diagram for explaining a semiconductor device A60 according to the sixth embodiment of the present disclosure.
  • FIG. 22 is a plan view showing the semiconductor device A60, corresponding to FIG. In FIG. 22 , for convenience of understanding, the outer shape of the sealing resin 7 is shown by an imaginary line (chain double-dashed line) through the sealing resin 7 .
  • the semiconductor device A60 of this embodiment differs from that of the first embodiment in that the first semiconductor element 11 and the second semiconductor element 12 are not provided.
  • the configuration and operation of other portions of this embodiment are the same as those of the first embodiment. It should be noted that each part of the above-described first to fifth embodiments and modifications may be combined arbitrarily.
  • the semiconductor device A60 does not include the first semiconductor element 11 and the second semiconductor element 12. Also, the semiconductor device A60 does not have the second die pad 4 and the wires 61 and 62 either. Only the insulating element 13 is mounted on the first die pad 3 , each wire 63 is conductively joined to the pad portion 53 , and each wire 64 is conductively joined to the pad portion 55 .
  • the semiconductor device A60 can suppress dielectric breakdown caused by peeling of the sealing resin 7 .
  • the semiconductor device A60 has the same effect as the semiconductor device A10 due to the configuration common to the semiconductor device A10.
  • the semiconductor device A60 may further include the first semiconductor element 11 (control element), may further include the second semiconductor element 12 (drive element), or may further include other elements.
  • the insulating element 13 may incorporate a circuit having the function of a control element, or may incorporate a circuit having the function of a driving element.
  • the mounted element is not limited to anything other than an insulating element.
  • the semiconductor device according to the present disclosure is not limited to the above-described embodiments.
  • the specific configuration of each part of the semiconductor device according to the present disclosure can be changed in various ways.
  • the present disclosure includes embodiments set forth in the following appendices.
  • Appendix 1 an insulating element (13); a conductive member (2) on which the insulating element is mounted; a sealing resin (7) covering the insulating element; with The semiconductor device according to claim 1, wherein the conductive member has an uneven portion (21) covered with the sealing resin.
  • Appendix 2. the conductive member includes a first die pad (3) on which the insulating element is mounted; The semiconductor device according to appendix 1, wherein the uneven portion includes a first region arranged on the first die pad.
  • the first die pad has a main surface (31) on which the insulating element is mounted, The semiconductor device according to appendix 2, wherein the first region is arranged on the main surface.
  • the semiconductor device according to appendix 3 wherein the first region is arranged only on part of the main surface.
  • Appendix 5. The first die pad has a first side surface (33) connected to the main surface, 5.
  • the semiconductor device according to appendix 3 or 4 wherein the uneven portion includes a second region arranged on the first side surface.
  • Appendix 6. The semiconductor device according to appendix 5, wherein the second region is arranged only on part of the first side surface.
  • Appendix 7. the first die pad has a second side surface (34) connected to the main surface and the first side surface; 7.
  • Appendix 9. The semiconductor device according to appendix 7 or 8, wherein at a first corner portion (39a) where the main surface, the first side surface, and the second side surface are connected to each other, the first region is arranged on the main surface, the second region is arranged on the first side surface, and the third region is arranged on the second side surface.
  • the first die pad has a third side surface (35) connected to the main surface and the second side surface; The uneven portion is a fourth region spaced apart from the first region on the main surface; a fifth region spaced apart from the third region on the second side; a sixth region disposed on the third side; including 10.
  • the semiconductor device according to any one of appendices 7 to 9, wherein at a second corner portion (39b) where the main surface, the second side surface, and the third side surface are connected to each other, the fourth region is arranged on the main surface, the fifth region is arranged on the second side surface, and the sixth region is arranged on the third side surface.
  • Appendix 11 The first die pad has a back surface (32) facing away from the main surface in the thickness direction, The uneven portion is a seventh region spaced apart from the second region on the first side; an eighth region spaced apart from the third region on the second side; a ninth region arranged on the back surface; including 11.
  • control element (11) conducting to said insulating element; a driving element (12) electrically conductive to the insulating element; further comprising The control element is mounted on the first die pad, 13.
  • Appendix 14. The semiconductor device according to any one of appendices 1 to 13, wherein the uneven portion includes a plurality of concave portions arranged irregularly. Appendix 15. 14. The semiconductor device according to any one of appendices 1 to 13, wherein the uneven portion is a plurality of concave portions regularly arranged.

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PCT/JP2022/047430 2022-01-20 2022-12-22 半導体装置 Ceased WO2023140042A1 (ja)

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CN202280089355.5A CN118633155A (zh) 2022-01-20 2022-12-22 半导体装置
US18/777,194 US20240379574A1 (en) 2022-01-20 2024-07-18 Semiconductor device

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US12417954B2 (en) * 2020-04-27 2025-09-16 Rohm Co., Ltd. Semiconductor device

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JPH0992778A (ja) * 1995-09-27 1997-04-04 Mitsui High Tec Inc 半導体装置
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JP2010161098A (ja) * 2009-01-06 2010-07-22 Nichiden Seimitsu Kogyo Kk リードフレームの製造方法及びリードフレーム、ヒートシンクの製造方法及びヒートシンク
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JPH0855866A (ja) * 1994-06-06 1996-02-27 Motorola Inc ポリマーと金属との間の界面接着を改善する方法および装置
JPH0992778A (ja) * 1995-09-27 1997-04-04 Mitsui High Tec Inc 半導体装置
US20060097366A1 (en) * 2003-07-19 2006-05-11 Ns Electronics Bangkok (1993) Ltd. Semiconductor package including leadframe roughened with chemical etchant to prevent separation between leadframe and molding compound
JP2005159137A (ja) * 2003-11-27 2005-06-16 Sharp Corp 光半導体素子およびこの光半導体素子を用いた電子機器
JP2010161098A (ja) * 2009-01-06 2010-07-22 Nichiden Seimitsu Kogyo Kk リードフレームの製造方法及びリードフレーム、ヒートシンクの製造方法及びヒートシンク
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