WO2023138153A1 - 半导体器件及其制作方法、电子设备 - Google Patents

半导体器件及其制作方法、电子设备 Download PDF

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WO2023138153A1
WO2023138153A1 PCT/CN2022/129022 CN2022129022W WO2023138153A1 WO 2023138153 A1 WO2023138153 A1 WO 2023138153A1 CN 2022129022 W CN2022129022 W CN 2022129022W WO 2023138153 A1 WO2023138153 A1 WO 2023138153A1
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dielectric layer
layer
trench
field plate
dielectric
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PCT/CN2022/129022
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English (en)
French (fr)
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蒲奎
姚昌荣
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华为技术有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/404—Multiple field plate structures
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes
    • H01L29/8725—Schottky diodes of the trench MOS barrier type [TMBS]

Definitions

  • the present application relates to the technical field of semiconductors, in particular to a semiconductor device, a manufacturing method thereof, and electronic equipment.
  • a split gate trench metal oxide semiconductor field effect transistor is widely used in the field of power semiconductors.
  • the breakdown voltage breakdown voltage, VBR
  • VBR breakdown voltage
  • RSP specific on resistance
  • C gd gate-drain capacitance
  • FIG. 1 is a schematic structural diagram of a SGT MOS provided in the related art
  • (b) in FIG. 1 is an electric field distribution curve of the SGT MOS in (a) along the dotted line.
  • a field plate FP field plate
  • the gate-drain capacitance C gd is reduced, and the switching speed of the device is improved; at the same time, due to the introduction of the field plate FP, the breakdown electric field of the device is changed from a single-peak electric field of a parallel plane junction to a double-peak electric field.
  • the device In the double-peak electric field, one electric field is located at the PN junction between the P-well (P-well) region and the N-drift region, and the other electric field is located at the bottom of the trench.
  • the horizontal depletion is introduced on the basis of the vertical depletion (PN junction) through the setting of the field plate, and the electric field of the device is changed from a triangular distribution to a bimodal electric field distribution.
  • the device can obtain a higher breakdown voltage.
  • the bimodal electric field formed by field plate modulation is far from the ideal high breakdown voltage (corresponding to the rectangular electric field in Figure 2). Therefore, it has always been the pursuit goal of the industry to improve the breakdown voltage of devices by further modulating the electric field.
  • the present application provides a semiconductor device, its manufacturing method, and electronic equipment, which can improve the breakdown voltage of the device.
  • the present application provides a semiconductor device, and the semiconductor device is provided with a split-gate trench type field effect transistor (which may be referred to as a transistor for short).
  • the transistor includes a substrate, an epitaxial layer arranged on the substrate, a field plate, and an isolation dielectric layer.
  • the epitaxial layer is provided with a groove on the side away from the substrate, and a field plate is arranged in the groove.
  • the isolation dielectric layer covers at least the side of the field plate, and the isolation dielectric layer includes a first dielectric layer and a second dielectric layer covering the side of the field plate, the first dielectric layer is closer to the groove bottom of the groove than the second dielectric layer, and the dielectric coefficient of the second dielectric layer is greater than that of the first dielectric layer.
  • the split-gate trench field effect transistor may also include: a first metal layer, a second metal layer, and an insulating dielectric layer; wherein the first metal layer is disposed on the side of the substrate away from the epitaxial layer, and the insulating dielectric layer is disposed between the epitaxial layer and the second metal layer; the substrate is made of an N-type lightly doped semiconductor material; the epitaxial layer is divided from bottom to top: N-type lightly doped layer (N-), P-type doped layer (P), and N-type heavily doped layer (N+); the field plate is located where the N-type lightly doped layer is located area (i.e. drift area).
  • the first metal layer is used as the drain of the transistor, and the second metal layer is used as the source of the transistor.
  • the N-type lightly doped layer (N-) and the P-type doped layer (P) form the PN junction in the transistor, and the N-type heavily doped layer (N+) acts as the drift region of the transistor; the isolation dielectric layer is filled between the field plate and the drift region.
  • the substrate is made of P-type lightly doped semiconductor material; the epitaxial layer is divided into: P-type lightly doped layer, N-type doped layer, and P-type heavily doped layer from bottom to top.
  • two or more types of dielectric materials are used for the isolation dielectric layer on the side of the field plate, so that the dielectric coefficient of the isolation dielectric layer increases from bottom to top.
  • the capacitance per unit area can be made close to the PN junction of the transistor.
  • the electric field reduces the probability of the field plate breaking down the epitaxial layer (drift region) at the bottom of the trench.
  • the split-gate trench field effect transistor has a double-gate structure, and the transistor is provided with a first gate and a second gate in the trench.
  • the first grid and the second grid are located on both sides of the top of the field plate, and an interlayer dielectric layer is arranged between the first grid, the second grid and the field plate; the interlayer dielectric layer is located on the groove bottom side of the isolation dielectric layer away from the trench. That is, the split-gate trench field effect transistor is a double-gate trench field effect transistor.
  • the split-gate trench field effect transistor has a single-gate structure, and the transistor is provided with a gate in the trench; the gate is located on the side of the field plate away from the substrate, and an interlayer dielectric layer is provided between the gate and the field plate. That is, the split-gate trench field effect transistor is a single-gate trench field effect transistor.
  • the isolation dielectric layer further includes a third dielectric layer covering side surfaces of the field plate.
  • the third dielectric layer is farther away from the bottom of the trench than the second dielectric layer; the dielectric coefficient of the third dielectric layer is greater than that of the second dielectric layer.
  • At least one of the first dielectric layer or the second dielectric layer has a graded permittivity; the graded permittivity gradually increases along the direction from the bottom of the trench to the notch.
  • the greater the number of peaks of the electric field that can be obtained the closer the breakdown electric field distribution is to a rectangular distribution.
  • the first dielectric layer is made of a first dielectric material; the second dielectric layer is made of a multi-element compound dielectric material, and the atomic or molecular components of the multi-element compound dielectric material gradually change along the direction from the groove bottom to the notch opening. That is, the first dielectric layer has a fixed permittivity, and the second dielectric layer has a gradual permittivity.
  • SiO x N y , HfO x N y and the like can be used for the second dielectric layer.
  • an isolation buffer layer is provided between the isolation dielectric layer and the sidewall of the trench in the side area near the top of the field plate; in this case, a good interface is formed between the isolation buffer layer and the sidewall of the trench, thereby avoiding reliability problems such as leakage current caused by direct contact between the second dielectric layer and the sidewall of the trench.
  • the isolation buffer layer uses SiO 2 .
  • the isolation dielectric layer extends and covers the top surface of the field plate.
  • at least part of the interlayer dielectric layer may be formed while forming the second dielectric layer, that is, all or part of the interlayer dielectric layer is made of the same material as the second dielectric layer.
  • the interlayer dielectric layer includes an intermediate dielectric layer; the dielectric coefficient of the intermediate dielectric layer is smaller than the dielectric coefficient of the second dielectric layer. In this way, the parasitic capacitance between the gate and the field plate can be reduced by reducing the dielectric coefficient of the interlayer dielectric layer.
  • the intermediate dielectric layer covers the top surface of the field plate.
  • the entire interlayer dielectric layer can be made of a dielectric material with a relatively small dielectric coefficient, so as to further reduce the parasitic capacitance between the gate and the field plate.
  • At least one stepped structure is provided on the side of the field plate; among the two stepped surfaces of the stepped structure, the stepped surface near the notch side of the groove protrudes from the stepped surface near the groove bottom side of the groove. In this way, by providing a stepped structure on the side of the field plate, it is also possible to suppress electric field spikes in the vertical direction, increase the breakdown voltage of the device, and improve the reliability of the device.
  • the embodiment of the present application also provides a semiconductor device, and the semiconductor device is provided with trench-type electronic components.
  • the trench electronic element includes: a substrate, an epitaxial layer arranged on the substrate, a field plate, and an isolation dielectric layer.
  • the epitaxial layer is provided with a first groove on a side away from the substrate.
  • a field plate is arranged in the first trench.
  • the isolation medium layer covers at least the sides of the field plate.
  • the isolation dielectric layer includes a first dielectric layer and a second dielectric layer, the first dielectric layer is closer to the bottom of the first groove relative to the second dielectric layer; the dielectric coefficient of the second dielectric layer is greater than that of the first dielectric layer.
  • two or more dielectric materials are used for the isolation dielectric layer on the side of the field plate, so that the dielectric coefficient of the isolation dielectric layer increases from bottom to top.
  • the trench-type electronic component may be a non-split-gate trench-type field-effect transistor; the trench-type field-effect transistor further includes a gate located in the first trench, and the gate is connected to the top of the field plate.
  • the trench-type electronic component is a double-trench field-effect transistor; in the double-trench field-effect transistor, the epitaxial layer is further provided with a second trench on the side away from the substrate, and the second trench is arranged in parallel with the first trench; the gate is located in the second trench; the depth of the second trench is smaller than the depth of the first trench.
  • the trench type electronic component is a trench MOS barrier Schottky diode; the trench MOS barrier Schottky diode also includes a first metal layer and a second metal layer; the first metal layer is located on the side of the substrate away from the epitaxial layer, and the second metal layer is located on the side of the epitaxial layer away from the substrate; the top of the field plate is connected to the second metal layer.
  • the trench electronic component is an insulated gate bipolar transistor; the substrate is made of an N-type semiconductor material; and the insulated gate bipolar transistor further includes a gate and a P-type semiconductor layer.
  • the gate is located in the first trench, and the gate is located on the side of the field plate away from the bottom of the first trench.
  • the gate and the field plate are provided with an interlayer dielectric layer.
  • the P-type semiconductor layer is located on the side of the substrate away from the epitaxial layer.
  • the epitaxial layer includes an N-type doped region, a P-type doped region, and an N-type heavily doped region in sequence along the direction away from the substrate.
  • An embodiment of the present application further provides an electronic device, including a printed circuit board and a semiconductor device as provided in any one of the foregoing possible implementation manners; the semiconductor device is electrically connected to the printed circuit board.
  • the embodiment of the present application also provides a method for manufacturing a semiconductor device, the method includes: providing a substrate, and growing an epitaxial layer on the surface of the substrate.
  • a groove is formed on the surface of the epitaxial layer, and a first dielectric layer is formed in the inner wall of the groove.
  • a field plate is formed in the groove formed with the first dielectric layer, and the first dielectric layer is etched back to a depth below the top of the field plate.
  • a second dielectric layer is formed on the side of the field plate and on the surface of the first dielectric layer, and the dielectric coefficient of the second dielectric layer is greater than that of the first dielectric layer.
  • the formation of the second dielectric layer on the side of the field plate and on the surface of the first dielectric layer may include: depositing a multi-element compound dielectric material on the side of the field plate and on the surface of the first dielectric layer, and controlling the atomic or molecular components in the multi-element compound dielectric material during the deposition process to form a second dielectric layer with a gradually increasing dielectric coefficient.
  • the manufacturing method may further include: forming an intermediate dielectric layer on the top of the field plate, and the dielectric coefficient of the intermediate dielectric layer is smaller than the dielectric coefficient of the second dielectric layer.
  • FIG. 1 is a schematic diagram of a SGT MOS and its breakdown electric field distribution provided by the related technology of the present application;
  • Figure 2 is a schematic diagram of the ideal electric field distribution of SGT MOS
  • FIG. 3 is a schematic diagram of a SGT MOS and its breakdown electric field distribution provided by the embodiment of the present application;
  • FIG. 4 is a schematic structural diagram of a SGT MOS provided in the embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a SGT MOS provided in the embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of a SGT MOS provided in the embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a SGT MOS provided in an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of a SGT MOS provided in an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of a SGT MOS provided in an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of a SGT MOS provided in an embodiment of the present application.
  • FIG. 11 is a flow chart of a method for manufacturing an SGT MOS provided in the embodiment of the present application.
  • Fig. 12 is a schematic diagram of the manufacturing process of a SGT MOS provided by the embodiment of the present application.
  • Fig. 13 is a schematic diagram of the fabrication process of a SGT MOS provided in the embodiment of the present application.
  • FIG. 14 is a schematic structural diagram of a SGT MOS provided in the embodiment of the present application.
  • FIG. 15 is a flow chart of a method for manufacturing an SGT MOS provided in an embodiment of the present application.
  • FIG. 16 is a schematic diagram of the fabrication process of a SGT MOS provided in the embodiment of the present application.
  • Fig. 17 is a schematic diagram of the fabrication process of a SGT MOS provided in the embodiment of the present application.
  • FIG. 18 is a schematic structural diagram of a non-SGT MOS provided in the embodiment of the present application.
  • FIG. 19 is a flow chart of a non-SGT MOS fabrication method provided in the embodiment of the present application.
  • FIG. 20 is a schematic diagram of the fabrication process of a non-SGT MOS provided in the embodiment of the present application.
  • FIG. 21 is a schematic diagram of the fabrication process of a non-SGT MOS provided in the embodiment of the present application.
  • FIG. 22 is a schematic structural diagram of a double-trench SGT MOS provided in an embodiment of the present application.
  • FIG. 23 is a schematic structural diagram of an IGBT provided in an embodiment of the present application.
  • FIG. 24 is a schematic structural diagram of a trench MOS barrier Schottky diode provided in an embodiment of the present application.
  • At least one of the following or similar expressions refer to any combination of these items, including any combination of single or plural items.
  • at least one item (piece) of a, b or c can represent: a, b, c, "a and b", “a and c", “b and c", or “a and b and c", wherein a, b, c can be single or multiple.
  • "Installation”, “connection”, “connection”, etc. should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, or an indirect connection through an intermediary, or it can be the internal communication of two components.
  • An embodiment of the present application provides an electronic device, the electronic device includes a printed circuit board (printed circuit board, PCB) and a semiconductor device electrically connected to the printed circuit board, the semiconductor device is provided with grooved electronic components.
  • PCB printed circuit board
  • the semiconductor device may be a central processing unit (CPU), a graphics processing unit (GPU), a microcontroller unit (MCU), a motor drive, an uninterrupted power supply (UPS) power supply, etc.
  • CPU central processing unit
  • GPU graphics processing unit
  • MCU microcontroller unit
  • UPS uninterrupted power supply
  • the electronic device may be a mobile phone, a tablet computer, a notebook, a vehicle computer, a smart watch, a smart bracelet and other electronic products.
  • the semiconductor device adopts a trench-type electronic component provided with an internal field plate (field plate), that is, a trench-type electronic component is provided with a trench and a field plate is provided in the trench.
  • the trench-type electronic components may be trench-type field effect transistors (such as split-gate structure, non-split-gate structure, double-trench structure, etc.), trench-type MOS barrier Schottky diodes, insulated gate bipolar transistors and other electronic components.
  • the dielectric layer on the side of the field plate (that is, the isolation dielectric layer) in the trench of the trench-type electronic component to have two or more dielectric coefficients (that is, the dielectric constant) along the depth direction of the trench, the electric field outside the field plate is modulated, and the original double-peak electric field (as shown in Figure 1) is stabilized (weakened) to obtain a three-peak electric field distribution (as shown in Figure 3) or a multi-peak electric field distribution, and even an approximately ideal rectangular electric field distribution (as shown in Figure 2) can be achieved, thereby improving the device.
  • Breakdown voltage and thus obtain lower specific on-resistance (RSP), lower gate-drain capacitance C gd etc., which improves the figure of merit of the device and improves the reliability of the device.
  • Embodiment 1 provides a semiconductor device using a split-gate (single-gate) trench field effect transistor (hereinafter referred to as a transistor for short).
  • a split-gate single-gate trench field effect transistor
  • Figure 3 (a) is a schematic structural diagram of two SGT MOSs (that is, two cells) connected in parallel in a semiconductor device;
  • Figure 3 (b) is the electric field distribution curve of the SGT MOS in (a) along the dotted line.
  • the following is only a schematic illustration of a single SGT MOS as an example.
  • the SGT MOS may include a substrate 1, an epitaxial layer 2, and an insulating dielectric layer 3 sequentially disposed on the substrate.
  • the substrate 1 may be an N-type heavily doped semiconductor material, that is, an N+ substrate, and the N+ substrate serves as a drain region of a transistor.
  • the epitaxial layer 2 can be divided into N-type lightly doped layer (N-), P-type doped layer (P), and N-type heavily doped layer (N+) from bottom to top. drift) to form a PN junction.
  • both the substrate 1 and the epitaxial layer 2 may be made of silicon (Si), and the insulating dielectric layer 3 may be made of SiO 2 ; but it is not limited thereto.
  • FIG. 3 is only a schematic illustration of an N-type transistor as an example.
  • the transistor can also be a P-type transistor.
  • the substrate 1 can be a P+ substrate
  • the epitaxial layer 2 can be divided into a P-type lightly doped layer (P-), an N-type doped layer (N), and a P-type heavily doped layer (P+).
  • P- P-type lightly doped layer
  • N N-type doped layer
  • P+ P-type heavily doped layer
  • a first metal layer M1 is provided on the lower surface of the substrate 1 as the drain D of the transistor; a second metal layer M2 is provided on the upper surface of the insulating medium layer 3 as the source S of the transistor.
  • the second metal layer M2 is connected to the well region (P-well) through the metal plug m.
  • the metal plug m may be a tungsten plug (W plug), but not limited thereto.
  • W plug tungsten plug
  • heavy doping (P+) can be performed at the position corresponding to the metal plug m in the well region (P-well).
  • a trench T is provided on the upper surface of the epitaxial layer 2 (that is, the surface away from the substrate 1 ), and a field plate FP and a gate G are provided in the trench T, and the gate G is located above the field plate FP.
  • the gate G and the field plate FP can be made of polycrystalline silicon (polycrystalline silicon), but not limited thereto.
  • the depth of the gate G is basically consistent with the lower surface of the well region (P-well), and the field plate FP is entirely located in the drift region (N-drift).
  • Dielectric material is filled between the gate G and the trench T, between the field plate FP and the trench T, and between the gate G and the field plate FP to isolate the gate G, the field plate FP and the epitaxial layer 2 .
  • the isolation dielectric layer 10 Compared with the prior art where one type of dielectric material (i.e., having one type of dielectric constant) is used on the side of the field plate FP, in the embodiment of the present application, two or more types of dielectric materials are used for the isolation dielectric layer 10 on the side of the field plate FP, so that the dielectric coefficient of the isolation dielectric layer 10 increases from bottom to top. ⁇ , ⁇ 10 ⁇ , ⁇ (N-drift) ⁇ , ⁇ , ⁇ (N-drift) ⁇ 10 ⁇ , ⁇ , ⁇ , ⁇ ( ⁇ 3) ⁇ , ⁇ , ⁇ (RSP) ⁇ - ⁇ C gd ⁇ , ⁇ , ⁇ , ⁇
  • the capacitance per unit area can be made close to the PN junction (between the P-well and the N-drift), and the electric field lines of the charge in the drift region (N-drift) gather toward the top of the field plate FP, which can weaken the electric field at the PN junction position and provide better protection for the PN junction;
  • the capacitance per unit area at the bottom of the plate is small, thereby weakening the electric field at the bottom of the field plate FP and reducing the probability of the field plate FP breaking down the drift region (N-drift) at the bottom of the trench T.
  • the above-mentioned method of increasing the dielectric coefficient of the isolation dielectric layer 10 from bottom to top can be a stepwise increase or a gradual increase, which can be determined according to the specific arrangement of the isolation dielectric layer 10, which is not limited in the present application.
  • the isolation dielectric layer 10 may include a first dielectric layer a1 and a second dielectric layer a2 covering side surfaces of the field plate FP.
  • the first dielectric layer a1 is located below, and the second dielectric layer a2 is located above; that is, the first dielectric layer a1 is closer to the bottom of the trench T than the second dielectric layer a2 .
  • the first dielectric layer a1 uses the first dielectric material
  • the second dielectric layer a2 uses the second dielectric material
  • the dielectric coefficient k2 of the second dielectric material is greater than the dielectric coefficient k1 of the first dielectric material, ie k2>k1.
  • the first dielectric material may be SiO 2 (dielectric coefficient about 3.9); the second dielectric material may be Si 3 N 4 (dielectric coefficient about 7.9), HfO 2 (dielectric coefficient about 25), Al 2 O 3 (dielectric coefficient about 9), etc.; but not limited thereto.
  • the isolation dielectric layer 10 may include a first dielectric layer a1 , a second dielectric layer a2 , and a third dielectric layer a3 covering the sides of the field plate FP sequentially from bottom to top.
  • the first dielectric layer a1 adopts the first dielectric material
  • the second dielectric layer a2 adopts the second dielectric material
  • the third dielectric layer a3 adopts the third dielectric material
  • the dielectric coefficient k2 of the second dielectric material is greater than the dielectric coefficient k1 of the first dielectric material
  • the dielectric coefficient k3 of the third dielectric material is greater than the dielectric coefficient k2 of the second dielectric material, that is, k3>k2>k1.
  • the first dielectric material can be SiO 2 (permittivity about 3.9)
  • the second dielectric material can be Si 3 N 4 (permittivity about 7.9)
  • the third dielectric material can be HfO 2 (permittivity about 25); but not limited thereto.
  • the isolation dielectric layer 10 in FIG. 3 contains two dielectric layers with different permittivity on the side of the field plate FP
  • the modulation effect of the field plate on the electric field is changed, and a new peak electric field is introduced at the position where the dielectric layer changes abruptly (that is, the position where the permittivity changes), thereby obtaining a three-peak electric field distribution.
  • the isolation dielectric layer 10 in FIG. 4 contains three dielectric layers (a1, a2, a3) with different permittivity on the side of the field plate FP, four peak electric field distributions can be obtained.
  • first dielectric layer “first dielectric layer”, “second dielectric layer” and “third dielectric layer” involved in this application only refer to the relative concept of meeting the aforementioned design requirements in the isolation dielectric layer 10, and do not absolutely refer to a certain (certain) dielectric layer fixed in the isolation dielectric layer 10;
  • the "sides of the field plate” involved in this application refer to the lateral sides of the field plate FP, as shown in Figure 3 (a) of the schematic cross-sectional view of the field plate FP, the sides of the field plate FP are the surfaces on the left and right sides of the field plate FP; in the longitudinal direction, the field plate FP has a planar structure.
  • the grid G located above the field plate extends in the same direction as the field plate FP in the longitudinal direction, and the lengths of the two are basically the same.
  • Fig. 3 and Fig. 4 are only schematically illustrated by taking the isolation dielectric layer 10 containing two and three dielectric layers with different dielectric coefficients as an example, but the present application is not limited thereto, and the isolation dielectric layer 10 can also be provided with 4 or more than 4 dielectric layers with different dielectric coefficients. The following are schematic illustrations by taking the isolation dielectric layer 10 containing two dielectric layers as an example.
  • each dielectric layer (a1, a2, a3) in the aforementioned isolation dielectric layer 10 a single dielectric material is used, that is, each dielectric layer has a fixed dielectric coefficient, and the dielectric coefficient of the isolation dielectric layer 10 increases stepwise from bottom to top.
  • part or all of the dielectric layers in the isolation dielectric layer 10 have a graded permittivity, that is, the permittivity changes continuously along the depth direction of the trench.
  • the change law of the gradient dielectric coefficient can be one or a combination of various forms such as linear, nonlinear, and piecewise functions.
  • the isolation dielectric layer 10 may include a first dielectric layer a1 and a second dielectric layer a2.
  • the first dielectric layer a1 is located below, and the second dielectric layer a2 is located above; that is, the first dielectric layer a1 is closer to the bottom of the trench T than the second dielectric layer a2 .
  • the second dielectric layer a2 can be made of a multi-component compound dielectric material, and the atomic or molecular components of the multi-component compound dielectric material gradually change from bottom to top, so as to ensure that the graded dielectric coefficient k2 gradually increases from bottom to top.
  • the multi-component dielectric material such as SiO x N y , HfO x N y and so on.
  • the multi-component compound dielectric material used in the second dielectric layer a2 and its atomic or molecular components can be selected according to the dielectric material used in the first dielectric layer a1.
  • the first dielectric material may be SiO 2 (dielectric coefficient about 3.9), and the second dielectric layer a2 may be SiO x N y .
  • the second dielectric layer a2 may use HfO x N y , and the dielectric coefficient k2 may be modulated within a range from 4 to 24.
  • the present application does not limit the manufacturing method of the above-mentioned second dielectric layer a2 having a graded dielectric coefficient k2, and in practice, an appropriate manufacturing method can be selected according to needs.
  • HDP-CVD high density plasma chemical vapor deposition
  • HDP-CVD technology can be used to achieve anisotropic deposition by etching while depositing; that is, while depositing in the vertical direction, the material deposited horizontally to the sidewall is etched; thereby obtaining a dielectric layer with a dielectric constant that changes gradually in the vertical direction (that is, from bottom to top).
  • the second dielectric layer a2 is only schematically illustrated as an example with a graded dielectric coefficient, but the present application is not limited thereto.
  • the first dielectric layer a1 may also be set to have a graded dielectric coefficient;
  • the isolation dielectric layer 10 may also be set to be a single dielectric layer with a graded dielectric coefficient.
  • the isolation dielectric layer 10 may also be set to be a single dielectric layer with a graded dielectric coefficient.
  • the isolation dielectric layer 10 in the case of using three dielectric layers (a1, a2, a3) for the isolation dielectric layer 10, one or more of the three dielectric layers (a1, a2, a3) can be set to have a graded dielectric coefficient.
  • the specific material of the isolation buffer layer 11 is not limited in the present application, as long as a good interface between the isolation buffer layer 11 and the sidewall of the trench T is ensured.
  • the epitaxial layer 2 is made of silicon (Si)
  • the second dielectric layer a2 is made of Si 3 N 4 , HfO 2 , Al 2 O 3 and other dielectric materials with high dielectric coefficients, but the quality of the interface between these dielectric materials and silicon is poor.
  • the isolation buffer layer 11 can be set to use SiO 2 , and SiO 2 can form a good interface with Si.
  • the isolation buffer layer 11 may also use silicon oxynitride (SiO x N y ), etc., which is not limited in this application.
  • the isolation buffer layer 11 can be fabricated separately; in some embodiments, as shown in FIG.
  • the second dielectric layer a2 can be set to extend from the side of the field plate FP and cover its upper surface (top surface), that is, when the second dielectric layer a2 is formed, the interlayer dielectric layer 20 between the gate G and the field plate FP is formed.
  • the interlayer dielectric layer 20 and the second dielectric layer a2 use the same dielectric material.
  • the corresponding interlayer dielectric layer 20 has a relatively high dielectric coefficient, which will lead to a large parasitic capacitance between the gate G and the field plate FP, which will further reduce the switching speed of the transistor. Therefore, the parasitic capacitance between the gate G and the field plate FP can be reduced by reducing the dielectric coefficient of the interlayer dielectric layer 20 .
  • the second dielectric layer a2 can be set to extend from the side of the field plate FP and slightly cover the top of the field plate FP, and an intermediate dielectric layer b is added between the gate G and the field plate FP.
  • the dielectric coefficient of the intermediate dielectric layer b is smaller than that of the second dielectric layer a2; in this case, the interlayer dielectric layer 20 includes upper and lower layers.
  • the upper layer may be a Si 3 N 4 layer with a thickness of about 15 nm
  • the lower layer may be a SiO 2 layer with a thickness of about 10 nm.
  • the interlayer dielectric layer 20 can all be made of an intermediate dielectric layer b with a small dielectric coefficient, that is, the intermediate dielectric layer b directly covers the upper surface of the field plate FP; of course, in this case, according to the actual manufacturing process, the interlayer dielectric layer 20 can be appropriately extended downward to the side of the field plate FP.
  • At least one stepped structure 30 may be provided on the side of the field plate FP.
  • the stepped structure 30 includes two stepped surfaces: an upper stepped surface (that is, the stepped surface on the side near the notch of the groove) and a lower stepped surface (that is, the stepped surface on the side near the bottom of the groove), the upper stepped surface protrudes from the lower stepped surface; that is, the width of the field plate FP is a structure that is wide at the top and narrow at the bottom.
  • the capacitance per unit area between the field plate and the drift region (N-drift) is changed, thereby changing the modulation effect of the field plate on the electric field, thereby introducing a new peak electric field at the position of the stepped structure 30, increasing the breakdown voltage of the device, and improving the reliability of the device.
  • the stepped structure 30 may be disposed on the side of the field plate FP in a region corresponding to the first dielectric layer a1 .
  • the stepped structure 30 may be disposed on the side of the field plate FP in a region corresponding to the second dielectric layer a2 .
  • the side surfaces of the field plate FP may be respectively provided with stepped structures 30 in regions corresponding to the first dielectric layer a1 and the second dielectric layer a2 .
  • Embodiment 1 of the present application also provides a fabrication method of a transistor as shown in FIG. 3 , as shown in FIG. 11 , the fabrication method may include:
  • Step 11 as shown in (a) of FIG. 12 , a substrate 1 is provided, and an epitaxial layer 2 is grown on the surface of the substrate 1 .
  • the above step 11 may include: providing an N+ silicon substrate, and growing an N- epitaxial silicon layer with a specific thickness and resistivity on the N+ silicon substrate.
  • Step 12 referring to (b) and (c) in FIG. 12 , a trench T is formed on the surface of the epitaxial layer 2 , and a first dielectric layer a1 is formed in the inner wall of the trench T.
  • the above step 12 may include: referring to FIG. 12 (b), using processes such as photolithography, trench etching, growth of a sacrificial oxide layer and its removal, etc., to form a trench T with a certain shape and interface quality. Then, as shown in (c) of FIG. 12 , a first dielectric layer a1 with a specific thickness is formed on the sidewall of the trench T and the surface of the epitaxial layer 2 .
  • the first dielectric layer a1 can be SiO 2 with a dielectric constant of about 3.9.
  • the SiO 2 can be grown entirely by thermal oxidation, or a thin layer can be grown by thermal oxidation first, and then the rest is deposited by CVD (chemical vapor deposition, chemical vapor deposition), and then annealed.
  • Step 13 referring to (d) in FIG. 12 , form a field plate FP in the groove T where the first dielectric layer a1 is formed, and etch back the first dielectric layer a1 to a depth below the top of the field plate FP.
  • the gate G needs to be formed on the top of the field plate FP later, so the depth of the top of the field plate FP formed in step 13 should meet the manufacturing requirements of the subsequent gate G.
  • step 13 may include: depositing a layer of polysilicon by LP-CVD (low pressure chemical vapor deposition, low pressure chemical vapor deposition), and forming a good filling of the trench T; then, etching back the polysilicon to a specific depth d0 without a mask to form a field plate FP, that is, forming a field plate polysilicon (field plate polysilicon) licon); and then self-aligned to engrave the first dielectric layer a1 back to another specific depth d1, and d1>d0.
  • LP-CVD low pressure chemical vapor deposition, low pressure chemical vapor deposition
  • the field plate polysilicon can be subjected to CMP (chemical mechanical polishing, chemical mechanical polishing) before etching back, so as to improve the flatness of its upper surface and ensure the isolation effect of the subsequently formed interlayer dielectric layer 20 on the field plate polysilicon-gate polysilicon (refer to FIG. 13 ).
  • CMP chemical mechanical polishing, chemical mechanical polishing
  • Step 14 with reference to (e) and (f) shown in Figure 12, form a second dielectric layer a2 on the side of the field plate FP and on the surface of the first dielectric layer a1; the dielectric coefficient of the second dielectric layer a2 is greater than that of the first dielectric layer a1.
  • the above step 14 may include: referring to FIG. 12 (e), depositing the second dielectric layer a2 by CVD, and filling the trench T well.
  • the second dielectric layer a2 can be made of Si 3 N 4 with a dielectric constant of about 7.5.
  • CMP may be performed on the surface of the second dielectric layer a2 as required, so as to improve the flatness of the upper surface thereof.
  • the second dielectric layer a2 can be etched back to another specific depth d2 in a self-aligned manner, and d2 ⁇ d0. In this way, the second dielectric layer a2 covers the field plate FP with a certain thickness as the interlayer dielectric layer 20 .
  • Step 15 referring to (a) and (b) in FIG. 13 , form a gate dielectric layer 12 on the sidewall of the trench T, and form a gate G on the surface of the second dielectric layer a2.
  • a gate dielectric layer 12 (also referred to as a gate dielectric layer or a gate oxide layer) is grown by thermal oxidation on the exposed sidewall of the trench T and the upper surface of the epitaxial layer 2, and the gate dielectric layer 12 may be SiO 2 .
  • a sacrificial oxide layer may be grown and removed before growing the gate dielectric layer 12 .
  • the gate dielectric layer 12 can also be formed by CVD. Then, as shown in (b) in FIG.
  • polysilicon is deposited on the surface of the second dielectric layer a2 by LP-CVD to form a good filling of the trench; next, the polysilicon is etched back to a specific depth (generally slightly lower than the upper surface of the epitaxial layer 2) without a mask to form the gate G; that is, the gate polysilicon (gate polysilicon) is formed.
  • the gate is formed through the photolithography mask, the polysilicon pattern to be preserved may be defined for the gate connection structure or other functions.
  • a P-type lightly doped layer (P), an N-type heavily doped layer (N+), etc. can be formed on the surface of the epitaxial layer 2 by ion implantation, and an insulating dielectric layer 3 and a second metal layer M2 are formed on the surface of the epitaxial layer, and the first metal layer M1 is formed on the lower surface of the substrate 1.
  • P lightly doped layer
  • N+ N-type heavily doped layer
  • the first metal layer M1 is formed on the lower surface of the substrate 1.
  • steps 11 to 15 are a fabrication method for the transistor shown in FIG. 3 , but the present application is not limited thereto, and other fabrication methods can also be used for fabrication.
  • the corresponding fabrication can be carried out in combination with related technologies, and the fabrication can also be carried out by referring to steps 11 to 15 for corresponding adjustments.
  • the manufacturing method is basically the same as that of the aforementioned steps 11 to 15.
  • the difference is that the second dielectric layer a2 has a different depth of etching back in step 14.
  • the depth of etching back can be controlled so that only the thinner second dielectric layer a2 remains on the surface of the field plate FP as a part of the interlayer dielectric layer 20 (corresponding to FIG. 7 ), or the second dielectric layer a2 on the surface of the field plate FP is completely removed by etching back. (corresponding to FIG. 8 ), and then the intermediate dielectric layer b is formed again by means of CVD and etching back using a dielectric material with a relatively low permittivity.
  • the second embodiment provides a semiconductor device using a split-gate (dual-gate) trench field effect transistor.
  • the main difference between the split-gate (double-gate) trench field effect transistor and the split-gate (single-gate) trench field effect transistor in the first embodiment is that the transistor is provided with two gates in the trench T: a first gate G1 and a second gate G2.
  • the first grid G1 and the second grid G2 are located on both sides of the top of the field plate FP.
  • an interlayer dielectric layer 20 is arranged between the first grid G1, the second grid G2 and the field plate FP; that is, the interlayer dielectric layer 20 is arranged above the isolation dielectric layer 10.
  • the first grid G1 and the second grid G2 are distributed on both sides of the field plate FP in the lateral direction, and the first grid G1 and the second grid G2 are basically consistent with the extension direction of the field plate FP in the longitudinal direction, and are basically consistent with the length of the field plate FP.
  • the first gate G1 and the second gate G2 can be connected on the surface of the epitaxial layer 2, so that the two can be in an equipotential body to ensure the normal operation of the transistor.
  • the setting of the isolation dielectric layer 10 located on the side of the field plate FP is basically the same as that in the first embodiment above.
  • the dielectric coefficient of the isolation dielectric layer 10 By setting the dielectric coefficient of the isolation dielectric layer 10 to increase from bottom to top, the purpose of changing the capacitance per unit area can be achieved, thereby changing the modulation effect of the field plate on the electric field, and introducing a new peak electric field at the position where the dielectric constant of the isolation dielectric layer 10 changes, thereby realizing multi-peak or even rectangular distribution of the breakdown electric field, and improving the breakdown voltage of the device.
  • Embodiment 2 of the present application also provides a method for manufacturing a transistor as shown in FIG. 14. As shown in FIG. 15, the manufacturing method may include:
  • Step 21 as shown in (a) of FIG. 16 , a substrate 1 is provided, and an epitaxial layer 2 is grown on the surface of the substrate 1 .
  • step 21 is basically the same as the step 11 in the first embodiment, and reference may be made to the related description of the above-mentioned step 11, which will not be repeated here.
  • Step 22 referring to (b) and (c) in FIG. 16 , form a trench T on the surface of the epitaxial layer 2 , and form a first dielectric layer a1 in the inner wall of the trench T.
  • step 22 is basically the same as the step 12 in the first embodiment, and reference may be made to the related description of the above-mentioned step 12, which will not be repeated here.
  • Step 23 referring to FIG. 16 (d), form a field plate FP in the groove T where the first dielectric layer a1 is formed, and etch back the first dielectric layer a1 to a depth below the top of the field plate FP.
  • step 23 may include: depositing a layer of polysilicon by LP-CVD (low pressure chemical vapor deposition, low pressure chemical vapor deposition), and forming a good filling of the trench T; then, etching back the polysilicon to a specific depth d0 (generally slightly lower than the upper surface of the epitaxial layer 2) without a mask to form a field plate FP; Accurately engrave the first dielectric layer a1 back to another specific depth d1, and d1>d0.
  • CMP chemical mechanical polishing, chemical mechanical polishing
  • Step 24 referring to (e) and (f) shown in Figure 16, form a second dielectric layer a2 on the side of the field plate FP and on the surface of the first dielectric layer a1, and engrave the second dielectric layer a2 back to the depth below the top of the field plate FP; the dielectric coefficient of the second dielectric layer a2 is greater than the dielectric coefficient of the first dielectric layer a1.
  • gates (G1, G2) need to be formed on the top of the second dielectric layer a2, so the depth of the top of the second dielectric layer a2 formed in step 24 should meet the manufacturing requirements of the subsequent gates (G1, G2).
  • the above step 24 may include: referring to FIG. 16 (e), depositing the second dielectric layer a2 by CVD, and filling the trench T well.
  • the second dielectric layer a2 can be made of Si 3 N 4 with a dielectric constant of about 7.5.
  • CMP may be performed on the surface of the second dielectric layer a2 to improve the flatness of the upper surface thereof.
  • the second dielectric layer a2 can be etched back to another specific depth d2 in a self-aligned manner, and d2 ⁇ d1.
  • Step 25 referring to (a) and (b) in FIG. 17 , form a gate dielectric layer 12 on the sidewalls of the field plate FP and the trench T, and form a first gate G1 and a second gate G2 on both sides of the field plate FP.
  • the above step 25 may include: as shown in (a) of FIG. 17 , growing a gate dielectric layer 12 by thermal oxidation on the exposed sidewall of the trench T and the upper surface of the epitaxial layer 2, and the gate dielectric layer 12 may be made of SiO 2 .
  • a sacrificial oxide layer may be grown and removed before growing the gate dielectric layer 12 .
  • the gate dielectric layer 12 can also be formed by CVD. Then, as shown in (b) in FIG.
  • polysilicon is deposited on the surface of the second dielectric layer a2 by LP-CVD to form a good filling of the trench; next, the polysilicon is etched back to a specific depth (generally slightly lower than the upper surface of the epitaxial layer 2) without a mask, thereby forming the first grid G1 and the second grid G2 on both sides of the field plate FP.
  • a specific depth generally slightly lower than the upper surface of the epitaxial layer 2
  • polysilicon patterns to be preserved may be defined for gate connection structures or other functions.
  • the interlayer dielectric layer 20 is formed while the gate dielectric layer 12 is formed, that is, the interlayer dielectric layer 20 and the gate dielectric layer 12 are manufactured by the same manufacturing process, and the materials of the gate dielectric layer 12 and the interlayer dielectric layer 20 are the same.
  • Embodiment 3 provides a semiconductor device using a non-split gate trench field effect transistor (non-split gate trench MOS).
  • the main difference between this non-split-gate trench field effect transistor and the split-gate (single-gate) trench field effect transistor in the first embodiment is that the gate G located in the trench T is connected to the top of the field plate FP, and the two can be connected as an integral structure. In this case, there is no interlayer dielectric layer between the gate G and the field plate FP.
  • the setting of the isolation dielectric layer 10 located on the side of the field plate FP is basically the same as that in the first embodiment above.
  • the dielectric coefficient of the isolation dielectric layer 10 By setting the dielectric coefficient of the isolation dielectric layer 10 to increase from bottom to top, the purpose of changing the capacitance per unit area can be achieved, thereby changing the modulation effect of the field plate on the electric field, and introducing a new peak electric field at the position where the dielectric constant of the isolation dielectric layer 10 changes, thereby realizing multi-peak or even rectangular distribution of the breakdown electric field, and improving the breakdown voltage of the device.
  • Embodiment 3 of the present application also provides a method for manufacturing a transistor as shown in FIG. 18. As shown in FIG. 19, the manufacturing method may include:
  • Step 31 as shown in (a) of FIG. 20 , a substrate 1 is provided, and an epitaxial layer 2 is grown on the surface of the substrate 1 .
  • the foregoing step 31 is basically the same as the foregoing step 11 in the first embodiment, and reference may be made to the relevant description of the foregoing step 11, which will not be repeated here.
  • Step 32 referring to (b) and (c) in FIG. 20 , form a trench T on the surface of the epitaxial layer 2 , and form a first dielectric layer a1 in the inner wall of the trench T.
  • the foregoing step 32 is basically the same as the foregoing step 12 in the first embodiment, and reference may be made to the relevant description of the foregoing step 12, which will not be repeated here.
  • Step 33 as shown in (d) of FIG. 20 , form a false field plate FP' in the groove formed on the inner wall of the first dielectric layer a1, and etch back the first dielectric layer a1 to a depth below the top of the false field plate FP'.
  • step 33 may include: depositing a layer of polysilicon by LP-CVD (low pressure chemical vapor deposition, low pressure chemical vapor deposition), and forming a good filling of the trench T; then, etching back the polysilicon to a specific depth d0 (generally lower than the upper surface of the epitaxial layer 2) without a mask to form a false field plate FP' (also may be called a sacrificial field plate); then the first dielectric layer a1 is etched back to another specific depth d1 in a self-aligned manner, and d1>d0.
  • LP-CVD low pressure chemical vapor deposition, low pressure chemical vapor deposition
  • Step 34 with reference to shown in (e) and (f) among Fig. 20, form the second dielectric layer a2 on the side that is positioned at false field plate FP ', the surface of first dielectric layer a1, and second dielectric layer a2 is engraved back to the depth below the top of false field plate FP ';
  • the dielectric coefficient of second dielectric layer a2 is greater than the dielectric coefficient of first dielectric layer a1.
  • step 34 may include: referring to (e) in FIG. 20 , depositing the second dielectric layer a2 by CVD, and filling the trench T well.
  • the second dielectric layer a2 can be made of Si 3 N 4 with a dielectric constant of about 7.5.
  • CMP may be performed on the surface of the second dielectric layer a2 as required, so as to improve the flatness of the upper surface thereof.
  • the second dielectric layer a2 can be etched back to another specific depth d2 in a self-aligned manner, and d2 ⁇ d1.
  • Step 35 referring to (a) and (b) in FIG. 21 , form a gate dielectric layer 12 on the sidewall of the trench T, and form an integrated structure of the gate G and the field plate FP after removing the false field plate FP'.
  • the above step 35 may include: referring to FIG. 21 (a), growing a gate dielectric layer 12 by thermal oxidation on the sidewall of the exposed trench T and the upper surface of the epitaxial layer 2, and removing the false field plate FP'.
  • the gate dielectric layer 12 can be made of SiO 2 .
  • a sacrificial oxide layer may be grown and removed before growing the gate dielectric layer 12 .
  • the gate dielectric layer 12 can also be formed by CVD. Then, as shown in (b) in FIG.
  • polysilicon is re-deposited by LP-CVD to form a good filling of the trench; next, the polysilicon is etched back to a specific depth (generally slightly lower than the upper surface of the epitaxial layer 2) without a mask, thereby forming an integral structure of the field plate FP and the gate G in the trench T.
  • a polysilicon pattern to be retained may be defined for gate connection structures or other functions.
  • Embodiment 4 provides a semiconductor device using a double-trench field effect transistor.
  • FIG. 22 is a schematic structural view of a double-trench field effect transistor in a semiconductor device (a unit cell is in a dotted line box in the figure). As shown in FIG. 22 , the main difference between the double-trench field effect transistor and the split-gate (single-gate) trench field effect transistor in the first embodiment is that the gate G and the field plate FP are located in different trenches.
  • the transistor is provided with a first trench T1 and a second trench T2 juxtaposed on the surface of the epitaxial layer 2 .
  • the depth of the second trench T2 is smaller than the depth of the first trench T1; the field plate FP is located in the first trench T1, and the gate G is located in the second trench T2.
  • the depth of the second trench T2 should pass through the well region (P-well) and enter into the surface layer of the drift region (N-drift), so as to meet the setting requirements of the gate G.
  • the depth of the first trench T1 should extend to the inside of the drift region (N-drift), so as to meet the setting requirement of the field plate FP.
  • the setting of the isolation dielectric layer 10 located on the side of the field plate FP is basically the same as that in the first embodiment.
  • the dielectric coefficient of the isolation dielectric layer 10 By setting the dielectric coefficient of the isolation dielectric layer 10 to increase from bottom to top, the purpose of changing the capacitance per unit area can be achieved, thereby changing the modulation effect of the field plate on the electric field, and introducing a new peak electric field at the position where the dielectric constant of the isolation dielectric layer 10 changes, thereby realizing multi-peak or even rectangular distribution of the breakdown electric field, and improving the breakdown voltage of the device.
  • the manufacturing method of the transistor in this embodiment it can be manufactured by referring to the related manufacturing method and related technology mentioned above, and will not be repeated here.
  • Embodiment 5 provides a semiconductor device using an insulated gate bipolar transistor (insulated gate bipolar transistor, IGBT).
  • IGBT insulated gate bipolar transistor
  • FIG. 23 is a schematic structural diagram of two IGBTs (that is, two cells) connected in parallel in a semiconductor device.
  • the design of the gate G and the field plate FP in this IGBT is similar to that of Embodiment 1.
  • the isolation dielectric layer 10 By setting the isolation dielectric layer 10 on the side of the field plate FP and using a dielectric material whose dielectric coefficient increases from bottom to top, the purpose of changing the capacitance per unit area can be achieved, thereby changing the modulation effect of the field plate on the electric field, and introducing a new peak electric field at the position where the dielectric constant of the isolation dielectric layer 10 changes, thereby realizing multi-peak or even rectangular distribution of the electric field, and improving the breakdown voltage of the device.
  • the main difference between the IGBT and the split-gate (single-gate) trench field effect transistor in the first embodiment is that generally, the IGBT can directly use a lightly doped N-type semiconductor substrate as a field stop layer (field stop), and a P-type doped layer is provided on the lower surface of the substrate as an emission layer (injection); other film layer structures (such as M1, M2, P-well, N-drift, etc.) are basically the same as those in the first embodiment, and will not be repeated here.
  • the first metal layer M1 and the second metal layer M2 serve as a collector and an emitter, respectively.
  • the manufacturing method of the IGBT in this embodiment can be made by referring to the relevant manufacturing method and related technology mentioned above, and will not be repeated here.
  • Embodiment 6 provides a semiconductor device using a trench MOS barrier schottky diode (trench MOS barrier schottky diode, TMBS).
  • trench MOS barrier schottky diode trench MOS barrier schottky diode, TMBS.
  • FIG. 24 is a schematic structural diagram of two trench MOS barrier Schottky diodes (that is, two cells) connected in parallel in a semiconductor device.
  • the design of the field plate FP of the trench MOS barrier Schottky diode (hereinafter referred to simply as the diode) is similar to that of the first embodiment.
  • the isolation dielectric layer 10 By setting the isolation dielectric layer 10 on the side of the field plate FP and using a dielectric material whose dielectric coefficient increases from bottom to top, the purpose of changing the capacitance per unit area can be achieved, thereby changing the modulation effect of the field plate on the electric field.
  • a new peak electric field is introduced at the position where the dielectric constant of the isolation dielectric layer 10 changes, thereby realizing multi-peak or even rectangular distribution of the electric field, and improving the breakdown voltage of the device.
  • the epitaxial layer 2 can only include the drift region (N-drift) of the N-type lightly doped layer, and the second metal layer M2 is directly arranged on the upper surface of the epitaxial layer 2 as the anode of the diode, and is connected (contacted) with the field plate FP, and the first metal layer M1 is used as the cathode of the diode (cathode).
  • N-drift drift region
  • the second metal layer M2 is directly arranged on the upper surface of the epitaxial layer 2 as the anode of the diode, and is connected (contacted) with the field plate FP, and the first metal layer M1 is used as the cathode of the diode (cathode).

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Abstract

一种半导体器件及其制作方法、电子设备，该半导体器件通过在场板（FP）的侧面采用至少两种不同介电系数的介质层（10），从而能够提高器件的击穿电压。该半导体器件中的分栅沟槽型场效应晶体管包括：衬底（1）、外延层（2）、场板（FP）、隔离介质层（10）。其中，外延层（2）设置于衬底（1）上，外延层（2）在远离衬底（1）一侧设置有沟槽（T）。场板（FP）位于沟槽（T）内，隔离介质层（10）至少覆盖场板（FP）的侧面；并且该隔离介质层（10）包括覆盖在场板（FP）侧面的第一介质层（a1）和第二介质层（a2），第一介质层（a1）相对于第二介质层（a2）靠近沟槽（T）的槽底，且第二介质层（a2）的介电系数大于第一介质层（a1）的介电系数。

Description

半导体器件及其制作方法、电子设备
本申请要求在2022年1月24日提交中国专利局、申请号为202210080586.1、发明名称为“半导体器件及其制作方法、电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体技术领域，尤其涉及一种半导体器件及其制作方法、电子设备。
背景技术
分栅沟槽型金属氧化物半导体场效应晶体管(split gate trench metal oxide semiconductor field effect transistor，SGT MOS)广泛的应用于功率半导体领域。对于SGT MOS而言，击穿电压(breakdown voltage，VBR)往往和一系列参数为折中互易(trade off)的关系。通过提高器件的击穿电压能力，就可以在同等电压下获得更低的比导通电阻(specific on resistance，RSP)、更低的栅极-漏极电容C gd等，从而能够实现更高的开关速度和更低的功耗，提高器件的可靠性。
图1中(a)为相关技术中提供的一种SGT MOS的结构示意图，图1中(b)为(a)中SGT MOS沿虚线位置的电场分布曲线。参考图1中(a)和(b)所示，在SGT MOS中，通过在沟槽栅极G的下方引入场板FP(field plate)，来屏蔽大部分从漏极D到栅极G的电场，减小了栅极-漏极电容C gd，提高了器件的开关速度；同时由于场板FP的引入，将器件的击穿电场由平行平面结的单峰电场转变为双峰电场。双峰电场中，一个电场位于P阱(P-well)区与N-漂移区之间的PN结处，另一个电场位于沟槽底部。这样一来，通过场板的设置在垂直耗尽(PN结)的基础上引入了水平耗尽，将器件电场由三角形分布改变为双峰电场分布。在采用同样掺杂浓度的外延规格情况下，器件可以获得更高的击穿电压。但是通过场板调制形成双峰电场，距离理想的高击穿电压(对应图2的矩形电场)还具有较大差距，因此通过进一步调制电场来提高器件的击穿电压，一直作为行业的追求目标。
发明内容
本申请提供一种半导体器件及其制作方法、电子设备，能够提高器件的击穿电压。
本申请提供一种半导体器件，该半导体器件中设置有分栅沟槽型场效应晶体管(可简称为晶体管)。该晶体管包括衬底、设置于衬底上的外延层、场板、隔离介质层。其中，外延层在远离衬底一侧设置有沟槽，沟槽内设置有场板。隔离介质层至少覆盖场板的侧面，并且隔离介质层中包括覆盖在场板侧面的第一介质层和第二介质层，第一介质层相对于第二介质层靠近沟槽的槽底，且第二介质层的介电系数大于第一介质层的介电系数。
示意的，在一些可能实现的方式中，上述分栅沟槽型场效应晶体管还可以包括：第一金属层、第二金属层、绝缘介质层；其中，第一金属层设置在衬底远离外延层的一侧，绝缘介质层设置在外延层与第二金属层之间；衬底采用N型轻掺杂半导体材料；外延层从下 到上分为：N型轻掺杂层(N-)、P型掺杂层(P)、N型重掺杂层(N+)；场板位于N型轻掺杂层所在的区域(即漂移区)。其中，第一金属层作为晶体管的漏极，第二金属层作为晶体管的源极。在外延层中，N型轻掺杂层(N-)、P型掺杂层(P)形成晶体管中的PN结，N型重掺杂层(N+)作为晶体管的漂移区；隔离介质层填充在场板与漂移区之间。当然，作为另一个可能实现的方式中，衬底采用P型轻掺杂半导体材料；外延层从下到上分为：P型轻掺杂层、N型掺杂层、P型重掺杂层。
相比于现有技术中，在位于场板的侧面采用一种介电材料(即具有一种介电常数)而言，本申请实施例中通过设置场板侧面的隔离介质层采用两种或两种以上的介电材料，使得该隔离介质层的介电系数从下到上增大。在此情况下，基于隔离介质层从下到上增大变化的介电系数，从而可以起到改变场板与外延层(漂移区)之间单位面积电容的目的，进而改变场板对电场的调制作用，使得外延层(漂移区)的电荷电场线在隔离介质层的介电常数变化的位置发生聚集，引入新的尖峰电场，同时削弱电场底部位置的电场尖峰，实现击穿电场的多尖峰分布，提升了器件的击穿电压，从而获得更低的比导通电阻(RSP)、更低的栅极-漏极电容C gd等，改善了器件的优值，实现了更高的开关速度和更低的功耗，提高了器件的可靠。
此处还应当理解的是，本申请中通过设置隔离介质层中靠近场板顶部的介电系数大于靠近场板底部的介电系数，在此情况下，一方面，能够使得在靠近晶体管的PN结处，单位面积电容较大，外延层(漂移区)的电荷电场线向场板顶部聚集，削弱PN结位置的电场，从而对PN结起到更好的保护作用；另一方面，能够使得在靠近场板底部的位置处单位面积电容较小，从而削弱了场板底部的电场，降低了场板在沟槽的底部击穿外延层(漂移区)的几率。
在一些可能实现的方式中，上述分栅沟槽型场效应晶体管为双栅结构，该晶体管在沟槽内设置有第一栅极和第二栅极。第一栅极和第二栅极位于场板顶端的两侧，且第一栅极、第二栅极与场板之间均设置有层间介质层；层间介质层位于隔离介质层远离沟槽的槽底一侧。也即该分栅沟槽型场效应晶体管为双栅沟槽型场效应晶体管。
在一些可能实现的方式中，上述分栅沟槽型场效应晶体管为单栅结构，该晶体管在沟槽内设置有栅极；该栅极位于场板远离衬底一侧，且栅极与场板之间设置有层间介质层。也即该分栅沟槽型场效应晶体管为单栅沟槽型场效应晶体管。
在一些可能实现的方式中，隔离介质层还包括覆盖在场板侧面的第三介质层。第三介质层相对于第二介质层远离沟槽的槽底；第三介质层的介电系数大于第二介质层的介电系数。通过设置隔离介质层含有三个不同介电系数的介质层，能够获得四尖峰电场分布，进一步的提高器件的击穿电压和可靠性。
在一些可能实现的方式中，第一介质层或第二介质层中的至少一个具有渐变介电系数；渐变介电系数沿沟槽的槽底到槽口的方向逐渐增大。在此情况下，能够获得的电场的尖峰数量越多，击穿电场分布越接近矩形分布。
在一些可能实现的方式中，第一介质层采用第一介电材料；第二介质层采用多元化合物介电材料，且多元化合物介电材料的原子或分子组分，沿沟槽的槽底到槽口的方向，逐渐变化。也即第一介质层具有固定的介电系数，第二介质层具有渐变介电系数。示意的，第二介质层可以采用SiO xN y、HfO xN y等。
在一些可能实现的方式中，在靠近场板顶端的侧面区域，隔离介质层与沟槽的侧壁之间设置有隔离缓冲层；在此情况下，通过该隔离缓冲层与沟槽的侧壁之间形成良好的界面，从而避免了第二介质层与沟槽的侧壁之间直接接触而导致泄漏电流等可靠性问题。
在一些可能实现的方式中，隔离缓冲层采用SiO 2。
在一些可能实现的方式中，隔离介质层延伸并覆盖至场板的顶表面。在此情况下，可以在形成第二介质层的同时，形成位于至少部分层间介质层，也即层间介质层中的全部或部分与第二介质层的材料相同。
在一些可能实现的方式中，层间介质层包括中间介质层；中间介质层的介电系数小于第二介质层的介电系数。这样一来，可以通过降低层间介质层的介电系数，来减小栅极与场板之间的寄生电容。
在一些可能实现的方式中，中间介质层覆盖场板的顶表面。在此情况下，整个层间介质层可以全部采用具有较小介电系数的介电材料，进一步的减小栅极与场板之间的寄生电容。
在一些可能实现的方式中，场板的侧面设置有至少一个阶梯结构；阶梯结构的两个阶梯面中，靠近沟槽的槽口一侧的阶梯面凸出于靠近沟槽的槽底一侧的阶梯面。这样一来，通过在场板的侧面设置阶梯结构，同样能够实现在垂直方向上抑制电场尖峰，提升器件的击穿电压，提高器件的可靠性。
本申请实施例还提供一种半导体器件，该半导体器件中设置有沟槽型电子元件。该沟槽型电子元件中包括：衬底、设置于所述衬底上的外延层、场板、隔离介质层。外延层在远离衬底一侧设置有第一沟槽。第一沟槽内设置有场板。隔离介质层至少覆盖场板的侧面。隔离介质层包括第一介质层和第二介质层，第一介质层相对于第二介质向靠近第一沟槽的槽底；第二介质层的介电系数大于第一介质层的介电系数。
在上述半导体器件采用的沟槽型电子元件中，通过设置场板侧面的隔离介质层采用两种或两种以上的介电材料，使得该隔离介质层的介电系数从下到上增大。在此情况下，基于隔离介质层从下到上增大变化的介电系数，从而可以起到改变单位面积电容的目的，改变场板对电场的调制作用，从而可以起到改变场板与外延层(漂移区)之间单位面积电容的目的，进而改变场板对电场的调制作用，使得外延层(漂移区)的电荷电场线在介质层突变的位置(也即介电常数变化的位置)发生聚集引入新的尖峰电场，同时削弱电场底部位置的电场尖峰，实现击穿电场的多尖峰分布，提升了器件的击穿电压，从而获得更低的比导通电阻(RSP)、更低的栅极-漏极电容C gd等，改善了器件的优值，实现了更高的开关速度和更低的功耗，提高了器件的可靠。
在一些可能实现的方式中，沟槽型电子元件可以为非分栅沟槽型场效应晶体管；该沟槽型场效应晶体管还包括位于第一沟槽内的栅极，且栅极与场板的顶部连接。
在一些可能实现的方式中，沟槽型电子元件为双沟槽型场效应晶体管；该双沟槽型场效应晶体管中，外延层在远离衬底一侧还设置有第二沟槽，第二沟槽与第一沟槽并列设置；栅极位于第二沟槽内的；第二沟槽的深度小于第一沟槽的深度。
在一些可能实现的方式中，沟槽型电子元件为沟槽MOS势垒肖特基二极管；该沟槽MOS势垒肖特基二极管还包括第一金属层和第二金属层；第一金属层位于衬底远离外延层的一侧，第二金属层位于外延层远离衬底的一侧；场板的顶部与第二金属层连接。
在一些可能实现的方式中，沟槽型电子元件为绝缘栅双极型晶体管；衬底采用N型半导体材料；该绝缘栅双极型晶体管还包括栅极、P型半导体层。栅极位于第一沟槽内，且栅极位于场板远离第一沟槽的槽底一侧，栅极与场板设置有层间介质层。P型半导体层位于衬底远离外延层的一侧。外延层在沿远离衬底的方向上依次为N型掺杂区、P型掺杂区、N型重掺杂区。
本申请实施例还提供一种电子设备，包括印刷线路板以及如前述任一种可能实现的方式中提供的半导体器件；半导体器件与印刷线路板电连接。
本申请实施例还提供一种半导体器件的制作方法，该制作方法包括：提供衬底，并在衬底表面生长外延层。在外延层的表面形成沟槽，并在沟槽的内壁中形成第一介质层。在形成有第一介质层的凹槽中形成场板，并将第一介质层回刻至场板顶部以下的深度。在位于场板的侧面、第一介质层的表面形成第二介质层，第二介质层的介电系数大于第一介质层的介电系数。
在一些可能实现的方式中，所述在位于场板的侧面、第一介质层的表面形成第二介质层，可以包括：在位于场板的侧面、第一介质层的表面，沉积多元化合物介电材料，并在沉积的过程中通过控制多元化合物介电材料中的原子或分子组分，以形成介电系数逐渐增大的第二介质层。
在一些可能实现的方式中，在场板的侧面形成包括第一介质层和第二介质层在内的隔离介质层之后，该制作方法还可以包括：在场板的顶部形成中间介质层，且中间介质层的介电系数小于第二介质层的介电系数。
附图说明
图1为本申请相关技术提供的一种SGT MOS及其击穿电场分布示意图；
图2为SGT MOS的理想电场分布示意图；
图3为本申请实施例提供的一种SGT MOS及其击穿电场分布示意图；
图4为本申请实施例提供的一种SGT MOS的结构示意图；
图5为本申请实施例提供的一种SGT MOS的结构示意图；
图6为本申请实施例提供的一种SGT MOS的结构示意图；
图7为本申请实施例提供的一种SGT MOS的结构示意图；
图8为本申请实施例提供的一种SGT MOS的结构示意图；
图9为本申请实施例提供的一种SGT MOS的结构示意图；
图10为本申请实施例提供的一种SGT MOS的结构示意图；
图11为本申请实施例提供的一种SGT MOS的制作方法流程图；
图12为本申请实施例提供的一种SGT MOS的制作过程示意图；
图13为本申请实施例提供的一种SGT MOS的制作过程示意图；
图14为本申请实施例提供的一种SGT MOS的结构示意图；
图15为本申请实施例提供的一种SGT MOS的制作方法流程图；
图16为本申请实施例提供的一种SGT MOS的制作过程示意图；
图17为本申请实施例提供的一种SGT MOS的制作过程示意图；
图18为本申请实施例提供的一种non-SGT MOS的结构示意图；
图19为本申请实施例提供的一种non-SGT MOS的制作方法流程图；
图20为本申请实施例提供的一种non-SGT MOS的制作过程示意图；
图21为本申请实施例提供的一种non-SGT MOS的制作过程示意图；
图22为本申请实施例提供的一种双沟槽的SGT MOS的结构示意图；
图23为本申请实施例提供的一种IGBT的结构示意图；
图24为本申请实施例提供的一种沟槽MOS势垒肖特基二极管的结构示意图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合本申请中的附图，对本申请中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请的说明书实施例和权利要求书及附图中的术语“第一”、“第二”等仅用于区分描述的目的，而不能理解为指示或暗示相对重要性，也不能理解为指示或暗示顺序。“和/或”，用于描述关联对象的关联关系，表示可以存在三种关系，例如，“A和/或B”可以表示：只存在A，只存在B以及同时存在A和B三种情况，其中A，B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。“至少一个(项)”是指一个或者多个，“多个”是指两个或两个以上。“以下至少一项(个)”或其类似表达，是指这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a，b或c中的至少一项(个)，可以表示：a，b，c，“a和b”，“a和c”，“b和c”，或“a和b和c”，其中a，b，c可以是单个，也可以是多个。“安装”、“连接”、“相连”等应做广义理解，例如可以是固定连接，也可以是可拆卸连接，或者一体地连接；可以是直接连接，也可以是通过中间媒介间接，也可以是两个元件内部的连通。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元。方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。“上”、“下”、“左”、“右”、“顶”、“底”等仅用于相对于附图中的部件的方位而言的，这些方向性术语是相对的概念，它们用于相对于的描述和澄清，其可以根据附图中的部件所放置的方位的变化而相应地发生变化。
本申请实施例提供一种电子设备，该电子设备中包括印刷线路板(printed circuit board，PCB)以及与该印刷线路板电连接的半导体器件，该半导体器件中设置有沟槽型电子元件。
本申请对于上述半导体器件的设置形式不做限定。示意的，该半导体器件可以是中央处理器(central processing unit，CPU)、图形处理器(graphics processing unit，GPU)、微控制单元(microcontroller unit；MCU)、电机驱动、不间断(uninterrupted power supply，UPS)电源等。
本申请对于上述电子设备的设置形式不做限制。示意的，该电子设备可以为手机、平板电脑、笔记本、车载电脑、智能手表、智能手环等电子产品。
在本申请实施例提供的电子设备中，半导体器件采用设置有体内场板(field plate)的沟槽型电子元件，也即沟槽型电子元件中设置有沟槽，并且在沟槽内设置有场板。本申请对于该沟槽型电子元件的具体形式不做限制。例如，该沟槽型电子元件可以是沟槽型场效 应晶体管(如分栅结构、非分栅结构、双沟槽结构等)、沟槽型MOS势垒肖特基二极管、绝缘栅双极型晶体管等电子元件。
在本申请实施例中，通过在沟槽型电子元件的沟槽内，设置场板侧面的介质层(也即隔离介质层)沿沟槽深度方向上具有两种或两种以上的介电系数(也即介电常数)，来对场板外的电场进行调制，平抑(削弱)原有的双峰电场(如图1)，获得三尖峰电场分布(如图3)或多尖峰电场分布，甚至可以达到近似理想的矩形电场分布(如图2)，从而提高了器件的击穿电压，进而获得更低的比导通电阻(RSP)、更低的栅极-漏极电容C gd等，改善了器件的优值，提高了器件的可靠。
以下通过具体实施例，结合沟槽型电子元件的具体设置形式，对本申请中位于场板侧面的隔离介质层的设置进行具体说明。
实施例一
本实施例一提供一种采用分栅(单栅)沟槽型场效应晶体管(下文可简称为晶体管)的半导体器件。
图3中(a)为半导体器件中并联的两个SGT MOS(也即两个元胞)的结构示意图；图3中(b)为(a)中的SGT MOS沿虚线位置的电场分布曲线。下文仅是以单个SGT MOS为例进行示意说明的。
参考图3中(a)所示，SGT MOS可以包括衬底1以及依次设置于衬底上的外延层2、绝缘介质层3。
示意的，衬底1可以采用N型重掺杂半导体材料，即N+衬底，该N+衬底作为晶体管的漏区。外延层2从下到上可以依次分为N型轻掺杂层(N-)、P型掺杂层(P)、N型重掺杂层(N+)，在该外延层2中，N型轻掺杂层(N-)作为晶体管的漂移区(N-drift)，P型掺杂层(P)作为晶体管的阱区(即P-well)，N型重掺杂层(N+)作为晶体管的源区；P阱(P-well)区与漂移区(N-drift)之间形成PN结。另外，衬底1和外延层2可以均采用硅(Si)材料，绝缘介质层3可以采用SiO 2；但并不限制于此。
需要说明的是，图3中仅是示意的以N型晶体管为例进行说明的，在另一些可能实现的方式中，该晶体管也可以为P型晶体管，在此情况下，衬底1可以采用P+衬底，外延层2从下到上可以依次分为P型轻掺杂层(P-)、N型掺杂层(N)、P型重掺杂层(P+)。以下实施例均是以N型晶体管为例进行说明的。
另外，在衬底1的下表面设置有第一金属层M1，作为晶体管的漏极D；绝缘介质层3的上表面设置有第二金属层M2，作为晶体管的源极S。第二金属层M2通过金属插塞m与阱区(P-well)连接。示意的，金属插塞m可以采用钨插塞(W plug)，但并不限制于此。为了降低金属插塞m与阱区(P-well)的接触电阻，以及与器件抗闩锁(latch-up)能力相关的P-well区的寄生电阻，可以在阱区(P-well)对应金属插塞m的位置进行重掺杂(P+)。
如图3所示，在外延层2的上表面(即远离衬底1一侧的表面)设置有沟槽T，在沟槽T内设置有场板FP和栅极G，栅极G位于场板FP的上方。示意的，栅极G和场板FP可以采用多晶硅材料(polycrystalline silicon)，但并不限制于此。通常栅极G的深度与阱区(P-well)的下表面基本一致，场板FP整体位于漂移区(N-drift)内。栅极G与沟槽T的槽壁之间、场板FP与沟槽T的槽壁之间、栅极G与场板FP之间均填充有介电材料， 以将栅极G、场板FP与外延层2之间进行隔离。
相比于现有技术中，在位于场板FP的侧面采用一种介电材料(即具有一种介电常数)而言，本申请实施例中通过设置场板FP侧面的隔离介质层10采用两种或两种以上的介电材料，使得该隔离介质层10的介电系数从下到上增大。在此情况下，基于隔离介质层10从下到上增大变化的介电系数，从而可以起到改变场板与漂移区(N-drift)之间单位面积电容，改变场板对电场的调制作用，使得漂移区(N-drift)的电荷电场线在隔离介质层10的介电常数变化的位置发生聚集，并引入新的尖峰电场，同时削弱电场底部位置的电场尖峰，实现击穿电场的三峰(如图3)或多峰分布，提升了器件的击穿电压，从而获得更低的比导通电阻(RSP)、更低的栅极-漏极电容C gd等，改善了器件的优值，实现了更高的开关速度和更低的功耗，提高了器件的可靠性。
另外，还应当理解的是，本申请中通过设置隔离介质层10中靠近场板FP顶部的介电系数大于靠近场板FP底部的介电系数，在此情况下，一方面，能够使得在靠近PN结(P-well与N-drift之间)处，单位面积电容较大，漂移区(N-drift)的电荷电场线向场板FP顶部聚集，能够削弱PN结位置的电场，对PN结起到更好的保护作用；另一方面，能够使得在靠近场板底部的位置处单位面积电容较小，从而削弱了场板FP底部的电场，降低了场板FP在沟槽T的底部击穿漂移区(N-drift)的几率。当然，对于上述隔离介质层10的介电系数从下到上的增大方式而言，可以是阶梯式增大，也可以是渐变式增大，具体可以根据隔离介质层10的具体设置方式而定，本申请对此不作限制。
例如，在一些可能实现的方式中，如图3所示，隔离介质层10可以包括覆盖场板FP侧面的第一介质层a1和第二介质层a2。第一介质层a1位于下方，第二介质层a2位于上方；也即第一介质层a1相对于第二介质层a2靠近沟槽T的槽底。第一介质层a1采用第一介电材料，第二介质层a2采用第二介电材料，并且第二介电材料的介电系数k2大于第一介电材料的介电系数k1，即k2＞k1。示意的，第一介电材料可以采用SiO 2(介电系数约为3.9)；第二介电材料可以采用Si 3N 4(介电系数约为7.9)、HfO 2(介电系数约为25)、Al 2O 3(介电系数约为9)等；但并不限制于此。
又例如，在一些可能实现的方式中，如图4所示，隔离介质层10可以包括从下到上依次覆盖在场板FP侧面的第一介质层a1、第二介质层a2、第三介质层a3。第一介质层a1采用第一介电材料，第二介质层a2采用第二介电材料，第三介质层a3采用第三介电材料，并且第二介电材料的介电系数k2大于第一介电材料的介电系数k1，第三介电材料的介电系数k3大于第二介电材料的介电系数k2，即k3＞k2＞k1。示意的，第一介电材料可以采用SiO 2(介电系数约为3.9)；第二介电材料可以采用Si 3N 4(介电系数约为7.9)，第三介电材料可以采用HfO 2(介电系数约为25)；但并不限制于此。
对于上述图3中隔离介质层10在场板FP的侧面含有两个不同介电系数的介质层的情况下，基于两种不同介电系数的介质层(a1、a2)的设置，改变场板对电场的调制作用，在介质层突变的位置(也即介电常数变化的位置)引入新的尖峰电场，从而获得三尖峰电场分布。对于图4中隔离介质层10在场板FP的侧面含有三个不同介电系数的介质层(a1、a2、a3)的情况下，能够获得四尖峰电场分布。
此处需要说明的是，本申请中所涉及的“第一介质层”、“第二介质层”、“第三介质层”，仅是指在隔离介质层10中满足前述设计要求下的相对概念，并不绝对指隔离介质层10中 固定的某个(某些)介质层；例如，当隔离介质层10包括5个介质层的情况下，可以认为从下到上设置的任意两个介质层(如次顶层和顶层)分别为第一介质层和第二介质层。
还需要说明的是，本申请中所涉及的“场板的侧面”是指场板FP在横向上的侧面，如图3中(a)中示意的场板FP的横向截面示意图，场板FP的侧面为场板FP左右两侧的表面；在纵向上场板FP呈面状结构。类似的，位于场板上方的栅极G在纵向上的场板FP延伸方向一致，且两者的长度也基本一致。
可以理解的是的，隔离介质层10中采用不同介电系数的介质层越多，能够获得的电场的尖峰数量越多，击穿电场分布越接近矩形分布。图3和图4仅是示意的以隔离介质层10含有两个和三个不同介电系数的介质层为例进行示意的说明，但本申请并不限制于此，隔离介质层10还可以设置有4或4个以上不同介电系数的介质层。下文均是以隔离介质层10中含有两个介质层为例进行示意说明的。
基于此，相比于前述隔离介质层10中的各介质层(a1、a2、a3)均采用单一的介质材料，也即每一介质层具有固定的介电系数，隔离介质层10的介电系数从下到上阶梯式增大。在另一些实施例中，隔离介质层10中的部分或全部的介质层的具有渐变介电系数，也即沿沟槽的深度方向上介电系数连续变化。该渐变介电系数的变化规律可以为线型、非线性、分段函数等多种形式中的一种或组合，采用该技术方案通过合理优化隔离介质层10的结构和工艺参数，可以获得近似理想的电场调制效果，即击穿电场为近似矩形分布。
例如，在一些可能实现的方式中，如图5所示，隔离介质层10可以包括第一介质层a1和第二介质层a2。第一介质层a1位于下方，第二介质层a2位于上方；也即第一介质层a1相对于第二介质层a2靠近沟槽T的槽底。其中，第一介质层a1采用第一介电材料，具有固定的介电系数k1；第二介质层a2具有渐变介电系数k2，该渐变介电系数k2从下到上(即沿沟槽的槽底到槽口的方向)逐渐增大，如k2＝k1+aX，也即第二介质层a2在与第一介质层a1相连接处为X坐标原点，即此处的介电系数与第一介质层a2的介电系数k1相同，并向上逐渐增加。
对于上述具有渐变介电系数k2的第二介质层a2而言，在一些可能实现的方式中，第二介质层a2可以采用多元化合物介电材料，该多元化合物介电材料的原子或分子组分从下到上逐渐变化，从而保证渐变介电系数k2从下到上逐渐增加。本申请中对于该多元化合物介电材料不做限制，如SiO xN y、HfO xN y等。实际中可以根据第一介质层a1采用的介电材料，来选取第二介质层a2采用的多元化合物介电材料及其原子或分子组分。
示意的，在一些实施例中，第一介电材料可以采用SiO 2(介电系数约为3.9)，第二介质层a2采用SiO xN y。如，第二介质层a2中，下端为SiO 2(介电系数约为3.9)，即x＝2，y＝0；上端为Si 3N 4(介电系数约为7.5)，即x＝0，y＝4/3；在形成第二介质层a2的中间区域通过改变各种气体的流量、反应温度、压强等，可以有效地控制x和y的数值，从而实现第二介质层a2的介电系数k2从3.9到7.5连续调制。
类似的，在另一些实施例中，第二介质层a2可以采用HfO xN y，介电系数k2可以实现从4到24的范围内调制变化。
另外，本申请对于上述具有渐变介电系数k2的第二介质层a2的制作方式不做限制，实际中可以根据需要选择合适的制作方法即可。例如，在一些可能实现的方式中，可以采用HDP-CVD(high density plasma chemical vapor deposition，高密度等离子化学气相淀积) 的工艺，采用一边沉积一边刻蚀，实现各向异性淀积；也即在垂直方向上沉积的同时，对水平沉积至侧壁的材料进行刻蚀；从而得到介电系数沿垂直方向(即从下到上)逐渐变化的介质层。
需要说明的是，图5中仅是示意的以第二介质层a2具有渐变介电系数为例进行说明的，但本申请并不限制于此，例如，在一些实施例中，也可以设置第一介质层a1具有渐变介电系数；又例如，在一些实施例中，还可以设置隔离介质层10为具有渐变介电系数的单一介质层。当然，如图4所示，对隔离介质层10采用三个介质层(a1、a2、a3)的情况下，可以设置三个介质层(a1、a2、a3)中的一个或者多个具有渐变介电系数。
另外，为了避免位于场板FP顶端侧面的隔离介质层10与沟槽T的侧壁之间形成的界面质量太差，而导致泄漏电流等可靠性问题，如图6所示，在一些可能实现的方式中，可以设置第二介质层a2与沟槽T的侧壁之间设置隔离缓冲层11，通过该隔离缓冲层11与沟槽T的侧壁之间形成良好的界面，从而避免了第二介质层a2与沟槽T的侧壁之间直接接触而导致泄漏电流等可靠性问题。
本申请中对于隔离缓冲层11的具体材料不作限制，只要保证隔离缓冲层11与沟槽T的侧壁之间形成良好的界面即可。示意的，在一些实施例中，外延层2采用硅(Si)材料，第二介质层a2采用Si 3N 4、HfO 2、Al 2O 3等具有高介电系数的介电材料，而这些介电材料与硅形成的界面质量较差，在此情况下，隔离缓冲层11可以设置采用SiO 2，SiO 2能够与Si形成良好的界面。当然，在另一些实施例中，隔离缓冲层11还可以采用氮氧化硅(SiO xN y)等，本申请对此不作限制。
需要说明的是，对于上述隔离缓冲层11制作而言，在一些实施例中，隔离缓冲层11可以单独制作；在一些实施例中，如图6所示，隔离缓冲层11可以与栅极氧化层12(即位于栅极G与沟槽T的侧壁之间)通过一次工艺进行制作。
另外，参考图3所示，对于位于栅极G与场板FP之间的层间介质层20而言，在一些可能实现的方式中，可以设置第二介质层a2从场板FP的侧面延伸并覆盖至其上表面(顶表面)，也即在形成第二介质层a2的同时，形成位于栅极G与场板FP之间的层间介质层20，在此情况下，层间介质层20与第二介质层a2采用相同的介质材料。
对于上述第二介质层a2从场板FP的侧面延伸并覆盖至其上表面的设置方式而言，由于第二介质层a2的介电系数较高，对应层间介质层20具有较高的介电系数，从而会导致栅极G与场板FP产生较大寄生电容，进而会导致晶体管的开关速度降低。因此，可以通过降低层间介质层20的介电系数，来减小栅极G与场板FP之间的寄生电容。
例如，在一些可能实现的方式中，如图7所示，可以设置第二介质层a2从场板FP的侧面延伸并略微覆盖场板FP顶部，并在栅极G与场板FP增加中间介质层b，该中间介质层b的介电系数小于第二介质层a2的介电系数；在此情况下，层间介质层20包括上下两层，下层与第二介质层a2材料相同，且厚度较薄；上层(b)采用介电系数较小的材料，且厚度较大。示意的，上层可以为厚度约为15nm左右的Si 3N 4层，下层为采用10nm左右的SiO 2层。
又例如，在另一些可能实现的方式中，如图8所示，可以将层间介质层20全部采用介电系数较小的中间介质层b，也即中间介质层b直接覆盖在场板FP的上表面；当然，在此情况下，根据实际的制作工艺，层间介质层20可以适当的向下延伸至场板FP的侧面。
此外，为了进一步对场板FP外的击穿电场进行调制，使得器件的设计更具有灵活性，在一些可能实现的方式中，参考图9和图10所示，可以在场板FP的侧面设置至少一个阶梯结构30。通常场板FP的左右两个侧面为对称结构。阶梯结构30包括两个阶梯面：上阶梯面(也即靠近沟槽的槽口一侧的阶梯面)和下阶梯面(也即靠近沟槽的槽底一侧的阶梯面)，上阶梯面凸出于下阶梯面；也即场板FP的宽度呈上宽下窄的结构。这样一来，通过在场板FP的侧面设置阶梯结构30，通过在阶梯结构30位置处改变介质层的厚度，来改变场板与漂移区(N-drift)之间单位面积电容，进而改变场板对电场的调制作用，从而在阶梯结构30位置引入新的尖峰电场，提升器件的击穿电压，提高器件的可靠性。
本申请中对于阶梯结构30在场板FP侧面的具体设置位置不做限制，实际中可以根据需要进行设置。例如，如图9所示，在一些可能实现的方式中，阶梯结构30可以设置在场板FP的侧面对应第一介质层a1的区域。又例如，如图10所示，在一些可能实现的方式中，阶梯结构30可以设置在场板FP的侧面对应第二介质层a2的区域。再例如，在一些可能实现的方式中，场板FP的侧面可以在对应第一介质层a1和第二介质层a2的区域内分别设置阶梯结构30。
本申请实施例一还提供一种如图3中示出的晶体管的制作方法，如图11所示，该制作方法可以包括：
步骤11、参考图12中(a)所示，提供衬底1，并在衬底1表面生长外延层2。
示意的，在一些可能实现的方式中，上述步骤11可以包括：提供在N+硅衬底，并在N+硅衬底上生长具有特定厚度和电阻率的N-外延硅层。
步骤12、参考图12中(b)和(c)所示，在外延层2的表面形成沟槽T，并在沟槽T的内壁中形成第一介质层a1。
示意的，在一些可能实现的方式中，上述步骤12可以包括：参考图12中(b)所示，采用光刻、沟槽刻蚀、牺牲氧化层生长及其去除等工艺，形成具有一定形貌和界面质量的沟槽T。然后，参考图12中(c)所示，在沟槽T侧壁和外延层2的表面形成具有特定厚度的第一介质层a1，该第一介质层a1可以采用介电常数约为3.9的SiO 2。该SiO 2可以全部采用热氧化生长，也可先采用热氧化生长一薄层，再通过CVD(chemical vapor deposition，化学气相淀积)淀积剩余部分，然后进行退火处理。
步骤13、参考图12中(d)所示，在形成有第一介质层a1的凹槽T中形成场板FP，并将第一介质层a1回刻至场板FP顶部以下的深度。
可以理解的是，后续在场板FP顶部需要形成栅极G，因此步骤13形成的场板FP顶部的深度应满足后续栅极G的制作要求。
示意的，在一些可能实现的方式中，参考图12中(d)所示，步骤13可以包括：通过LP-CVD(low pressure chemical vapor deposition，低压化学气相淀积)淀积一层多晶硅，并对沟槽T形成良好的填充；然后，无需掩模地将该多晶硅回刻(etch-back)到一特定深度d0形成场板FP，也即形成场板多晶硅(field plate polysilicon)；然后自对准地将第一介质层a1回刻到另一特定深度d1，且d1>d0。可选的，场板多晶硅在回刻之前可进行CMP(chemical mechanical polishing，化学机械抛光)，以提升其上表面的平整度，保证后续形成的层间介质层20对场板多晶硅-栅极多晶硅的隔离效果(可参考图13)。
步骤14、参考图12中(e)和(f)所示，在位于场板FP的侧面、第一介质层a1的 表面形成第二介质层a2；第二介质层a2的介电系数大于第一介质层a1的介电系数。
示意的，在一些可能实现的方式中，上述步骤14可以包括：参考图12中(e)所示，通过CVD淀积第二介质层a2，并对沟槽T形成良好的填充。该第二介质层a2可以采用介电常数约为7.5的Si 3N 4。在沉积第二介质层a2之后根据需要可以对第二介质层a2的表面进行CMP，以提升其上表面的平整度。然后，参考图12中(f)所示，可以自对准地将第二介质层a2回刻到另一特定深度d2，且d2<d0。这样，第二介质层a2覆盖场板FP一定厚度作为层间介质层20。
步骤15、参考图13中(a)和(b)所示，在沟槽T的侧壁形成栅介质层12，并在第二介质层a2的表面形成栅极G。
示意的，在一些可能实现的方式中，参考图13中(a)所示，在暴露的沟槽T的侧壁和外延层2的上表面通过热氧化生长一层栅介质层12(也可以称为栅极介质层、栅极氧化层)，该栅介质层12可以采用SiO 2。可选地，在生长栅介质层12之前可以进行一次牺牲氧化层的生长并将其去除。当然，栅介质层12也可通过CVD形成。然后，参考图13中(b)所示，通过LP-CVD在第二介质层a2的表面淀积多晶硅，对沟槽形成良好的填充；接下来，无需掩模地将该多晶硅回刻到一特定深度(一般略低于外延层2的上表面)，形成栅极G；也即形成栅极多晶硅(gate polysilicon)。可选地，通过光刻掩模形成栅极的同时，可以定义需要保留的多晶硅图形，以用于栅极连接结构或其它功能。
此处可以理解的是，前述步骤11～步骤15的制作过程中所涉及关键步骤均可以采用自对准工艺，使得整个制作工艺控制较为容易，也即器件具有较强的可制造性。
当然，在完成栅极G的制作之后，参考图3所示，在外延层2的表面可以通过离子注入的方式形成P型轻掺杂层(P)、N型重掺杂层(N+)等，并在外延层的表面制作绝缘介质层3、第二金属层M2，在衬底1的下表面制作第一金属层M1等，具体可以结合相关技术进行制作即可，此处不再赘述。
需要说明的是，前述步骤11～步骤15是针对图3中示出的晶体管的一种制作方式，但本申请并不限制于此，也可以采用其他的制作方来进行制作。对于其他结构的晶体管的制作方式，可以结合相关技术进行对应的制作即可，也可以参考步骤11～步骤15进行对应的调整进行制作。
例如，对于图7和图8中栅极G和场板FP之间的层间介质层20采用较小介电系数的中间介质层b的情况下，其制作方式与前述步骤11～步骤15基本一致，区别在于步骤14中第二介质层a2回刻深度不同，可以控制回刻深度在场板FP的表面仅保留较薄的第二介质层a2作为层间介质层20的一部分(对应图7)，或者通过回刻将场板FP的表面的第二介质层a2全部去除(对应图8)，然后采用相对较低的介电系数的介电材料通过CVD和回刻的方式再形成中间介质层b。
实施例二
本实施例二提供一种采用分栅(双栅)沟槽型场效应晶体管的半导体器件。
如图14所示，该分栅(双栅)沟槽型场效应晶体管与前述实施例一中的分栅(单栅)沟槽型场效应晶体管的主要区别在于，该晶体管在沟槽T内设置有两个栅极：第一栅极G1和第二栅极G2。第一栅极G1和第二栅极G2位于场板FP顶端的两侧，在水平方向上，第一栅极G1、第二栅极G2与场板FP之间设置为层间介质层20；也即层间介质层20设 置于隔离介质层10的上方。
此处可以理解的是，在凹槽T内，第一栅极G1和第二栅极G2分布在场板FP横向上的两侧，而在纵向上第一栅极G1、第二栅极G2与场板FP的延伸方向基本一致，且与场板FP的长度基本一致。另外，第一栅极G1和第二栅极G2可以在外延层2的表面连接，以使得两者能够处于等势体，保证晶体管的正常工作。
在该实施例二中，位于场板FP侧面的隔离介质层10的设置与前述实施例一中基本一致，通过设置隔离介质层10从下到上增大变化的介电系数，从而可以起到改变单位面积电容的目的，进而改变场板对电场的调制作用，在隔离介质层10的介电常数变化的位置引入新的尖峰电场，进而实现击穿电场的多峰甚至矩形分布，提升器件的击穿电压。
本申请实施例二还提供一种如图14中示出的晶体管的制作方法，如图15所示，该制作方法可以包括：
步骤21、参考图16中(a)所示，提供衬底1，并在衬底1表面生长外延层2。
上述步骤21与前述实施例一中的步骤11基本一致，可以参考前述步骤11的相关说明，此处不再赘述。
步骤22、参考图16中(b)和(c)所示，在外延层2的表面形成沟槽T，并在沟槽T的内壁中形成第一介质层a1。
上述步骤22与前述实施例一中的步骤12基本一致，可以参考前述步骤12的相关说明，此处不再赘述。
步骤23、参考图16中(d)所示，在形成有第一介质层a1的凹槽T中形成场板FP，并将第一介质层a1回刻至场板FP顶部以下的深度。
示意的，在一些可能实现的方式中，参考图16中(d)所示，该步骤23可以包括：通过LP-CVD(low pressure chemical vapor deposition，低压化学气相淀积)淀积一层多晶硅，并对沟槽T形成良好的填充；然后，无需掩模地将该多晶硅回刻(etch-back)到一特定深度d0(一般略微低于外延层2的上表面)形成场板FP；然后自对准地将第一介质层a1回刻到另一特定深度d1，且d1>d0。可选的，场板多晶硅在回刻之前可进行CMP(chemical mechanical polishing，化学机械抛光)，以提升其上表面的平整度。
步骤24、参考图16中(e)和(f)所示，在位于场板FP的侧面、第一介质层a1的表面形成第二介质层a2，并将第二介质层a2回刻至场板FP顶部以下的深度；第二介质层a2的介电系数大于第一介质层a1的介电系数。
可以理解的是，后续在第二介质层a2的顶部需要形成栅极(G1、G2)，因此步骤24形成的第二介质层a2顶部的深度应满足后续栅极(G1、G2)的制作要求。
示意的，在一些可能实现的方式中，上述步骤24可以包括：参考图16中(e)所示，通过CVD淀积第二介质层a2，并对沟槽T形成良好的填充。该第二介质层a2可以采用介电常数约为7.5的Si 3N 4。在沉积第二介质层a2之后根据需要可以对第二介质层a2的表面进行CMP，以提升其上表面的平整度。然后，参考图16中(f)所示，可以自对准地将第二介质层a2回刻到另一特定深度d2，且d2<d1。
步骤25、参考图17中(a)和(b)所示，在场板FP与沟槽T的侧壁均形成栅介质层12，并在位于场板FP的两侧分别形成第一栅极G1和第二栅极G2。
示意的，在一些可能实现的方式中，上述步骤25可以包括：参考图17中(a)所示， 在暴露的沟槽T的侧壁和外延层2的上表面通过热氧化生长一层栅介质层12，该栅介质层12可以采用SiO 2。可选地，在生长栅介质层12之前可以进行一次牺牲氧化层的生长并将其去除。当然，栅介质层12也可通过CVD形成。然后，参考图17中(b)所示，在场板FP的两侧，通过LP-CVD在第二介质层a2的表面淀积多晶硅，对沟槽形成良好的填充；接下来，无需掩模地将该多晶硅回刻到一特定深度(一般略低于外延层2的上表面)，从而在场板FP的两侧分别形成第一栅极G1和第二栅极G2。可选地，通过光刻掩模形成栅极(G1、G2)的同时，可以定义需要保留的多晶硅图形，以用于栅极连接结构或其它功能。
可以理解的是，采用上述制作工艺中，在形成栅介质层12的同时形成了层间介质层20，也即层间介质层20与栅介质层12是采用同一制作工艺制作而成，栅介质层12和层间介质层20的材料相同。
当然，在完成栅极(G1、G2)的制作之后的其他制作工艺可以结合相关技术进行制作即可，此处不再赘述。
关于该实施例二中晶体管的其他相关设置结构，如隔离介质层10、隔离缓冲层11、层间介质层20、阶梯结构30等，可以对应参考前述实施例一的相关内容，此处不再赘述。
实施例三
本实施例三提供一种采用非分栅沟槽型场效应晶体管(non-split gate trench MOS)的半导体器件。
如图18所示，该非分栅沟槽型场效应晶体管与前述实施例一中的分栅(单栅)沟槽型场效应晶体管的主要区别在于，位于沟槽T内的栅极G与场板FP的顶部连接，两者可以是连接的一体结构。在此情况下，栅极G与场板FP不存在层间介质层。
在该实施例三中，位于场板FP侧面的隔离介质层10的设置与前述实施例一中基本一致，通过设置隔离介质层10从下到上增大变化的介电系数，从而可以起到改变单位面积电容的目的，进而改变场板对电场的调制作用，在隔离介质层10的介电常数变化的位置引入新的尖峰电场，进而实现击穿电场的多峰甚至矩形分布，提升器件的击穿电压。
本申请实施例三还提供一种如图18中示出的晶体管的制作方法，如图19所示，该制作方法可以包括：
步骤31、参考图20中(a)所示，提供衬底1，并在衬底1表面生长外延层2。
上述步骤31与前述实施例一中的步骤11基本一致，可以参考前述步骤11的相关说明，此处不再赘述。
步骤32、参考图20中(b)和(c)所示，在外延层2的表面形成沟槽T，并在沟槽T的内壁中形成第一介质层a1。
上述步骤32与前述实施例一中的步骤12基本一致，可以参考前述步骤12的相关说明，此处不再赘述。
步骤33、参考图20中(d)所示，在位于第一介质层a1内壁形成的凹槽中形成假场板FP'，并将第一介质层a1回刻至假场板FP'顶部以下的深度。
示意的，在一些可能实现的方式中，参考图20中(d)所示，该步骤33可以包括：通过LP-CVD(low pressure chemical vapor deposition，低压化学气相淀积)淀积一层多晶硅，并对沟槽T形成良好的填充；然后，无需掩模地将该多晶硅回刻(etch-back)到一特 定深度d0(一般低于外延层2的上表面)形成假场板FP'(也可以称为牺牲场板)；然后自对准地将第一介质层a1回刻到另一特定深度d1，且d1>d0。
步骤34、参考图20中(e)和(f)所示，在位于假场板FP'的侧面、第一介质层a1的表面形成第二介质层a2，并将第二介质层a2回刻至假场板FP'顶部以下的深度；第二介质层a2的介电系数大于第一介质层a1的介电系数。
示意的，在一些可能实现的方式中，步骤34可以包括：参考图20中(e)所示，通过CVD淀积第二介质层a2，并对沟槽T形成良好的填充。该第二介质层a2可以采用介电常数约为7.5的Si 3N 4。在沉积第二介质层a2之后根据需要可以对第二介质层a2的表面进行CMP，以提升其上表面的平整度。然后，参考图20中(f)所示，可以自对准地将第二介质层a2回刻到另一特定深度d2，且d2<d1。
步骤35、参考图21中(a)和(b)所示，在沟槽T的侧壁形成栅介质层12，并在去除假场板FP'之后形成栅极G与场板FP的一体结构。
示意的，在一些可能实现的方式中，上述步骤35可以包括：参考图21中(a)所示，在暴露的沟槽T的侧壁和外延层2的上表面通过热氧化生长一层栅介质层12，并去除假场板FP'。该栅介质层12可以采用SiO 2。可选地，在生长栅介质层12之前可以进行一次牺牲氧化层的生长并将其去除。当然，栅介质层12也可通过CVD形成。然后，参考图21中(b)所示，通过LP-CVD重新沉积多晶硅对沟槽形成良好的填充；接下来，无需掩模地将该多晶硅回刻到一特定深度(一般略低于外延层2的上表面)，从而在沟槽T内形成场板FP的与栅极G的一体结构。可选地，通过光刻掩模形成栅极G的同时，可以定义需要保留的多晶硅图形，以用于栅极连接结构或其它功能。
当然，在完成栅极G的制作之后的其他制作工艺，可以结合相关技术进行制作即可，此处不再赘述。
关于该实施例三中晶体管的其他相关设置结构，如隔离介质层10、隔离缓冲层11、阶梯结构30等，可以对应参考前述实施例一的相关内容，此处不再赘述。
实施例四
本实施例四提供一种采用双沟槽型场效应晶体管的半导体器件。
图22为半导体器件中双沟槽型场效应晶体管的结构示意图(图中虚线框中为一个元胞)。如图22所示，该双沟槽型场效应晶体管与前述实施例一中的分栅(单栅)沟槽型场效应晶体管的主要区别在于，栅极G与场板FP位于不同的沟槽中。
参考图22所示，该晶体管在外延层2的表面并列设置有第一沟槽T1和第二沟槽T2。其中，第二沟槽T2的深度小于第一沟槽T1的深度；场板FP位于第一沟槽T1中，栅极G位于第二沟槽T2。
示意的，通常第二沟槽T2的深度应穿过阱区(P-well)进入漂移区(N-drift)的表层内，以满足栅极G的设置要求。第一沟槽T1的深度应延伸至漂移区(N-drift)内部，以保证场板FP的设置要求。
在该实施例四中，位于场板FP侧面的隔离介质层10的设置与前述实施例一中基本一致，通过设置隔离介质层10从下到上增大变化的介电系数，从而可以起到改变单位面积电容的目的，进而改变场板对电场的调制作用，在隔离介质层10的介电常数变化的位置引入新的尖峰电场，进而实现击穿电场的多峰甚至矩形分布，提升器件的击穿电压。
关于该实施例中晶体管的制作方式，可以参考前文的相关制作方法以及相关技术进行制作即可，此处不再赘述。
关于该实施例四中晶体管的其他相关设置结构，如隔离介质层10、隔离缓冲层11、层间介质层20、阶梯结构30等，可以对应参考前述实施例一的相关内容，此处不再赘述。
实施例五
本实施例五提供一种采用绝缘栅双极型晶体管(insulated gate bipolar transistor，IGBT)的半导体器件。
图23为半导体器件中并联的两个IGBT(也即两个元胞)的结构示意图。如图23所示，该IGBT中栅极G与场板FP的设计与实施例一类似，通过设置场板FP侧面的隔离介质层10采用介电系数从下到上增大变化的介电材料，从而可以起到改变单位面积电容的目的，进而改变场板对电场的调制作用，在隔离介质层10的介电常数变化的位置引入新的尖峰电场，进而实现电场的多峰甚至矩形分布，提升器件的击穿电压。
该IGBT与前述实施例一中的分栅(单栅)沟槽型场效应晶体管的主要区别在于：一般地，该IGBT可以直接采轻掺杂的N型半导体衬底作为场截止层(field stop)，衬底下表面设置有P型掺杂层作为发射层(injection)；其他膜层结构(如M1、M2、P-well、N-drift等)与实施例一中基本一致，此处不再赘述。
可以理解的是，由于IGBT与前述场效应晶体管的工作原理不同，因此即便两者中设置相同(或者说相似)的膜层，其作用不完全相同。例如，在该IGBT中，第一金属层M1和第二金属层M2分别作为集电极(collector)、发射极(emitter)。
该实施例中IGBT的制作方式，可以参考前文的相关制作方法以及相关技术进行制作即可，此处不再赘述。
关于该实施例五中晶体管的其他相关设置结构，如隔离介质层10、隔离缓冲层11、层间介质层20、阶梯结构30等，可以对应参考前述实施例一的相关内容，此处不再赘述。
实施例六
本实施例六提供一种采用沟槽MOS势垒肖特基二极管(trench MOS barrier schottky diode，TMBS)的半导体器件。
图24为半导体器件中并联的两个沟槽MOS势垒肖特基二极管(也即两个元胞)的结构示意图。如图24所示，该沟槽MOS势垒肖特基二极管(下文可简称为二极管)中场板FP的设计与实施例一类似，通过设置场板FP侧面的隔离介质层10采用介电系数从下到上增大变化的介电材料，从而可以起到改变单位面积电容的目的，进而改变场板对电场的调制作用，在隔离介质层10的介电常数变化的位置引入新的尖峰电场，进而实现电场的多峰甚至矩形分布，提升器件的击穿电压。
该二极管与前述实施例一中的晶体管的主要区别在于，外延层2可以仅包括N型轻掺杂层的漂移区(N-drift)，并且第二金属层M2作为二极管的阳极(anode)直接设置在外延层2的上表面，并且与场板FP连接(接触)，第一金属层M1作为二极管的阴极(cathode)。
关于该实施例中二极管的制作方式，可以参考前文的相关制作方法以及相关技术进行制作即可，此处不再赘述。
关于该实施例中二极管的其他相关设置结构，如隔离介质层10、隔离缓冲层11、阶梯结构30等，可以对应参考前述实施例一的相关内容，此处不再赘述。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (22)

  1. 一种半导体器件，其特征在于，包括分栅沟槽型场效应晶体管；其中，所述分栅沟槽型场效应晶体管包括：
    衬底；
    设置于所述衬底上的外延层，所述外延层在远离所述衬底一侧设置有沟槽；
    场板，所述场板位于所述沟槽内；
    隔离介质层，所述隔离介质层至少覆盖所述场板的侧面；
    所述隔离介质层包括覆盖在所述场板侧面的第一介质层和第二介质层，所述第一介质层相对于所述第二介质层靠近所述沟槽的槽底，且所述第二介质层的介电系数大于所述第一介质层的介电系数。
  2. 根据权利要求1所述的半导体器件，其特征在于，
    所述分栅沟槽型场效应晶体管还包括：位于所述沟槽内的第一栅极和第二栅极；
    所述第一栅极和所述第二栅极位于所述场板顶端的两侧，且所述第一栅极、所述第二栅极与所述场板之间均设置有层间介质层；
    所述层间介质层位于所述隔离介质层远离所述沟槽的槽底一侧。
  3. 根据权利要求1所述的半导体器件，其特征在于，
    所述分栅沟槽型场效应晶体管还包括：位于所述沟槽内的栅极；
    所述栅极位于所述场板远离所述衬底一侧，且所述栅极与所述场板之间设置有层间介质层。
  4. 根据权利要求1-3任一项所述的半导体器件，其特征在于，
    所述隔离介质层还包括覆盖在所述场边侧面的第三介质层；
    所述第三介质层相对于所述第二介质层远离所述沟槽的槽底；所述第三介质层的介电系数大于所述第二介质层的介电系数。
  5. 根据权利要求1-4任一项所述的半导体器件，其特征在于，
    所述第一介质层或所述第二介质层中的至少一个具有渐变介电系数；
    所述渐变介电系数沿所述沟槽的槽底到槽口的方向逐渐增大。
  6. 根据权利要求5所述的半导体器件，其特征在于，
    所述第一介质层采用第一介电材料；
    所述第二介质层采用所述多元化合物介电材料，且所述多元化合物介电材料的原子或分子组分，沿所述沟槽的槽底到槽口的方向，逐渐变化。
  7. 根据权利要求3-6任一项所述的半导体器件，其特征在于，
    在靠近所述场板顶端的侧面区域，所述隔离介质层与所述沟槽的侧壁之间设置有隔离缓冲层。
  8. 根据权利要求7所述的半导体器件，其特征在于，
    所述隔离缓冲层采用SiO 2。
  9. 根据权利要求3-8任一项所述的半导体器件，其特征在于，
    所述隔离介质层延伸并覆盖至所述场板的顶表面。
  10. 根据权利要求3-9任一项所述的半导体器件，其特征在于，
    所述层间介质层包括中间介质层；
    所述中间介质层的介电系数小于所述第二介质层的介电系数。
  11. 根据权利要求10所述的半导体器件，其特征在于，
    所述中间介质层覆盖所述场板的顶表面。
  12. 根据权利要求1-11任一项所述的半导体器件，其特征在于，
    所述场板的侧面设置有至少一个阶梯结构；
    所述阶梯结构的两个阶梯面中，靠近所述沟槽的槽口一侧的阶梯面凸出于靠近所述沟槽的槽底一侧的阶梯面。
  13. 根据权利要求1-12任一项所述的半导体器件，其特征在于，
    所述分栅沟槽型场效应晶体管还包括：第一金属层、第二金属层、绝缘介质层；其中，所述第一金属层设置在所述衬底远离所述外延层的一侧，所述绝缘介质层设置在所述外延层与所述第二金属层之间；
    所述衬底采用N型轻掺杂半导体材料；所述外延层沿厚度方向上分为：N型轻掺杂层、P型掺杂层、N型重掺杂层；其中，所述N型轻掺杂层相对于所述N型重掺杂层靠近所述衬底；所述场板位于所述N型轻掺杂层所在的区域；
    或者，所述衬底为P型轻掺杂半导体材料；所述外延层沿厚度方向上分为：P型轻掺杂层、N型掺杂层、P型重掺杂层；其中，所述P型轻掺杂层相对于所述P型重掺杂层靠近所述衬底；所述场板位于所述P型轻掺杂层所在的区域。
  14. 一种半导体器件，其特征在于，包括沟槽型电子元件；
    所述沟槽型电子元件包括：
    衬底；
    设置于所述衬底上的外延层，所述外延层在远离所述衬底一侧设置有第一沟槽；
    场板，所述场板位于所述第一沟槽内；
    隔离介质层，所述隔离介质层至少覆盖所述场板的侧面；
    所述隔离介质层包括覆盖在所述场板侧面的第一介质层和第二介质层，所述第一介质层相对于所述第二介质向靠近所述第一沟槽的槽底；所述第二介质层的介电系数大于所述第一介质层的介电系数。
  15. 根据权利要求14所述的半导体器件，其特征在于，
    所述沟槽型电子元件为非分栅沟槽型场效应晶体管；
    所述沟槽型场效应晶体管还包括栅极；
    所述栅极位于所述第一沟槽内，且所述栅极与所述场板的顶部连接。
  16. 根据权利要求14所述的半导体器件，其特征在于，
    所述沟槽型电子元件为双沟槽型场效应晶体管；
    所述双沟槽型场效应晶体管还包括栅极；
    所述外延层在远离所述衬底一侧还设置有第二沟槽；所述第二沟槽与所述第一沟槽并列设置；所述第二沟槽的深度小于所述第一沟槽的深度；
    所述栅极位于所述第二沟槽内。
  17. 根据权利要求14所述的半导体器件，其特征在于，
    所述沟槽型电子元件为沟槽MOS势垒肖特基二极管；
    所述沟槽MOS势垒肖特基二极管还包括第一金属层和第二金属层；
    所述第一金属层位于所述衬底远离所述外延层的一侧，所述第二金属层位于所述外延层远离所述衬底的一侧；
    所述场板的顶部与所述第二金属层连接。
  18. 根据权利要求14所述的半导体器件，其特征在于，
    所述沟槽型电子元件为绝缘栅双极型晶体管；
    所述衬底采用N型半导体材料；
    所述绝缘栅双极型晶体管还包括栅极、P型半导体层；
    所述栅极位于所述第一沟槽内，且所述栅极位于所述场板远离所述第一沟槽的槽底一侧，所述栅极与所述场板设置有层间介质层；
    所述P型半导体层位于所述衬底远离所述外延层的一侧；
    所述外延层在沿远离所述衬底的方向上依次为N型轻掺杂区、P型掺杂区、N型重掺杂区。
  19. 一种电子设备，其特征在于，包括印刷线路板以及如权利要求1-18任一项所述的半导体器件；所述半导体器件与所述印刷线路板电连接。
  20. 一种半导体器件的制作方法，其特征在于，包括：
    提供衬底，并在所述衬底表面生长外延层；
    在所述外延层的表面形成沟槽，并在所述沟槽的内壁中形成第一介质层；
    在形成有所述第一介质层的凹槽中形成场板，并将所述第一介质层回刻至所述场板顶部以下的深度；
    在位于所述场板的侧面、所述第一介质层的表面形成第二介质层；所述第二介质层的介电系数大于所述第一介质层的介电系数。
  21. 根据权利要求20所述半导体器件的制作方法，其特征在于，
    所述在位于所述场板的侧面、所述第一介质层的表面形成第二介质层，包括：
    在位于所述场板的侧面、所述第一介质层的表面，沉积多元化合物介电材料，并在沉积的过程中通过控制多元化合物介电材料中的原子或分子组分，以形成介电系数逐渐增大的第二介质层。
  22. 根据权利要求20或21所述半导体器件的制作方法，其特征在于，
    在所述场板的侧面形成包括第一介质层和所述第二介质层在内的隔离介质层之后，所述制作方法还包括：
    在所述场板的顶部形成中间介质层，且所述中间介质层的介电系数小于所述第二介质层的介电系数。
PCT/CN2022/129022 2022-01-24 2022-11-01 半导体器件及其制作方法、电子设备 WO2023138153A1 (zh)

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