WO2023132129A1 - 光検出装置 - Google Patents

光検出装置 Download PDF

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Publication number
WO2023132129A1
WO2023132129A1 PCT/JP2022/042169 JP2022042169W WO2023132129A1 WO 2023132129 A1 WO2023132129 A1 WO 2023132129A1 JP 2022042169 W JP2022042169 W JP 2022042169W WO 2023132129 A1 WO2023132129 A1 WO 2023132129A1
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Prior art keywords
current
voltage
signal
pixels
transistor
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Ceased
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PCT/JP2022/042169
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English (en)
French (fr)
Japanese (ja)
Inventor
直嗣 武田
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Sony Semiconductor Solutions Corp
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Sony Semiconductor Solutions Corp
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Priority to US18/711,246 priority Critical patent/US20260012715A1/en
Priority to JP2023572360A priority patent/JPWO2023132129A1/ja
Publication of WO2023132129A1 publication Critical patent/WO2023132129A1/ja
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/47—Image sensors with pixel address output; Event-driven image sensors; Selection of pixels to be read out based on image data
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/703—SSIS architectures incorporating pixels for producing signals other than image signals
    • H04N25/704—Pixels specially adapted for focusing, e.g. phase difference pixel sets

Definitions

  • the present disclosure relates to a photodetector.
  • An EVS Event-based Vision Sensor
  • luminance change is output, and an output value corresponding to the amount of incident light is not output. Therefore, it has been difficult to apply the AF (Auto Focus) function of the image plane phase difference method to the EVS.
  • a photodetector includes a plurality of first pixels that photoelectrically convert incident light from a portion on one side to generate a first current, and a portion of the first pixels that is opposite to the portion. a plurality of second pixels for generating a second current by photoelectrically converting the incident light from the second pixel; a plurality of first luminance circuits for generating; a plurality of second luminance circuits provided corresponding to each of the plurality of second pixels for generating a second luminance signal corresponding to the second current; a plurality of first current comparison circuits provided corresponding to each of the first pixels for comparing the first luminance signal with a reference signal and converting the first luminance signal into a first digital signal; a plurality of second current comparator circuits provided corresponding to each of the two pixels, comparing the second luminance signal with the reference signal and converting the second luminance signal into a second digital signal; and a controller that adjusts the focal position of the incident light based on the signal and the second
  • the control unit adjusts the focal position so that the first and second digital signals from the first and second pixels adjacent to each other are approximately the same.
  • the plurality of first pixels and the plurality of second pixels are alternately arranged adjacent to each other, and the controller controls the arrangement of the first digital signals from the plurality of first pixels and the plurality of second pixels.
  • a deviation direction and a deviation amount of the focus position are determined from the arrangement of the second digital signals from the two pixels.
  • the control unit adjusts the focus position so that the arrangement of the first digital signals from the plurality of first pixels and the arrangement of the second digital signals from the plurality of second pixels are substantially the same.
  • first current-voltage conversion circuits provided corresponding to each of the plurality of first pixels and generating a first voltage signal corresponding to the first current; and a plurality of second current-voltage conversion circuits for generating a second voltage signal corresponding to the second current.
  • the first current-voltage conversion circuit includes a first conversion transistor that converts the first current into a first voltage signal and outputs the voltage signal from a first gate, and a first output connected to the first gate with a predetermined constant current.
  • a first current source transistor that supplies a signal line; and a first voltage supply transistor that supplies a constant voltage corresponding to the predetermined constant current from the first output signal line to the source of the first conversion transistor.
  • the second current-voltage conversion circuit includes a second conversion transistor that converts the second current into a second voltage signal and outputs the second voltage signal from a second gate, and a second conversion transistor that outputs a predetermined constant current to the second gate.
  • a second current source transistor that supplies an output signal line; and a second voltage supply transistor that supplies a constant voltage corresponding to the predetermined constant current from the second output signal line to the source of the second conversion transistor.
  • the first luminance circuit includes a third conversion transistor that converts the first current into a third voltage signal and outputs the third voltage signal from the gate, and the second luminance circuit converts the second current into a fourth voltage signal.
  • the first current comparator circuit is connected between a high voltage source and a first output, the gate is connected to the gate of the third conversion transistor; a third current source transistor for passing a third current responsive to one current; a third current source transistor connected between the first output and a low voltage source, a gate receiving the reference signal and a first reference responsive to the reference signal; a current-passing first reference current transistor, said second current comparison circuit being connected between said high voltage source and a second output, having a gate connected to the gate of said fourth conversion transistor; a fifth current source transistor for passing a fifth current corresponding to a second current; a fifth current source transistor connected between the second output and the low voltage source, having a gate receiving the reference signal; and a second reference current transistor for passing two reference currents.
  • the first current comparison circuit outputs a first digital signal from the first output if the third current is greater than the first reference current, and the third current is less than the first reference current.
  • the first current comparison circuit outputs a second digital signal having an inverse logic to the first digital signal from the first output section, and if the fifth current is greater than the second reference current,
  • the second current comparing circuit outputs the first digital signal from the second output, and if the fifth current is less than the second reference current, the second current comparing circuit outputs the second output. output the second digital signal from the unit.
  • a plurality of third pixels photoelectrically converting the incident light received on the entire surface to generate a third current, wherein the plurality of first pixels and the plurality of second pixels are adjacent to the plurality of third pixels; are arranged alternately and substantially evenly.
  • a first semiconductor chip including the first and second pixels; a second semiconductor chip including the first and second current-voltage conversion circuits; the first and second luminance circuits; and the first and second current comparison circuits. It is configured by stacking semiconductor chips.
  • a first semiconductor chip including the plurality of first and second pixels, the first and second conversion transistors, and the first and second voltage supply transistors; the first and second current source transistors; , a second luminance circuit, and a second semiconductor chip including the first and second current comparator circuits are laminated.
  • the first luminance circuit includes a first conversion transistor that converts the first current into a first voltage signal and outputs the signal from a first gate, and a first output signal line that outputs a predetermined constant current to the first gate. and a first voltage supply transistor that supplies a constant voltage corresponding to the predetermined constant current from the first output signal line to the source of the first conversion transistor, wherein the The second luminance circuit includes a second conversion transistor for converting the second current into a second voltage signal and outputting it from a second gate, and a predetermined constant current to a second output signal line connected to the second gate.
  • a first current comparison circuit converts the first voltage signal into the first digital signal as the first luminance signal
  • a second current comparison circuit converts the second voltage signal into the second luminance signal as the second luminance signal. Convert to digital signal.
  • the first luminance circuit includes a first conversion transistor that converts the first current into a first voltage signal and outputs the voltage signal from a first gate, and a predetermined constant current to a first output signal line connected to the first gate. and a first voltage supply transistor for supplying a constant voltage corresponding to the predetermined constant current from the first output signal line to the source of the first conversion transistor,
  • the second luminance circuit has a second conversion transistor that converts the second current into a second voltage signal and outputs the second voltage signal from a second gate, and supplies a predetermined constant current to a second output signal line connected to the second gate.
  • the first A current comparison circuit converts the gate voltage of the first voltage supply transistor into the first digital signal as the first luminance signal
  • the second current comparison circuit converts the gate voltage of the second voltage supply transistor into the second luminance signal. 2 is converted into the second digital signal as a luminance signal.
  • control unit changes the reference signal.
  • the first and second pixels are adjacent to each other and constitute a plurality of third pixels that photoelectrically convert the incident light received from the entire surface to generate a third current.
  • FIG. 1 is a block diagram showing a configuration example of an imaging apparatus according to a first embodiment
  • FIG. FIG. 4 is a diagram showing an example of a layered structure of the photodetector according to the first embodiment
  • FIG. 2 is a diagram showing an example of a plan view of a light receiving chip according to the first embodiment
  • FIG. 2 is a plan view showing an example of a detection chip according to the first embodiment
  • FIG. 4 is a plan view showing an example of an address event detection unit in the first embodiment
  • FIG. 3 is a block diagram showing a configuration example of an address event detection circuit in the first embodiment
  • FIG. 4 is a circuit diagram showing configuration examples of a current-voltage conversion circuit, a luminance circuit, and a current comparison circuit according to the first embodiment
  • FIG. 4 is a circuit diagram showing a configuration example of a subtractor and a quantizer
  • FIG. FIG. 2 is a plan view showing the arrangement of a plurality of pixels in a light receiving section
  • 4A and 4B are diagrams showing image plane phase difference AF processing according to the first embodiment
  • FIG. 4A and 4B are diagrams showing image plane phase difference AF processing according to the first embodiment
  • FIG. 4A and 4B are diagrams showing image plane phase difference AF processing according to the first embodiment
  • FIG. 4A and 4B are diagrams showing image plane phase difference AF processing according to the first embodiment
  • FIG. 4A and 4B are diagrams showing image plane phase difference AF processing according to the first embodiment
  • FIG. 4A and 4B are diagrams showing image plane phase difference AF processing according to the first embodiment
  • FIG. 4A and 4B are diagrams showing image plane phase difference AF processing according to the first embodiment
  • FIG. 4A and 4B are diagrams showing image plane phase difference AF processing according to the first embodiment
  • FIG. 4A and 4B are diagrams showing image plane phase difference AF processing according to the first embodiment;
  • FIG. FIG. 10 is a flowchart showing the operation of the photodetector according to the modification;
  • FIG. 10 is a plan view showing the arrangement of first pixels, second pixels, and normal pixels of a light receiving portion according to the second embodiment;
  • FIG. 11 is a plan view showing the arrangement of first pixels, second pixels, and normal pixels of a light receiving section according to a third embodiment;
  • the circuit diagram which shows the structural example of the photodetector by 4th Embodiment.
  • the circuit diagram which shows the structural example of the photodetector by 4th Embodiment.
  • the circuit diagram which shows the structural example of the photodetector by 6th Embodiment. 1 is a block diagram showing an example of a schematic configuration of a vehicle control system;
  • FIG. FIG. 2 is an explanatory diagram showing an example of installation positions of an information detection unit outside the vehicle and an imaging unit;
  • Synchronous solid-state imaging devices that capture image data (frames) in synchronization with synchronization signals such as vertical synchronization signals are used in imaging devices.
  • image data can only be acquired at each period of the synchronization signal (for example, 1/60th of a second). Difficulty responding to requests.
  • each pixel is provided with an address event detection circuit that detects in real time that the amount of light in a pixel exceeds a threshold as an event.
  • This address event detection circuit is provided with a current-voltage conversion circuit including two N-type transistors connected in a loop, and the circuit converts the photocurrent from the photodiode into a voltage signal.
  • EVS can generate and output data much faster than synchronous solid-state imaging devices. Therefore, the EVS can improve safety by performing image recognition processing of people and obstacles at high speed, for example, in the traffic field.
  • FIG. 1 is a block diagram showing a configuration example of an imaging device 100 according to the first embodiment.
  • the imaging device 100 captures image data, and includes an imaging lens 110 , a photodetector (EVS) 200 , a recording unit 120 and a control unit 130 .
  • EVS photodetector
  • As the imaging device 100 a camera mounted on an industrial robot, an in-vehicle camera, or the like is assumed.
  • the imaging lens 110 collects incident light and guides it to the photodetector 200 .
  • the photodetector 200 photoelectrically converts incident light to capture image data.
  • the photodetection device 200 performs predetermined signal processing such as image recognition processing on the captured image data, and outputs the processed data to the recording unit 120 via the signal line 209 . .
  • the recording unit 120 records data from the photodetector 200 .
  • the control unit 130 controls the photodetector 200 to capture image data. Also, the control unit 130 changes the relative distance between the imaging lens 110 and the photodetector 200 to adjust the focal position of the incident light.
  • FIG. 2 is a diagram showing an example of the layered structure of the photodetector 200 according to the first embodiment.
  • the photodetector 200 includes a detector chip 202 and a photodetector chip 201 which are stacked. These chips 201 and 202 are joined by vias or the like. In addition to vias, Cu--Cu bonding and bumps can also be used for bonding.
  • FIG. 3 is a diagram showing an example of a plan view of the light receiving chip 201 in the first embodiment.
  • the light receiving chip 201 is provided with a light receiving portion 220 and via arrangement portions 211 to 213 .
  • Vias for example, TSV (Through Silicon Via) connected to the detection chip 202 are arranged in the via arrangement portions 211 to 213 .
  • a plurality of photodiodes 221 are arranged in a two-dimensional lattice pattern in the light receiving section 220 .
  • the photodiode 221 photoelectrically converts incident light to generate a photocurrent.
  • Each photodiode 221 is assigned a pixel address consisting of a row address and a column address and treated as a pixel.
  • FIG. 4 is a plan view showing an example of the detection chip 202 in the first embodiment.
  • the detection chip 202 is provided with via placement sections 231 to 233 , a signal processing circuit 240 , a row driving circuit 251 , a column driving circuit 252 , an address event detection section 260 and a bias supply section 270 .
  • Vias (for example, TSVs) connected to the light receiving chip 201 are arranged in the via arrangement portions 231 to 233 .
  • the address event detection section 260 generates a detection signal from each photocurrent of the plurality of photodiodes 221 and outputs it to the signal processing circuit 240 .
  • This detection signal is a 1-bit signal that indicates whether or not it is detected as an address event that the amount of incident light exceeds a predetermined threshold.
  • the row drive circuit 251 selects a row address and causes the address event detector 260 to output a detection signal corresponding to the row address.
  • the column drive circuit 252 selects a column address and causes the address event detection section 260 to output a detection signal corresponding to the column address.
  • the signal processing circuit 240 performs predetermined signal processing on the detection signal from the address event detection section 260 .
  • the signal processing circuit 240 arranges the detection signals as pixel signals in a two-dimensional lattice, and acquires image data having 1-bit information for each pixel. Then, the signal processing circuit 240 executes signal processing such as image recognition processing on the image data.
  • Signal processing circuit 240 also processes digital signal Vcm from address event detection circuit 300 in FIG.
  • the bias supply unit 270 generates bias voltages such as the bias voltage Vbias and the reference voltage Vref in FIG. 7 and supplies them to the address event detection circuit 300 .
  • the bias supply section 270 may supply the bias voltage Vbias and the reference voltage Vref for each row.
  • FIG. 5 is a plan view showing an example of the address event detector 260 in the first embodiment.
  • a plurality of address event detection circuits 300 are arranged in a two-dimensional lattice.
  • Each of the address event detection circuits 300 is assigned a pixel address and connected to the photodiode 221 of the same address.
  • the address event detection circuit 300 is provided corresponding to each photodiode 221 as a pixel.
  • the address event detection circuit 300 quantizes the voltage signal corresponding to the photocurrent from the corresponding photodiode 221 and outputs it as a detection signal. Also, the address event detection circuit 300 outputs a digital signal Vcm corresponding to the photocurrent from the corresponding photodiode 221 to perform the image plane phase difference AF.
  • FIG. 6 is a block diagram showing a configuration example of the address event detection circuit 300 in the first embodiment.
  • the address event detection circuit 300 includes a current-voltage conversion circuit 310 , a buffer 320 , a subtractor 330 , a quantizer 340 , a transfer circuit 350 , a luminance circuit 360 and an AD conversion circuit 370 .
  • the current-voltage conversion circuit 310 converts the photocurrent from the corresponding photodiode 221 into a voltage signal Vout.
  • Current-voltage conversion circuit 310 supplies voltage signal Vout to buffer 320 .
  • the buffer 320 corrects the voltage signal Vout from the current-voltage conversion circuit 310. Buffer 320 outputs the corrected voltage signal to subtractor 330 .
  • the subtractor 330 reduces the level of the voltage signal Vout from the buffer 320 according to the row driving signal from the row driving circuit 251. Subtractor 330 supplies the reduced voltage signal Vout to quantizer 340 .
  • the quantizer 340 quantizes the voltage signal Vout from the subtractor 330 into a digital signal and outputs it to the transfer circuit 350 as a detection signal.
  • the transfer circuit 350 transfers the detection signal from the quantizer 340 to the signal processing circuit 240 according to the column drive signal from the column drive circuit 252 .
  • the luminance circuit 360 is connected to the current-voltage conversion circuit 310 and generates a luminance signal Vcp according to the photocurrent from the photodiode 221 corresponding to each pixel.
  • An AD conversion circuit 370 as a current comparison circuit compares a luminance current Ipda based on the luminance signal Vcp with a reference current Iref based on a reference signal (reference voltage) Vref, and AD (Analog-to-Digital) converts the luminance signal Vcp into a digital signal. do.
  • FIG. 7 is a circuit diagram showing a configuration example of the current-voltage conversion circuit 310, luminance circuit 360, and AD conversion circuit 370 in the first embodiment.
  • the current-voltage conversion circuit 310 includes a conversion transistor 311 , a capacitor 312 , a current source transistor 313 and a voltage supply transistor 314 .
  • a conversion transistor 311 and the voltage supply transistor 314 for example, an N-type MOS (Metal-Oxide-Semiconductor) transistor is used.
  • a P-type MOS transistor, for example, is used as the current source transistor 313 .
  • the conversion transistor 311 converts the photocurrent Ipd from the corresponding photodiode 221 into a voltage signal Vout and outputs it from the gate.
  • the source of conversion transistor 311 is connected to the cathode of photodiode 221 and the gate of voltage supply transistor 314 via input signal line 315 .
  • the drain of the conversion transistor 311 is connected to the high voltage source VDD through the luminance circuit 360, and the gate is connected through the output signal line 316 to the drain of the current source transistor 313, the drain of the voltage supply transistor 314, and the buffer 320. is connected to the input terminal of
  • the current source transistor 313 supplies a predetermined constant current to the output signal line 316 .
  • a predetermined bias voltage Vbias is applied to the gate of the current source transistor 313 .
  • the source is connected to high voltage supply VDD and the drain is connected to output signal line 316 .
  • the voltage supply transistor 314 supplies a constant voltage corresponding to the constant current from the output signal line 316 to the source of the conversion transistor 311 via the input signal line 315 .
  • the source voltage of the conversion transistor 311 is fixed at a constant voltage. Therefore, when light is incident, the gate-source voltage of the conversion transistor 311 rises according to the photocurrent Ipd, and the level of the voltage signal Vout rises.
  • Capacitor 312 functions as a capacitance that compensates for the phase delay of voltage signal Vout.
  • a capacitance between wirings or a capacitive element such as a transistor can also be used as a capacitor.
  • the conversion transistor 311 and the voltage supply transistor 314 form a loop circuit. Under certain conditions, this loop circuit becomes a negative feedback circuit, and the voltage signal Vout may oscillate.
  • the capacitor 312 compensates for the phase delay of the voltage signal Vout, suppresses the oscillation of the loop circuit of the current-voltage conversion circuit 310, and stabilizes it.
  • the luminance circuit 360 has a conversion transistor 361 .
  • a P-type MOS transistor for example, is used for the conversion transistor 361 .
  • the source of conversion transistor 361 is connected to high voltage source VDD.
  • the drain of conversion transistor 361 is connected to the drain of conversion transistor 311 and the gate of conversion transistor 361 .
  • a gate of the conversion transistor 361 is connected to the drain of the conversion transistor 311 and the AD conversion circuit 370 .
  • the conversion transistor 361 generates a voltage corresponding to the photocurrent Ipd flowing through the photodiode 221 as the luminance signal Vcp, and outputs it from the gate of the conversion transistor 361 .
  • the AD conversion circuit 370 has a current source transistor 371 , a reference current transistor 372 and a buffer 373 .
  • a P-type MOS transistor for example, is used for the current source transistor 371 .
  • An N-type MOS transistor for example, is used for the reference current transistor 372 .
  • a CMOS circuit for example, is used for the buffer 373 .
  • the source of the current source transistor 371 is connected to the high voltage source VDD.
  • the drain of current source transistor 371 is connected to the drain of reference current transistor 372 and the input of buffer 373 .
  • the gate of current source transistor 371 is connected to the gate and drain of conversion transistor 361 .
  • the current source transistor 371 and the conversion transistor 361 form a current mirror circuit, and the current source transistor 371 flows a current Ipda corresponding to a predetermined mirror ratio with respect to the photocurrent Ipd.
  • the current Ipda has a current value proportional to the photocurrent Ipd.
  • the drain of the reference current transistor 372 is connected to the drain of the current source transistor 371 and the input of the buffer 373 .
  • the source of reference current transistor 372 is connected to a low voltage source (eg, ground).
  • the gate of reference current transistor 372 receives reference voltage Vref.
  • the reference voltage Vref is set to a predetermined value, but can be changed arbitrarily.
  • the reference current transistor 372 passes a reference current Iref according to the reference voltage Vref.
  • the input of the buffer 373 is connected to a node Nda between the current source transistor 371 and the reference current transistor 372, and outputs the voltage level of the node Nda as a digital signal from the output section.
  • the AD conversion circuit 370 outputs a high level (“1”) digital signal from the output section of the buffer 373 .
  • the voltage of the node Nda becomes a low level voltage close to the voltage of the low voltage source (eg ground potential). Therefore, the AD conversion circuit 370 outputs a low level (“0”) digital signal from the output section of the buffer 373 .
  • the AD conversion circuit 370 compares the current Ipda corresponding to the photocurrent Ipd with the reference current Iref, and outputs a digital signal Vcm based on the magnitude relationship therebetween. Thereby, the AD conversion circuit 370 can output digital signals Vcm having logics opposite to each other depending on whether the luminance of the incident light is higher or lower than the threshold value.
  • FIG. 8 is a circuit diagram showing a configuration example of the subtractor 330 and the quantizer 340.
  • FIG. Subtractor 330 comprises capacitors 331 and 333 , inverter 332 and switch 334 .
  • the quantizer 340 also includes a comparator 341 .
  • Capacitor 333 is connected in parallel with inverter 332 .
  • the switch 334 opens and closes the path connecting both ends of the capacitor 333 according to the row drive signal.
  • the inverter 332 inverts the voltage signal input via the capacitor 331 .
  • the inverter 332 outputs the inverted signal to the non-inverting input terminal (+) of the comparator 341 .
  • Equation 8 represents the subtraction operation of the voltage signal, and the gain of the subtraction result is C1/C2. Since it is usually desired to maximize the gain, it is preferable to design the capacitance value C1 to be large and the capacitance value C2 to be small. On the other hand, if C2 is too small, the kTC noise may increase and the noise characteristics may deteriorate, so the reduction of the capacitance of C2 is limited within the range in which noise can be tolerated. In addition, since the address event detection circuit 300 including the subtractor 330 is mounted for each pixel, the capacitance values C1 and C2 are restricted in terms of area.
  • the capacitance values C1 and C2 also vary in their possible range in proportion to the pixel size, but in a normal design, for example, the capacitance value C1 is set to a value of 20 to 200 femtofarads (fF). be done. Capacitance value C2 is set to a value between 1 and 20 femtofarads (fF).
  • the comparator 341 compares the voltage signal from the subtractor 330 with a predetermined threshold voltage Vth applied to the inverting input terminal (-). The comparator 341 outputs a signal indicating the comparison result to the transfer circuit 350 as a detection signal.
  • the capacitors 331 and 333 are provided as capacitive elements, wiring capacitors, transistors, or the like may be provided instead.
  • the type of the capacitive element having the capacitance value C1 and the type of the capacitive element having the capacitance value C2 are desirably the same because the relative accuracy affects the characteristics.
  • the capacitive element having the capacitance value CC and the capacitive elements having the capacitance values C1 and C2 may be of different types.
  • an inter-wiring capacitance may be used as the capacitive element having the capacitance value CC
  • capacitors may be used as the capacitive elements having the capacitance values C1 and C2.
  • FIG. 9 is a plan view showing the arrangement of a plurality of pixels in the light receiving section 220.
  • Each pixel 222 has a photodiode 221 and photoelectrically converts incident light to generate current.
  • R (Red), G (Green), and B (Blue) pixels 222 (hereinafter also referred to as normal pixels 222) photoelectrically convert incident light corresponding to each color.
  • the RGB normal pixels 222 are not shielded from light, and receive incident light of each color of RGB over the entire surface and perform photoelectric conversion. Therefore, the R normal pixel 222 photoelectrically converts red light, the G normal pixel 222 photoelectrically converts green light, and the B normal pixel 222 photoelectrically converts blue light.
  • the first pixel PnL (n is a positive integer) shields a portion on one side and photoelectrically converts incident light from the exception portion to generate a first current.
  • the first pixel PnL shields approximately half of the left side and photoelectrically converts incident light from approximately the right half.
  • the second pixel PnR shields a portion of the first pixel PnL opposite to the shielded portion, and photoelectrically converts incident light from the exception portion to generate a second current.
  • the second pixel PnR shields approximately half of the right side and photoelectrically converts incident light from approximately the left side.
  • the first pixels PnL and the second pixels PnR are arranged adjacent to the normal pixels 222, and are arranged alternately and substantially evenly.
  • a second pixel P1R is arranged next to the first pixel P1L with a B (Blue) pixel 222 interposed therebetween.
  • a first pixel P2L is arranged next to the second pixel P1R with another B (Blue) pixel 222 interposed therebetween.
  • the first pixels PnL and the second pixels PnR are alternately and substantially evenly arranged.
  • the RGB normal pixels 222 are also arranged substantially evenly along with the first and second pixels PnL and PnR.
  • the current-voltage conversion circuit 310, luminance circuit 360 and AD conversion circuit 370 in FIG. 7 are provided corresponding to each of the first pixel PnL and the second pixel PnR.
  • the current-voltage conversion circuit 310, the luminance circuit 360 and the AD conversion circuit 370 corresponding to the first pixel PnL are called the first current-voltage conversion circuit 310, the first luminance circuit 360 and the first AD conversion circuit 370 for convenience.
  • the current-voltage conversion circuit 310, the luminance circuit 360 and the AD conversion circuit 370 corresponding to the second pixel PnR are called the second current-voltage conversion circuit 310, the second luminance circuit 360 and the second AD conversion circuit 370 for convenience.
  • the first current-voltage conversion circuit 310 is provided corresponding to each of the plurality of first pixels PnL, and generates a first voltage signal corresponding to the photocurrent Ipd flowing through the corresponding first pixel PnL.
  • a second current-voltage conversion circuit 310 is provided corresponding to each of the plurality of second pixels PnR, and generates a second voltage signal corresponding to the photocurrent Ipd flowing through the corresponding second pixel PnR.
  • the first current-voltage conversion circuit 310 includes a first conversion transistor 311 , a first current source transistor 313 and a first voltage supply transistor 314 .
  • the first conversion transistor 311 converts the photocurrent Ipd into an output signal Vout and outputs it from the gate.
  • the first current source transistor 313 supplies a predetermined constant current to the first output signal line 316 connected to the gate of the first conversion transistor 311 .
  • the first voltage supply transistor 314 supplies a constant voltage corresponding to a predetermined constant current from the first output signal line 316 to the source of the first conversion transistor 311 .
  • the second current-voltage conversion circuit 310 includes a second conversion transistor 311 , a second current source transistor 313 , and a second voltage supply transistor 314 .
  • the second conversion transistor 311 converts the photocurrent Ipd into an output signal Vout and outputs it from the gate.
  • the second current source transistor 313 supplies a predetermined constant current to the second output signal line 316 connected to the gate of the second conversion transistor 311 .
  • the second voltage supply transistor 314 supplies a constant voltage corresponding to a predetermined constant current from the second output signal line 316 to the source of the second conversion transistor 311 .
  • the first and second power supply voltage conversion circuits 310 can output voltage signals Vout corresponding to the respective photocurrents Ipd.
  • the first luminance circuit 360 is provided corresponding to each of the plurality of first pixels PnL, and generates a first luminance signal Vcp according to the photocurrent Ipd flowing through the corresponding first pixel PnL.
  • the second luminance circuit 360 is provided corresponding to each of the plurality of second pixels PnR and generates a second luminance signal Vcp according to the photocurrent Ipd flowing through the corresponding second pixel PnR.
  • the first luminance circuit 360 includes a third conversion transistor 361 that converts the photocurrent Ipd into a luminance signal Vcp and outputs it from the gate. Thereby, the first luminance circuit 360 is provided corresponding to each of the plurality of first pixels PnL, and generates the first luminance signal Vcp corresponding to the photocurrent Ipd flowing through the corresponding first pixel PnL.
  • the second luminance circuit 360 includes a fourth conversion transistor 361 that converts the photocurrent Ipd into a luminance signal Vcp and outputs it from the gate.
  • the second luminance circuit 360 is provided corresponding to each of the plurality of second pixels PnR and generates a second luminance signal Vcp according to the photocurrent Ipd flowing through the corresponding second pixel PnR.
  • the first AD conversion circuit 370 includes a third current source transistor 371 , a first reference current transistor 372 and a first buffer 373 .
  • the third current source transistor 371 is connected between the high voltage source VDD and the output and has its gate connected to the gate of the third conversion transistor 361 .
  • the third current source transistor 371 causes the current Ipda corresponding to the photocurrent Ipd to flow.
  • a first reference current transistor 372 is connected between the output and a low voltage source GND, and receives a reference signal Vref at its gate. This causes the first reference current transistor 372 to flow the reference current Iref corresponding to the reference signal Vref.
  • the first AD conversion circuit 370 is provided corresponding to each of the plurality of first pixels PnL, compares the current Ipda corresponding to the first luminance signal Vcp with the current Iref corresponding to the reference signal Vref, and converts the first luminance signal Vcp can be AD-converted into the first digital signal Vcm.
  • the first buffer 373 is connected to the node Nda of the first AD conversion circuit 370 and outputs the digital signal Vcm.
  • the second AD conversion circuit 370 includes a fifth current source transistor 371 and a second reference current transistor 372.
  • the fifth current source transistor 371 is connected between the high voltage source VDD and the output, and has its gate connected to the gate of the fourth conversion transistor 361 .
  • the fifth current source transistor 371 causes the current Ipda corresponding to the photocurrent Ipd to flow.
  • a second reference current transistor 372 is connected between the output and the low voltage source GND, and has its gate receiving the reference signal Vref.
  • the reference signal Vref is the same as the reference signal Vref received by the first reference current transistor 372 . This causes the second reference current transistor 372 to flow the reference current Iref according to the reference signal Vref.
  • the second AD conversion circuit 370 is provided corresponding to each of the plurality of second pixels PnR, compares the current Ipda corresponding to the second luminance signal Vcp with the current Iref corresponding to the reference signal Vref, and converts the second luminance signal Vcp can be AD-converted to the second digital signal Vcm.
  • the second buffer 373 is connected to the node Nda of the second AD conversion circuit 370 and outputs the digital signal Vcm.
  • the first and second pixels PnL and PnR may be pixels without color filters, or may be pixels receiving the same color of R, G, and B.
  • the photodetector 200 executes image plane phase difference AF processing using luminance signals from the first and second pixels PnL and PnR.
  • 10A to 12B are diagrams showing image plane phase difference AF processing according to the first embodiment.
  • 10A, 11A, and 12A are conceptual diagrams showing the positional relationship among the object to be imaged OB, the imaging lens 110, the focal position F, and the light receiving section 220.
  • FIG. 10B, 11B and 12B are graphs showing the relationship between the positions of the first and second pixels PnL and PnR and the current Ipda proportional to the photocurrent Ipd.
  • the digital signals Vcm in FIGS. 10B, 11B, and 12B show the digital signal Vcm of the first pixel PnL in the upper stage, and the digital signal Vcm of the second pixel PnR in the lower stage.
  • FIG. 10A and 10B show a case (front focus state) in which the focal position F is positioned closer to the imaging lens 110 than the light receiving surface of the light receiving unit 220.
  • FIG. The incident light L1 is incident light passing through one side of the imaging lens 110, and the incident light L2 is incident light passing through the other side of the imaging lens 110.
  • FIG. In the case of the front focus state the incident light L1 passes through the focal position F and enters the second pixel PnR.
  • the incident light L2 passes through the focal position F and enters the first pixel PnL. Therefore, as shown in FIG. 10A, the incident lights L1 and L2 pass through the focal position F and are incident on the light receiving section 220 while being mutually inverted. Thereby, as shown in FIG.
  • the current Ipda of the incident light L1 is detected by the second pixel PnR.
  • a current Ipda of the incident light L2 is detected by the first pixel PnL.
  • the current Ipda substantially represents the photocurrent Ipd (luminance) because it is proportional to the photocurrent Ipd with a predetermined mirror ratio.
  • the first luminance circuit 360 generates the first luminance signal Vcp according to the photocurrent Ipd of the first pixel PnL.
  • the first AD conversion circuit 370 receives the first luminance signal Vcp, generates a current Ipda proportional to the photocurrent Ipd, and compares the current Ipda with the reference current Iref.
  • the first AD conversion circuit 370 outputs a digital signal Vcm according to the magnitude relationship between the current Ipda and the reference current Iref. For example, when the current Ipda is larger than the reference current Iref, the first AD conversion circuit 370 outputs a high level voltage (eg, "1") as the digital signal Vcm from the output section. When the current Ipda is smaller than the reference current Iref, the first AD conversion circuit 370 outputs a low level voltage (eg, "0") as the digital signal Vcm from the output section.
  • the second luminance circuit 360 generates a second luminance signal Vcp according to the photocurrent Ipd of the second pixel PnR.
  • the second AD conversion circuit 370 receives the second luminance signal Vcp, generates a current Ipda proportional to the photocurrent Ipd, and compares the current Ipda with the reference current Iref.
  • the second AD conversion circuit 370 outputs a digital signal Vcm according to the magnitude relationship between the current Ipda and the reference current Iref. For example, when the current Ipda is greater than the reference current Iref, the second AD conversion circuit 370 outputs a high level voltage (eg, "1") as the digital signal Vcm from the output section. When the current Ipda is smaller than the reference current Iref, the second AD conversion circuit 370 outputs a low level voltage (for example, "0") as the digital signal Vcm from the output section.
  • the first and second AD conversion circuits 370 can output the digital signal Vcm corresponding to the current Ipda corresponding to the photocurrent Ipd of the first and second pixels PnL and PnR, respectively.
  • the digital signal Vcm of FIG. 10B shows the digital signal Vcm of the first pixel PnL in the upper stage and the digital signal Vcm of the second pixel PnR in the lower stage.
  • the digital signals Vcm of the first and second pixels PnL and PnR adjacent to each other are shown at the same pixel positions in the upper and lower rows, respectively.
  • the current Ipda of the first pixel PnL receiving the incident light L2 is smaller than the reference current Iref, so the digital signal Vcm from the first AD conversion circuit 370 corresponding to the first pixel PnL is "0". Since the current Ipda of the second pixel PnR that has received the incident light L1 is larger than the reference current Iref, the digital signal Vcm from the second AD conversion circuit 370 corresponding to the second pixel PnR is "1".
  • the digital signal Vcm from the second AD conversion circuit 370 corresponding to the second pixel PnR changes from "1" to "0". ”.
  • the digital signal Vcm from the first AD conversion circuit 370 corresponding to the first pixel PnL changes from "1" to "0". ”.
  • the digital signal Vcm from the second AD conversion circuit 370 corresponding to the second pixel PnR changes from "0" to "1". ”.
  • the digital signal Vcm from the first AD conversion circuit 370 corresponding to the first pixel PnL changes from "0" to "1". ”.
  • the digital signal Vcm from the second AD conversion circuit 370 corresponding to the second pixel PnR changes from "1" to "0". ”.
  • the focal position F when the focal position F is shifted from the light receiving surface of the light receiving unit 220, the pixel position where the digital signal Vcm changes differs (shifts) between the first pixel PnL and the second pixel PnR.
  • FIG. 11A and 11B show a case (in-focus state) in which the focal position F is located on the light receiving surface of the light receiving unit 220.
  • FIG. In the in-focus state the incident lights L1 and L2 are both incident on the first and second pixels PnL and PnR. Thereby, as shown in FIG. 11B, the current Ipda of the incident light L1, L2 is detected by both the first and second pixels PnL, PnR.
  • the current Ipda is approximately equal in the first and second pixels PnL and PnR.
  • the currents Ipda of the first and second pixels PnL and PnR are substantially the same depending on the pixel position.
  • the current Ipda of the first and second pixels PnL, PnR receiving the incident light L1, L2 is smaller than the reference current Iref, and therefore corresponds to the first and second pixels PnL, PnR.
  • the digital signals Vcm from the first and second AD conversion circuits 370 are both "0".
  • the digital signals Vcm from the first and second AD conversion circuits 370 corresponding to the first and second pixels PnL and PnR both change from “0" to "1".
  • the digital signals Vcm from the first and second AD conversion circuits 370 corresponding to the first and second pixels PnL and PnR both change from "1" to "0".
  • FIG. 12A and 12B show a case (rear focus state) in which the focal position F is located on the side opposite to the imaging lens 110 with respect to the light receiving surface of the light receiving unit 220.
  • FIG. 12A In the case of the rear focus state, the incident light L1 passes through the focal position F and enters the first pixel PnL.
  • the incident light L2 passes through the focal position F and enters the second pixel PnR. Therefore, as shown in FIG. 12A, the incident lights L1 and L2 pass through the focal position F and enter the light receiving section 220 in a non-inverted state.
  • FIG. 12B the current Ipda of the incident light L1 is detected by the first pixel PnL.
  • a current Ipda of the incident light L2 is detected by the second pixel PnR.
  • the current Ipda of the first pixel PnL that has received the incident light L1 is greater than the reference current Iref.
  • Vcm is "1". Since the current Ipda of the second pixel PnR that has received the incident light L2 is smaller than the reference current Iref, the digital signal Vcm from the second AD conversion circuit 370 corresponding to the second pixel PnR is "0".
  • the digital signal Vcm from the first AD conversion circuit 370 corresponding to the first pixel PnL changes from "1" to "0". ”.
  • the digital signal Vcm from the second AD conversion circuit 370 corresponding to the second pixel PnR changes from "1" to "0". ”.
  • the digital signal Vcm from the first AD conversion circuit 370 corresponding to the first pixel PnL changes from "1" to "0". ”.
  • the focal position F when the focal position F is shifted from the light receiving surface of the light receiving unit 220, the pixel position where the digital signal Vcm changes differs (shifts) between the first pixel PnL and the second pixel PnR.
  • the shift directions of the digital signal Vcm are opposite to each other between the front-focused state and the rear-focused state.
  • the digital signal Vcm of the second pixel PnR is shifted in the direction indicated by the dashed arrow A1 in FIG. 10A with respect to the digital signal Vcm of the first pixel PnL.
  • the relative deviation amount between the digital signal Vcm of the first pixel PnL and the digital signal Vcm of the second pixel PnR is 8 digits.
  • the digital signal Vcm of the first pixel PnL is shifted in the direction indicated by the dashed arrow A2 in FIG. 12A with respect to the digital signal Vcm of the second pixel PnR.
  • the relative deviation amount between the digital signal Vcm of the first pixel PnL and the digital signal Vcm of the second pixel PnR is 8 digits.
  • the shift direction of the digital signals Vcm of the first and second pixels PnL and PnR indicates the shift direction of the focal position F with respect to the light receiving surface of the light receiving unit 220
  • the shift amount of the digital signal Vcm shows the amount of deviation of the focal position F with respect to the light receiving surface of .
  • the control unit 130 reduces the distance between the imaging lens 110 and the light receiving unit 220 according to the deviation direction A1 of the digital signals Vcm of the first and second pixels PnL and PnR.
  • the imaging lens 110 or the light receiving unit 220 is moved so as to move.
  • the control unit 130 moves the imaging lens 110 or the light receiving unit 220 by a predetermined distance according to the shift amount (for example, 8 digits) of the digital signals Vcm of the first and second pixels PnL and PnR.
  • the control unit 130 adjusts the focus position F so that the digital signals of the first and second pixels PnL and PnR are approximately the same.
  • control unit 130 can align focal position F with the light receiving surface of light receiving unit 220, and the front focus state of photodetector 200 can be brought into focus. can.
  • the control unit 130 increases the distance between the imaging lens 110 and the light receiving unit 220 in accordance with the shift direction A2 of the digital signals Vcm of the first and second pixels PnL and PnR. Then, the imaging lens 110 or the light receiving section 220 is moved. At this time, the control unit 130 moves the imaging lens 110 or the light receiving unit 220 by a predetermined distance according to the shift amount (for example, 8 digits) of the digital signals Vcm of the first and second pixels PnL and PnR. Accordingly, the control unit 130 adjusts the focus position F so that the digital signals of the first and second pixels PnL and PnR are approximately the same. As a result, as shown in FIGS. 11A and 11B, the control unit 130 can align the focal point F with the light receiving surface of the light receiving unit 220, and the rear focus state of the photodetector 200 can be brought into focus. can.
  • the shift amount for example, 8 digits
  • the correspondence relationship between the shift direction (A1 or A2) of the digital signal Vcm and the moving direction of the imaging lens 110 or the light receiving unit 220 is known in advance. Therefore, the information of the correspondence relation should be stored in advance in the memory 131 in the control unit 130 shown in FIG. Also, the correspondence relationship between the shift amount of the digital signal Vcm (the number of digits of the digital value) and the movement distance of the imaging lens 110 or the light receiving unit 220 is known in advance. Therefore, the information of the corresponding relationship may also be stored in the memory 131 in advance.
  • the moving direction and moving distance of the imaging lens 110 or the light receiving unit 220 are uniquely determined according to the shift direction and shift amount of the digital signals Vcm of the first and second pixels PnL and PnR. Therefore, the control unit 130 does not need to move the position of the imaging lens 110 or the light receiving unit 220 by trial and error in order to specify the position of the focused state, and can specify the position of the focused state in a short time. be able to.
  • the first pixel PnL with one half of the light shielded and the second pixel PnR with the other half of the light shielded are arranged adjacent to each other.
  • PnR to adjust the focal position F of the incident light based on the digital signal Vcm corresponding to each photocurrent Ipd.
  • the control unit 130 determines the shift direction and shift amount of the focal position F from the arrangement of the digital signals Vcm from the first pixels PnL and the arrangement of the digital signals Vcm from the second pixels PnR.
  • the shift direction and shift amount of the focal position F are the relative shift direction (A1 or A2) and shift amount ( The number of digits of the digital signal Vcm) can be uniquely determined.
  • the control unit 130 adjusts the focal position so that the arrangement of the digital signals Vcm from the first pixels PnL and the arrangement of the digital signals Vcm from the second pixels PnR are substantially the same, thereby setting the focal position F on the light receiving unit 220. It can be adapted to the light receiving surface. Thereby, the control section 130 can easily focus the incident light on the light receiving surface of the light receiving section 220 . That is, according to this embodiment, the on-field phase difference AF function can be easily applied to the EVS.
  • the photodetector 200 apart from the current-voltage conversion circuit 310, the luminance circuit 360 that outputs the luminance signal Vcp from the photocurrent Ipd, and the AD conversion circuit that AD-converts the luminance signal Vcp to generate the digital signal Vcm. 370 are provided.
  • the photodetector 200 can perform the image plane phase difference AF function simultaneously with the operation of the EVS.
  • the photodetector 200 allows the luminance circuit 360 and the AD conversion circuit 370 to perform the image plane phase difference AF function even when no luminance change event occurs in the EVS.
  • the reference voltage Vref in FIG. 7 may be a predetermined voltage.
  • the reference voltage Vref may not be appropriate, such as when the current Ipda is always lower than the reference current Iref, or when the current Ipda is always higher than the reference current Iref.
  • the digital signals Vcm shown in FIGS. 10B, 11B, and 12B are all "0" or all "1" for both the first and second pixels PnL and PnR. Therefore, control unit 130 cannot perform the on-image plane phase difference AF function.
  • the reference voltage Vref is made variable.
  • the control unit 130 changes the reference voltage Vref stepwise or continuously to adjust the reference current Iref.
  • FIG. 12C is a flowchart showing the operation of the photodetector 200 according to the modification.
  • the signal processing circuit 240 acquires the digital signal Vcm of each of the first and second pixels PnL and PnR (S10).
  • the control unit 130 determines whether the image plane phase difference AF function can be executed using the arrangement of the digital signals Vcm (S20). For example, when the digital signal Vcm is biased toward one logic in the first and second pixels PnL and PnR, the control unit 130 controls the ratio of "0" and "1" in the arrangement of the digital signal Vcm to be approximately half.
  • the reference voltage Vref is set so that Of course, the ratio of "0" and "1" in the digital signal Vcm is not limited to half, and may be a ratio within a predetermined range.
  • the control unit 130 adjusts the reference voltage Vref (S30).
  • the change direction of the reference voltage Vref is determined based on the digital signal Vcm. For example, when the digital signal Vcm is biased toward "0", it is determined that the reference current Iref is too high, and the control section 130 reduces the reference voltage Vref. On the other hand, when the digital signal Vcm is biased toward "1", it is determined that the reference current Iref is too low, and the control section 130 increases the reference voltage Vref. Thus, the reference voltage Vref is adjusted and steps S10 and S20 are executed again.
  • the control unit 130 executes the image plane phase difference AF function. That is, the control unit 130 compares the arrangement of the digital signals Vcm of the first and second pixels PnL and PnR to calculate the shift direction and amount of the focus position F (S40). Next, the control unit 130 calculates the moving direction and moving amount of the imaging lens 110 or the light receiving unit 220 based on the shifting direction and shifting amount of the focal position F (S50). Next, control unit 130 moves imaging lens 110 or light receiving unit 220 according to the calculated movement direction and movement amount (S60). Thereby, the focal position F fits the light receiving surface of the light receiving unit 220 .
  • the photodetector 200 performs imaging (S70).
  • the photodetector 200 can appropriately perform the image plane phase difference AF function after appropriately adjusting the reference voltage Vref.
  • FIG. 13 is a plan view showing the arrangement of the first pixels PnL, the second pixels PnR and the normal pixels 222 of the light receiving section 220 according to the second embodiment.
  • the first and second pixels PnL and PnR are intermittently and substantially evenly arranged in an arbitrary pixel row. Adjacent first and second pixels PnL and PnR may be adjacent with the normal pixel 222 interposed therebetween as shown in FIG. 13, or may be adjacent so as to be in contact with each other.
  • the pixel row is used to perform the image plane phase difference AF function described with reference to FIGS. 10A to 12B. can be executed.
  • first and second pixels PnL and PnR may be intermittently and substantially evenly arranged in any pixel column.
  • the arrangement of the first and second pixels PnL and PnR is not limited to FIG. 13, and may be arbitrary as long as the arrangement of the digital signals Vcm shown in FIGS. 10B, 11B, and 12B can be obtained.
  • FIG. 14 is a plan view showing the arrangement of the first pixels PnL, the second pixels PnR and the normal pixels 222 of the light receiving section 220 according to the third embodiment.
  • the first and second pixels PnL and PnR adjacent to each other and the normal pixel 222 are composed of the same pixels. Therefore, approximately half of the normal pixels 222 on one side are used as the first pixels PnL, and approximately half of the normal pixels 222 on the other side are used as the second pixels PnR.
  • the normal pixel 222 photoelectrically converts incident light received from the entire surface.
  • the on-chip lens OCL is provided corresponding to each normal pixel 222 . Accordingly, the adjacent first and second pixels PnL and PnR provided in one normal pixel 222 correspond to one on-chip lens OCL.
  • the normal pixel 222 can also function as a pixel for detecting each color of RGB, and can also be used as the first and second pixels PnL and PnR for the image plane phase difference AF function.
  • the normal pixel 222 is used for the image plane phase difference AF function as the first and second pixels PnL and PnR.
  • the normal pixels 222 are used as the EVS for imaging processing.
  • FIG. 15 to 17 are circuit diagrams showing configuration examples of the photodetector 200 according to the fourth embodiment. 15 to 17 show specific examples of the light receiving chip 201 and the detection chip 202 shown in FIG.
  • the photodiodes 221 constituting the first and second pixels PnL and PnR and the normal pixels 222, that is, the light receiving section 220, are configured by one semiconductor chip as the light receiving chip 201.
  • FIG. Other configurations of the address event detection circuit 300 are configured as other semiconductor chips as the detection chip 202.
  • FIG. The photodetector 200 is configured such that a light receiving chip 201 and a detection chip 202 are stacked as shown in FIG.
  • the area of the photodiode 221 can be increased, and the amount of light received can be increased.
  • the photodiode 221, the conversion transistor 311, the voltage supply transistor 314 and the capacitor 312 are composed of one semiconductor chip as the light receiving chip 201. That is, the N-type MOS transistors 311 and 314 and the capacitor 312 of the current-voltage conversion circuit 310 are provided on the light receiving chip 201 .
  • Other configurations of the address event detection circuit 300 (current source transistor 313, luminance circuit 360, AD conversion circuit 370, etc.) are configured as other semiconductor chips as the detection chip 202.
  • the N-type MOS transistors 311 and 314 in the light-receiving chip 201, it is possible to lay out the detection chip 202 even if the circuit scale of the detection chip 202 is increased. That is, the area efficiency of the light receiving chip 201 and the detection chip 202 can be improved.
  • the photodiode 221 and the address event detection circuit 300 are composed of one semiconductor chip as the light receiving chip 201.
  • a subsequent signal processing circuit 240 (FIG. 4) connected to the voltage signal Vout is configured in another semiconductor chip as the detection chip 202 .
  • the entire address event detection circuit 300 in the light receiving chip 201 even if the circuit scale of the signal processing circuit 240 becomes large, it can be configured with the light receiving chip 201 and the detection chip 202. That is, the area efficiency of the light receiving chip 201 and the detection chip 202 can be improved.
  • FIG. 18 is a circuit diagram showing a configuration example of the photodetector 200 according to the fifth embodiment.
  • the AD conversion circuit 380 AD-converts the voltage signal Vout output from the current-voltage conversion circuit 310 to generate the digital signal Vcm. Therefore, the current-voltage conversion circuit 310 also functions as the luminance circuit 360 .
  • the first and second luminance circuits 360 each have the same configuration as the current-voltage conversion circuit 310, and output the voltage signal Vout as the luminance signal Vcp.
  • the AD conversion circuit 380 is connected with the output signal line 316 .
  • the AD conversion circuit 380 AD-converts the voltage signal Vout into a digital signal Vcm using the voltage signal Vout as the luminance signal Vcp.
  • Other configurations and operations of current-voltage conversion circuit 310 are similar to those of FIG. Therefore, the fifth embodiment can obtain the same effect as the first embodiment.
  • the voltage signal Vout is used as the luminance signal Vcp, and the luminance signal Vcp is not generated from the photocurrent Ipd, so the conversion transistor 361 can be omitted. Therefore, the circuit scale of the address event detection circuit 300 can be reduced.
  • FIG. 19 is a circuit diagram showing a configuration example of the photodetector 200 according to the sixth embodiment.
  • the AD conversion circuit 380 AD-converts the voltage of the input signal line 315 as the luminance signal Vcp to generate the digital signal Vcm. Therefore, the current-voltage conversion circuit 310 also functions as the luminance circuit 360 .
  • the first and second luminance circuits 360 each have the same configuration as the current-voltage conversion circuit 310, and output the voltage of the input signal line 315 as the luminance signal Vcp.
  • the AD conversion circuit 380 AD-converts the input signal line 315 into a digital signal Vcm using the voltage of the input signal line 315 as the luminance signal Vcp.
  • Other configurations and operations of current-voltage conversion circuit 310 are similar to those of FIG. Therefore, the sixth embodiment can obtain the same effect as the first embodiment.
  • the voltage of the input signal line 315 is used as the luminance signal Vcp, and the luminance signal Vcp is not generated from the photocurrent Ipd, so the conversion transistor 361 can be omitted. Therefore, the circuit scale of the address event detection circuit 300 can be reduced.
  • the technology (this technology) according to the present disclosure can be applied to various products.
  • the technology according to the present disclosure can be realized as a device mounted on any type of moving body such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility, airplanes, drones, ships, and robots. may
  • FIG. 20 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology according to the present disclosure can be applied.
  • a vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001.
  • the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside information detection unit 12030, an inside information detection unit 12040, and an integrated control unit 12050.
  • a microcomputer 12051, an audio/image output unit 12052, and an in-vehicle network I/F (Interface) 12053 are illustrated.
  • the drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs.
  • the driving system control unit 12010 includes a driving force generator for generating driving force of the vehicle such as an internal combustion engine or a driving motor, a driving force transmission mechanism for transmitting the driving force to the wheels, and a steering angle of the vehicle. It functions as a control device such as a steering mechanism to adjust and a brake device to generate braking force of the vehicle.
  • the body system control unit 12020 controls the operation of various devices equipped on the vehicle body according to various programs.
  • the body system control unit 12020 functions as a keyless entry system, a smart key system, a power window device, or a control device for various lamps such as headlamps, back lamps, brake lamps, winkers or fog lamps.
  • body system control unit 12020 can receive radio waves transmitted from a portable device that substitutes for a key or signals from various switches.
  • the body system control unit 12020 receives the input of these radio waves or signals and controls the door lock device, power window device, lamps, etc. of the vehicle.
  • the vehicle exterior information detection unit 12030 detects information outside the vehicle in which the vehicle control system 12000 is installed.
  • the vehicle exterior information detection unit 12030 is connected with an imaging section 12031 .
  • the vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image of the exterior of the vehicle, and receives the captured image.
  • the vehicle exterior information detection unit 12030 may perform object detection processing or distance detection processing such as people, vehicles, obstacles, signs, or characters on the road surface based on the received image.
  • the imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of received light.
  • the imaging unit 12031 can output the electric signal as an image, and can also output it as distance measurement information.
  • the light received by the imaging unit 12031 may be visible light or non-visible light such as infrared rays.
  • the in-vehicle information detection unit 12040 detects in-vehicle information.
  • the in-vehicle information detection unit 12040 is connected to, for example, a driver state detection section 12041 that detects the state of the driver.
  • the driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 detects the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041. It may be calculated, or it may be determined whether the driver is dozing off.
  • the microcomputer 12051 calculates control target values for the driving force generator, the steering mechanism, or the braking device based on the information inside and outside the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and controls the drive system control unit.
  • a control command can be output to 12010 .
  • the microcomputer 12051 realizes ADAS (Advanced Driver Assistance System) functions including collision avoidance or shock mitigation, follow-up driving based on inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, or vehicle lane deviation warning. Cooperative control can be performed for the purpose of ADAS (Advanced Driver Assistance System) functions including collision avoidance or shock mitigation, follow-up driving based on inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, or vehicle lane deviation warning. Cooperative control can be performed for the purpose of ADAS (Advanced Driver Assistance System) functions including collision avoidance or shock mitigation, follow-up driving based on inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, or vehicle
  • the microcomputer 12051 controls the driving force generator, the steering mechanism, the braking device, etc. based on the information about the vehicle surroundings acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, so that the driver's Cooperative control can be performed for the purpose of autonomous driving, etc., in which vehicles autonomously travel without depending on operation.
  • the microcomputer 12051 can output a control command to the body system control unit 12030 based on the information outside the vehicle acquired by the information detection unit 12030 outside the vehicle.
  • the microcomputer 12051 controls the headlamps according to the position of the preceding vehicle or the oncoming vehicle detected by the vehicle exterior information detection unit 12030, and performs cooperative control aimed at anti-glare such as switching from high beam to low beam. It can be carried out.
  • the audio/image output unit 12052 transmits at least one of audio and/or image output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle.
  • an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are illustrated as output devices.
  • the display unit 12062 may include at least one of an on-board display and a head-up display, for example.
  • FIG. 21 is a diagram showing an example of the installation position of the imaging unit 12031.
  • the imaging unit 12031 has imaging units 12101, 12102, 12103, 12104, and 12105.
  • the imaging units 12101, 12102, 12103, 12104, and 12105 are provided at positions such as the front nose, side mirrors, rear bumper, back door, and windshield of the vehicle 12100, for example.
  • An image pickup unit 12101 provided in the front nose and an image pickup unit 12105 provided above the windshield in the passenger compartment mainly acquire images in front of the vehicle 12100 .
  • Imaging units 12102 and 12103 provided in the side mirrors mainly acquire side images of the vehicle 12100 .
  • An imaging unit 12104 provided in the rear bumper or back door mainly acquires an image behind the vehicle 12100 .
  • the imaging unit 12105 provided above the windshield in the passenger compartment is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, and the like.
  • FIG. 21 shows an example of the imaging range of the imaging units 12101 to 12104.
  • the imaging range 12111 indicates the imaging range of the imaging unit 12101 provided in the front nose
  • the imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided in the side mirrors, respectively
  • the imaging range 12114 The imaging range of an imaging unit 12104 provided in the rear bumper or back door is shown. For example, by superimposing the image data captured by the imaging units 12101 to 12104, a bird's-eye view image of the vehicle 12100 viewed from above can be obtained.
  • At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information.
  • at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.
  • the microcomputer 12051 determines the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and changes in this distance over time (relative velocity with respect to the vehicle 12100). , it is possible to extract, as the preceding vehicle, the closest three-dimensional object on the traveling path of the vehicle 12100, which runs at a predetermined speed (for example, 0 km/h or more) in substantially the same direction as the vehicle 12100. can. Furthermore, the microcomputer 12051 can set the inter-vehicle distance to be secured in advance in front of the preceding vehicle, and perform automatic brake control (including following stop control) and automatic acceleration control (including following start control). In this way, cooperative control can be performed for the purpose of automatic driving in which the vehicle runs autonomously without relying on the operation of the driver.
  • automatic brake control including following stop control
  • automatic acceleration control including following start control
  • the microcomputer 12051 converts three-dimensional object data related to three-dimensional objects to other three-dimensional objects such as motorcycles, ordinary vehicles, large vehicles, pedestrians, and utility poles. It can be classified and extracted and used for automatic avoidance of obstacles. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into those that are visible to the driver of the vehicle 12100 and those that are difficult to see. Then, the microcomputer 12051 judges the collision risk indicating the degree of danger of collision with each obstacle, and when the collision risk is equal to or higher than the set value and there is a possibility of collision, an audio speaker 12061 and a display unit 12062 are displayed. By outputting an alarm to the driver via the drive system control unit 12010 and performing forced deceleration and avoidance steering via the drive system control unit 12010, driving support for collision avoidance can be performed.
  • At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays.
  • the microcomputer 12051 can recognize a pedestrian by determining whether or not the pedestrian exists in the captured images of the imaging units 12101 to 12104 .
  • recognition of a pedestrian is performed by, for example, a procedure for extracting feature points in images captured by the imaging units 12101 to 12104 as infrared cameras, and performing pattern matching processing on a series of feature points indicating the outline of an object to determine whether or not the pedestrian is a pedestrian.
  • the audio image output unit 12052 outputs a rectangular outline for emphasis to the recognized pedestrian. is superimposed on the display unit 12062 . Also, the audio/image output unit 12052 may control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.
  • the imaging apparatus 100 according to the present disclosure can be applied to, for example, the imaging unit 12031 among the configurations described above.
  • this technique can take the following structures. (1) a plurality of first pixels photoelectrically converting incident light from one side portion to generate a first current; a plurality of second pixels photoelectrically converting the incident light from a portion opposite to the portion of the first pixel to generate a second current; a plurality of first luminance circuits provided corresponding to each of the plurality of first pixels and generating a first luminance signal corresponding to the first current; a plurality of second luminance circuits provided corresponding to each of the plurality of second pixels and generating a second luminance signal corresponding to the second current; a plurality of first current comparison circuits provided corresponding to each of the plurality of first pixels, comparing the first luminance signal with a reference signal and converting the first luminance signal into a first digital signal; a plurality of second current comparison circuits provided corresponding to each of the plurality of second pixels, comparing the second luminance signal with the reference signal, and converting the second luminance signal into a second digital signal; and a control unit that adjust
  • a plurality of first current-voltage conversion circuits provided corresponding to each of the plurality of first pixels and generating a first voltage signal corresponding to the first current; (1) to (4), further comprising: a plurality of second current-voltage conversion circuits provided corresponding to each of the plurality of second pixels and generating a second voltage signal corresponding to the second current;
  • the first current-voltage conversion circuit is a first conversion transistor that converts the first current into a first voltage signal and outputs the first voltage signal from a first gate; a first current source transistor that supplies a predetermined constant current to a first output signal line connected to the first gate; a first voltage supply transistor that supplies a constant voltage corresponding to the predetermined constant current from the first output signal line to the source of the first conversion transistor;
  • the second current-voltage conversion circuit is a second conversion transistor that converts the second current into a second voltage signal and outputs the second voltage signal from a second gate; a second current source transistor that supplies a predetermined constant current to a second output signal line connected to the second gate;
  • the photodetector according to (5) further comprising a second voltage supply transistor that supplies a constant voltage corresponding to the predetermined constant current from the second output signal line to the source of the second conversion transistor.
  • the first luminance circuit is a third conversion transistor that converts the first current into a third voltage signal and outputs the third voltage signal from the gate;
  • the second luminance circuit is a fourth conversion transistor for converting the second current into a fourth voltage signal and outputting it from the gate;
  • the first current comparator circuit a third current source transistor connected between a high voltage source and a first output, having a gate connected to the gate of the third conversion transistor and flowing a third current according to the first current; a first reference current transistor connected between the first output and a low voltage source, having a gate receiving the reference signal and passing a first reference current according to the reference signal;
  • the second current comparator circuit a fifth current source transistor connected between the high voltage source and the second output, having a gate connected to the gate of the fourth conversion transistor, and supplying a fifth current corresponding to the second current;
  • a second reference current transistor connected between the second output and the low voltage source, having a gate receiving the reference signal and passing a second reference current according to the reference signal;
  • the first current comparing circuit outputs a first digital signal from the first output; when the third current is smaller than the first reference current, the first current comparison circuit outputs a second digital signal having a logic opposite to the first digital signal from the first output section; if the fifth current is greater than the second reference current, the second current comparison circuit outputs the first digital signal from the second output;
  • a photodetector device according to (7) or (8), further comprising a second buffer connected to the second output.
  • (10) further comprising a plurality of third pixels photoelectrically converting the incident light received on the entire surface to generate a third current; Any one of (1) to (9), wherein the plurality of first pixels and the plurality of second pixels are arranged adjacent to the plurality of third pixels and are arranged alternately and substantially evenly. 3.
  • the photodetector according to . (11) a first semiconductor chip including the first and second pixels; a second semiconductor chip including the first and second current-voltage conversion circuits; the first and second luminance circuits; and the first and second current comparison circuits.
  • the photodetector according to (5) or (6) which is configured by stacking semiconductor chips.
  • a first semiconductor chip including the plurality of first and second pixels, the first and second conversion transistors, and the first and second voltage supply transistors; the first and second current source transistors; , a second luminance circuit, and a second semiconductor chip including the first and second current comparator circuits are stacked.
  • the plurality of first and second pixels, the first and second current-voltage conversion circuits, the first and second luminance circuits, and the first and second current comparison circuits are composed of one semiconductor chip.
  • the first luminance circuit is a first conversion transistor that converts the first current into a first voltage signal and outputs the first voltage signal from a first gate; a first current source transistor that supplies a predetermined constant current to a first output signal line connected to the first gate; a first voltage supply transistor that supplies a constant voltage corresponding to the predetermined constant current from the first output signal line to the source of the first conversion transistor;
  • the second luminance circuit is a second conversion transistor that converts the second current into a second voltage signal and outputs the second voltage signal from a second gate; a second current source transistor that supplies a predetermined constant current to a second output signal line connected to the second gate; a second voltage supply transistor that supplies a constant voltage corresponding to the predetermined constant current from the second output signal line to the source of the second conversion transistor;
  • the first current comparison circuit converts the first voltage signal into the first digital signal as the first luminance signal, The photodetector according to any one of (1) to (4), wherein the second current comparison circuit converts the second voltage signal as the
  • the first luminance circuit is a first conversion transistor that converts the first current into a first voltage signal and outputs the first voltage signal from a first gate; a first current source transistor that supplies a predetermined constant current to a first output signal line connected to the first gate; a first voltage supply transistor that supplies a constant voltage corresponding to the predetermined constant current from the first output signal line to the source of the first conversion transistor;
  • the second luminance circuit is a second conversion transistor that converts the second current into a second voltage signal and outputs the second voltage signal from a second gate; a second current source transistor that supplies a predetermined constant current to a second output signal line connected to the second gate; a second voltage supply transistor that supplies a constant voltage corresponding to the predetermined constant current from the second output signal line to the source of the second conversion transistor;
  • the first current comparison circuit converts the gate voltage of the first voltage supply transistor into the first digital signal as the first luminance signal, The light detection according to any one of (1) to (4), wherein the second current comparison circuit converts the gate voltage of

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  • Engineering & Computer Science (AREA)
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  • Signal Processing (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)
PCT/JP2022/042169 2022-01-06 2022-11-14 光検出装置 Ceased WO2023132129A1 (ja)

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JP2021093610A (ja) * 2019-12-10 2021-06-17 ソニーセミコンダクタソリューションズ株式会社 固体撮像素子、および、撮像装置

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