WO2023130565A1 - 寄生参数的获取方法以及设备 - Google Patents

寄生参数的获取方法以及设备 Download PDF

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Publication number
WO2023130565A1
WO2023130565A1 PCT/CN2022/079774 CN2022079774W WO2023130565A1 WO 2023130565 A1 WO2023130565 A1 WO 2023130565A1 CN 2022079774 W CN2022079774 W CN 2022079774W WO 2023130565 A1 WO2023130565 A1 WO 2023130565A1
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Prior art keywords
signal line
parasitic
circuit
target
layout
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English (en)
French (fr)
Inventor
尤劭
唐佩佩
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2115/00—Details relating to the type of the circuit
    • G06F2115/12—Printed circuit boards [PCB] or multi-chip modules [MCM]

Definitions

  • the present disclosure relates to but is not limited to a method and device for acquiring parasitic parameters.
  • Chip design can usually be divided into logical design and physical design, that is, circuit schematic design and layout design.
  • the former obtains the gate-level netlist circuit of the chip, which is an idealized circuit model.
  • the latter generates GDSII data for manufacturing through place-and-route and physical verification.
  • the layout contains a large number of physical parameter features, such as parasitic capacitance and parasitic resistance, and these physical parameter features will have a greater impact on the function and performance of the circuit. Therefore, accurate acquisition of these physical parameters is very important for the chip design and manufacturing process.
  • An embodiment of the present disclosure provides a method for acquiring parasitic parameters, the method is applied to a server, and the method includes:
  • the parasitic parameters of the signal lines of the target circuit are determined according to the structure information of the parasitic resistance and/or capacitance network of the signal lines of the target layout.
  • the parasitic parameters of the target circuit signal line are determined according to the structure information of the parasitic resistance and/or capacitance network of the target layout signal line, specifically including:
  • the equivalent resistance and/or equivalent capacitance of the equivalent circuit is calculated by constructing an equivalent circuit , it does not need to be calculated directly based on complex structural information, which can simplify the calculation process.
  • the power supply input terminal of the equivalent circuit is determined, and the excitation current at the power supply input terminal is detected when the excitation voltage is provided to the power supply input terminal;
  • the equivalent resistance when calculating the equivalent resistance value of the equivalent circuit, the equivalent resistance can be calculated according to the excitation and response value by providing excitation for the equivalent circuit and obtaining the response value of the equivalent circuit under the excitation, without The impedance of multiple resistors and/or capacitors in the equivalent circuit is used to calculate the equivalent resistance value, which can simplify the calculation process.
  • the structural information of the parasitic resistance and/or capacitance network includes the capacitance of at least one parasitic capacitance; the parasitic parameters of the target circuit signal line are determined according to the parasitic resistance and/or structural information of the capacitance network of the signal line of the target layout, Specifically include:
  • the total capacitance obtained by superimposing the capacitance of at least one parasitic capacitance is taken as the capacitance of the equivalent parasitic capacitance of the signal line of the target circuit.
  • the parasitic parameter of the signal line of the target circuit is the capacitance of the equivalent parasitic capacitance of the signal line of the target circuit
  • the parasitic resistance of the signal line of the target layout and/or the capacitance of several parasitic capacitances in the capacitance network are extracted, The capacitance of several parasitic capacitors is superimposed and used as the capacitance of the equivalent parasitic capacitor.
  • the target layout signal line is determined according to the position of the target circuit signal line in the target circuit module and the layout corresponding to the circuit schematic diagram, specifically including:
  • the target layout signal line is a layout signal line corresponding to the target circuit signal line in the layout.
  • the target layout signal line is determined according to the position of the target circuit signal line in the target circuit module and the layout corresponding to the circuit schematic diagram, specifically including:
  • the target layout signal line is a layout signal line located outside the target circuit module in the layout and connected to the input port or output port connected to the target circuit signal line .
  • the target layout signal line corresponding to the target circuit signal line it is determined based on the positional relationship of the target circuit signal line in the target circuit module. Since the signal line inside the target circuit module is not connected to the external signal line, there is no need to consider the influence of other circuit modules on the target circuit signal line, so the target layout signal line of the target circuit signal line is the corresponding layout of the target circuit signal line in the layout signal line. Since the port signal line of the target circuit module is connected to the external signal line, when determining the signal line of the target layout, the layout is located outside the target circuit module and connected to the input port or output port connected to the target circuit signal line inside the layout The signal line is used as the signal line of the target layout. Taking into account the influence of other circuit modules on the signal line, and then calculating the parasitic parameters based on the signal line of the target layout, the accuracy of the parasitic parameters can be improved.
  • obtaining the position of the target circuit signal line in the circuit schematic diagram in the target circuit module specifically includes:
  • the position of the target circuit signal line in the target circuit module is determined according to the identification of the target circuit signal line and the locally stored position relationship table.
  • the method before extracting the structural information of the parasitic resistance and/or capacitance network of the target layout signal line from the locally stored layout parasitic netlist, the method further includes:
  • the client receives an upload request sent by the client, wherein the upload request includes a parasitic netlist of a layout corresponding to the circuit schematic diagram;
  • the parasitic netlist of the layout corresponding to the circuit schematic diagram is stored locally.
  • the method further includes:
  • the parasitic parameters of each target circuit signal line can be graphically displayed, so as to achieve more intuitive marking of the parasitic parameters in the circuit schematic.
  • Another embodiment of the present disclosure provides a method for acquiring parasitic parameters, the method is applied to a client, and the method includes:
  • the parameter acquisition request is used to determine the position of the target circuit signal line in the circuit schematic diagram in the target circuit module, the position of the target circuit signal line in the target circuit module and the layout corresponding to the circuit schematic diagram
  • the parasitic netlist of the target layout signal line and the locally stored layout is used to determine the structure information of the parasitic resistance and/or capacitance network of the target layout signal line; the parasitic resistance and/or capacitance network of the target layout signal line
  • the structural information of the capacitive network is used to determine the parasitic parameters of the signal lines of the target circuit.
  • the method also includes:
  • An upload request is sent to the server, wherein the upload request is used to make the server store the parasitic netlist of the layout locally.
  • the method also includes:
  • a server including: a processor, and a memory communicatively connected to the processor;
  • the memory stores computer-executable instructions
  • the processor executes the computer-executed instructions stored in the memory, so as to realize the method for acquiring parasitic parameters provided in the foregoing embodiments.
  • Yet another embodiment of the present disclosure provides a client, including: a processor, and a memory communicatively connected to the processor;
  • the memory stores computer-executable instructions
  • the processor executes the computer-executed instructions stored in the memory, so as to realize the method for acquiring parasitic parameters provided in the foregoing embodiments.
  • Another embodiment of the present disclosure provides a computer-readable storage medium.
  • Computer-executable instructions are stored in the computer-readable storage medium. When the computer-executable instructions are executed by a processor, they are used to implement the parasitic parameter acquisition method provided by the above-mentioned embodiments.
  • the parasitic parameter acquisition method and device acquire the position of the target circuit signal line in the target circuit module, so as to determine the target layout according to the position of the target circuit signal line in the target circuit module and the layout corresponding to the circuit schematic diagram signal line, and then obtain the structure information of the parasitic resistance and/or capacitance network of the signal line of the target layout based on the parasitic netlist of the layout, so as to determine the structure information of the signal line of the target circuit according to the structure information of the parasitic resistance and/or capacitance network of the signal line of the target layout parasitic parameters.
  • the present disclosure can automatically output the parasitic parameters of the signal lines, and the efficiency is higher.
  • the calculation process can be simplified by extracting the structure information of the parasitic resistance and/or capacitance network of the target layout signal line, and then calculating the parasitic parameters based on the structure information.
  • FIG. 1 is a schematic structural diagram of a parameter acquisition system provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic flowchart of a method for obtaining parasitic parameters according to another embodiment of the present disclosure
  • FIG. 3 is a circuit schematic diagram provided by an embodiment of the present disclosure.
  • FIG. 4 is a schematic flowchart of a method for obtaining parasitic parameters according to another embodiment of the present disclosure
  • FIG. 5 is a schematic flowchart of a method for obtaining parasitic parameters according to another embodiment of the present disclosure
  • FIG. 6 is a schematic diagram of a parasitic netlist provided by another embodiment of the present disclosure.
  • FIG. 7 is a user interface diagram provided by another embodiment of the present disclosure.
  • FIG. 8 is a schematic circuit schematic diagram of module A where the signal line of the target circuit is located according to another embodiment of the present disclosure
  • FIG. 9 is a schematic diagram of structural information of a parasitic resistance and/or capacitance network provided by another embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of an equivalent circuit provided by another embodiment of the present disclosure.
  • FIG. 11 is a schematic diagram of a marked circuit principle diagram provided by another embodiment of the present disclosure.
  • FIG. 12 is a schematic diagram of a report file provided by another embodiment of the present disclosure.
  • FIG. 13 is a schematic structural diagram of an acquisition device provided by another embodiment of the present disclosure.
  • Fig. 14 is a schematic structural diagram of an acquisition device provided by yet another embodiment of the present disclosure.
  • FIG. 15 is a schematic structural diagram of a server provided by another embodiment of the present disclosure.
  • Fig. 16 is a schematic structural diagram of a client provided by another embodiment of the present disclosure.
  • circuit design engineers usually need to track the parasitic capacitance and/or parasitic resistance value of some abnormal signal lines in the circuit, and judge the parasitic effect by the parasitic parameter values of these parasitic devices The impact on the circuit, and then improve, optimize and perfect the circuit.
  • the parasitic parameter acquisition method and equipment provided by the embodiments of the present disclosure firstly determine the target layout signal line corresponding to the target circuit signal line according to the position of the target circuit signal line in the target circuit module, and then determine the corresponding target layout signal line from the layout Extract the structure information of the parasitic resistance and/or capacitance network of the signal line of the target layout from the parasitic netlist of the target layout, so as to determine the parasitic parameters of the signal line of the target circuit based on the structure information, and back-label the parasitic parameters of the signal line of the target circuit to the circuit principle
  • it is used for circuit design engineers to debug, verify or optimize circuit design to meet the higher requirements faced by current chip design.
  • an embodiment of the present disclosure provides a parameter acquisition system, and the parameter acquisition system includes a server 100 and a client 200 .
  • the client 200 is used to initiate a parasitic parameter acquisition request to the server 100.
  • the server 100 obtains the target circuit signal line by analyzing the acquisition request, and determines the parasitic parameters of the target circuit signal line based on the locally stored parasitic netlist, and determines the target circuit signal line.
  • parasitic parameters For specific manners of parasitic parameters, reference may be made to the following embodiments, which will not be repeated here.
  • FIG. 2 another embodiment of the present disclosure provides a method for obtaining parasitic parameters.
  • the method for obtaining parasitic parameters is applied to a server.
  • the method for obtaining parasitic parameters specifically includes the following steps:
  • the schematic circuit diagram of a certain module D includes multiple circuit modules, for example: module A, module B, module C, . . . . Multiple circuit modules are connected to each other, and the specific interconnection relationship of each circuit module is determined according to the function to be realized in the circuit schematic diagram.
  • Each circuit module includes a plurality of sub-circuits and circuit signal lines connecting each sub-circuit, and also includes circuit signal lines for connecting with other circuit modules.
  • the sub-circuit I1, the sub-circuit I2, the sub-circuit I3, and the sub-circuit I4, the sub-circuit I1 to the sub-circuit I4 may be any one or a combination of inverters, AND gates, NOT gates, XOR gates and the like.
  • the circuit signal lines include a circuit signal line netB connecting the sub-circuit I1 and the sub-circuit I2, a circuit signal line netC connecting the sub-circuit I2 and the sub-circuit I3, and a circuit signal line netD connecting the sub-circuit I2 and the sub-circuit I4.
  • the circuit signal line also includes a circuit signal line netA connecting the input port 01 of the module A and the sub-circuit I1, and a circuit signal line netE connecting the output port 02 of the module A and the sub-circuit I3.
  • the target circuit signal line is a signal line inside the target circuit module. If the position of the target circuit signal line in the target circuit module includes the internal signal line and the port signal line.
  • the internal signal line refers to the circuit signal line that connects each sub-circuit in the target circuit module
  • the port signal line refers to the circuit signal line located inside the target circuit module and used to connect the target circuit module and other circuit modules.
  • the position of the target circuit signal line in the target circuit module is obtained by determining the function of the target circuit signal line.
  • the target circuit signal line is a circuit signal line for connecting each sub-circuit, then determine the position of the target circuit signal line in the target circuit module as an internal signal line. If the target circuit signal line is a circuit signal line for connecting the target circuit module and other circuit modules, then determine the position of the target circuit signal line in the target circuit module as the port signal line.
  • the layout corresponding to the circuit schematic diagram refers to the layout generated according to the circuit schematic diagram, and the internal sub-circuits and circuit signal lines of each circuit module in the circuit schematic diagram are reflected in the layout one by one.
  • the methods for determining the target layout signal lines are different. If the position of the target circuit signal line in the target circuit module is an internal signal line, the target layout signal line is a layout signal line corresponding to the target circuit signal line in the layout.
  • the target layout signal line is located outside the target circuit module in the layout and is connected to the input port or output port of the target circuit signal line in the target circuit module Connected layout signal lines.
  • the target circuit module is module A, which has two ports, which are sequentially marked as input port 01 and output port 02
  • the input port 01 of the target circuit module is connected to an output port 03 of module B
  • the target circuit module The output port 02 of the module is connected to an input port 04 of the module C.
  • the target circuit signal line is the port signal line netA connected to the input port 01 and connected to the module B through the input port 01
  • the target layout signal line is located outside the module A and set at the input port 01 of the module A and the output of the module B
  • the layout signal line corresponding to the circuit signal line netF between ports 03.
  • the target circuit signal line is the port signal line netE connected to the output port 02 and connected to the module C through the output port 02
  • the target layout signal line is located outside the module A and set on the output port 02 of the module A and the module
  • the circuit signal line netG between the input port 04 of C corresponds to the layout signal line.
  • the target circuit signal line is the circuit signal line netB connecting sub-circuit I1 and sub-circuit I2
  • the target layout signal The lines are sequentially the layout signal line corresponding to the circuit signal line netB, the layout signal line corresponding to the circuit signal line netC, and the layout signal line corresponding to the circuit signal line netD.
  • the parasitic resistance and/or parasitic capacitance network means that the network only includes parasitic resistance, the network only includes parasitic capacitance, or the network includes both parasitic resistance and parasitic capacitance.
  • the parasitic netlist of the layout includes the parasitic resistance value and/or parasitic capacitance value of the layout signal line between each sub-circuit, and the connection relationship between each parasitic resistance and/or parasitic capacitance and the sub-circuit in each circuit module.
  • the structure information of the parasitic resistance and/or capacitance network of the target layout signal line is obtained by extracting the relevant information of the parasitic capacitance and/or parasitic resistance associated with the target layout signal line in the parasitic netlist.
  • S104 Determine the parasitic parameters of the signal lines of the target circuit according to the structure information of the parasitic resistance and/or capacitance network of the signal lines of the target layout.
  • parameter calculation may be performed based on the structural information of the parasitic resistance and/or capacitance network to obtain the parasitic parameters of the target circuit signal line. It is also possible to build a parasitic circuit based on the structural information of the parasitic resistance and/or capacitance network, collect the response value of the parasitic circuit under the excitation of the excitation power supply, and calculate the parasitic parameters of the signal line of the target circuit based on the response value.
  • the positional relationship of the target circuit signal line in the target circuit module is determined, so as to determine the target layout signal line according to the position and the corresponding layout of the circuit schematic diagram, and then from the local Extract the structure information of the parasitic resistance and/or capacitance network of the signal line of the target layout from the stored parasitic net list of the layout, so as to determine the parasitic parameters of the signal line of the target circuit according to the structure information of the parasitic resistance and/or capacitance network.
  • this solution can accurately obtain the parasitic parameters of the signal line, and the efficiency is higher.
  • the calculation process can be simplified by extracting the structure information of the parasitic resistance and/or capacitance network of the target layout signal line, and then calculating the parasitic parameters based on the structure information.
  • FIG. 4 another embodiment of the present disclosure provides a parasitic parameter acquisition method.
  • the parasitic parameter acquisition method is applied to a parameter acquisition system.
  • the parasitic parameter acquisition method specifically includes the following steps:
  • the server receives an upload request sent by the client.
  • the client obtains the parasitic netlist of the layout corresponding to the circuit schematic diagram, and generates an upload request according to the parasitic netlist of the layout.
  • the server locally stores the parasitic netlist of the layout corresponding to the circuit schematic diagram.
  • the server parses the upload request to obtain the parasitic netlist of the layout corresponding to the circuit schematic diagram, and stores the parasitic netlist of the layout locally.
  • the server receives the parameter acquisition request sent by the client.
  • the client acquires the identification of the signal line of the target circuit, and generates a parameter acquisition request according to the identification of the signal line of the target circuit.
  • the user When acquiring the identification of the signal line of the target circuit, the user inputs the identification of the signal line of the target circuit through the user interface.
  • the server determines the position of the target circuit signal line in the target circuit module according to the identifier of the target circuit signal line and the locally stored position relationship table.
  • the position relationship table is used to indicate the correspondence between the identification of the circuit signal line and the position of the circuit signal line in the corresponding circuit module, and the position of the circuit signal line in the corresponding circuit module includes the internal signal line and the port signal line .
  • the position relationship table is searched using the identification of the target circuit signal line to obtain the position of the target circuit signal line in the target circuit module.
  • the server determines the target layout signal line according to the position of the target circuit signal line in the target circuit module and the layout corresponding to the circuit schematic diagram.
  • the target layout signal line is the layout signal line corresponding to the target circuit signal line in the layout. If the position of the target circuit signal line in the target circuit module is a port signal line, the target layout signal line is located outside the target circuit module in the layout and is connected to the input port or output port of the target circuit signal line in the target circuit module Connected layout signal lines.
  • the server extracts the structural information of the parasitic resistance and/or capacitance network of the target layout signal line from the locally stored layout parasitic netlist.
  • the structure information of the parasitic resistance and/or capacitance network of the target layout signal line is obtained by extracting the relevant information of the parasitic resistance and/or capacitance associated with the target layout signal line in the parasitic netlist.
  • the server determines the parasitic parameters of the signal line of the target circuit according to the structure information of the parasitic resistance and/or capacitance network of the signal line of the target layout.
  • the structural information of the parasitic resistance and/or capacitance network includes the capacitance of at least one parasitic capacitance in the parasitic resistance and/or capacitance network, and the parasitic parameters of the signal line of the target circuit are its total
  • the total capacitance obtained by superimposing the capacitance of at least one parasitic capacitance is taken as the capacitance of the parasitic capacitance of the signal line of the target circuit.
  • an equivalent circuit is built according to the structure information of the parasitic resistance and/or capacitance network of the target layout signal line, and the equivalent resistance and/or equivalent capacitance of the equivalent circuit are calculated to obtain the target circuit signal line parasitic parameters.
  • the equivalent resistance of the equivalent circuit determines the power input end of the equivalent circuit, and detect the excitation current at the power input end when the excitation voltage is supplied to the power input end, and then calculate the ratio of the excitation voltage to the excitation current , to obtain the equivalent resistance value of the equivalent circuit, and use the equivalent resistance value as the resistance value of the equivalent parasitic resistance of the signal line of the target circuit.
  • the server adds graphic data representing parasitic parameters of the target circuit signal line to the schematic circuit diagram, so as to generate graphic data corresponding to the marked circuit schematic diagram.
  • the server may mark the parasitic parameters of the signal line of the target circuit in the schematic circuit diagram, and display the parameters graphically.
  • the graphical data representing the parasitic parameters of the target circuit signal line is acquired, and the graphical data representing the parasitic parameters of the target circuit signal line is added to the schematic circuit diagram to obtain the graphical data corresponding to the marked circuit schematic diagram.
  • the client receives the response result sent by the server.
  • the server After obtaining the graphic data corresponding to the marked circuit schematic diagram, the server generates a response result according to the graphic data corresponding to the marked circuit schematic diagram, and sends the response result to the client.
  • the client terminal displays data corresponding to the marked circuit schematic diagram.
  • the client parses the response result to obtain the data corresponding to the marked circuit schematic diagram, and performs display processing on the data corresponding to the marked circuit schematic diagram, so as to realize The labeled circuit schematic is displayed on the user interface.
  • the equivalent resistance can be calculated according to the excitation and response value by providing excitation for the equivalent circuit and obtaining the response value of the equivalent circuit under the excitation, without the need to base on the equivalent circuit
  • the impedance of multiple parasitic resistors is then calculated as the equivalent resistance value, which can simplify the calculation process.
  • the target layout signal line corresponding to the target circuit signal line it is determined based on the positional relationship of the target circuit signal line in the target circuit module, fully considering the influence of other circuit modules on the signal line, and then based on the target layout signal line. Parasitic parameter calculation can improve the accuracy of parasitic parameters.
  • another embodiment of the present disclosure provides a method for obtaining parasitic parameters.
  • the method for obtaining parasitic parameters is applied to a parameter obtaining system.
  • the method for obtaining parasitic parameters specifically includes the following steps:
  • the server receives an upload request sent by the client.
  • the client obtains the parasitic netlist of the layout corresponding to the circuit schematic diagram, and generates an upload request according to the parasitic netlist of the layout corresponding to the circuit schematic diagram, so as to send the upload request to the server.
  • the server locally stores the parasitic netlist of the layout.
  • the server parses the upload request to obtain the parasitic netlist of the layout corresponding to the circuit schematic diagram, and stores the parasitic netlist of the layout corresponding to the circuit schematic diagram locally.
  • the parasitic netlist of the layout corresponding to the circuit principle diagram shown in FIG. 3 stored in the server is shown in FIG. 6 .
  • the parasitic netlist includes parameters of parasitic resistance and parasitic capacitance of the layout signal lines corresponding to each circuit signal line.
  • the parasitic parameters of the parasitic resistance and parasitic capacitance under the layout signal line netA are the parasitic parameters of the parasitic resistance and parasitic capacitance of the layout signal line corresponding to the circuit signal line netF
  • the parasitic parameters of the parasitic resistance and parasitic capacitance under the layout signal line netE are the parasitic parameters of the parasitic resistance and parasitic capacitance of the layout signal line corresponding to the circuit signal line netG.
  • the parasitic parameters of the parasitic resistance and parasitic capacitance under the layout signal line netB are the parasitic parameters of the parasitic resistance and parasitic capacitance of the layout signal line corresponding to the circuit signal line netB
  • the parasitic parameters of the parasitic resistance and parasitic capacitance under the layout signal line netC are the circuit
  • the parasitic parameters of the parasitic resistance and parasitic capacitance of the layout signal line corresponding to the signal line netC, and the parasitic parameters of the parasitic resistance and parasitic capacitance of the layout signal line netD are the parasitic parameters of the parasitic resistance and parasitic capacitance of the layout signal line corresponding to the circuit signal line netD parameter.
  • the resistance value of the equivalent resistance of the circuit signal line netB is expressed in ohms.
  • the parasitic resistance and/or capacitance network of the circuit signal line netB includes a parasitic capacitance Cg1 , a parasitic capacitance Cg2 , a parasitic resistance R1 , a parasitic resistance R2 , a parasitic resistance R3 and a parasitic resistance R4 .
  • the node 0 represents the ground terminal
  • the parasitic capacitor Cg1 is located between the node netMos1 and the node 0, and the capacitance value of the parasitic capacitor Cg1 is x11.
  • the parasitic capacitance Cg2 is located between the node net02 and the node 0, and the capacitance value of the parasitic capacitance Cg2 is x12.
  • the parasitic resistance R1 is located between the node netMos1 and the node net01, and the resistance value of the parasitic resistance R1 is y11.
  • the parasitic resistance R2 is located between the node net01 and the node net02, and the resistance value of the parasitic resistance R2 is y12.
  • the parasitic resistance R3 is located between the node net01 and the node 0, and the resistance value of the parasitic resistance R3 is y11.
  • the parasitic resistance R4 is located between the node net02 and the node 0, and the resistance value of the parasitic resistance R4 is y14.
  • the server receives the parameter acquisition request sent by the client.
  • the client receives the identification of the target circuit signal line input by the user through the user interface, and generates a parameter acquisition request according to the identification of the target circuit signal line.
  • the user selects the input signal to be extracted from the target circuit module, including the circuit signal line netA, the circuit signal line netB, the circuit signal line netC, the circuit signal line netE and the circuit signal line netD in the target circuit module A as the target circuit signal line.
  • the server determines the position of the target circuit signal line in the target circuit module according to the identifier of the target circuit signal line and the locally stored position relationship table.
  • the server determines the target layout signal line according to the position of the target circuit signal line in the target circuit module and the layout corresponding to the circuit schematic diagram.
  • the circuit signal line netB, the circuit signal line netC and the circuit signal line netD are internal signal lines
  • the target layout signal lines corresponding to the circuit signal line netB, the circuit signal line netC and the circuit signal line netD are the circuit signal line netB in sequence
  • the circuit signal line netA and the circuit signal line netE are port signal lines, the circuit signal line netA is connected to the input port 01, and the circuit signal line netF is located outside the module A and connected to the input port 01, then the circuit signal line netA corresponds to the target layout signal line It is the target layout signal line corresponding to the circuit signal line netF, the circuit signal line netE is connected to the output port 02, the circuit signal line netG is located outside the module A, and is connected to the output port 02, and the target layout signal line corresponding to the circuit signal line netE is the circuit signal Line netG corresponds to the target layout signal line.
  • the server extracts the structural information of the parasitic resistance and/or capacitance network of the target layout signal line from the locally stored layout parasitic netlist.
  • the structure information of the parasitic resistance and/or capacitance network of the target layout signal line is extracted from the parasitic netlist.
  • the target circuit signal line is the circuit signal line netB, the circuit signal line netC, and the circuit signal line netE, extract the parasitic parameters of the parasitic resistance and parasitic capacitance under the layout signal line netB, and the parasitic resistance under the layout signal line netC from the parasitic netlist and parasitic parameters of parasitic capacitance, and parasitic parameters of parasitic resistance and/or parasitic capacitance under the layout signal line netD.
  • the parasitic parameters of the parasitic resistance and parasitic capacitance under netA in the parasitic netlist are the parasitic resistance and parasitic capacitance of the layout signal line corresponding to the circuit signal line netF Parameters
  • the parasitic parameters of the parasitic resistance and parasitic capacitance under netE are the parasitic parameters of the parasitic resistance and parasitic capacitance of the layout signal line corresponding to the circuit signal line netG
  • the parasitic parameters of the parasitic resistance and parasitic capacitance under neF can be directly extracted and netG The following parasitic parameters of parasitic resistance and parasitic capacitance.
  • FIG. 9 shows the structural information of the parasitic resistance and/or capacitance network of the layout signal line netB corresponding to the circuit signal line netB, including parasitic capacitance Cg1, parasitic capacitance Cg2, parasitic resistance R1, parasitic Resistor R2, parasitic resistance R3 and parasitic resistance R4.
  • the server builds an equivalent circuit according to the structure information of the parasitic resistance and/or capacitance network of the signal line of the target layout.
  • S307a Determine the power input end of the equivalent circuit, and detect the excitation current at the power input end when the excitation voltage is provided to the power input end.
  • x2 ⁇ represents the resistance value of the equivalent parasitic resistance of the signal line of the target circuit.
  • the total capacitance obtained by superimposing the capacitance of at least one parasitic capacitance is used as the capacitance of the equivalent parasitic capacitance of the signal line of the target circuit.
  • the structure information of the parasitic resistance and/or capacitance network includes the capacitance x11 of the parasitic capacitance Cg1 and the capacitance x12 of the parasitic capacitance Cg2.
  • y2F represents the capacitance of the equivalent parasitic capacitance of the signal line of the target circuit.
  • the server adds graphic data representing the equivalent parasitic capacitance and equivalent parasitic resistance value of the signal line of the target circuit to the schematic circuit diagram, so as to generate data corresponding to the marked circuit schematic diagram.
  • the client receives the response result sent by the server.
  • the client displays data corresponding to the marked circuit schematic diagram.
  • the parasitic parameters of the circuit signal lines can be marked in the schematic circuit diagram, and a report file of marking the parasitic parameters of the circuit signal lines as shown in FIG. 12 can also be output.
  • the user triggers the generation of an upload request through a graphical interactive interface to upload the parasitic netlist file to the server, and specifies the target circuit signal line.
  • the position of the circuit signal line is the port signal line, and its parasitic netlist file
  • the layout signal line corresponding to the internal signal line between the two modules of the upper-level circuit is used as the target layout signal line corresponding to the target circuit signal line.
  • the server is also used to extract the structural information of the parasitic resistance and/or capacitance network of the signal line of the target layout from the parasitic netlist, and build an equivalent circuit, and obtain its equivalent parasitic resistance value by providing excitation for the equivalent circuit.
  • the parasitic capacitance is extracted from the structural information of the parasitic resistance and/or capacitance network. Mark the calculated equivalent parasitic capacitance and equivalent parasitic resistance in the circuit schematic diagram, and output the report file.
  • an embodiment of the present disclosure provides a device 400 for acquiring parasitic parameters.
  • the device specifically includes:
  • the first processing module 401 is used to obtain the position of the target circuit signal line in the target circuit module in the schematic circuit diagram;
  • the first processing module 401 is also used to determine the target layout signal line according to the position of the target circuit signal line in the target circuit module and the layout corresponding to the circuit schematic diagram;
  • the first processing module 401 is further configured to extract the structure information of the parasitic resistance and/or capacitance network of the target layout signal line from the locally stored layout parasitic netlist;
  • the first processing module 401 is further configured to determine the parasitic parameters of the signal lines of the target circuit according to the structure information of the parasitic resistance and/or capacitance network of the signal lines of the target layout.
  • the first processing module 401 is specifically used to:
  • the first processing module 401 is specifically used to:
  • the first processing module 401 is specifically used to:
  • the total capacitance after superimposing the capacitance of at least one parasitic capacitance is taken as the capacitance of the equivalent parasitic capacitance of the signal line of the target circuit;
  • the structural information of the parasitic resistance and/or capacitance network includes the capacitance of at least one parasitic capacitance in the parasitic resistance and/or capacitance network.
  • the first processing module 401 is specifically used to:
  • the target layout signal line is a layout signal line corresponding to the target circuit signal line in the layout.
  • the first processing module 401 is specifically used to:
  • the target layout signal line is a layout signal line located outside the target circuit module in the layout and connected to a port on a corresponding side of the target circuit module.
  • the device further includes a first receiving module 402;
  • the first receiving module 402 is specifically configured to: receive a parameter acquisition request sent by the client, where the parameter acquisition request includes the identification of the target circuit signal line;
  • the first processing module 401 is specifically configured to: determine the position of the target circuit signal line in the target circuit module according to the identification of the target circuit signal line and the locally stored position relationship table.
  • the first receiving module 402 is specifically configured to: receive an upload request sent by the client, wherein the upload request includes a parasitic netlist of a layout corresponding to the circuit schematic diagram;
  • the parasitic netlist of the layout corresponding to the circuit schematic diagram is stored locally.
  • the device further includes a first sending module 403;
  • the first processing module 401 is specifically configured to add graphic data representing parasitic parameters of target circuit signal lines in the schematic circuit diagram, so as to generate data corresponding to the marked circuit schematic diagram;
  • the first sending module 403 is configured to generate a response message according to the data corresponding to the marked circuit schematic diagram, and send the response message to the client.
  • an embodiment of the present disclosure provides a device 500 for acquiring parasitic parameters.
  • the device specifically includes:
  • the second processing module 501 is configured to obtain the identification of the signal line of the target circuit
  • the second processing module 501 is further configured to generate a parameter acquisition request according to the identification of the signal line of the target circuit;
  • the second sending module 502 is configured to send a parameter acquisition request to the server, wherein the parameter acquisition request is used to determine the position of the target circuit signal line in the circuit schematic diagram in the target circuit module, and the position of the target circuit signal line in the target circuit module
  • the layout corresponding to the position and the circuit schematic diagram is used to determine the target layout signal line, and the parasitic netlist of the target layout signal line and the locally stored layout is used to determine the structure information of the parasitic resistance and/or capacitance network of the target layout signal line; the target layout
  • the parasitic resistance of the signal line and/or the structural information of the capacitive network are used to determine the parasitic parameters of the signal line of the target circuit.
  • the second processing module 501 is further configured to: obtain a parasitic netlist of the layout, and generate an upload request according to the parasitic netlist;
  • the second sending module 502 is further configured to send an upload request to the server, wherein the upload request is used to make the server store the parasitic netlist of the layout locally.
  • the device further includes a second receiving module 503;
  • the second receiving module 503 is configured to receive a response result sent by the server, wherein the response result includes data corresponding to the marked circuit schematic diagram;
  • the second processing module 501 is configured to display data corresponding to the marked circuit schematic diagram.
  • an embodiment of the present disclosure provides a server 600 , and the server 600 includes a first memory 601 and a first processor 602 .
  • the first memory 601 is used to store computer instructions executable by the first processor
  • the first processor 602 implements each step in the method in the foregoing embodiments when executing computer instructions. For details, refer to the related descriptions in the foregoing method embodiments.
  • the first memory 601 may be independent or integrated with the first processor 602 .
  • the server further includes a bus for connecting the first memory 601 and the first processor 602 .
  • an embodiment of the present disclosure provides a client 700 , and the client 700 includes a second memory 701 and a second processor 702 .
  • the second memory 701 is used to store computer instructions executable by the second processor
  • the second processor 702 implements various steps in the methods in the above-mentioned embodiments when executing computer instructions. For details, refer to the related descriptions in the foregoing method embodiments.
  • the second memory 701 may be independent or integrated with the second processor 702 .
  • the client further includes a bus for connecting the second memory 701 and the second processor 702 .
  • Embodiments of the present disclosure also provide a computer-readable storage medium, in which computer instructions are stored, and when a processor executes the computer instructions, each step in the method in the foregoing embodiments is implemented.
  • Embodiments of the present disclosure also provide a computer program product, including computer instructions, and when the computer instructions are executed by a processor, each step in the method in the foregoing embodiments is implemented.

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Abstract

一种寄生参数的获取方法以及设备，该方法包括：获取电路原理图中目标电路信号线在目标电路模块内的位置（S101），根据目标电路信号线在目标电路模块内的位置和电路原理图对应的版图确定目标版图信号线（S102），从本地存储的版图的寄生网表中提取目标版图信号线的寄生电阻和/或电容网络的结构信息（S103），根据目标版图信号线的寄生电阻和/或电容网络的结构信息确定目标电路信号线的寄生参数（S104）。通过上述方式可实现自动获取寄生参数，效率更高，准确率更高，且计算过程更简单。

Description

寄生参数的获取方法以及设备
本公开要求于2022年01月10日提交中国专利局、申请号为202210022116.X、申请名称为“寄生参数的获取方法以及设备”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及但不限定于一种寄生参数的获取方法以及设备。
背景技术
芯片设计通常可分为逻辑设计和物理设计，即电路原理图设计和版图设计。前者得到芯片的门级网表电路，为理想化电路模型。后者通过布局布线及物理验证产生供制造用的GDSII数据。
显然，版图中包含大量物理参数特征，例如：寄生电容和寄生电阻，这些物理参数特征会对电路的功能及性能产生较大的影响。因此，准确获得这些物理参数特征对于芯片设计及制造过程至关重要。
发明内容
本公开实施例提供一种寄生参数的获取方法，方法应用于服务器，方法包括：
获取电路原理图中目标电路信号线在目标电路模块内的位置；
根据目标电路信号线在目标电路模块内的位置和电路原理图对应的版图确定目标版图信号线；
从本地存储的版图的寄生网表中提取目标版图信号线的寄生电阻和/或电容网络的结构信息；
根据目标版图信号线的寄生电阻和/或电容网络的结构信息确定目标电路信号线的寄生参数。
在一实施例中，根据目标版图信号线的寄生电阻和/或电容网络的结构信息确定目标电路信号线的寄生参数，具体包括：
根据目标版图信号线的寄生电阻和/或电容网络的结构信息搭建等效电路；
计算等效电路的等效电阻和/或等效电容，以获得目标电路信号线的寄生参数。
在上述方案中，在从寄生网表中提取目标版图信号线的寄生电阻和/或电容网络的结构信息后，通过构建等效电路，再计算等效电路的等效电阻和/或等效电容，无需直接根据复杂的结构信息计算，可以简化计算过程。
在一实施例中，确定等效电路的电源输入端，并在向电源输入端提供激励电压时检测电源输入端的激励电流；
计算激励电压和激励电流的比值，以获得等效电路的等效阻值，并将等效阻值作为目标电路信号线的等效寄生电阻的阻值。
在上述方案中，在计算等效电路的等效阻值时，可以通过为等效电路提供激励并获得等效电路在激励下的响应值，从而根据激励和响应值计算等效电阻，无需基于等效电路中多个电阻和/或电容的阻抗再计算等效阻值，可以简化计算过程。
在一实施例中，寄生电阻和/或电容网络的结构信息包括至少一个寄生电容的电容量；根据目标版图信号线的寄生电阻和/或电容网络的结构信息确定目标电路信号线的寄生参数，具体包括：
将至少一个寄生电容的电容量叠加后的总电容量作为目标电路信号线的等效寄生电容的电容量。
在上述方案中，当目标电路信号线的寄生参数为目标电路信号线的等效寄生电容的电容量时，提取目标版图信号线的寄生电阻和/或电容网络中若干个寄生电容的电容量，并将若干个寄生电容的电容量进行叠加后作为等效寄生电容的电容量，无需搭建等效电路，也无需向等效电路提供激励，可以简化计算过程。
在一实施例中，根据目标电路信号线在目标电路模块内的位置和电路原理图对应的版图确定目标版图信号线，具体包括：
若目标电路信号线在目标电路模块内的位置为内部信号线，目标版图信号线为目标电路信号线在版图中对应的版图信号线。
在一实施例中，根据目标电路信号线在目标电路模块内的位置和电路原理图对应的版图确定目标版图信号线，具体包括：
若目标电路信号线在目标电路模块内的位置为端口信号线，目标版图信号线为版图中位于目标电路模块的外部，且与目标电路信号线所连接的输入端口或者输出端口连接的版图信号线。
在上述方案中，在确定目标电路信号线对应的目标版图信号线时，基于目标电路信号线在目标电路模块内的位置关系确定。由于目标电路模块内部的信号线不与外部信号线连接，无需考虑其他电路模块对该目标电路信号线的影响，故目标电路信号线的目标版图信号线为目标电路信号线在版图中对应的版图信号线。由于目标电路模块的端口信号线与外部信号线连接，在确定目标版图信号线时，版图中位于目标电路模块的外部，且与内的目标电路信号线所连接的输入端口或者输出端口连接的版图信号线作为目标版图信号线，考虑到其他电路模块对信号线的影响，再基于目标版图信号线进行寄生参数计算，可以提高寄生参数的准确性。
在一实施例中，获取电路原理图中的目标电路信号线在目标电路模块内的位置，具体包括：
接收客户端发送的参数获取请求，其中，参数获取请求包括目标电路信号线的标识；
根据目标电路信号线的标识和本地存储的位置关系表确定目标电路信号线在目标电路模块内的位置。
在一实施例中，在从本地存储的版图的寄生网表中提取目标版图信号线的寄生电阻和/或电容网络的结构信息之前，方法还包括：
接收客户端发送的上传请求，其中，上传请求中包括电路原理图对应的版图的寄生网表；
将电路原理图对应的版图的寄生网表存储在本地。
在一实施例中，在根据目标版图信号线的寄生电阻和/或电容网络的结构信息确定目标电路信号线的寄生参数之后，方法还包括：
在电路原理图对应的图形数据中增加表示目标电路信号线的寄生参数的图形数据，以生成标记后的电路原理图对应的数据；
根据标记后的电路原理图对应的数据生成响应消息，并向客户端发送响应消息。
在上述方案中，通过在电路原理图对应的图形数据中增加表示目标电路信号线的寄生参数的图形数据，可以实现图形化显示各个目标电路信号线的寄生参数，从而实现更加直观将寄生参数标记在电路原理图中。
本公开另一实施例提供一种寄生参数的获取方法，方法应用于客户端，方法包括：
获取目标电路信号线的标识；
根据目标电路信号线的标识生成参数获取请求；
向服务器发送参数获取请求，其中，参数获取请求用于确定电路原理图中的目标电路信号线在目标电路模块内的位置，目标电路信号线在目标电路模块内的位置和电路原理图对应的版图用于确定目标版图信号线，目标版图信号线和本地存储的版图的寄生网表用于确定目标版图信号线的寄生电阻和/或电容网络的结构信息；目标版图信号线的寄生电阻和/或电容网络的结构信息用于确定目标电路信号线的寄生参数。
在一实施例中，方法还包括：
获取版图的寄生网表，并根据寄生网表生成上传请求；
向服务器发送上传请求，其中，上传请求用于使服务器将版图的寄生网表存储在本地。
在一实施例中，方法还包括：
接收服务器发送的响应结果，其中，响应结果包括标记后的电路原理图对应的数据；
显示标记后的电路原理图对应的数据。
本公开又一实施例提供一种服务器，包括：处理器，以及与处理器通信连接的存储器；
存储器存储计算机执行指令；
处理器执行存储器存储的计算机执行指令，以实现上述实施例提供的寄生参数的获取方法。
本公开再一实施例提供一种客户端，包括：处理器，以及与处理器通信连接的存储器；
存储器存储计算机执行指令；
处理器执行存储器存储的计算机执行指令，以实现上述实施例提供的寄生参数的获取方法。
本公开另一实施例提供一种计算机可读存储介质，计算机可读存储介质中存储有计算机执行指令，计算机执行指令被处理器执行时用于实现上述实施例提供的寄生参数的获取方法。
本公开实施例提供的寄生参数的获取方法以及设备，获取目标电路信号线在目标电路模块内的位置，以根据目标电路信号线在目标电路模块内的位置和电路原理图对应的版图确定目标版图信号线，再基于版图的寄生网表获取目标版图信号线的寄生电阻和/或电容网络的结构信息，以根据目标版图信号线的寄生电阻和/或电容网络的结构信息确定目标电路信号线的寄生参数。相较于人工计算电路信号线的寄生参数的方案，本公开可实现自动化输出信号线的寄生参数， 效率更高。且在确定目标版图信号线时，根据目标电路信号线在目标电路模块中的位置确定，可以充分考虑到信号线的位置对寄生参数的影响，提高寄生参数的准确性。此外，在确定目标版图信号线后，通过提取目标版图信号线的寄生电阻和/或电容网络的结构信息后，再基于该结构信息计算寄生参数，可以简化计算过程。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。
图1为本公开一实施例提供参数获取系统的结构示意图；
图2为本公开另一实施例提供寄生参数的获取方法的流程示意图；
图3为本公开一实施例提供的电路原理图；
图4为本公开另一实施例提供寄生参数的获取方法的流程示意图；
图5为本公开另一实施例提供寄生参数的获取方法的流程示意图；
图6为本公开另一实施例提供的寄生网表的示意图；
图7为本公开另一实施例提供的用户界面图；
图8为本公开另一实施例提供的目标电路信号线所在的模块A的电路原理示意图；
图9为本公开另一实施例提供的寄生电阻和/或电容网络的结构信息的示意图；
图10为本公开另一实施例提供的等效电路的示意图；
图11为本公开另一实施例提供的标记后的电路原理图的示意图；
图12为本公开另一实施例提供的报告文件的示意图；
图13为本公开又一实施例提供的获取装置的结构示意图；
图14为本公开再一实施例提供的获取装置的结构示意图；
图15为本公开又一实施例提供的服务器的结构示意图；
图16为本公开又一实施例提供的客户端的结构示意图。
通过上述附图，已示出本公开明确的实施例，后文中将有更详细的描述。这些附图和文字描述并不是为了通过任何方式限制本公开构思的范围，而是通过参考特定实施例为本领域技术人员说明本公开的概念。
具体实施方式
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施方式并不代表与本公开相一致的所有实施方式。相反，它们仅是与如所附权利要求书中所详述的、本公开的一些方面相一致的装置和方法的例子。
准确获得版图中的物理参数特征对于芯片设计及制造过程至关重要。尤其是在后仿真完成后的电路验证和改进阶段，电路设计工程师通常需要追踪电路中某些异常信号线的寄生电容量和/ 或寄生电阻值，通过这些寄生器件的寄生参数值来判断寄生效应对电路的影响，进而改进、优化和完善电路。
然而，获得信号线的寄生电容量和/或寄生电阻值并不容易，在现有技术中还没有可以自动输出电路原理图中电路信号线的寄生电容和/或寄生电阻的方案。电路设计工程师通常人工基于庞大的寄生网表估算特定信号线的等效寄生电容和/或等效寄生电阻。电路设计工程师还会直接通过版图的走线肉眼估计其寄生效应，但是很难达到将寄生电阻阻值和寄生电容的电容量进行量化。并且这种方法耗时，准确性差，不利于项目研发。
针对现有技术的局限性，本公开实施例提供的寄生参数的获取方法以及设备，先根据目标电路信号线在目标电路模块中的位置确定目标电路信号线对应的目标版图信号线，再从版图的寄生网表中提取目标版图信号线的寄生电阻和/或电容网络的结构信息，以基于该结构信息确定目标电路信号线的寄生参数，并将目标电路信号线的寄生参数反标到电路原理图中，以供电路设计工程师进行调试、验证或优化电路设计，以满足目前芯片设计所面临的更高要求。
如图1所示，本公开一实施例提供一种参数获取系统，该参数获取系统包括服务器100和客户端200。服务器100和客户端200之间通信连接。客户端200用于向服务器100发起寄生参数的获取请求，服务器100通过解析获取请求获得目标电路信号线，并基于本地存储的寄生网表确定目标电路信号线的寄生参数，确定目标电路信号线的寄生参数的具体方式可以参考如下实施例，此处不再赘述。
如图2所示，本公开另一实施例提供一种寄生参数的获取方法，该寄生参数的获取方法应用于服务器，该寄生参数的获取方法具体包括如下步骤：
S101、获取电路原理图中目标电路信号线在目标电路模块内的位置。
在该步骤中，如图3所示，某模块D的电路原理图包括多个电路模块，例如：模块A、模块B、模块C、……。多个电路模块之间相互连接，各电路模块的具体相互连接关系根据该电路原理图所要实现功能确定。
每个电路模块中包括多个子电路和连接各个子电路的电路信号线，还包括用于与其他电路模块连接的电路信号线。例如子电路I1、子电路I2、子电路I3、子电路I4，子电路I1至子电路I4可以为反相器、与门、非门、异或门等中任意一项或者多项组合。电路信号线包括连接子电路I1和子电路I2的电路信号线netB，连接子电路I2和子电路I3的电路信号线netC，连接子电路I2和子电路I4的电路信号线netD。电路信号线还包括连接模块A的输入端口01和子电路I1的电路信号线netA，以及连接模块A的输出输出端口02和子电路I3的电路信号线netE。
其中，目标电路信号线为目标电路模块内部的信号线。若目标电路信号线在目标电路模块内的位置包括内部信号线和端口信号线。内部信号线是指使目标电路模块内各个子电路相互连接的电路信号线，端口信号线是指位于目标电路模块内部，且用于连接目标电路模块和其他电路模块的电路信号线。
在一实施例中，通过确定目标电路信号线的功能获取目标电路信号线在目标电路模块内的位置。
若目标电路信号线是用于连接各子电路的电路信号线，则确定目标电路信号线在目标电路 模块内的位置为内部信号线。若目标电路信号线是用于连接目标电路模块和其他电路模块的电路信号线，则确定目标电路信号线在目标电路模块内的位置为端口信号线。
S102、根据目标电路信号线在目标电路模块内的位置和电路原理图对应的版图确定目标版图信号线。
在该步骤中，电路原理图对应的版图是指根据电路原理图生成的版图，电路原理图中各电路模块内部子电路和电路信号线都在版图中一一对应体现。
当目标电路信号线在目标电路模块内的位置不同时，确定目标版图信号线的方式不同。若目标电路信号线在目标电路模块内的位置为内部信号线，目标版图信号线为目标电路信号线在版图中对应的版图信号线。
若目标电路信号线在目标电路模块内的位置为端口信号线，目标版图信号线为版图中位于目标电路模块的外部，且与目标电路模块内的目标电路信号线所连接的输入端口或者输出端口连接的版图信号线。
例如：继续参考图3，当目标电路模块为模块A，其有两个端口，依次标记为输入端口01和输出端口02，目标电路模块的输入端口01连接模块B的一个输出端口03，目标电路模块的输出端口02连接模块C的一个输入端口04。当目标电路信号线为连接输入端口01并通过输入端口01与模块B连接的端口信号线netA时，目标版图信号线为位于模块A外部的且设置于模块A的输入端口01和模块B的输出端口03的之间的电路信号线netF对应的版图信号线。同理，当目标电路信号线为连接输出端口02并通过输出端口02与模块C连接的端口信号线netE时，目标版图信号线为位于模块A外部的且设置于模块A的输出端口02和模块C的输入端口04的之间的电路信号线netG对应的版图信号线。
当目标电路信号线为连接子电路I1和子电路I2的电路信号线netB，连接子电路I2和子电路I3的电路信号线netC，以及连接子电路I2和子电路I4的电路信号线netD时，目标版图信号线依次为电路信号线netB对应的版图信号线、电路信号线netC对应的版图信号线以及电路信号线netD对应的版图信号线。
S103、从本地存储的版图的寄生网表中提取目标版图信号线的寄生电阻和/或寄生电容网络的结构信息。
在该步骤中，寄生电阻和/或寄生电容网络是指网络中仅包含寄生电阻、网络中仅包含寄生电容或者网络中包含寄生电阻和寄生电容。版图的寄生网表包括有各个子电路之间版图信号线的寄生电阻值和/或寄生电容值，以及各个寄生电阻和/或寄生电容与各个电路模块中子电路之间的连接关系。通过提取寄生网表中与目标版图信号线关联的寄生电容和/或寄生电阻的相关信息，以获得目标版图信号线的寄生电阻和/或电容网络的结构信息。
S104、根据目标版图信号线的寄生电阻和/或电容网络的结构信息确定目标电路信号线的寄生参数。
在该步骤中，在获得目标版图信号线的寄生电阻和/或电容网络的结构信息，可基于寄生电阻和/或电容网络的结构信息进行参数计算，以获得目标电路信号线的寄生参数。还可以基于寄生电阻和/或电容网络的结构信息搭建寄生电路，采集寄生电路在激励电源的激励下的响应值， 基于响应值计算目标电路信号线的寄生参数。
在上述技术方案中，为获得目标电路信号线的寄生参数，确定目标电路信号线在目标电路模块内的位置关系，以根据该位置和电路原理图对应的版图确定目标版图信号线，再从本地存储的版图的寄生网表中提取目标版图信号线的寄生电阻和/或电容网络的结构信息，以根据寄生电阻和/或电容网络的结构信息确定目标电路信号线的寄生参数。相较于人力估算寄生参数的方式，本方案可以实现准确获得信号线的寄生参数，且效率更高。且在确定目标版图信号线时，根据目标电路信号线在目标电路模块中的位置确定，可以充分考虑到信号线的位置对寄生参数的影响，提高寄生参数的准确性。此外，在确定目标版图信号线后，通过提取目标版图信号线的寄生电阻和/或电容网络的结构信息后，再基于该结构信息计算寄生参数，可以简化计算过程。
如图4所示，本公开另一实施例提供一种寄生参数的获取方法，该寄生参数的获取方法应用于参数获取系统，该寄生参数的获取方法具体包括如下步骤：
S201、服务器接收客户端发送的上传请求。
在该步骤中，客户端获取电路原理图对应的版图的寄生网表，并根据版图的寄生网表生成上传请求。
S202、服务器将电路原理图对应的版图的寄生网表存储在本地。
在该步骤中，服务器解析上传请求，以获得电路原理图对应的版图的寄生网表，并将版图的寄生网表存储在本地。
S203、服务器接收客户端发送的参数获取请求。
在该步骤中，客户端获取目标电路信号线的标识，并根据目标电路信号线的标识生成参数获取请求。
在获取目标电路信号线的标识时，用户通过用户界面输入目标电路信号线的标识。
S204、服务器根据目标电路信号线的标识和本地存储的位置关系表确定目标电路信号线在目标电路模块内的位置。
在该步骤中，位置关系表用于表示电路信号线的标识与电路信号线在对应电路模块内的位置之间对应关系，电路信号线在对应电路模块内的位置包括内部信号线和端口信号线。在从参数获取请求中解析出目标电路信号线的标识后，使用目标电路信号线的标识查找位置关系表，以获得目标电路信号线在目标电路模块内的位置。
S205、服务器根据目标电路信号线在目标电路模块内的位置和电路原理图对应的版图确定目标版图信号线。
在该步骤中，若目标电路信号线在目标电路模块内的位置为内部信号线，目标版图信号线为目标电路信号线在版图中对应的版图信号线。若目标电路信号线在目标电路模块内的位置为端口信号线，目标版图信号线为版图中位于目标电路模块的外部，且与目标电路模块内的目标电路信号线所连接的输入端口或者输出端口连接的版图信号线。
S206、服务器从本地存储的版图的寄生网表中提取目标版图信号线的寄生电阻和/或电容网络的结构信息。
在该步骤中，通过提取寄生网表中与目标版图信号线关联的寄生电阻和/或电容的相关信息，以获得目标版图信号线的寄生电阻和/或电容网络的结构信息。
S207、服务器根据目标版图信号线的寄生电阻和/或电容网络的结构信息确定目标电路信号线的寄生参数。
在该步骤中，作为其中一种实现方式，寄生电阻和/或电容网络的结构信息包括寄生电阻和/或电容网络中的至少一个寄生电容的电容量，目标电路信号线的寄生参数为其总寄生电容的电容量，将至少一个寄生电容的电容量叠加后的总电容量作为目标电路信号线的寄生电容的电容量。在上述技术方案中，无需搭建等效电路，也无需向等效电路提供激励，可以简化计算过程。
作为另一种实现方式，根据目标版图信号线的寄生电阻和/或电容网络的结构信息搭建等效电路，并计算等效电路的等效电阻和/或等效电容，以获得目标电路信号线的寄生参数。
更具体地，在计算等效电路的等效电阻时，确定等效电路的电源输入端，并在向电源输入端提供激励电压时检测电源输入端的激励电流，再计算激励电压和激励电流的比值，以获得等效电路的等效阻值，并将等效阻值作为目标电路信号线的等效寄生电阻的阻值。
S208、服务器在电路原理图中增加表示目标电路信号线的寄生参数的图形数据，以生成标记后的电路原理图对应的图形数据。
在该步骤中，服务器在获得目标电路信号线的寄生参数后，可以在电路原理图中将目标电路信号线的寄生参数标记上，并将参数图形化显示出来。
更具体地，获取表示目标电路信号线的寄生参数的图形数据，将表示目标电路信号线的寄生参数的图形数据增加到电路原理图中，以获得标记后的电路原理图对应的图形数据。
S209、客户端接收服务器发送的响应结果。
在该步骤中，服务器在获得标记后的电路原理图对应的图形数据后，根据标记后的电路原理图对应的图形数据生成响应结果，并向客户端发送响应结果。
S210、客户端显示标记后的电路原理图对应的数据。
在该步骤中，客户端在接收到响应结果后，对响应结果进行解析，以获得标记后的电路原理图对应的数据，并对标记后的电路原理图对应的数据进行显示处理，以实现在用户界面上显示标记后的电路原理图。
在上述技术方案中，在从寄生网表中提取目标版图信号线的寄生电阻和/或电容网络的结构信息后，通过构建等效电路，再计算等效电路的等效电阻和/或等效电容，无需直接根据复杂的结构信息计算，可以简化计算过程。且在计算等效电路的等效阻值时，可以通过为等效电路提供激励并获得等效电路在激励下的响应值，从而根据激励和响应值计算等效电阻，无需基于等效电路中多个寄生电阻的阻抗再计算等效阻值，可以简化计算过程。此外，在确定目标电路信号线对应的目标版图信号线时，基于目标电路信号线在目标电路模块内的位置关系确定，充分考虑到其他电路模块对信号线的影响，再基于目标版图信号线进行寄生参数计算，可以提高寄生参数的准确性。
如图5所示，本公开另一实施例提供一种寄生参数的获取方法，该寄生参的获取方法应用于参数获取系统，该寄生参的获取方法具体包括如下步骤：
S301、服务器接收客户端发送的上传请求。
在该步骤中，客户端获取电路原理图对应的版图的寄生网表，并根据电路原理图对应的版图的寄生网表生成上传请求，以向服务器发送该上传请求。
S302、服务器将版图的寄生网表存储在本地。
在该步骤中，服务器解析上传请求，以获得电路原理图对应的版图的寄生网表，并将电路原理图对应的版图的寄生网表存储在本地。
例如，服务器存储的图3所示的电路原理图对应的版图的寄生网表如图6所示。寄生网表中包含各个电路信号线对应的版图信号线的寄生电阻、寄生电容的参数。其中，版图信号线netA下的寄生电阻和寄生电容的寄生参数是电路信号线netF对应的版图信号线的寄生电阻和寄生电容的寄生参数，版图信号线netE下的寄生电阻和寄生电容的寄生参数是电路信号线netG对应的版图信号线的寄生电阻和寄生电容的寄生参数。
版图信号线netB下的寄生电阻和寄生电容的寄生参数是电路信号线netB对应的版图信号线的寄生电阻和寄生电容的寄生参数，版图信号线netC下的寄生电阻和寄生电容的寄生参数是电路信号线netC对应的版图信号线的寄生电阻和寄生电容的寄生参数，版图信号线netD下的寄生电阻和寄生电容的寄生参数是电路信号线netD对应的版图信号线的寄生电阻和寄生电容的寄生参数。
以电路信号线netB为例说明。电路信号线netB的等效电阻的阻值用欧姆表示。电路信号线netB的寄生电阻和/或电容网络中包含寄生电容Cg1、寄生电容Cg2、寄生电阻R1、寄生电阻R2、寄生电阻R3以及寄生电阻R4。
其中，节点0表示接地端，寄生电容Cg1位于节点netMos1和节点0之间，寄生电容Cg1的电容值为x11。寄生电容Cg2位于节点net02和节点0之间，寄生电容Cg2的电容值为x12。寄生电阻R1位于节点netMos1和节点net01之间，寄生电阻R1的电阻值为y11。寄生电阻R2位于节点net01和节点net02之间，寄生电阻R2的电阻值为y12。寄生电阻R3位于节点net01和节点0之间，寄生电阻R3的电阻值为y11。寄生电阻R4位于节点net02和节点0之间，寄生电阻R4的电阻值为y14。
S303、服务器接收客户端发送的参数获取请求。
在该步骤中，客户端接收用户通过用户界面输入的目标电路信号线的标识，根据目标电路信号线的标识生成参数获取请求。
如图7所示，用户选择输入信号从目标电路模块中抽取，包括目标电路模块A内电路信号线netA、电路信号线netB、电路信号线netC、电路信号线netE以及电路信号线netD作为目标电路信号线。
S304、服务器根据目标电路信号线的标识和本地存储的位置关系表确定目标电路信号线在目标电路模块内的位置。
在该步骤中，针对图8所示的模块A的电路原理图，通过查找本地存储的位置关系表，确定电路信号线netB、电路信号线netC以及电路信号线netD为内部信号线，电路信号线netA和电路信号线netE为端口信号线。
S305、服务器根据目标电路信号线在目标电路模块内的位置和电路原理图对应的版图确定目标版图信号线。
在该步骤中，电路信号线netB、电路信号线netC以及电路信号线netD为内部信号线，电路信号线netB、电路信号线netC以及电路信号线netD对应的目标版图信号线依次为电路信号线netB在版图中对应的版图信号线、电路信号线netC在版图中对应的版图信号线以及电路信号线netD在版图中对应的版图信号线。
电路信号线netA和电路信号线netE为端口信号线，电路信号线netA连接输入端口01，电路信号线netF位于模块A外部，且与输入端口01连接，则电路信号线netA对应的目标版图信号线为电路信号线netF对应的目标版图信号线，电路信号线netE连接输出端口02，电路信号线netG位于模块A外部，且与输出端口02连接，电路信号线netE对应的目标版图信号线为电路信号线netG对应的目标版图信号线。
S306、服务器从本地存储的版图的寄生网表中提取目标版图信号线的寄生电阻和/或电容网络的结构信息。
在该步骤中，在确定目标版图信号线后，从寄生网表中提取目标版图信号线的寄生电阻和/或电容网络的结构信息。
当目标电路信号线为电路信号线netB、电路信号线netC以及电路信号线netE，从寄生网表中提取版图信号线netB下的寄生电阻和寄生电容的寄生参数、版图信号线netC下的寄生电阻和寄生电容的寄生参数、以及版图信号线netD下的寄生电阻和/或寄生电容的寄生参数。
当目标电路信号线为电路信号线netA和电路信号线netE，由于寄生网表中netA下的寄生电阻和寄生电容的寄生参数是电路信号线netF对应的版图信号线的寄生电阻和寄生电容的寄生参数，netE下的寄生电阻和寄生电容的寄生参数是电路信号线netG对应的版图信号线的寄生电阻和寄生电容的寄生参数，则可以直接提取neF下的寄生电阻和寄生电容的寄生参数和netG下的寄生电阻和寄生电容的寄生参数。
以电路信号线netB为例，图9中示出了电路信号线netB对应的版图信号线netB的寄生电阻和/或电容网络的结构信息,包含寄生电容Cg1、寄生电容Cg2、寄生电阻R1、寄生电阻R2、寄生电阻R3以及寄生电阻R4。
S307a1、服务器根据目标版图信号线的寄生电阻和/或电容网络的结构信息搭建等效电路。
在该步骤中，以电路信号线netB对应的版图信号线netB为例，在继续参考图9示出的寄生电阻和/或电容网络的结构信息可知，寄生电容Cg1位于节点netMos1和节点0之间，寄生电容Cg2位于节点net02和节点0之间，寄生电阻R1位于节点netMos1和节点net01之间，寄生电阻R2位于节点net01和节点net02之间，寄生电阻R3位于节点net01和节点0之间，寄生电阻R4位于节点net02和节点0之间。基于上述结构信息可搭建图10所示的等效电路。
S307a2、确定等效电路的电源输入端，并在向电源输入端提供激励电压时检测电源输入端的激励电流。
在该步骤中，以电路信号线netB为例，确定图10所示的等效电路的电源输入端为节点netMos1和节点0，将节点netMos1连接直流电源正极，将节点0连接直流电源负极，直流电源 向等效电路提供幅值为Vin的直流激励，检测到流经节点netMos1的激励电流的幅值为I。
S307a3、计算激励电压和激励电流的比值，以获得等效电路的等效阻值，并将等效阻值作为目标电路信号线的等效寄生电阻的阻值。
在该步骤中，以电路信号线netB为例，根据如下公式计算获得等效电路的等效阻值：
R(netB)＝Vin/I＝x2Ω
其中，x2Ω表示目标电路信号线的等效寄生电阻的阻值。
S307b、将至少一个寄生电容的电容量叠加后的总电容量作为目标电路信号线的等效寄生电容的电容量。
在该步骤中，以电路信号线netB为例，寄生电阻和/或电容网络的结构信息包括寄生电容Cg1的电容量x11和寄生电容Cg2的电容量x12。
根据如下公式计算目标电路信号线B的等效寄生电容的电容量：
C(netB)＝x11+x12＝y2F
其中，y2F表示目标电路信号线的等效寄生电容的电容。
S308、服务器在电路原理图中增加表示目标电路信号线的等效寄生电容量和等效寄生电阻值的图形数据，以生成标记后的电路原理图对应的数据。
S309、客户端接收服务器发送的响应结果。
S310、客户端显示标记后的电路原理图对应的数据。
在该步骤中，如图11所示，可以在电路原理图中标记电路信号线的寄生参数，还可以输出如图12所示的标记电路信号线的寄生参数的报告文件。
在上述技术方案中，用户通过图形化交互界面触发生成上传请求，以将寄生网表文件上传至服务器，并指定目标电路信号线，对于电路信号线的位置为端口信号线，其在版图的寄生网表中不存在对应的目标版图信号线，因此，将上一级电路的两个模块之间内部信号线对应的版图信号线作为目标电路信号线对应的目标版图信号线。服务器还用于从寄生网表中提取目标版图信号线的寄生电阻和/或电容网络的结构信息，并搭建等效电路，通过为等效电路提供激励而真得计算得到其等效寄生电阻值，并从寄生电阻和/或电容网络的结构信息中提取寄生电容量。将运算得到的等效寄生电容量和等效寄生电阻值标识到电路原理图，并输出报告文件。
如图13所示，本公开一实施例提供一种寄生参数的获取装置400，装置具体包括：
第一处理模块401，用于获取电路原理图中目标电路信号线在目标电路模块内的位置；
第一处理模块401还用于根据目标电路信号线在目标电路模块内的位置和电路原理图对应的版图确定目标版图信号线；
第一处理模块401还用于从本地存储的版图的寄生网表中提取目标版图信号线的寄生电阻和/或电容网络的结构信息；
第一处理模块401还用于根据目标版图信号线的寄生电阻和/或电容网络的结构信息确定目标电路信号线的寄生参数。
在一实施例中，第一处理模块401具体用于：
根据目标版图信号线的寄生电阻和/或电容网络的结构信息搭建等效电路；
计算等效电路的等效电阻和/或等效电容，以获得目标电路信号线的寄生参数。
在一实施例中，第一处理模块401具体用于：
确定等效电路的电源输入端，并在向电源输入端提供激励电压时检测电源输入端的激励电流；
计算激励电压和激励电流的比值，以获得等效电路的等效阻值，并将等效阻值作为目标电路信号线的等效寄生电阻的阻值。
在一实施例中，第一处理模块401具体用于：
将至少一个寄生电容的电容量叠加后的总电容量作为目标电路信号线的等效寄生电容的电容量；
其中，寄生电阻和/或电容网络的结构信息包括寄生电阻和/或电容网络中的至少一个寄生电容的电容量。
在一实施例中，第一处理模块401具体用于：
若目标电路信号线在目标电路模块内的位置为内部信号线，目标版图信号线为目标电路信号线在版图中对应的版图信号线。
在一实施例中，第一处理模块401具体用于：
若目标电路信号线在目标电路模块内的位置为端口信号线，目标版图信号线为版图中位于目标电路模块的外部，且与目标电路模块的对应侧的端口连接的版图信号线。
在一实施例中，装置还包括第一接收模块402；
第一接收模块402具体用于：接收客户端发送的参数获取请求，其中，参数获取请求包括目标电路信号线的标识；
第一处理模块401具体用于：根据目标电路信号线的标识和本地存储的位置关系表确定目标电路信号线在目标电路模块内的位置。
在一实施例中，第一接收模块402具体用于：接收客户端发送的上传请求，其中，上传请求中包括电路原理图对应的版图的寄生网表；
将电路原理图对应的版图的寄生网表存储在本地。
在一实施例中，装置还包括第一发送模块403；
第一处理模块401具体用于在电路原理图中增加表示目标电路信号线的寄生参数的图形数据，以生成标记后的电路原理图对应的数据；
第一发送模块403用于根据标记后的电路原理图对应的数据生成响应消息，并向客户端发送响应消息。
如图14所示，本公开一实施例提供一种寄生参数的获取装置500，装置具体包括：
第二处理模块501，用于获取目标电路信号线的标识；
第二处理模块501还用于根据目标电路信号线的标识生成参数获取请求；
第二发送模块502，用于向服务器发送参数获取请求，其中，参数获取请求用于确定电路原理图中的目标电路信号线在目标电路模块内的位置，目标电路信号线在目标电路模块内的位置和电路原理图对应的版图用于确定目标版图信号线，目标版图信号线和本地存储的版图的寄 生网表用于确定目标版图信号线的寄生电阻和/或电容网络的结构信息；目标版图信号线的寄生电阻和/或电容网络的结构信息用于确定目标电路信号线的寄生参数。
在一实施例中，第二处理模块501还用于：获取版图的寄生网表，并根据寄生网表生成上传请求；
第二发送模块502还用于向服务器发送上传请求，其中，上传请求用于使服务器将版图的寄生网表存储在本地。
在一实施例中，装置还包括第二接收模块503；
第二接收模块503用于接收服务器发送的响应结果，其中，响应结果包括标记后的电路原理图对应的数据；
第二处理模块501用于显示标记后的电路原理图对应的数据。
如图15所示，本公开一实施例提供一种服务器600，服务器600包括第一存储器601和第一处理器602。
其中，第一存储器601用于存储第一处理器可执行的计算机指令；
第一处理器602在执行计算机指令时实现上述实施例中方法中的各个步骤。具体可以参见前述方法实施例中的相关描述。
可选地，上述第一存储器601既可以是独立的，也可以跟第一处理器602集成在一起。当第一存储器601独立设置时，该服务器还包括总线，用于连接第一存储器601和第一处理器602。
如图16所示，本公开一实施例提供一种客户端700，客户端700包括第二存储器701和第二处理器702。
其中，第二存储器701用于存储第二处理器可执行的计算机指令；
第二处理器702在执行计算机指令时实现上述实施例中方法中的各个步骤。具体可以参见前述方法实施例中的相关描述。
可选地，上述第二存储器701既可以是独立的，也可以跟第二处理器702集成在一起。当第二存储器701独立设置时，该客户端还包括总线，用于连接第二存储器701和第二处理器702。
本公开实施例还提供一种计算机可读存储介质，计算机可读存储介质中存储有计算机指令，当处理器执行计算机指令时，实现上述实施例中方法中的各个步骤。
本公开实施例还提供一种计算机程序产品，包括计算机指令，该计算机指令被处理器执行时实现上述实施例中方法中的各个步骤。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本公开旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由下面的权利要求书指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求书来限制。

Claims (15)

  1. 一种寄生参数的获取方法，所述方法应用于服务器，所述方法包括：
    获取电路原理图中目标电路信号线在目标电路模块内的位置；
    根据所述目标电路信号线在所述目标电路模块内的位置和所述电路原理图对应的版图确定目标版图信号线；
    从本地存储的所述版图的寄生网表中提取所述目标版图信号线的寄生电阻和/或电容网络的结构信息；
    根据所述目标版图信号线的寄生电阻和/或电容网络的结构信息确定所述目标电路信号线的寄生参数。
  2. 根据权利要求1所述的寄生参数的获取方法，其中，根据所述目标版图信号线的寄生电阻和/或电容网络的结构信息确定所述目标电路信号线的寄生参数，具体包括：
    根据所述目标版图信号线的寄生电阻和/或电容网络的结构信息搭建等效电路；
    计算所述等效电路的等效电阻和/或等效电容，以获得所述目标电路信号线的寄生参数。
  3. 根据权利要求2所述的寄生参数的获取方法，其中，计算所述等效电路的等效电阻，以获得所述目标电路信号线的寄生参数，具体包括：
    确定所述等效电路的电源输入端，并在向所述电源输入端提供激励电压时检测所述电源输入端的激励电流；
    计算所述激励电压和所述激励电流的比值，以获得所述等效电路的等效阻值，并将所述等效阻值作为所述目标电路信号线的等效寄生电阻的阻值。
  4. 根据权利要求1所述的寄生参数的获取方法，其中，所述寄生电阻和/或电容网络的结构信息包括至少一个寄生电容的电容量；根据所述目标版图信号线的寄生电阻和/或电容网络的结构信息确定所述目标电路信号线的寄生参数，具体包括：
    将所述至少一个寄生电容的电容量叠加后的总电容量作为所述目标电路信号线的等效寄生电容的电容量。
  5. 根据权利要求1所述的寄生参数的获取方法，其中，根据所述目标电路信号线在所述目标电路模块内的位置和所述电路原理图对应的版图确定目标版图信号线，具体包括：
    若所述目标电路信号线在所述目标电路模块内的位置为内部信号线，所述目标版图信号线为所述目标电路信号线在所述版图中对应的版图信号线。
  6. 根据权利要求1所述的寄生参数的获取方法，其中，根据所述目标电路信号线在所述目标电路模块内的位置和所述电路原理图对应的版图确定目标版图信号线，具体包括：
    若所述目标电路信号线在目标电路模块内的位置为端口信号线，所述目标版图信号线为所述版图中位于所述目标电路模块的外部，且与所述目标电路信号线所连接的输入端口或者输出端口连接的版图信号线。
  7. 根据权利要求1至6中任意一项所述的寄生参数的获取方法，其中，获取电路原理图中的目标电路信号线在目标电路模块内的位置，具体包括：
    接收客户端发送的参数获取请求，其中，所述参数获取请求包括目标电路信号线的标识；
    根据所述目标电路信号线的标识和本地存储的位置关系表确定所述目标电路信号线在所述目标电路模块内的位置。
  8. 根据权利要求1至6中任意一项所述的寄生参数的获取方法，其中，在从本地存储的所述版图的寄生网表中提取所述目标版图信号线的寄生电阻和/或电容网络的结构信息之前，所述方法还包括：
    接收客户端发送的上传请求，其中，所述上传请求中包括所述电路原理图对应的版图的寄生网表；
    将所述电路原理图对应的版图的寄生网表存储在本地。
  9. 根据权利要求1至6中任意一项所述的寄生参数的获取方法，其中，在根据所述目标版图信号线的寄生电阻和/或电容网络的结构信息确定所述目标电路信号线的寄生参数之后，所述方法还包括：
    在所述电路原理图中增加表示所述目标电路信号线的寄生参数的图形数据，以生成标记后的电路原理图对应的数据；
    根据所述标记后的电路原理图对应的数据生成响应消息，并向客户端发送所述响应消息。
  10. 一种寄生参数的获取方法，所述方法应用于客户端，所述方法包括：
    获取目标电路信号线的标识；
    根据所述目标电路信号线的标识生成参数获取请求；
    向服务器发送所述参数获取请求，其中，所述参数获取请求用于确定电路原理图中的目标电路信号线在目标电路模块内的位置，所述目标电路信号线在目标电路模块内的位置和所述电路原理图对应的版图用于确定目标版图信号线，所述目标版图信号线和本地存储的所述版图的寄生网表用于确定所述目标版图信号线的寄生电阻和/或电容网络的结构信息；所述目标版图信号线的寄生电阻和/或电容网络的结构信息用于确定所述目标电路信号线的寄生参数。
  11. 根据权利要求10所述的寄生参数的获取方法，其中，所述方法还包括：
    获取所述版图的寄生网表，并根据所述寄生网表生成上传请求；
    向所述服务器发送所述上传请求，其中，所述上传请求用于使所述服务器将所述版图的寄生网表存储在本地。
  12. 根据权利要求10或11所述的寄生参数的获取方法，其中，所述方法还包括：
    接收所述服务器发送的响应结果，其中，所述响应结果包括标记后的电路原理图对应的数据；
    显示所述标记后的电路原理图对应的数据。
  13. 一种服务器，包括：处理器，以及与所述处理器通信连接的存储器；
    所述存储器存储计算机执行指令；
    所述处理器执行所述存储器存储的计算机执行指令，以实现如权利要求1至9中任一项所述的寄生参数的获取方法。
  14. 一种客户端，包括：处理器，以及与所述处理器通信连接的存储器；
    所述存储器存储计算机执行指令；
    所述处理器执行所述存储器存储的计算机执行指令，以实现如权利要求10至12中任一项所述的寄生参数的获取方法。
  15. 一种计算机可读存储介质，所述计算机可读存储介质中存储有计算机执行指令，所述计算机执行指令被处理器执行时用于实现如权利要求1至9任一项，或者10至12中任意一项所述的寄生参数的获取方法。
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CN116881515A (zh) * 2023-09-07 2023-10-13 杭州行芯科技有限公司 对不同算法求解的电容结果进行比较的方法及电子设备
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