WO2023130486A1 - 阵列基板和液晶显示面板 - Google Patents

阵列基板和液晶显示面板 Download PDF

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Publication number
WO2023130486A1
WO2023130486A1 PCT/CN2022/071274 CN2022071274W WO2023130486A1 WO 2023130486 A1 WO2023130486 A1 WO 2023130486A1 CN 2022071274 W CN2022071274 W CN 2022071274W WO 2023130486 A1 WO2023130486 A1 WO 2023130486A1
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WO
WIPO (PCT)
Prior art keywords
substrate
gate
active pattern
line
terminal
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Application number
PCT/CN2022/071274
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English (en)
French (fr)
Inventor
汪丽芳
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武汉华星光电技术有限公司
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Application filed by 武汉华星光电技术有限公司 filed Critical 武汉华星光电技术有限公司
Priority to US17/597,944 priority Critical patent/US12001106B2/en
Priority to JP2022510120A priority patent/JP2024512828A/ja
Priority to KR1020227026233A priority patent/KR20230107469A/ko
Publication of WO2023130486A1 publication Critical patent/WO2023130486A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136222—Colour filters incorporated in the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting

Definitions

  • the present application relates to the field of display technology, in particular to an array substrate and a liquid crystal display panel.
  • the size of the vehicle panel is getting larger and larger.
  • circuits are installed on both sides to input signals to the scanning lines, but since the gate layer is generally formed of molybdenum, the resistance is relatively large, and as the size of the vehicle panel increases, the voltage drop in the lateral direction of the panel will be caused It is extremely serious, resulting in large delay differences in different areas of the panel, and poor display uniformity of the panel.
  • the charging time of each row is shortened and the charging rate is reduced by increasing the interval time between each row of level transmission, or by increasing the number of output terminals and driving chip data, but this The design will lead to a large space occupation, which cannot meet the requirements.
  • the channels of the components will be made smaller, which will further increase the distortion of the scanning signal.
  • the existing display device has the technical problem of distortion of the scanning signal of the display device caused by the high impedance of the gate layer.
  • Embodiments of the present application provide an array substrate and a liquid crystal display panel, which are used to alleviate the technical problem of distortion of scanning signals of the display device caused by the high impedance of the gate layer in the existing display device.
  • An embodiment of the present application provides an array substrate, the array substrate includes:
  • a gate insulating layer disposed on a side of the active layer away from the substrate
  • a first metal layer disposed on a side of the active layer away from the substrate, the first metal layer is formed with a gate;
  • a second metal layer disposed on a side of the interlayer insulating layer away from the first metal layer, the second metal layer is formed with a source, a drain and a scan line;
  • the array substrate further includes a data line
  • the data line includes a first portion disposed on the first metal layer and a second portion disposed on the second metal layer, between the scan line and the data line At the intersection of the lines, the second part of the data line is connected to the first part of the data line through the interlayer insulating layer, and the scanning line is connected to the gate through the interlayer insulating layer.
  • the active layer includes an active pattern
  • the projection of the active pattern on the substrate is located on one side of the projection of the scan line on the substrate, and the active pattern The projection of the source pattern on the substrate does not coincide with the projection of the scan line on the substrate.
  • the active pattern includes a channel region and a doped region, and the active pattern located in the channel region is arranged along a horizontal direction.
  • a gap is formed on the side of the scan line close to the drain, and the width of the scan line at the region where the drain is connected to the active pattern is smaller than that of the scan line at the area where the drain is connected to the active pattern. The width of the region where the source electrode is connected to the active pattern.
  • the distance between the part of the active pattern on the side where the source is connected to the active pattern and the scanning line is greater than that between the drain and the active pattern.
  • the active pattern connects the distance between the portion of the active pattern on one side and the scan line.
  • the active pattern includes a channel region and a doped region, and in the channel region, the projection of the active pattern on the substrate is the same as that of the gate on the substrate In the doped region, the source and the drain are connected to the active pattern through the interlayer insulating layer and the gate insulating layer.
  • the gate includes a first gate portion and a second gate portion, the projection of the first gate portion on the substrate is located on the substrate where the scan line is In the projection of the first gate part, the width of the first gate part is smaller than the width of the scan line, and the projection of the second gate part on the substrate is different from the projection of the active pattern on the substrate There is overlap.
  • At least one via hole is formed in the interlayer insulating layer in a region corresponding to the first gate portion, and the first gate portion is connected to the scan line through the via hole.
  • the via hole includes a first via hole and a second via hole
  • the first gate is partially connected to the scan line through the first via hole
  • the first gate A part passes through the second via hole and is connected to the scan line.
  • the second gate portion includes a first switch portion and a second switch portion, the first switch portion and the second switch portion are connected to the first gate portion, and the The first switch part is insulated from the second switch part.
  • an embodiment of the present application provides a liquid crystal display panel
  • the liquid crystal display panel includes an array substrate, a color filter substrate, and a liquid crystal layer disposed between the array substrate and the color filter substrate, and the array substrate includes:
  • a gate insulating layer disposed on a side of the active layer away from the substrate
  • a first metal layer disposed on a side of the active layer away from the substrate, the first metal layer is formed with a gate;
  • a second metal layer disposed on a side of the interlayer insulating layer away from the first metal layer, the second metal layer is formed with a source, a drain and a scan line;
  • the array substrate further includes a data line
  • the data line includes a first portion disposed on the first metal layer and a second portion disposed on the second metal layer, between the scan line and the data line At the intersection of the lines, the second part of the data line is connected to the first part of the data line through the interlayer insulating layer, and the scanning line is connected to the gate through the interlayer insulating layer.
  • the active layer includes an active pattern
  • the projection of the active pattern on the substrate is located on one side of the projection of the scan line on the substrate, and the active pattern The projection of the source pattern on the substrate does not coincide with the projection of the scan line on the substrate.
  • the active pattern includes a channel region and a doped region, and the active pattern located in the channel region is arranged along a horizontal direction.
  • the distance between the part of the active pattern on the side where the source is connected to the active pattern and the scanning line is greater than that between the drain and the active pattern.
  • the active pattern connects the distance between the portion of the active pattern on one side and the scan line.
  • the active pattern includes a channel region and a doped region, and in the channel region, the projection of the active pattern on the substrate is the same as that of the gate on the substrate In the doped region, the source and the drain are connected to the active pattern through the interlayer insulating layer and the gate insulating layer.
  • the gate includes a first gate portion and a second gate portion, the projection of the first gate portion on the substrate is located on the substrate where the scan line is In the projection of the first gate part, the width of the first gate part is smaller than the width of the scan line, and the projection of the second gate part on the substrate is different from the projection of the active pattern on the substrate There is overlap.
  • At least one via hole is formed in the interlayer insulating layer in a region corresponding to the first gate portion, and the first gate portion is connected to the scan line through the via hole.
  • the via hole includes a first via hole and a second via hole
  • the first gate is partially connected to the scan line through the first via hole
  • the first gate A part passes through the second via hole and is connected to the scan line.
  • the second gate portion includes a first switch portion and a second switch portion, the first switch portion and the second switch portion are connected to the first gate portion, and the The first switch part is insulated from the second switch part.
  • the first part of the data line includes a first terminal, a first connection line and a second terminal
  • the second part of the data line includes a second connection line, a third terminal and a fourth terminal
  • the first connection Both ends of the line are connected to the first terminal and the second terminal
  • the third terminal is connected to the second connection line
  • the first terminal and the third terminal pass through the interlayer insulating layer
  • the fourth terminal is connected to the second connection line
  • the second terminal and the fourth terminal are connected through a via hole in the interlayer insulating layer
  • the third terminal is connected to the substrate
  • the projected area on the substrate is greater than or equal to the projected area of the first terminal on the substrate
  • the projected area of the fourth terminal on the substrate is greater than or equal to the projected area of the second terminal on the substrate projected area.
  • the present application provides an array substrate and a liquid crystal display panel;
  • the array substrate includes a substrate, an active layer, a gate insulating layer, a first metal layer, an interlayer insulating layer and a second metal layer, and the active layer is disposed on the substrate
  • the gate insulating layer is arranged on the side of the active layer away from the substrate
  • the first metal layer is arranged on the side of the active layer away from the substrate
  • the first metal layer is formed with a gate
  • the interlayer insulating layer is arranged on The first metal layer is away from the side of the gate insulating layer
  • the second metal layer is arranged on the side of the interlayer insulating layer away from the first metal layer
  • the second metal layer is formed with source electrodes, drain electrodes and scanning lines, wherein the array
  • the substrate also includes a data line.
  • the data line includes a first part disposed on the first metal layer and a second part disposed on the second metal layer. At the junction of the scan line and the data line, the second part of the data line passes through the interlayer
  • the insulating layer is connected to the first part of the data line, and the gate is connected to the scanning line through the interlayer insulating layer.
  • the width of the channel of the thin film transistor is not related to the width of the scanning line, so the width of the scanning line can be increased to reduce the width of the scanning line.
  • the scanning line is formed by the second metal layer whose impedance is smaller than the first metal layer, which further reduces the impedance of the scanning line, and can make the channel width of the thin film transistor smaller, improve the charging efficiency of the array substrate, and reduce The difference in distortion that occurs in the scanned signal.
  • FIG. 1 is a schematic diagram of a conventional liquid crystal display device.
  • FIG. 2 is a waveform diagram of scanning signals from two sides to the middle area of a conventional liquid crystal display device.
  • FIG. 3 is a schematic diagram of a first type of array substrate provided by an embodiment of the present application.
  • FIG. 4 is a second schematic view of the array substrate provided by the embodiment of the present application.
  • FIG. 5 is a third schematic diagram of the array substrate provided by the embodiment of the present application.
  • FIG. 6 is a schematic diagram of a liquid crystal display panel provided by an embodiment of the present application.
  • the existing display device will have a structure with double gates and an "n"-shaped active pattern.
  • the display device includes an active layer, a gate layer 12, and a source-drain layer 13.
  • the active layer includes polysilicon 111 and doping ions 112.
  • the doping of polysilicon 111 is realized by doping ions 112.
  • the source and drain layers 13 are connected to the active layer through the via holes in the interlayer insulating layer.
  • the connection between the electrode and the active pattern, the connection between the source and drain electrodes and the pixel electrode is indicated by reference numeral 15, and the via hole of the planarization layer and the passivation layer is indicated by reference numeral 16.
  • the channel length L1 of the thin film transistor will be designed to be small, and the channel length is also the width of the scan line, resulting in the width of the scan line It will also be smaller. According to the resistance formula, the smaller the width of the scan line, the higher the impedance, resulting in a larger voltage drop on the scan line and distortion of the scan signal.
  • the horizontal length is much greater than the vertical length
  • the GOA (gate on array, gate drive circuit) circuit Set on the left and right sides of the display device
  • the existing display device has the technical problem of distortion of the scanning signal of the display device caused by the high impedance of the gate layer.
  • an embodiment of the present application provides an array substrate, and the array substrate 2 includes:
  • an active layer 215 disposed on one side of the substrate 211;
  • a gate insulating layer 216 disposed on a side of the active layer 215 away from the substrate 211;
  • the first metal layer 217 is disposed on the side of the active layer 215 away from the substrate 211, and the first metal layer 217 is formed with a gate 217d;
  • the second metal layer 219 is disposed on the side of the interlayer insulating layer 218 away from the first metal layer 217, and the second metal layer 219 is formed with a source electrode 219e, a drain electrode 219f and a scanning line 219c;
  • the array substrate 2 further includes a data line 32, and the data line 32 includes a first portion 321 disposed on the first metal layer 217 and a second portion 322 disposed on the second metal layer 219.
  • the junction of the scanning line 219c and the data line 32, the second part 322 of the data line 32 passes through the interlayer insulating layer 218 and is connected to the first part 321 of the data line 32, and the scanning line 219c It is connected to the gate 217d through the interlayer insulating layer 218 .
  • An embodiment of the present application provides an array substrate.
  • the width of the channel of the thin film transistor is not related to the width of the scan line, so it can Increase the width of the scanning line to reduce the impedance of the scanning line, and at the same time, the scanning line is formed by the second metal layer whose impedance is smaller than that of the first metal layer, which further reduces the impedance of the scanning line, and can make the channel width of the thin film transistor smaller , improve the charging efficiency of the array substrate, and reduce the distortion difference of the scanning signal.
  • each film layer is schematically illustrated by the exploded view in FIG. 4 .
  • Each film layer The setting and connection between are described in detail in the following embodiments.
  • the active layer 215 includes an active pattern, and the projection of the active pattern on the substrate 211 is located at the scanning line 219c at the One side of the projection on the substrate 211 , and the projection of the active pattern on the substrate 211 does not coincide with the projection of the scan line 219 c on the substrate 211 .
  • the line width of the scan line is not related to the channel length of the thin film transistor, and the channel length of the thin film transistor needs to be set smaller to increase the charging rate and reduce the coupling capacitance, which can be used for
  • the channel length of the thin film transistor is designed without affecting the width of the scan line.
  • the line width of the scan line can be increased, and the impedance of the scan line can be reduced, so that while reducing the impedance of the scan line, the pixel resolution can be improved.
  • the charging rate, while the coupling capacitance of the scan line can be reduced according to the design of the scan line and the data line.
  • the active pattern includes a channel region and a doped region, and the active pattern located in the channel region is arranged along a horizontal direction.
  • the embodiment of the present application makes the channel length of the thin film transistor independent of the line width of the scanning line, so the active pattern can be made The pattern is set horizontally to increase the line width of the scan line and reduce the voltage drop of the scan line.
  • the part of the active pattern of the channel region is represented by the symbol 215b
  • the part of the active pattern of the doped region is represented by the symbol 215a
  • the part of the active pattern is represented by the symbol 215c Represents the doped material of the active pattern
  • the undoped active pattern is represented by the reference numeral 215b, therefore, the active pattern of the channel region and the doped region can be obtained through the doped material and the undoped active pattern .
  • the lightly doped region is not shown in the drawings of the embodiments of the present application.
  • the doped region refers to the heavily doped region, but in actual design, there will be a lightly doped region, and the lightly doped region is arranged in the heavily doped region and the channel. Between regions, details will not be repeated in the following embodiments.
  • the doped region 215a includes a first doped region, a second doped region and a third doped region arranged in sequence
  • the channel region 215b includes a first channel a channel region and a second channel region
  • the first channel region is located between the first doped region and the second doped region
  • the second channel region is located in the second doped region and between the third doped region.
  • the channel length of the thin film transistor and the line length of the scanning line Width is not related, the active pattern can be arranged horizontally, so that the doped region and the channel region are arranged horizontally in sequence, and the doped region in the middle can improve the conductivity of the active pattern, reduce power consumption, and increase the line width of the scanning line , to reduce the voltage drop across the scan line.
  • the scan line 219c is formed with a gap 301 on a side close to the drain 219f, and the scan line 219c is formed between the drain 219f and the drain 219f.
  • the width of the region where the active pattern is connected is smaller than the width of the region where the scan line 219c is connected to the source electrode 219e and the active pattern.
  • a gap is formed on the scanning line on the side where the drain is connected to the pixel electrode, so that there is a certain distance between the scanning line and the drain, so as to avoid a short circuit between the drain and the scanning line and avoid formation of a gap between the scanning line and the pixel electrode. Parasitic capacitance affects the normal display of display devices.
  • the part of the active pattern on the side where the source electrode 219e is connected to the active pattern is connected to the scanning line 219c
  • the distance between them is greater than the distance between the part of the active pattern on the side where the drain electrode 219f is connected to the active pattern and the scanning line 219c.
  • the distance between the part of the active pattern on the side where the source is connected to the active pattern and the scanning line larger than the distance between the part of the active pattern on the side where the drain is connected to the active pattern and the scanning line, so that When the source is connected to the data line, the area where the data line is connected from the second metal layer to the first metal layer can be reserved to avoid causing the first metal layer to be damaged when the data line is connected from the second metal layer to the first metal layer. It is connected to the active layer, or there is a short circuit problem with the scan line, which affects the normal display.
  • the above embodiment is described in detail by taking the source electrode connected to the data line as an example, and the data line on the side of the source electrode to realize the transfer line arrangement of the first metal layer and the second metal layer.
  • the embodiment of the present application is not limited thereto.
  • the data line is located on the side of the drain for wiring connection between the first metal layer and the second metal layer, the part of the active pattern on the side of the drain and the part of the scan line can be connected accordingly. The distance between them is greater than the distance between the part of the active pattern on the source side and the scan line.
  • the active pattern includes a channel region and a doped region, and in the channel region, the projection of the active pattern on the substrate is the same as that of the gate on the substrate. Projections on the bottom overlap, and in the doped region, the source and the drain are connected to the active pattern through the interlayer insulating layer and the gate insulating layer.
  • the switching function of the gate of the thin film transistor of the array substrate is realized, and the source and drain are connected to the doped region to realize the switching function of the array substrate.
  • the signal transmission function of the thin film transistor so that when an electrical signal is input, the transmission of the signal can be controlled through the thin film transistor.
  • the gate 217d includes a first gate portion 311 and a second gate portion 312, and the first gate portion 311 is formed on the substrate 211 projection on the substrate 211 within the projection of the scan line 219c, the width of the first gate portion 311 is smaller than the width of the scan line 219c, and the second gate portion 312 is in the The projection on the substrate 211 overlaps with the projection of the active pattern on the substrate 211 .
  • the width of the scan line can not be affected by the gate, so that the width of the scan line is larger than that of the second gate.
  • the width of the gate part reduces the impedance of the scan line and the voltage drop of the scan line, and the first gate part and the second gate part can realize the switching function.
  • the gate includes a first gate part and a second gate part, the projection of the first gate part on the substrate is located on the substrate where the scan line is In the projection on the first gate part, the width of the first gate part is equal to the width of the scan line, and the projection of the second gate part on the substrate is the same as that of the active pattern on the substrate The projections overlap.
  • the width of the first gate portion is equal to the width of the scan line such that in When increasing the width of the scan line to reduce the impedance of the scan line, the connection stability between the gate and the scan line can also be increased by increasing the area of the gate, and the impedance at the connection between the gate and the scan line can be reduced, and Since the increased part of the gate does not exceed the width of the scan line, the size of the pixel will not be increased.
  • At least one via hole is formed in the interlayer insulating layer, and the first gate part passes through the via hole and the scanning line is connected to .
  • the interlayer insulation can be directly passed through the overlapping part of the gate and the scan line, that is, the overlapping part of the first gate part and the scan line
  • a via hole is provided in the layer, so that the first gate part is connected to the scanning line, so that the opening and closing of the gate can be controlled by the signal transmitted on the scanning line, so as to realize the switching function of the thin film transistor.
  • the via holes include a first via hole 45 and a second via hole 46, and the first gate portion 311 passes through the first via hole.
  • the hole 45 is connected to the scan line 219c
  • the first gate portion 311 is connected to the scan line 219c through the second via hole 46 .
  • the above embodiment has been described in detail by taking the via hole formed in the interlayer insulating layer as an example including the first via hole and the second via hole, but the embodiment of the present application is not limited thereto, for example, in order to further increase the Connectivity, the third via hole can be set, so that the first gate part of the gate and the scan line are connected through the first via hole, the second via hole and the third via hole, and the gate and scan lines can be further improved if necessary.
  • the vias can be further increased to increase the connectivity between the gate and the scanning lines.
  • the second gate part 312 includes a first switch part 312a and a second switch part 312b, and the first switch part 312a and the second switch part 312a
  • the part 312b is connected to the first gate part 311, and the first switch part 312a is insulated from the second switch part 312b.
  • FIG. 4 is an exploded view of the active layer 215 , the first metal layer 217 and the second metal layer 219
  • FIG. 5 is a top view of each film layer of the array substrate.
  • the active layer 215 includes an undoped active pattern and a doped material 215c of the active pattern
  • the first metal layer 217 includes the first portion 321 of the data line 32 and the gate 217d
  • the second metal layer 219 includes the second part 322 of the data line 32, the source electrode 219e, the drain electrode 219f and the scanning line 219c, as shown in FIG.
  • the data line 32 is formed by using the first metal layer 217 .
  • the first part 321 of the data line 32 includes the first terminal 217a, the first connecting line 217b and the second terminal 217c
  • the second part 322 of the data line 32 includes the second connecting line 219a, the third terminal 219b and the fourth terminal 219d
  • the first terminal 217a and the third terminal 219b are connected through the via hole in the interlayer insulating layer
  • the second terminal 217c and the fourth terminal 219d are connected through the via hole in the interlayer insulating layer.
  • the connecting part of the first terminal and the third terminal, the connecting part of the second terminal and the fourth terminal, in Fig. 5, covers the first terminal, and the fourth terminal covers the second terminal, so the first terminal is not shown in Fig. 5 A terminal and a second terminal.
  • the source electrode 219e and the drain electrode 219f are connected to the active pattern through the via holes in the interlayer insulating layer and the gate insulating layer. As shown in FIG. part.
  • FIG. 5 The connection part with the pixel electrode.
  • the scan signal when the scan signal is input, the scan signal will be conducted from the scan line 219c of the second metal layer, and then passed to the gate 217d through the connection 45 and 46 between the scan line 219c and the gate 217d , turn on the gate 217d, and when the data line inputs a data signal, the data signal will be conducted from the second connection line 219a of the data line 32 of the second metal layer to the third terminal 219b, and then be conducted from the third terminal 219b to the first Terminal 217a, then conducted from the first terminal 217a to the first connection line 217b, then conducted from the first connection line 217b to the second terminal 217c, then conducted from the second terminal 217c to the fourth terminal 219d, and then from the fourth terminal 219d Conducted to the second connection line 219a, and then conducted from the second connection line 219a to the source 219e, so as to input the data signal.
  • the scan signal since the scan signal is routed through the second metal layer
  • the first part of the data line includes a first terminal, a first connection line and a second terminal
  • the second part of the data line includes a second connection line, a third terminal and a fourth terminal, so Both ends of the first connection line are connected to the first terminal and the second terminal, the third terminal is connected to the second connection line, and the first terminal and the third terminal pass through the layer
  • the via hole in the interlayer insulating layer is connected
  • the fourth terminal is connected to the second connection line
  • the second terminal and the fourth terminal are connected through the via hole in the interlayer insulating layer
  • the third terminal is connected to the via hole in the interlayer insulating layer.
  • the projected area on the substrate is greater than or equal to the projected area of the first terminal on the substrate, and the projected area of the fourth terminal on the substrate is greater than or equal to the projected area of the second terminal on the substrate.
  • the projected area on the substrate By making the projected area of the third terminal on the substrate greater than or equal to the projected area of the first terminal on the substrate, the projected area of the fourth terminal on the substrate is greater than or equal to the projected area of the second terminal on the substrate , when the first part of the data line and the second part of the data line are connected through the first terminal, the second terminal, the third terminal and the fourth terminal, the first terminal and the second terminal can be connected with the third terminal and the fourth terminal.
  • the whole surface is connected to improve the connection effect and reduce the impedance.
  • the resistance per unit area of the first metal layer is smaller than the resistance per unit area of the second metal layer.
  • the resistance of the material of the second metal layer is smaller than the resistance of the material of the first metal layer.
  • the scan lines of the pixels located in the same row are integrally formed.
  • scanning lines of multiple pixels can be formed at the same time, so that the scanning lines of pixels in the same row are all formed using the second metal layer, reducing the delay of scanning signals from both sides to the middle area.
  • the array substrate 2 further includes a light-shielding layer 212 , a blocking layer 213 and a buffer layer 214 , and the light-shielding layer 212 is correspondingly disposed in the area where the active layer 215 is disposed.
  • the array substrate 2 further includes a planarization layer 220 , a first electrode layer 221 , a passivation layer 222 and a second electrode layer 223 , and the source and drain layers 219 pass through the planarization layer 220 .
  • the via holes in the passivation layer 220 and the passivation layer 222 are connected to the second electrode layer 223 .
  • both sides of the first electrode layer 221 are disconnected in FIG. 3, but in practice, in order to insulate the first electrode layer and the second electrode layer, the first electrode layer will form a via hole, blunt The layer is filled into the via hole to separate the first electrode layer and the second electrode layer, the second electrode layer is connected to the source and drain layers through the passivation layer and the planarization layer, and the first electrode layer is set on the entire surface, only forming There are vias, not a multi-segment setup.
  • the embodiment of the present application provides a liquid crystal display panel, which includes an array substrate, a color filter substrate 52 and an array substrate arranged between the array substrate and the color filter substrate 52.
  • the liquid crystal layer 51, the array substrate includes:
  • an active layer 215 disposed on one side of the substrate 211;
  • a gate insulating layer 216 disposed on a side of the active layer 215 away from the substrate 211;
  • the first metal layer 217 is disposed on the side of the active layer 215 away from the substrate 211, and the first metal layer 217 is formed with a gate 217d;
  • the second metal layer 219 is disposed on the side of the interlayer insulating layer 218 away from the first metal layer 217, and the second metal layer 219 is formed with a source electrode 219e, a drain electrode 219f and a scanning line 219c;
  • the array substrate 2 further includes a data line 32, and the data line 32 includes a first portion 321 disposed on the first metal layer 217 and a second portion 322 disposed on the second metal layer 219.
  • the junction of the scanning line 219c and the data line 32, the second part 322 of the data line 32 passes through the interlayer insulating layer 218 and is connected to the first part 321 of the data line 32, and the scanning line 219c It is connected to the gate 217d through the interlayer insulating layer 218 .
  • An embodiment of the present application provides a liquid crystal display panel.
  • the liquid crystal display panel includes an array substrate, a color filter substrate, and a liquid crystal layer disposed between the array substrate and the color filter substrate.
  • the active layer includes an active pattern, and the projection of the active pattern on the substrate is located at the position of the projection of the scanning line on the substrate. One side, and the projection of the active pattern on the substrate does not coincide with the projection of the scan line on the substrate.
  • the active pattern in the liquid crystal display panel, includes a channel region and a doped region, and the active pattern located in the channel region is arranged along a horizontal direction.
  • the distance between the part of the active pattern on the side where the source electrode is connected to the active pattern and the scanning line is, greater than the distance between the scan line and the part of the active pattern on the side where the drain electrode is connected to the active pattern.
  • the active pattern in the liquid crystal display panel, includes a channel region and a doped region, and in the channel region, the projection of the active pattern on the substrate is consistent with the The projection of the gate on the substrate overlaps, and in the doped region, the source and the drain pass through the interlayer insulating layer and the gate insulating layer to connect to the active pattern.
  • the gate in the liquid crystal display panel, includes a first gate part and a second gate part, and the projection of the first gate part on the substrate is located at the scanning In the projection of the line on the substrate, the width of the first gate part is smaller than the width of the scanning line, and the projection of the second gate part on the substrate is the same as that of the active pattern.
  • the projections on the substrate overlap.
  • the liquid crystal display panel in the region corresponding to the first gate part, at least one via hole is formed in the interlayer insulating layer, and the first gate part passes through the via hole. holes for the scanline connections.
  • the via hole includes a first via hole and a second via hole, and the first gate part is connected to the scanning line through the first via hole, And the first gate part is connected to the scan line through the second via hole.
  • the second gate part includes a first switch part and a second switch part, and the first switch part and the second switch part are connected with the first gate The pole parts are connected, and the first switch part is insulated from the second switch part.
  • the first part of the data line includes a first terminal, a first connection line and a second terminal
  • the second part of the data line includes a second connection line, a third terminal and a fourth terminal.
  • terminal the two ends of the first connection line are connected to the first terminal and the second terminal
  • the third terminal is connected to the second connection line
  • the first terminal and the third terminal pass through
  • the via hole in the interlayer insulating layer is connected
  • the fourth terminal is connected to the second connection line
  • the second terminal and the fourth terminal are connected through the via hole in the interlayer insulating layer
  • the first The projected area of the three terminals on the substrate is larger than or equal to the projected area of the first terminal on the substrate
  • the projected area of the fourth terminal on the substrate is larger than or equal to the projected area of the second terminal.
  • the projected area of the terminal on the substrate is larger than or equal to the projected area of the second terminal.
  • the resistance per unit area of the first metal layer is smaller than the resistance per unit area of the second metal layer.
  • Embodiments of the present application provide an array substrate and a liquid crystal display panel;
  • the array substrate includes a substrate, an active layer, a gate insulating layer, a first metal layer, an interlayer insulating layer, and a second metal layer, and the active layer is disposed on On one side of the substrate, the gate insulating layer is arranged on the side of the active layer away from the substrate, the first metal layer is arranged on the side of the active layer away from the substrate, the first metal layer is formed with a gate, and the interlayer insulating layer The first metal layer is arranged on the side away from the gate insulating layer, the second metal layer is arranged on the side of the interlayer insulating layer away from the first metal layer, and the second metal layer is formed with a source electrode, a drain electrode and a scanning line, wherein , the array substrate further includes a data line, the data line includes a first portion disposed on the first metal layer and a second portion disposed on the second metal layer, at the junction of the scan line and
  • the width of the channel of the thin film transistor is not related to the width of the scanning line, so the width of the scanning line can be increased to reduce the width of the scanning line.
  • the scanning line is formed by the second metal layer whose impedance is smaller than the first metal layer, which further reduces the impedance of the scanning line, and can make the channel width of the thin film transistor smaller, improve the charging efficiency of the array substrate, and reduce The difference in distortion that occurs in the scanned signal.

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Abstract

一种阵列基板（2）和液晶显示面板；该阵列基板（2）通过将扫描线（219c）设置在第二金属层（219），使薄膜晶体管的通道的宽度与扫描线（219c）的宽度并不关联，因此可以增加扫描线（219c）的宽度，且第二金属层（219）的阻抗较小，减小了扫描线（219c）的阻抗，且薄膜晶体管的通道的宽度较小，提高阵列基板（2）的充电效率，且减小扫描信号出现的失真差异。

Description

阵列基板和液晶显示面板 技术领域
本申请涉及显示技术领域，尤其是涉及一种阵列基板和液晶显示面板。
 背景技术
随着车载面板技术的发展，车载面板的尺寸越来越大。现有面板的驱动过程中，会在两侧设置电路对扫描线输入信号，但由于栅极层一般采用钼形成，电阻较大，随着车载面板的尺寸增大，会导致面板横向的压降极其严重，导致面板不同区域的延迟差异较大，面板的显示均一性较差。针对这一问题，现有显示器件中会通过增加每行级传之间的间隔时间，导致每行的充电时间变短，充电率降低，或者通过增加输出端子数量和驱动芯片数据，但这一设计会导致空间占用较大，无法满足需求，同时，为了降低漏电问题，会使得元器件的通道较小，这会进一步增加扫描信号的失真。
所以，现有显示器件存在栅极层的阻抗较大所导致的显示器件的扫描信号失真的技术问题。
 技术问题
本申请实施例提供一种阵列基板和液晶显示面板，用以缓解现有显示器件存在栅极层的阻抗较大所导致的显示器件的扫描信号失真的技术问题。
 技术解决方案
为解决上述问题，本申请提供的技术方案如下：
本申请实施例提供一种阵列基板，该阵列基板包括：
衬底；
有源层，设置于所述衬底一侧；
栅极绝缘层，设置于所述有源层远离所述衬底的一侧；
第一金属层，设置于所述有源层远离所述衬底的一侧，所述第一金属层形成有栅极；
层间绝缘层，设置于所述第一金属层远离所述栅极绝缘层的一侧；
第二金属层，设置于所述层间绝缘层远离所述第一金属层的一侧，所述第二金属层形成有源极、漏极和扫描线；
其中，所述阵列基板还包括数据线，所述数据线包括设置于所述第一金属层的第一部分和设置于所述第二金属层的第二部分，在所述扫描线与所述数据线的交界处，所述数据线的第二部分穿过所述层间绝缘层与所述数据线的第一部分连接，所述扫描线穿过所述层间绝缘层与所述栅极连接。
在一些实施例中，所述有源层包括有源图案，所述有源图案在所述衬底上的投影位于所述扫描线在所述衬底上的投影的一侧，且所述有源图案在所述衬底上的投影与所述扫描线在所述衬底上的投影不重合。
在一些实施例中，所述有源图案包括沟道区和掺杂区，位于所述沟道区的有源图案沿水平方向设置。
在一些实施例中，所述扫描线在靠近所述漏极的一侧形成有缺口，所述扫描线在所述漏极与所述有源图案连接的区域的宽度，小于所述扫描线在所述源极与所述有源图案连接的区域的宽度。
在一些实施例中，在所述掺杂区，位于所述源极与所述有源图案连接一侧的有源图案的部分与所述扫描线之间的距离，大于位于所述漏极与所述有源图案连接一侧的有源图案的部分与所述扫描线之间的距离。
在一些实施例中，所述有源图案包括沟道区和掺杂区，在所述沟道区，所述有源图案在所述衬底上的投影与所述栅极在所述衬底上的投影存在重叠，在所述掺杂区，所述源极和所述漏极穿过所述层间绝缘层和所述栅极绝缘层连接至所述有源图案。
在一些实施例中，所述栅极包括第一栅极部分和第二栅极部分，所述第一栅极部分在所述衬底上的投影、位于所述扫描线在所述衬底上的投影内，所述第一栅极部分的宽度小于所述扫描线的宽度，所述第二栅极部分在所述衬底上的投影与所述有源图案在所述衬底上的投影存在重叠。
在一些实施例中，在所述第一栅极部分对应的区域，所述层间绝缘层形成有至少一个过孔，所述第一栅极部分穿过所述过孔所述扫描线连接。
在一些实施例中，所述过孔包括第一过孔和第二过孔，所述第一栅极部分穿过所述第一过孔与所述扫描线连接，且所述第一栅极部分穿过所述第二过孔与所述扫描线连接。
在一些实施例中，所述第二栅极部分包括第一开关部分和第二开关部分，所述第一开关部分和所述第二开关部分与所述第一栅极部分连接，且所述第一开关部分与所述第二开关部分之间绝缘设置。
同时，本申请实施例提供一种液晶显示面板，该液晶显示面板包括阵列基板、彩膜基板和设置于所述阵列基板与所述彩膜基板之间的液晶层，所述阵列基板包括：
衬底；
有源层，设置于所述衬底一侧；
栅极绝缘层，设置于所述有源层远离所述衬底的一侧；
第一金属层，设置于所述有源层远离所述衬底的一侧，所述第一金属层形成有栅极；
层间绝缘层，设置于所述第一金属层远离所述栅极绝缘层的一侧；
第二金属层，设置于所述层间绝缘层远离所述第一金属层的一侧，所述第二金属层形成有源极、漏极和扫描线；
其中，所述阵列基板还包括数据线，所述数据线包括设置于所述第一金属层的第一部分和设置于所述第二金属层的第二部分，在所述扫描线与所述数据线的交界处，所述数据线的第二部分穿过所述层间绝缘层与所述数据线的第一部分连接，所述扫描线穿过所述层间绝缘层与所述栅极连接。
在一些实施例中，所述有源层包括有源图案，所述有源图案在所述衬底上的投影位于所述扫描线在所述衬底上的投影的一侧，且所述有源图案在所述衬底上的投影与所述扫描线在所述衬底上的投影不重合。
在一些实施例中，所述有源图案包括沟道区和掺杂区，位于所述沟道区的有源图案沿水平方向设置。
在一些实施例中，在所述掺杂区，位于所述源极与所述有源图案连接一侧的有源图案的部分与所述扫描线之间的距离，大于位于所述漏极与所述有源图案连接一侧的有源图案的部分与所述扫描线之间的距离。
在一些实施例中，所述有源图案包括沟道区和掺杂区，在所述沟道区，所述有源图案在所述衬底上的投影与所述栅极在所述衬底上的投影存在重叠，在所述掺杂区，所述源极和所述漏极穿过所述层间绝缘层和所述栅极绝缘层连接至所述有源图案。
在一些实施例中，所述栅极包括第一栅极部分和第二栅极部分，所述第一栅极部分在所述衬底上的投影、位于所述扫描线在所述衬底上的投影内，所述第一栅极部分的宽度小于所述扫描线的宽度，所述第二栅极部分在所述衬底上的投影与所述有源图案在所述衬底上的投影存在重叠。
在一些实施例中，在所述第一栅极部分对应的区域，所述层间绝缘层形成有至少一个过孔，所述第一栅极部分穿过所述过孔所述扫描线连接。
在一些实施例中，所述过孔包括第一过孔和第二过孔，所述第一栅极部分穿过所述第一过孔与所述扫描线连接，且所述第一栅极部分穿过所述第二过孔与所述扫描线连接。
在一些实施例中，所述第二栅极部分包括第一开关部分和第二开关部分，所述第一开关部分和所述第二开关部分与所述第一栅极部分连接，且所述第一开关部分与所述第二开关部分之间绝缘设置。
在一些实施例中，数据线的第一部分包括第一端子、第一连接线和第二端子，数据线的第二部分包括第二连接线、第三端子和第四端子，所述第一连接线的两端与所述第一端子和第二端子连接，所述第三端子与所述第二连接线连接，所述第一端子与所述第三端子穿过所述层间绝缘层的过孔连接，所述第四端子与所述第二连接线连接，所述第二端子和所述第四端子穿过层间绝缘层的过孔连接，所述第三端子在所述衬底上的投影面积大于或者等于所述第一端子在所述衬底上的投影面积，所述第四端子在所述衬底上的投影面积大于或者等于所述第二端子在所述衬底上的投影面积。
 有益效果
本申请提供一种阵列基板和液晶显示面板；该阵列基板包括衬底、有源层、栅极绝缘层、第一金属层、层间绝缘层和第二金属层，有源层设置于衬底一侧，栅极绝缘层设置于有源层远离衬底的一侧，第一金属层设置于有源层远离衬底的一侧，第一金属层形成有栅极，层间绝缘层设置于第一金属层远离栅极绝缘层的一侧，第二金属层设置于层间绝缘层远离第一金属层的一侧，第二金属层形成有源极、漏极和扫描线，其中，阵列基板还包括数据线，数据线包括设置于第一金属层的第一部分和设置于第二金属层的第二部分，在扫描线与数据线的交界处，数据线的第二部分穿过层间绝缘层与数据线的第一部分连接，栅极穿过层间绝缘层与扫描线连接。本申请通过将扫描线设置在第二金属层，则在设置薄膜晶体管的通道时，薄膜晶体管的通道的宽度与扫描线的宽度并不关联，因此可以增加扫描线的宽度以减小扫描线的阻抗，同时扫描线采用阻抗小于第一金属层的第二金属层形成，进一步减小了扫描线的阻抗，且可以使薄膜晶体管的通道的宽度较小，提高阵列基板的充电效率，且减小扫描信号出现的失真差异。
 附图说明
下面结合附图，通过对本申请的具体实施方式详细描述，将使本申请的技术方案及其它有益效果显而易见。
图1为现有液晶显示器件的示意图。
图2为现有液晶显示器件的两侧至中间区域的扫描信号的波形图。
图3为本申请实施例提供的阵列基板的第一种示意图。
图4为本申请实施例提供的阵列基板的第二种示意图。
图5为本申请实施例提供的阵列基板的第三种示意图。
图6为本申请实施例提供的液晶显示面板的示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
如图1所示，现有显示器件为了降低漏电问题，会设置双栅、有源图案为“n”字型的结构，显示器件包括有源层、栅极层12、源漏极层13，有源层包括多晶硅111和掺杂离子112，通过掺杂离子112实现多晶硅111的掺杂，源漏极层13通过层间绝缘层的过孔与有源层连接，具体以标号14表示源漏极和有源图案的连接，以标号15表示源漏极和像素电极的连接，标号16表示平坦化层和钝化层的过孔。为了提高像素的充电率，降低扫描线的耦合电容，从图1中可以看到，薄膜晶体管的通道长度L1会设计的较小，而该通道长度的也是扫描线的宽度，导致扫描线的宽度也会较小，根据电阻公式可知，扫描线的宽度越小，阻抗越高，导致扫描线的压降较大，扫描信号失真。
具体的，相较于小尺寸的显示器件中横向长度小于纵向长度，对于中大尺寸的显示器件，会呈现横向长度远大于纵向长度的状态，而GOA（gate on array，栅极驱动电路）电路设置在显示器件的左右两侧，扫描线会横向连接至两侧的GOA电路，数据线纵向设置，导致扫描线的长度过大，而由电阻公式可以知道扫描线的长度越大，电阻越大，导致面板横向的压降极其严重，如图2所示，以栅极驱动电路设置在显示器件两侧为例，从显示器件的左侧向中间区域，从显示器件的右侧向中间区域，具体的扫描信号的波形中可以看到，t1小于t2，t2小于t3，由于扫描线的压降，导致扫描信号从两侧向中间区域失真严重，在显示器件显示时，会导致面板不同区域的延迟差异较大，显示器件的显示均一性较差，且为避免延迟导致的错冲，会通过增加每行级传之间的间隔时间，导致每行的充电时间变短，充电率降低，或者通过增加输出端子数量和驱动芯片数据，但这一设计会导致空间占用较大，无法满足需求。所以，现有显示器件存在栅极层的阻抗较大所导致的显示器件的扫描信号失真的技术问题。
如图3、图4、图5所示，本申请实施例提供一种阵列基板，该阵列基板2包括：
衬底211；
有源层215，设置于所述衬底211一侧；
栅极绝缘层216，设置于所述有源层215远离所述衬底211的一侧；
第一金属层217，设置于所述有源层215远离所述衬底211的一侧，所述第一金属层217形成有栅极217d；
层间绝缘层218，设置于所述第一金属层217远离所述栅极绝缘层216的一侧；
第二金属层219，设置于所述层间绝缘层218远离所述第一金属层217的一侧，所述第二金属层219形成有源极219e、漏极219f和扫描线219c；
其中，所述阵列基板2还包括数据线32，所述数据线32包括设置于所述第一金属层217的第一部分321和设置于所述第二金属层219的第二部分322，在所述扫描线219c与所述数据线32的交界处，所述数据线32的第二部分322穿过所述层间绝缘层218与所述数据线32的第一部分321连接，所述扫描线219c穿过所述层间绝缘层218与所述栅极217d连接。
本申请实施例提供一种阵列基板，该阵列基板通过将扫描线设置在第二金属层，则在设置薄膜晶体管的通道时，薄膜晶体管的通道的宽度与扫描线的宽度并不关联，因此可以增加扫描线的宽度以减小扫描线的阻抗，同时扫描线采用阻抗小于第一金属层的第二金属层形成，进一步减小了扫描线的阻抗，且可以使薄膜晶体管的通道的宽度较小，提高阵列基板的充电效率，且减小扫描信号出现的失真差异。
需要说明的是，在图5中，阵列基板中各膜层或者器件叠合，导致部分膜层的结构被遮挡，各膜层的具体结构通过图4中的分解图进行示意说明，各膜层之间的设置和连接在下述实施例进行详细说明。
针对薄膜晶体管的通道长度与扫描线的宽度关联会导致扫描线的宽度较小，进而导致扫描线的阻抗较大的问题。在一种实施例中，如图3至图5所示，所述有源层215包括有源图案，所述有源图案在所述衬底211上的投影位于所述扫描线219c在所述衬底211上的投影的一侧，且所述有源图案在所述衬底211上的投影与所述扫描线219c在所述衬底211上的投影不重合。通过使扫描线和栅极分开设置，使得扫描线的线宽与薄膜晶体管的通道长度并不关联，对于薄膜晶体管的通道长度需要设定的较小以提高充电率和减小耦合电容，可以对薄膜晶体管的通道长度进行设计，而不会影响到扫描线的宽度，相应的可以增加扫描线的线宽，减小扫描线的阻抗，从而在减小扫描线的阻抗的同时，提高了像素的充电率，而扫描线的耦合电容可以根据扫描线和数据线的设计进行减小。
在一种实施例中，所述有源图案包括沟道区和掺杂区，位于所述沟道区的有源图案沿水平方向设置。相较于当前显示器件需要将有源图案设置为“n”字型，减小扫描线宽度，本申请实施例使薄膜晶体管的通道长度与扫描线的线宽并不关联，因此可以使得有源图案水平设置，增加扫描线的线宽，减小扫描线的压降。
需要说明的是，在图3中，沟道区的有源图案的部分以标号215b表示，掺杂区的有源图案的部分以标号215a表示，而在图4和图5中，以标号215c表示有源图案的掺杂材料，以标号215b表示未进行掺杂的有源图案，因此，可以通过掺杂材料和未进行掺杂的有源图案得到沟道区和掺杂区的有源图案。
需要说明的是，为了便于说明各膜层的设计和各膜层的连接，便于示出各膜层之间的叠合状态，在本申请实施例的附图中没有示出轻掺杂区，本申请实施例中的附图和说明书中没有特指时，掺杂区是指重掺杂区，但实际设计时会存在轻掺杂区，轻掺杂区设置于重掺杂区和沟道区之间，在下述实施例中不再赘述。
具体的，如图3至图5所示，所述掺杂区215a包括依次设置的第一掺杂区、第二掺杂区和第三掺杂区，所述沟道区215b包括第一沟道区和第二沟道区，所述第一沟道区位于所述第一掺杂区和所述第二掺杂区之间，所述第二沟道区位于所述第二掺杂区和所述第三掺杂区之间。通过使得掺杂区和沟道区水平设置，使得薄膜晶体管的通道长度与扫描线的线宽并不关联，增加扫描线的线宽，减小扫描线的压降。
具体的，如图1、图5所示，相较于当前有源图案需要设置为“n”字型，减小扫描线宽度，本申请实施例中使薄膜晶体管的通道长度与扫描线的线宽并不关联，可以通过水平设置有源图案，使得掺杂区和沟道区依次水平设置，中间的掺杂区可以提高有源图案的导电性能，减小功耗，增加扫描线的线宽，减小扫描线的压降。
在一种实施例中，如图3至图5所示，所述扫描线219c在靠近所述漏极219f的一侧形成有缺口301，所述扫描线219c在所述漏极219f与所述有源图案连接的区域的宽度，小于所述扫描线219c在所述源极219e与所述有源图案连接的区域的宽度。通过使得在漏极与像素电极连接的一侧，在扫描线上形成缺口，使得扫描线和漏极存在一定的间距，避免漏极和扫描线出现短路，且避免扫描线和像素电极之间形成寄生电容，影响显示器件的正常显示。
在一种实施例中，如图3至图5所示，在所述掺杂区，位于所述源极219e与所述有源图案连接一侧的有源图案的部分与所述扫描线219c之间的距离，大于位于所述漏极219f与所述有源图案连接一侧的有源图案的部分与所述扫描线219c之间的距离。通过使得源极与有源图案连接一侧的有源图案的部分与扫描线之间的距离，大于漏极与有源图案连接一侧的有源图案的部分与扫描线之间的距离，使得在源极与数据线连接时，能够预留数据线从第二金属层连接至第一金属层的区域，避免在数据线从第二金属层连接至第一金属层时，导致第一金属层连接至有源层，或者与扫描线出现短路问题，影响正常显示。
具体的，上述实施例以源极与数据线连接，数据线在源极一侧实现第一金属层和第二金属层的转线设置为例进行了详细说明。但本申请实施例不限于此，在数据线位于漏极一侧进行第一金属层和第二金属层的走线连接时，可以相应的使漏极一侧有源图案的部分与扫描线之间的距离，大于源极一侧有源图案的部分与扫描线之间的距离。
在一种实施例中，所述有源图案包括沟道区和掺杂区，在所述沟道区，所述有源图案在所述衬底上的投影与所述栅极在所述衬底上的投影存在重叠，在所述掺杂区，所述源极和所述漏极穿过所述层间绝缘层和所述栅极绝缘层连接至所述有源图案。通过在沟道区使栅极和有源图案在衬底上的投影存在重叠，实现阵列基板的薄膜晶体管的栅极的开关功能，通过源极和漏极与掺杂区连接，实现阵列基板的薄膜晶体管的信号传输的功能，从而使得在输入电信号时，可以通过薄膜晶体管控制信号的传输。
针对当前显示器件需要减小薄膜晶体管的通道长度以保证像素的充电率和减小扫描线的耦合电容，会导致扫描线的阻抗较大的技术问题。在一种实施例中，如图3至图5所示，所述栅极217d包括第一栅极部分311和第二栅极部分312，所述第一栅极部分311在所述衬底211上的投影、位于所述扫描线219c在所述衬底211上的投影内，所述第一栅极部分311的宽度小于所述扫描线219c的宽度，所述第二栅极部分312在所述衬底211上的投影与所述有源图案在所述衬底211上的投影存在重叠。通过将栅极分为第一栅极部分和第二栅极部分，由于栅极和扫描线位于不同膜层，因此，扫描线的宽度可以不受栅极的影响，使得扫描线的宽度大于第一栅极部分的宽度，减小扫描线的阻抗，减小扫描线的压降，且第一栅极部分和第二栅极部分可以实现开关功能。
在一种实施例中，所述栅极包括第一栅极部分和第二栅极部分，所述第一栅极部分在所述衬底上的投影、位于所述扫描线在所述衬底上的投影内，所述第一栅极部分的宽度等于所述扫描线的宽度，所述第二栅极部分在所述衬底上的投影与所述有源图案在所述衬底上的投影存在重叠。通过使得第一栅极部分在所述衬底上的投影、位于所述扫描线在所述衬底上的投影内，所述第一栅极部分的宽度等于所述扫描线的宽度，使得在增加扫描线的宽度以减小扫描线的阻抗时，也可以通过增加栅极的面积，增加栅极和扫描线的连接稳定性，并且可以减小栅极和扫描线的连接处的阻抗，且由于栅极增加部分并未超出扫描线的宽度，也不会增加像素的尺寸。
在一种实施例中，在所述第一栅极部分对应的区域，所述层间绝缘层形成有至少一个过孔，所述第一栅极部分穿过所述过孔所述扫描线连接。通过使第一栅极部分和扫描线具有重叠，使得栅极和扫描线连接时，可以直接通过在栅极和扫描线重叠的部分，即第一栅极部分和扫描线重叠部分对层间绝缘层设置过孔，使得第一栅极部分与扫描线连接，从而可以通过扫描线上传输的信号控制栅极的开启和关闭，实现薄膜晶体管的开关功能。
在一种实施例中，如图4、图5所示，所述过孔包括第一过孔45和所述第二过孔46，所述第一栅极部分311穿过所述第一过孔45与所述扫描线219c连接，且所述第一栅极部分311穿过所述第二过孔46与所述扫描线219c连接。通过使得第一栅极部分与扫描线存在多处连接，使得栅极和扫描线的连通性较好，提高信号传输的效率和稳定性。
具体的，上述实施例以层间绝缘层形成的过孔包括第一过孔和第二过孔为例进行了详细说明，但本申请实施例不限于此，例如为了进一步增加栅极和扫描线的连通性，可以设置第三过孔，使得栅极的第一栅极部分和扫描线通过第一过孔、第二过孔和第三过孔进行连接，且在需要进一步提高栅极和扫描线的连通性时，可以进一步增加过孔，增加栅极和扫描线的连通性。
针对显示器件存在漏电的问题。在一种实施例中，如图3至图5所示，所述第二栅极部分312包括第一开关部分312a和第二开关部分312b，所述第一开关部分312a和所述第二开关部分312b与所述第一栅极部分311连接，且所述第一开关部分312a与所述第二开关部分312b之间绝缘设置。通过设置第一开关部分和第二开关部分，使第一开关部分和第二开关部分与有源图案的沟道区的投影存在重合，使得栅极为双栅设计，通过双栅设计减小阵列基板的漏电问题。
具体的，如图4、图5所示，图4为有源层215、第一金属层217和第二金属层219的分解图，图5为阵列基板的各膜层的俯视图。从图4和图5可以看到，有源层215包括未进行掺杂的有源图案和有源图案的掺杂材料215c，第一金属层217包括数据线32的第一部分321和栅极217d，第二金属层219包括数据线32的第二部分322、源极219e、漏极219f和扫描线219c，如图5所示，由于数据线32和扫描线219c会存在交叉部分，因此，在数据线32和扫描线219c的交界区域，使数据线32采用第一金属层217形成。
具体的，数据线32的第一部分321包括第一端子217a、第一连接线217b和第二端子217c，数据线32的第二部分322包括第二连接线219a、第三端子219b和第四端子219d，第一端子217a和第三端子219b通过层间绝缘层的过孔连接，第二端子217c与第四端子219d通过层间绝缘层的过孔连接，具体的，图5中以标号44表示第一端子和第三端子的连接部分、第二端子和第四端子的连接部分，在图5中第三端子覆盖第一端子、第四端子覆盖第二端子，因此图5中未示出第一端子和第二端子。
具体的，源极219e和漏极219f通过层间绝缘层和栅极绝缘层的过孔与有源图案连接，如图5所示，以标号41表示源极和漏极与有源层连接的部分。
具体的，为了便于展示各膜层的叠合状态，图5中未示出部分膜层在图5中，以标号43表示平坦化层和钝化层形成的过孔，以标号42表示漏极与像素电极的连接部分。
从图4、图5可以看到，在输入扫描信号时，扫描信号会从第二金属层的扫描线219c传导，然后通过扫描线219c和栅极217d的连接处45和46传递至栅极217d，开启栅极217d，而数据线在输入数据信号时，数据信号会从第二金属层的数据线32的第二连接线219a传导至第三端子219b，然后从第三端子219b传导至第一端子217a，然后从第一端子217a传导至第一连接线217b，然后从第一连接线217b传导至第二端子217c，然后从第二端子217c传导至第四端子219d，然后从第四端子219d传导至第二连接线219a，然后从第二连接线219a传导至源极219e，以输入数据信号。该过程中由于扫描信号通过第二金属层走线，且可以增加扫描线的线宽，减小了扫描信号的延迟。
需要说明的是，上述实施例中以图4和图5示出的各膜层的分解图和俯视图进行了详细说明，但本申请实施例不限于此，例如图4、图5中的任一特征可以应用在其他实施例中，并不限于图4、图5所对应的实施例。
具体的，在一种实施例中，数据线的第一部分包括第一端子、第一连接线和第二端子，数据线的第二部分包括第二连接线、第三端子和第四端子，所述第一连接线的两端与所述第一端子和第二端子连接，所述第三端子与所述第二连接线连接，所述第一端子与所述第三端子穿过所述层间绝缘层的过孔连接，所述第四端子与所述第二连接线连接，所述第二端子和所述第四端子穿过层间绝缘层的过孔连接，所述第三端子在所述衬底上的投影面积大于或者等于所述第一端子在所述衬底上的投影面积，所述第四端子在所述衬底上的投影面积大于或者等于所述第二端子在所述衬底上的投影面积。通过使得第三端子在衬底上的投影面积大于或者等于第一端子在衬底上的投影面积，使第四端子在衬底上的投影面积大于或者等于第二端子在衬底上的投影面积，使得数据线的第一部分和数据线的第二部分通过第一端子、第二端子、第三端子和第四端子连接时，可以使第一端子和第二端子与第三端子和第四端子整面连接，提高连接效果，减小阻抗。
在一种实施例中，所述第一金属层的单位面积的电阻小于所述第二金属层的单位面积的电阻。在阵列基板中，第二金属层的材料的电阻小于第一金属层的材料的电阻，通过采用第二金属层形成扫描线，使得在信号输入时，扫描线的压降较小，减小信号的失真问题。
在一种实施例中，位于同一行的像素的扫描线一体成型。在形成同一行的像素时，可以同时形成多个像素的扫描线，使得同一行的像素的扫描线均采用第二金属层形成，减小扫描信号从两侧向中间区域的延迟。
在一种实施例中，如图3所示，所述阵列基板2还包括遮光层212、阻挡层213和缓冲层214，所述遮光层212对应设置于所述有源层215设置区域。
在一种实施例中，如图3所示，所述阵列基板2还包括平坦化层220、第一电极层221、钝化层222和第二电极层223，源漏极层219穿过平坦化层220、钝化层222的过孔与第二电极层223连接。
如图3所示，在图3中第一电极层221两侧断开，但在实际中，为了使第一电极层和第二电极层绝缘设置，会使得第一电极层形成过孔，钝化层填充至过孔内隔开第一电极层和第二电极层，第二电极层穿过钝化层和平坦化层与源漏极层连接，第一电极层为整面设置，只是形成有过孔，而不是多段设置。
同时，如图4至图6所示，本申请实施例提供一种液晶显示面板，该液晶显示面板包括阵列基板、彩膜基板52和设置于所述阵列基板与所述彩膜基板52之间的液晶层51，所述阵列基板包括：
衬底211；
有源层215，设置于所述衬底211一侧；
栅极绝缘层216，设置于所述有源层215远离所述衬底211的一侧；
第一金属层217，设置于所述有源层215远离所述衬底211的一侧，所述第一金属层217形成有栅极217d；
层间绝缘层218，设置于所述第一金属层217远离所述栅极绝缘层216的一侧；
第二金属层219，设置于所述层间绝缘层218远离所述第一金属层217的一侧，所述第二金属层219形成有源极219e、漏极219f和扫描线219c；
其中，所述阵列基板2还包括数据线32，所述数据线32包括设置于所述第一金属层217的第一部分321和设置于所述第二金属层219的第二部分322，在所述扫描线219c与所述数据线32的交界处，所述数据线32的第二部分322穿过所述层间绝缘层218与所述数据线32的第一部分321连接，所述扫描线219c穿过所述层间绝缘层218与所述栅极217d连接。
本申请实施例提供一种液晶显示面板，该液晶显示面板包括阵列基板、彩膜基板和设置于阵列基板和彩膜基板之间的液晶层，该阵列基板通过将扫描线设置在第二金属层，则在设置薄膜晶体管的通道时，薄膜晶体管的通道的宽度与扫描线的宽度并不关联，因此可以增加扫描线的宽度以减小扫描线的阻抗，同时扫描线采用阻抗小于第一金属层的第二金属层形成，进一步减小了扫描线的阻抗，且可以使薄膜晶体管的通道的宽度较小，提高阵列基板的充电效率，且减小扫描信号出现的失真差异。
在一种实施例中，在液晶显示面板中，所述有源层包括有源图案，所述有源图案在所述衬底上的投影位于所述扫描线在所述衬底上的投影的一侧，且所述有源图案在所述衬底上的投影与所述扫描线在所述衬底上的投影不重合。
在一种实施例中，在液晶显示面板中，所述有源图案包括沟道区和掺杂区，位于所述沟道区的有源图案沿水平方向设置。
在一种实施例中，在液晶显示面板中，在所述掺杂区，位于所述源极与所述有源图案连接一侧的有源图案的部分与所述扫描线之间的距离，大于位于所述漏极与所述有源图案连接一侧的有源图案的部分与所述扫描线之间的距离。
在一种实施例中，在液晶显示面板中，所述有源图案包括沟道区和掺杂区，在所述沟道区，所述有源图案在所述衬底上的投影与所述栅极在所述衬底上的投影存在重叠，在所述掺杂区，所述源极和所述漏极穿过所述层间绝缘层和所述栅极绝缘层连接至所述有源图案。
在一种实施例中，在液晶显示面板中，所述栅极包括第一栅极部分和第二栅极部分，所述第一栅极部分在所述衬底上的投影、位于所述扫描线在所述衬底上的投影内，所述第一栅极部分的宽度小于所述扫描线的宽度，所述第二栅极部分在所述衬底上的投影与所述有源图案在所述衬底上的投影存在重叠。
在一种实施例中，在液晶显示面板中，在所述第一栅极部分对应的区域，所述层间绝缘层形成有至少一个过孔，所述第一栅极部分穿过所述过孔所述扫描线连接。
在一种实施例中，在液晶显示面板中，所述过孔包括第一过孔和第二过孔，所述第一栅极部分穿过所述第一过孔与所述扫描线连接，且所述第一栅极部分穿过所述第二过孔与所述扫描线连接。
在一种实施例中，在液晶显示面板中，所述第二栅极部分包括第一开关部分和第二开关部分，所述第一开关部分和所述第二开关部分与所述第一栅极部分连接，且所述第一开关部分与所述第二开关部分之间绝缘设置。
在一种实施例中，在液晶显示面板中，数据线的第一部分包括第一端子、第一连接线和第二端子，数据线的第二部分包括第二连接线、第三端子和第四端子，所述第一连接线的两端与所述第一端子和第二端子连接，所述第三端子与所述第二连接线连接，所述第一端子与所述第三端子穿过所述层间绝缘层的过孔连接，所述第四端子与所述第二连接线连接，所述第二端子和所述第四端子穿过层间绝缘层的过孔连接，所述第三端子在所述衬底上的投影面积大于或者等于所述第一端子在所述衬底上的投影面积，所述第四端子在所述衬底上的投影面积大于或者等于所述第二端子在所述衬底上的投影面积。
在一种实施例中，在液晶显示面板中，所述第一金属层的单位面积的电阻小于所述第二金属层的单位面积的电阻。
根据上述实施例可知：
本申请实施例提供一种阵列基板和液晶显示面板；该阵列基板包括衬底、有源层、栅极绝缘层、第一金属层、层间绝缘层和第二金属层，有源层设置于衬底一侧，栅极绝缘层设置于有源层远离衬底的一侧，第一金属层设置于有源层远离衬底的一侧，第一金属层形成有栅极，层间绝缘层设置于第一金属层远离栅极绝缘层的一侧，第二金属层设置于层间绝缘层远离第一金属层的一侧，第二金属层形成有源极、漏极和扫描线，其中，阵列基板还包括数据线，数据线包括设置于第一金属层的第一部分和设置于第二金属层的第二部分，在扫描线与数据线的交界处，数据线的第二部分穿过层间绝缘层与数据线的第一部分连接，栅极穿过层间绝缘层与扫描线连接。本申请通过将扫描线设置在第二金属层，则在设置薄膜晶体管的通道时，薄膜晶体管的通道的宽度与扫描线的宽度并不关联，因此可以增加扫描线的宽度以减小扫描线的阻抗，同时扫描线采用阻抗小于第一金属层的第二金属层形成，进一步减小了扫描线的阻抗，且可以使薄膜晶体管的通道的宽度较小，提高阵列基板的充电效率，且减小扫描信号出现的失真差异。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上对本申请实施例所提供的一种阵列基板和液晶显示面板进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种阵列基板，其包括：
    衬底；
    有源层，设置于所述衬底一侧；
    栅极绝缘层，设置于所述有源层远离所述衬底的一侧；
    第一金属层，设置于所述有源层远离所述衬底的一侧，所述第一金属层形成有栅极；
    层间绝缘层，设置于所述第一金属层远离所述栅极绝缘层的一侧；
    第二金属层，设置于所述层间绝缘层远离所述第一金属层的一侧，所述第二金属层形成有源极、漏极和扫描线；
    其中，所述阵列基板还包括数据线，所述数据线包括设置于所述第一金属层的第一部分和设置于所述第二金属层的第二部分，在所述扫描线与所述数据线的交界处，所述数据线的第二部分穿过所述层间绝缘层与所述数据线的第一部分连接，所述扫描线穿过所述层间绝缘层与所述栅极连接。
  2. 如权利要求1所述的阵列基板，其中，所述有源层包括有源图案，所述有源图案在所述衬底上的投影位于所述扫描线在所述衬底上的投影的一侧，且所述有源图案在所述衬底上的投影与所述扫描线在所述衬底上的投影不重合。
  3. 如权利要求2所述的阵列基板，其中，所述有源图案包括沟道区和掺杂区，位于所述沟道区的有源图案沿水平方向设置。
  4. 如权利要求3所述的阵列基板，其中，所述扫描线在靠近所述漏极的一侧形成有缺口，所述扫描线在所述漏极与所述有源图案连接的区域的宽度，小于所述扫描线在所述源极与所述有源图案连接的区域的宽度。
  5. 如权利要求3所述的阵列基板，其中，在所述掺杂区，位于所述源极与所述有源图案连接一侧的有源图案的部分与所述扫描线之间的距离，大于位于所述漏极与所述有源图案连接一侧的有源图案的部分与所述扫描线之间的距离。
  6. 如权利要求2所述的阵列基板，其中，所述有源图案包括沟道区和掺杂区，在所述沟道区，所述有源图案在所述衬底上的投影与所述栅极在所述衬底上的投影存在重叠，在所述掺杂区，所述源极和所述漏极穿过所述层间绝缘层和所述栅极绝缘层连接至所述有源图案。
  7. 如权利要求1所述的阵列基板，其中，所述栅极包括第一栅极部分和第二栅极部分，所述第一栅极部分在所述衬底上的投影、位于所述扫描线在所述衬底上的投影内，所述第一栅极部分的宽度小于所述扫描线的宽度，所述第二栅极部分在所述衬底上的投影与所述有源图案在所述衬底上的投影存在重叠。
  8. 如权利要求7所述的阵列基板，其中，在所述第一栅极部分对应的区域，所述层间绝缘层形成有至少一个过孔，所述第一栅极部分穿过所述过孔所述扫描线连接。
  9. 如权利要求8所述的阵列基板，其中，所述过孔包括第一过孔和第二过孔，所述第一栅极部分穿过所述第一过孔与所述扫描线连接，且所述第一栅极部分穿过所述第二过孔与所述扫描线连接。
  10. 如权利要求7所述的阵列基板，其中，所述第二栅极部分包括第一开关部分和第二开关部分，所述第一开关部分和所述第二开关部分与所述第一栅极部分连接，且所述第一开关部分与所述第二开关部分之间绝缘设置。
  11. 一种液晶显示面板，其包括阵列基板、彩膜基板和设置于所述阵列基板与所述彩膜基板之间的液晶层，所述阵列基板包括：
    衬底；
    有源层，设置于所述衬底一侧；
    栅极绝缘层，设置于所述有源层远离所述衬底的一侧；
    第一金属层，设置于所述有源层远离所述衬底的一侧，所述第一金属层形成有栅极；
    层间绝缘层，设置于所述第一金属层远离所述栅极绝缘层的一侧；
    第二金属层，设置于所述层间绝缘层远离所述第一金属层的一侧，所述第二金属层形成有源极、漏极和扫描线；
    其中，所述阵列基板还包括数据线，所述数据线包括设置于所述第一金属层的第一部分和设置于所述第二金属层的第二部分，在所述扫描线与所述数据线的交界处，所述数据线的第二部分穿过所述层间绝缘层与所述数据线的第一部分连接，所述扫描线穿过所述层间绝缘层与所述栅极连接。
  12. 如权利要求11所述的液晶显示面板，其中，所述有源层包括有源图案，所述有源图案在所述衬底上的投影位于所述扫描线在所述衬底上的投影的一侧，且所述有源图案在所述衬底上的投影与所述扫描线在所述衬底上的投影不重合。
  13. 如权利要求12所述的液晶显示面板，其中，所述有源图案包括沟道区和掺杂区，位于所述沟道区的有源图案沿水平方向设置。
  14. 如权利要求13所述的液晶显示面板，其中，在所述掺杂区，位于所述源极与所述有源图案连接一侧的有源图案的部分与所述扫描线之间的距离，大于位于所述漏极与所述有源图案连接一侧的有源图案的部分与所述扫描线之间的距离。
  15. 如权利要求12所述的液晶显示面板，其中，所述有源图案包括沟道区和掺杂区，在所述沟道区，所述有源图案在所述衬底上的投影与所述栅极在所述衬底上的投影存在重叠，在所述掺杂区，所述源极和所述漏极穿过所述层间绝缘层和所述栅极绝缘层连接至所述有源图案。
  16. 如权利要求11所述的液晶显示面板，其中，所述栅极包括第一栅极部分和第二栅极部分，所述第一栅极部分在所述衬底上的投影、位于所述扫描线在所述衬底上的投影内，所述第一栅极部分的宽度小于所述扫描线的宽度，所述第二栅极部分在所述衬底上的投影与所述有源图案在所述衬底上的投影存在重叠。
  17. 如权利要求16所述的液晶显示面板，其中，在所述第一栅极部分对应的区域，所述层间绝缘层形成有至少一个过孔，所述第一栅极部分穿过所述过孔所述扫描线连接。
  18. 如权利要求17所述的液晶显示面板，其中，所述过孔包括第一过孔和第二过孔，所述第一栅极部分穿过所述第一过孔与所述扫描线连接，且所述第一栅极部分穿过所述第二过孔与所述扫描线连接。
  19. 如权利要求16所述的液晶显示面板，其中，所述第二栅极部分包括第一开关部分和第二开关部分，所述第一开关部分和所述第二开关部分与所述第一栅极部分连接，且所述第一开关部分与所述第二开关部分之间绝缘设置。
  20. 如权利要求11所述的液晶显示面板，其中，数据线的第一部分包括第一端子、第一连接线和第二端子，数据线的第二部分包括第二连接线、第三端子和第四端子，所述第一连接线的两端与所述第一端子和第二端子连接，所述第三端子与所述第二连接线连接，所述第一端子与所述第三端子穿过所述层间绝缘层的过孔连接，所述第四端子与所述第二连接线连接，所述第二端子和所述第四端子穿过层间绝缘层的过孔连接，所述第三端子在所述衬底上的投影面积大于或者等于所述第一端子在所述衬底上的投影面积，所述第四端子在所述衬底上的投影面积大于或者等于所述第二端子在所述衬底上的投影面积。
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