WO2023129806A1 - Appareil de test de microstructures - Google Patents

Appareil de test de microstructures Download PDF

Info

Publication number
WO2023129806A1
WO2023129806A1 PCT/US2022/081421 US2022081421W WO2023129806A1 WO 2023129806 A1 WO2023129806 A1 WO 2023129806A1 US 2022081421 W US2022081421 W US 2022081421W WO 2023129806 A1 WO2023129806 A1 WO 2023129806A1
Authority
WO
WIPO (PCT)
Prior art keywords
target
dielectric material
die
micro
metal contacts
Prior art date
Application number
PCT/US2022/081421
Other languages
English (en)
Inventor
Erik William Young
Rajiv Pathak
Original Assignee
Lumileds Llc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lumileds Llc filed Critical Lumileds Llc
Publication of WO2023129806A1 publication Critical patent/WO2023129806A1/fr

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2607—Circuits therefor
    • G01R31/2632—Circuits therefor for testing diodes
    • G01R31/2635—Testing light-emitting diodes, laser diodes or photodiodes
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/282—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere
    • G01R31/2831—Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means

Definitions

  • Embodiments of the disclosure generally relate to test apparatus of microstructures, which include micro-light emitting diode (uLED) dies and monolithic arrays, and methods of manufacturing and using the same.
  • uLED micro-light emitting diode
  • Semiconductor light-emitting devices or optical power emitting devices such as devices that emit ultraviolet (UV) or infrared (IR) optical power
  • LEDs semiconductor light or optical power emitting devices
  • LEDs are attractive candidates for light sources, such as camera flashes, for hand-held battery-powered devices, such as cameras and cell phones. They may also be used, for example, for other applications, such as for automotive lighting, torch for video, and general illumination, such as home, shop, office and studio lighting, theater/stage lighting and architectural lighting.
  • High-intensity/brightness light emitting devices capable of operation across the visible spectrum include Group III-V semiconductors, particularly binary, ternary, and quaternary alloys of gallium, aluminum, indium, and nitrogen, also referred to as Ill-nitride materials.
  • Ill-nitride light emitting devices are fabricated by epitaxially growing a stack of semiconductor layers of different compositions and dopant concentrations on a growth substrate such as a sapphire, silicon carbide, Ill-nitride, or other suitable substrate by metalorganic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or other epitaxial techniques.
  • MOCVD metalorganic chemical vapor deposition
  • MBE molecular beam epitaxy
  • the stack grown on the growth substrate typically includes one or more n-type layers doped with, for example, Si, formed over the substrate, a light emitting or active region formed over the n-type layer or layers, and one or more p-type layers doped with, for example, Mg, formed over the active region.
  • microLEDs pLEDs or uLEDs
  • uLEDs microLEDs
  • uLEDs typically have dimensions of about 50 pm in diameter or width and smaller that are used to in the manufacture of color displays by aligning in close proximity microLEDs comprising red, blue and green wavelengths.
  • test apparatuses for micro-sized structures including uLED test dies and uLEDs, and methods of manufacturing and using the same.
  • An aspect is a micro-structure test apparatus comprising: a target wafer comprising: a target substrate, a plurality of target metal contacts, a first target dielectric material isolating the target metal contacts, a beginning contact area, an ending contact area, a first probe pad in communication the beginning contact area, and a second probe pad in communication with the ending contact area; the plurality of the target metal contacts and the first target dielectric material having respective exposed surfaces for accepting complementing structures of a micro-structure die comprising a plurality of die metal contacts and a die dielectric material.
  • Another aspect is: a method of manufacturing a micro-structure test apparatus comprising: preparing a target wafer; and preparing a first probe pad in communication with the beginning contact area, and a second probe pad in communication with the ending contact area.
  • the target wafer is prepared by: depositing an etch stop layer on a target substrate; depositing a primary dielectric material on the target substrate; preparing a dielectric material mask on the target substrate, etching the primary dielectric material, and removing the dielectric material mask, thereby preparing a primary dielectric material layer; preparing a primary metal contact material on the target substrate; planarizing a preliminary surface of the target substrate including the primary metal contact material to prepare a primary metal contact layer; depositing a secondary dielectric material on the target substrate; preparing a contact mask on the target substrate, etching the secondary dielectric material, and removing the contact mask, thereby preparing a secondary dielectric material layer; preparing a secondary metal contact material on the target substrate; and planarizing a second surface of the target substrate including
  • a method of testing a micro-structure die comprises: bonding the micro- structure die comprising a plurality of die metal contacts and a die dielectric material to the micro-structure test apparatus according to any embodiment herein; applying power to the micro- structure test apparatus; detecting electrical continuity; and identifying acceptable or defective bonds between the target metal contacts and the die metal contacts.
  • a transmission mask comprising: a body and a plurality of contact opening templates, one of the body and the plurality of contact opening templates being of a transparent material, and the other of the body and the plurality of contact opening templates being of an opaque material, each contact opening having a diameter “d” and a center “c”, and a pitch “p” between adjacent centers of each of the metal contact opening templates, the “d” being in a range of greater than or equal to 0.5 micrometers and less than or equal to 30 micrometers, and the “p” being in a of greater than or equal to 1 micrometer and less than or equal to 60 micrometers.
  • FIG. 1 is a schematic view illustrating in an expanded cross-section a portion of a test vehicle for micro- structures according to one or more embodiments
  • FIG. 2 is a schematic top view of a test vehicle for micro- structures according to one or more embodiments
  • FIG. 3 is a schematic top view of a transmission mask for micro- structures according to one or more embodiments;
  • FIG. 4 provides a process flow diagram for manufacture of test vehicle according to one or more embodiments;
  • FIG. 5 provides a process flow diagram for testing of a micro-structure according to one or more embodiments.
  • FIG. 6 is a schematic view illustrating in an expanded cross-section a portion of a test vehicle for micro- structures according to one or more embodiments.
  • Reference to LED refers to a light emitting diode that emits light when current flows through it.
  • the LEDs herein have one or more characteristic dimensions (e.g., height, width, depth, thickness, etc. dimensions) in a range of greater than or equal to 75 micrometers to less than or equal to 300 micrometers.
  • one or more dimensions of height, width, depth, thickness have values in a range of 100 to 300 micrometers. Reference herein to micrometers allows for variation of ⁇ 1-5%.
  • one or more dimensions of height, width, depth, thickness have values of 200 micrometers ⁇ 1-5%.
  • the LEDs are referred to as micro-LEDs (uLEDs or pLEDs), referring to a light emitting diode having one or more characteristic dimensions (e.g., height, width, depth, thickness, etc. dimensions) on the order of micrometers or tens of micrometers.
  • one or more dimensions of height, width, depth, thickness have values in a range of 1 to less than 75 micrometers, for example from 1 to 50 micrometers, or from 1 to 25 micrometers.
  • the LEDs herein may have a characteristic dimension ranging from 1 micrometers to 300 micrometers, and all values and sub-ranges therebetween.
  • Methods of depositing materials, layers, and thin films include but are not limited to: sputter deposition, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced atomic layer deposition (PEALD), plasma enhanced chemical vapor deposition (PECVD), and combinations thereof.
  • ALD atomic layer deposition
  • CVD chemical vapor deposition
  • PVD physical vapor deposition
  • PEALD plasma enhanced atomic layer deposition
  • PECVD plasma enhanced chemical vapor deposition
  • the semiconductor layers are formed by epitaxial (EPI) growth.
  • the semiconductor layers according to one or more embodiments comprise epitaxial layers, III- nitride layers, or epitaxial Ill-nitride layers.
  • the semiconductor layers comprise a Ill-nitride material, and in specific embodiments epitaxial Ill-nitride material.
  • the Ill-nitride material comprises one or more of gallium (Ga), aluminum (Al), and indium (In).
  • the semiconductor layers comprise one or more of gallium nitride (GaN), aluminum nitride (AIN), indium nitride (InN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), indium aluminum nitride (InAlN), aluminum indium gallium nitride (AlInGaN) and the like.
  • the Ill-nitride materials may be doped with one or more of silicon (Si), oxygen (O), boron (B), phosphorus (P), germanium (Ge), manganese (Mn), or magnesium (Mg) depending upon whether p-type or n- type Ill-nitride material is needed.
  • the semiconductor layers have a combined thickness in a range of from about 2 pm to about 10 pm, and all values and subranges therebetween.
  • test apparatuses herein are designed to test processes that bond wafers with micron- sized pixel dies and arrays.
  • a test apparatus includes a target wafer with micro-features.
  • the target wafer comprises: a target substrate, a plurality of target metal contacts, a target dielectric material isolating the target metal contacts, a beginning contact area, an ending contact area, a first probe pad positioned in communication the beginning contact area, and a second probe pad positioned in communication with the ending contact area.
  • the target wafer is configured to receive a microstructure, including metal contacts and dielectric material.
  • Target metal contacts and target dielectric material of the target wafer having respective exposed surfaces for accepting complementing structures of the micro- structure comprising a plurality of test die metal contacts and a test die dielectric material.
  • Suitable testable micro- structures include a test die and active uLED die.
  • the test die is configured as a uLED die excluding any semiconductor layers with or without active regions for the purposes of testing, and including test die metal contacts and a test die dielectric material.
  • the active uLED die is configured with semiconductor layers including an active region along with uLED metal contacts and uLED dielectric material.
  • Suitable applications for uLEDs developed with the test apparatus and test vehicles herein include but are not limited to augmented reality/virtual reality (AR/VR) systems.
  • AR/VR systems include: augmented (AR) or virtual reality (VR) headsets, glasses, or projectors.
  • Contact masks providing contact opening templates of varying diameters and pitches between centers of the contact openings are used.
  • the contact opening templates are used to block dielectric material from reaching the substrate during deposition of the dielectric material.
  • Patterns of the contact masks generally create uniformity among the contact diameters and pitches of the target wafer. Resulting wafers, including the target wafer, herein can have a very small array pitches and metal contact diameters, which are challenging to test.
  • pitch is the distance between centers of two elements, for example metal contacts.
  • Embodiments herein may utilize patterns wherein the pitch is in a range of greater than or equal to 1 micrometer and less than or equal to 60 micrometers, and all values and subranges therebetween.
  • Embodiments herein may utilize patterns wherein the metal contact openings have a diameter in a range of 0.5 micrometers and less than or equal to 30 micrometers, and all values and subranges therebetween.
  • FIG. 1 is a schematic view illustrating, in an expanded cross-section, a portion of a test vehicle 10 for micro-structures according to one or more embodiments.
  • the test vehicle 10 comprises a target wafer 12 and a source wafer 28.
  • the portion of the target wafer 12 shown comprises: a target substrate 14, an etch stop layer 16, a plurality of target metal contacts 18 and 20, a first target dielectric material 24 isolating the target metal contacts 18 and 20 and a beginning contact area 22.
  • the etch stop layer 16 is on the target substrate 12 below the target metal contacts 18 and 20 and the first target dielectric material 24. Further features of the target wafer of the test vehicle are discussed with respect to FIG. 2.
  • the etch stop layer 16 is a second dielectric material, which is different from the first dielectric material 24.
  • the source wafer 28 which is a micro- structure to be tested, comprises a die substrate 38 on which a plurality of die metal contacts 30 and 32, and a die dielectric material 34 are located.
  • the die dielectric material 34 isolates the die metal contacts 30 and 32.
  • the source wafer 28 of this embodiment is a micro-structure die excludes any semiconductor layers.
  • surfaces are shown as “exposed” in that prior to bonding to form the test vehicle, the surfaces are accessible for a bonding process. Upon assembly, bonding occurs at and between the exposed surfaces.
  • the target metal contact 18 of the target wafer 12 has exposed surfaces 19a and 19b, which are isolated by a portion of the first target dielectric material 24 spanning from the target metal contact 18 to an exposed surface 26a.
  • the target metal contact 20 of the target wafer 12 has exposed surfaces 21a and 21b, which are isolated by a portion of the first dielectric material 24 spanning from the target metal contact 20 to an exposed surface 26b.
  • the first dielectric material 24 also spans from a surface of the target substrate 14 to exposed surfaces 25a, 25b, 25c, and 25d.
  • the die metal contact 30 of the source wafer 28 has exposed surfaces 31a and 31b, which are isolated by a portion of the die dielectric material 34 spanning from the die metal contact 30 to an exposed surface 36a.
  • the die metal contact 32 of the source wafer 28 has exposed surfaces 33a and 33b, which are isolated by a portion of the die dielectric material 34 spanning from the die metal contact 32 to an exposed surface 36b.
  • the die dielectric material 34 spans from a surface of the die substrate 38 to exposed surfaces 35a, 35b, 35c, and 35d.
  • hybrid bonding means that there is a combination of a metal-to-metal bonds and dielectric-to-dielectric bonds.
  • the target dielectric material surface 26c bonds to the die dielectric material surface 35d; the target dielectric material surface 25c bonds to the die dielectric material surface 36b; the target dielectric material surface 26b bonds to the die dielectric material surface 35c; the target dielectric material surface 25b bonds to the die dielectric material surface 36a; the target dielectric material surface 26a bonds to the die dielectric material surface 35b; and the target dielectric material surface 25 a bonds to the die dielectric material surface 35 a.
  • the target metal contact surface 23 a bonds to the die metal contact surface 33b; the target metal contact surface 21b bonds to the die metal contact surface 33a; the target metal contact surface 21a bonds to the die metal contact surface 31b; the target metal contact surface 19b bonds to the die metal contact surface 31a; the target metal contact surface 19a bonds to a respective corresponding die metal contact surface of the die metal contact adjacent to the die metal contact 30.
  • the test vehicle 10 Upon bonding of the source wafer 28 to the target wafer 12, the test vehicle 10 is formed, wherein the die metal contacts 30 and 32 are connected in series by the target metal contacts 18 and 20. As an example, the die metal contact 32 is connected to two adjacent target metal contacts 20 and 22. Throughout the test vehicle, all of die metal contacts are analogously connected to two adjacent target metal contacts. There are the beginning contact area 23b and an ending contact area of the target wafer that communicate with probe pads.
  • FIG. 2 shows a schematic top view of a test vehicle 100 for micro-structures according to one or more embodiments.
  • FIG. 2 provides a detailed schematic view of an arrangement of a series of target metal contacts denoted by exemplary target metal contacts 118, 120, 122, and die metal contacts denoted by exemplary die metal contacts 130 and 132 as assembled to the target wafer 112.
  • First target dielectric material 124 and die dielectric material (not numbered) according to one or more embodiments is present but for the purposes of illustration is transparent for viewing the various metal contacts.
  • die metal contact 130 is bonded to target metal contact 118 by way of the die metal contact material that had an exposed surface 131a (analogous to exposed surface 31a of FIG.
  • die metal contact 130 is bonded to target metal contact 120 by way of the die metal contact material that had an exposed surface 131b (analogous to exposed surface 31b of FIG. 1).
  • Die metal contact 132 is bonded to the target metal contact 120 by way of the die metal contact material that had an exposed surface 133b (analogous to exposed surface 33b of FIG. 1); and the die metal contact 132 is bonded to an target metal contact adjacent to target metal contact 120 or to target metal contact 122 when at the beginning or ending of the series by way of the die metal contact material that had an exposed surface 133a (analogous to exposed surface 33a of FIG. 1).
  • the connections of the die metal contacts may be considered “daisy chains”.
  • a beginning contact area 123b-l of the target metal contact 122 is connected to and/or in communication with, and ultimately in electrical communication with, a first probe pad 104.
  • An ending contact area 123b-3 of a target metal contact analogous to the target metal contact 122 is in connected to and/or in communication with, and ultimately in electrical communication with, a second probe pad 108.
  • Any number of probe pads and corresponding contact areas may be included to allow for testing at intermediate points throughout the series of metal contacts.
  • intermediate contact area 123b-2 of a target metal contact analogous to the target metal contact 122 is in connected to and/or in communication with, and ultimately in electrical communication with, a third probe pad 106.
  • a test apparatus for micro-structures comprises: a target wafer comprising: a target substrate, a plurality of target metal contacts, a first target dielectric material isolating the target metal contacts, a beginning contact area, an ending contact area, a first probe pad in communication the beginning contact area, and a second probe pad in communication with the ending contact area.
  • the plurality of the target metal contacts and the first target dielectric material have respective exposed surfaces for accepting complementing structures of a micro-structure die comprising a plurality of die metal contacts and a die dielectric material.
  • the target metal contacts comprise one or more of: copper (Cu), aluminum (Al), nickel (Ni), titanium (Ti), titanium-tungsten (TiW), silver (Ag), gold (Au), platinum (Pt), and palladium (Pd).
  • the target wafer comprises an etch stop layer on the target substrate below the target metal contacts and the first target dielectric material.
  • the etch stop layer comprises a second dielectric material different from the first target dielectric material.
  • the first target dielectric material comprise one or more of: silicon oxide (SiO), silicon dioxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), aluminum oxide (AI2O3), and aluminum nitride (AIN).
  • An exemplary etch stop layer comprises SiN, in which case the first target dielectric material would comprise one or more of: silicon oxide (SiO), silicon dioxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), and aluminum oxide (AI2O3).
  • die dielectric material comprises one or more of: silicon oxide (SiO), silicon dioxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), aluminum oxide (AI2O3), and aluminum nitride (AIN).
  • the target substrate comprises a material selected from the group consisting of: ceramic, silicon, aluminum, sapphire, silicon carbide, and III- nitride.
  • the exposed surfaces of the target metal contacts have a diameter in a range of 0.5 micrometers to less than or equal to 30 micrometers, including all values and subranges therebetween.
  • a pitch between centers of the target metal contacts is in a range of greater than or equal to 1 micrometers to less than or equal to 60 micrometers, including all values and subranges therebetween.
  • the exposed surfaces of the target metal contacts have a diameter in a range of 0.5 micrometers to less than or equal to 30 micrometers, including all values and subranges therebetween; and a pitch between centers of the target metal contacts is in a range of greater than or equal to 1 micrometers to less than or equal to 60 micrometers, including all values and subranges therebetween.
  • the metal contact diameters and pitches therebetween can be defined by a contact mask in one or more embodiments.
  • the contact mask is prepared on the substrate by use of a transmission mask.
  • the transmission mask is typically a UV-transparent material, e.g., quartz, on which an opaque material, e.g., chrome, is patterned.
  • a photoresist Upon deposition of a photoresist on a target substrate, the transmission mask having transparent and opaque portions is used in conjunction with a light source (e.g., UV-light) to activate/develop desired portions of the photoresist, and thereafter portions of the photoresist are removed, thereby forming the contact mask.
  • a light source e.g., UV-light
  • either positive photoresist or negative resist may be used.
  • FIG. 3 is a schematic top view of a transmission mask for micro- structures according to one or more embodiments.
  • Use of transmission mask 150 with a light source and partial removal thereafter corresponds to preparation of a suitable contact mask on the substrate for preparation of the target wafer 112 of FIG. 2.
  • the transmission mask 150 comprises a mask body 154 on which a plurality of metal contact opening templates 152 are formed.
  • the body is transparent and the contact opening templates are opaque. In one or more embodiments, depending on the application and type of photoresist, the body is opaque and the contact opening templates are transparent.
  • Each of the metal contact opening templates 152 has a diameter “d” and a center “c”. There is a pitch “p” between adjacent centers of each of the metal contact opening templates 152.
  • Transmission masks of varying sizes of contact opening diameters and pitches between centers of the contact openings may be used to create various test apparatuses. The varying-sizes can inform development efforts as to which pitches and diameters are amenable to processing, specifically bonding, of large volumes of micro- structures.
  • the contact mask is prepared to allow for metal deposition onto primary contact metal material to prepare surfaces of the metal contacts of the target substrate that will be bonded to corresponding surfaces of metal contacts of a source substrate.
  • the transmission mask, and corresponding contact mask pattern includes metal contact openings having a diameter in a range of 0.5 micrometers and less than or equal to 30 micrometers, including all values and subranges therebetween and/or a pitch between centers of the metal contact openings is in a range of greater than or equal to 1 micrometer and less than or equal to 60 micrometers, including all values and subranges therebetween.
  • FIG. 4 provides a process flow diagram for manufacture 200 of test vehicle according to one or more embodiments.
  • a test apparatus is prepared.
  • a target wafer including probe pads is prepared.
  • the features of the target wafer are prepared as follows.
  • An etch stop layer is deposited on a target substrate of the target wafer.
  • a primary dielectric material is deposited on the target substrate.
  • a dielectric material mask of, for example, a photoresist material is prepared on the target substrate, then the primary dielectric material is etched in a pattern to the etch stop layer to create areas for receipt of a primary metal contact material, and the dielectric material mask is removed, which results in the preparation or formation of a primary dielectric material layer.
  • the primary metal contact material is prepared on the target substrate.
  • preparing of the primary metal contact layer comprises depositing a seed layer and thereafter conducting metal plating on the seed layer.
  • a preliminary surface of the target substrate including the primary metal contact material is planarized to prepare a primary metal contact layer.
  • This planarization technique seeks to provide less than or equal to 5 A planarity.
  • the planarization step includes chemical mechanical polishing (CMP).
  • CMP chemical mechanical polishing
  • cleaning and/or removal of particles may be conducted to a desired specification, elimination of residual metal and other debris.
  • a secondary dielectric material is prepared and/or deposited on the target substrate.
  • a contact mask is prepared on the target substrate.
  • the contact mask is a result of light treatment of photoresist through a transmission mask, which in one embodiment is represented by FIG. 3, and partial removal of the photoresist thereafter.
  • the secondary dielectric material is etched in a pattern to prepare areas for receipt of a secondary metal contact metal.
  • the contact mask is then removed, which prepares and/or forms a secondary dielectric material layer. Some portions of the secondary dielectric material layer are in combination with the first dielectric material layer and span from the etch stop layer to an exposed surface.
  • the secondary metal contact material is prepared on the target substrate.
  • preparing of the secondary metal contact layer comprises depositing a seed layer and thereafter conducting metal plating on the seed layer.
  • a second surface of the target substrate including the secondary metal contact material is then planarized to form a plurality of target metal contacts including a beginning contact area and an ending contact area, isolated by the primary and secondary dielectric material layers.
  • Planarizing the second surface of the target substrate seeks to provide less than or equal to 5A planarity.
  • this planarization step includes chemical mechanical polishing (CMP).
  • CMP chemical mechanical polishing
  • cleaning and/or removal of particles may be conducted to a desired specification, elimination of residual metal and other debris.
  • preparing of the secondary metal contact layer comprises depositing a seed layer and conducting metal plating on the seed layer.
  • the methods further comprise preparing one or more intermediate probe pads in communication with one or more the of the target metal contacts between the beginning contact area and the ending contact area.
  • a micro-structure die e.g., uLED die or uLED test die
  • a micro-structure die is positioned on the test apparatus.
  • the micro- structure is bonded to the target wafer of the test apparatus.
  • a test vehicle is formed, wherein the die metal contacts are connected in series by the target metal contacts.
  • FIG. 5 provides a process flow diagram for a method of testing a micro-structure
  • test apparatus Power is applied to the test apparatus.
  • electrical continuity is detected from the test apparatus. This may be accomplished by applying a voltage across the pads.
  • a testable micro-structure is an active uLED die.
  • FIG. 6 provided is a schematic view illustrating in an expanded cross-section a portion of a test vehicle for micro-structures according to one or more embodiments.
  • the test vehicle 400 comprises a target wafer 412 and a source wafer 428.
  • the portion of the target wafer 412 shown comprises: a target substrate 414, an etch stop layer 416, a plurality of target metal contacts 418 and 420, a first target dielectric material 424 isolating the target metal contacts 418 and 420 and a beginning contact area 422.
  • the etch stop layer 416 is on the target substrate 412 below the target metal contacts 418 and 420 and the first target dielectric material 424. Further features of the target wafer of the test vehicle are analogous to those discussed with respect to FIG. 2. In one or more embodiments, the etch stop layer 416 is a second dielectric material, which is different from the first dielectric material 424.
  • the source wafer 428 which is a micro- structure to be tested, comprises a die substrate 438 on which a plurality of die metal contacts 430 and 432, and a die dielectric material 434 are located.
  • the die dielectric material 434 isolates the die metal contacts 430 and 432.
  • the source wafer 428 of this embodiment is an active micro- structure die, further including a stack of semiconductor layers 440 including an active region 442 on the source substrate 438.
  • surfaces are shown as “exposed” in that prior to bonding to form the test vehicle, the surfaces are accessible for a bonding process. Upon assembly, bonding occurs at and between the exposed surfaces.
  • the target metal contact 418 of the target wafer 412 has exposed surfaces 419a and 419b, which are isolated by a portion of the first target dielectric material 424 spanning from the target metal contact 418 to an exposed surface 426a.
  • the target metal contact 420 of the target wafer 412 has exposed surfaces 421a and 421b, which are isolated by a portion of the first dielectric material 424 spanning from the target metal contact 420 to an exposed surface 426b.
  • the first dielectric material 424 also spans from a surface of the target substrate 414 to exposed surfaces 425a, 425b, 425c, and 425d.
  • the die metal contact 430 of the source wafer 428 has exposed surfaces 431a and 431b, which are isolated by a portion of the die dielectric material 434 spanning from the die metal contact 430 to an exposed surface 436a.
  • the die metal contact 432 of the source wafer 428 has exposed surfaces 433a and 433b, which are isolated by a portion of the die dielectric material 434 spanning from the die metal contact 432 to an exposed surface 436b.
  • the die dielectric material 434 spans from a surface of the die substrate 438 to exposed surfaces 435a, 435b, 435c, and 435d.
  • hybrid bonding means that there is a combination of a metal-to-metal bonds and dielectric-to-dielectric bonds.
  • the target dielectric material surface 426c bonds to the die dielectric material surface 435d; the target dielectric material surface 425c bonds to the die dielectric material surface 436b; the target dielectric material surface 426b bonds to the die dielectric material surface 435c; the target dielectric material surface 425b bonds to the die dielectric material surface 436a; the target dielectric material surface 426a bonds to the die dielectric material surface 435b; and the target dielectric material surface 425 a bonds to the die dielectric material surface 435a.
  • the target metal contact surface 423 a bonds to the die metal contact surface 433b; the target metal contact surface 421b bonds to the die metal contact surface 433a; the target metal contact surface 421a bonds to the die metal contact surface 431b; the target metal contact surface 419b bonds to the die metal contact surface 431a; the target metal contact surface 419a bonds to a respective corresponding die metal contact surface of the die metal contact adjacent to the die metal contact 430.
  • the test vehicle 400 Upon bonding of the source wafer 428 to the target wafer 412, the test vehicle 400 is formed, wherein the die metal contacts 430 and 432 are connected in series by the target metal contacts 418 and 420. As an example, the die metal contact 432 is connected to two adjacent target metal contacts 420 and 422. Throughout the test vehicle, all of die metal contacts are analogously connected to two adjacent target metal contacts. There are the beginning contact area 423b and an ending contact area of the target wafer that communicate with probe pads.
  • Embodiment (a) A micro- structure test apparatus comprising: a target wafer comprising: a target substrate, a plurality of target metal contacts, a first target dielectric material isolating the target metal contacts, a beginning contact area, an ending contact area, a first probe pad in communication the beginning contact area, and a second probe pad in communication with the ending contact area; the plurality of the target metal contacts and the first target dielectric material having respective exposed surfaces for accepting complementing structures of a micro-structure die comprising a plurality of die metal contacts and a die dielectric material.
  • Embodiment (b) The micro-structure test apparatus of embodiment (a), wherein the micro- structure die excludes any semiconductor layers.
  • Embodiment (c) The micro- structure test apparatus of embodiment (a) or
  • micro-structure die includes a stack of semiconductor layers including an active region.
  • Embodiment (d). The micro- structure test apparatus of any of embodiments (a) to (c) comprising one or more intermediate probe pads in communication with one or more the of the target metal contacts between the beginning contact area and the ending contact area.
  • Embodiment (e). The micro- structure test apparatus of any of embodiments (a) to (d), wherein the target wafer comprises an etch stop layer on the target substrate below the target metal contacts and the first target dielectric material.
  • Embodiment (f) The micro-structure test apparatus of embodiment (e), wherein the etch stop layer comprises a second dielectric material different from the first target dielectric material.
  • Embodiment (g) The micro- structure test apparatus of any of embodiments (a) to (f), wherein the target metal contacts comprise one or more of: copper (Cu), aluminum (Al), nickel (Ni), titanium (Ti), titanium-tungsten (TiW), silver (Ag), gold (Au), platinum (Pt), and palladium (Pd).
  • Embodiment (h) The micro- structure test apparatus of any of embodiments (a) to (g), wherein the first target dielectric material comprise one or more of: silicon oxide (SiO), silicon dioxide (SiCh), silicon nitride (SiN), silicon carbide (SiC), aluminum oxide (AI2O3), and aluminum nitride (AIN).
  • the first target dielectric material comprise one or more of: silicon oxide (SiO), silicon dioxide (SiCh), silicon nitride (SiN), silicon carbide (SiC), aluminum oxide (AI2O3), and aluminum nitride (AIN).
  • Embodiment (i) The micro- structure test apparatus of any of embodiments (a) to (h), wherein the exposed surfaces of the target metal contacts have a diameter in a range of 0.5 micrometers to less than or equal to 30 micrometers.
  • Embodiment (j) The micro- structure test apparatus of any of embodiments (a) to (i), wherein a pitch between centers of the target metal contacts is in a range of greater than or equal to 1 micrometers to less than or equal to 60 micrometers.
  • Embodiment (k) The micro- structure test apparatus of any of embodiments (a) to (j), wherein the target substrate comprises a material selected from the group consisting of: ceramic, silicon, aluminum, sapphire, silicon carbide, and Ill-nitride.
  • Embodiment (1) The micro- structure test apparatus of any of embodiments (a) to (k), wherein upon bonding of the micro- structure die to the target wafer, a test vehicle is formed, wherein the die metal contacts are connected in series by the target metal contacts.
  • Embodiment (m) The micro- structure test apparatus of embodiment (1), wherein the target metal contacts and the die metal contacts comprise the same metal.
  • Embodiment (n) The micro- structure test apparatus of any of embodiments (a) to (m), wherein the target dielectric material and the die dielectric material comprise the same dielectric material.
  • Embodiment (o) The micro- structure test apparatus of any of embodiments (a) to (n), wherein the die dielectric material comprises one or more of: silicon oxide (SiO), silicon dioxide (SiCh), silicon nitride (SiN), silicon carbide (SiC), aluminum oxide (AI2O3), and aluminum nitride (AIN).
  • the die dielectric material comprises one or more of: silicon oxide (SiO), silicon dioxide (SiCh), silicon nitride (SiN), silicon carbide (SiC), aluminum oxide (AI2O3), and aluminum nitride (AIN).
  • Embodiment (p) A method of manufacturing a micro-structure test apparatus comprising: preparing a target wafer and preparing a first probe pad in communication with the beginning contact area, and a second probe pad in communication with the ending contact area; the target wafer being prepared by: depositing an etch stop layer on a target substrate; depositing a primary dielectric material on the target substrate; preparing a dielectric material mask on the target substrate, etching the primary dielectric material, and removing the dielectric material mask, thereby preparing a primary dielectric material layer; preparing a primary metal contact material on the target substrate; planarizing a preliminary surface of the target substrate including the primary metal contact material to prepare a primary metal contact layer; depositing a secondary dielectric material on the target substrate; preparing a contact mask on the target substrate, etching the secondary dielectric material, and removing the contact mask to prepare a secondary dielectric material layer; preparing a secondary metal contact material on the target substrate; and planarizing a second surface of the target substrate including the secondary
  • Embodiment (q) The method of embodiment (p), wherein the contact mask includes metal contact opening templates having a diameter in a range of 0.5 micrometers and less than or equal to 30 micrometers.
  • Embodiment (r) The method of embodiment (p) or (q), wherein a pitch between centers of the metal contact opening templates is in a range of greater than or equal to 1 micrometer and less than or equal to 60 micrometers.
  • Embodiment (s). The method of any of embodiments (p) to (r), wherein the preparing of the primary metal contact layer and the preparing of the secondary metal contact layer independently comprise: depositing a seed layer and conducting metal plating on the seed layer.
  • Embodiment (t) The method of any of embodiments (p) to (s) comprising preparing one or more intermediate probe pads in communication with one or more the of the target metal contacts between the beginning contact area and the ending contact area.
  • Embodiment (u) A method of testing a micro-structure die comprising: bonding the micro- structure die comprising a plurality of die metal contacts and a die dielectric material to the micro-structure test apparatus according to any of embodiments (a) to (o); applying power to the micro- structure test apparatus; detecting electrical continuity; and identifying acceptable or defective bonds between the target metal contacts and the die metal contacts.
  • Embodiment (v) The method of embodiment (u), wherein upon the bonding of the micro-structure die to the target wafer of the micro-structure test apparatus, a test vehicle is formed, wherein the die metal contacts are connected in series by the target metal contacts.
  • Embodiment (w) The method of embodiment (u) or (v), wherein bonds between the target metal contacts and the die metal contacts are evaluated.
  • Embodiment (x) The method of any of embodiments (u) to (w), wherein bonds between the first target dielectric material and the die dielectric material are evaluated.
  • Embodiment (y) Any of the embodiments (a) to (x), wherein each uLED has at least one characteristic dimension of greater than or equal to 1 micrometer less than or equal to 300 micrometers, the characteristic dimension being selected from the group consisting of: height, width, depth, thickness, and combinations thereof.
  • Embodiment (z) Any of the embodiments (a) to (y), wherein for each uLED a p-contact and an n-contact are formed on a same side of a pixel or stack of semiconductor layers.
  • Embodiment (aa) A transmission mask comprising: a body and a plurality of contact opening templates, one of the body and the plurality of contact opening templates being of a transparent material, and the other of the body and the plurality of contact opening templates being of an opaque material, each contact opening having a diameter “d” and a center “c”, and a pitch “p” between adjacent centers of each of the metal contact opening templates, the “d” being in a range of greater than or equal to 0.5 micrometers and less than or equal to 30 micrometers, and the “p” being in a of greater than or equal to 1 micrometer and less than or equal to 60 micrometers.

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

Un appareil de test de microstructures comprend : une tranche cible comprenant : un substrat cible, une pluralité de contacts métalliques cibles, un premier matériau diélectrique cible isolant les contacts métalliques cibles, une zone de contact de début, une zone de contact de fin, une première pastille de sonde en communication avec la zone de contact de début, et une seconde pastille de sonde en communication avec la zone de contact de fin; la pluralité des contacts métalliques cibles et le premier matériau diélectrique cible ayant des surfaces exposées respectives permettant d'accepter des structures complémentaires d'une puce de microstructure comprenant une pluralité de contacts métalliques de puce et un matériau diélectrique de puce.
PCT/US2022/081421 2021-12-31 2022-12-13 Appareil de test de microstructures WO2023129806A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US202163295616P 2021-12-31 2021-12-31
US63/295,616 2021-12-31
US202263320842P 2022-03-17 2022-03-17
US63/320,842 2022-03-17

Publications (1)

Publication Number Publication Date
WO2023129806A1 true WO2023129806A1 (fr) 2023-07-06

Family

ID=87000210

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2022/081421 WO2023129806A1 (fr) 2021-12-31 2022-12-13 Appareil de test de microstructures

Country Status (1)

Country Link
WO (1) WO2023129806A1 (fr)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050253161A1 (en) * 2004-05-11 2005-11-17 Stanley Electric Co., Ltd. Semiconductor light emitting device on insulating substrate and its manufacture method
US20140267683A1 (en) * 2013-03-15 2014-09-18 LuxVue Technology Corporation Method of fabricating a light emitting diode display with integrated defect detection test
US20170133282A1 (en) * 2013-03-13 2017-05-11 Taiwan Semiconductor Manufacturing Company, Ltd. Chip-on-Wafer Process Control Monitoring for Chip-on-Wafer-on-Substrate Packages
US20190157501A1 (en) * 2017-11-20 2019-05-23 Lg Display Co., Ltd. Display device and method of manufacturing the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050253161A1 (en) * 2004-05-11 2005-11-17 Stanley Electric Co., Ltd. Semiconductor light emitting device on insulating substrate and its manufacture method
US20170133282A1 (en) * 2013-03-13 2017-05-11 Taiwan Semiconductor Manufacturing Company, Ltd. Chip-on-Wafer Process Control Monitoring for Chip-on-Wafer-on-Substrate Packages
US20140267683A1 (en) * 2013-03-15 2014-09-18 LuxVue Technology Corporation Method of fabricating a light emitting diode display with integrated defect detection test
US20190157501A1 (en) * 2017-11-20 2019-05-23 Lg Display Co., Ltd. Display device and method of manufacturing the same

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
LIU ZHAOJUN, LIN CHUN-HO, HYUN BYUNG-RYOOL, SHER CHIN-WEI, LV ZHIJIAN, LUO BINGQING, JIANG FULONG, WU TOM, HO CHIH-HSIANG, KUO HAO: "Micro-light-emitting diodes with quantum dots in display technology", LIGHT: SCIENCE & APPLICATIONS, vol. 9, no. 1, XP093075704, DOI: 10.1038/s41377-020-0268-1 *

Similar Documents

Publication Publication Date Title
US10008652B2 (en) Light emitting diode device with reconstituted LED components on substrate
US8815622B2 (en) Laser liftoff structure and related methods
TWI442602B (zh) 發光結構及其製造方法
US8309377B2 (en) Fabrication of reflective layer on semiconductor light emitting devices
US20120064642A1 (en) Method to remove sapphire substrate
JP2019114804A (ja) 支持基板に接合された発光デバイス
CN102388436B (zh) 发光二极管的制造设备与方法
US20130264587A1 (en) Stacked led device using oxide bonding
JP2023518180A (ja) 共通電極を有する発光ダイオードデバイス
JP2023516813A (ja) 電流拡散層を有する発光ダイオードデバイス
JP7507317B2 (ja) フリップチップマイクロ発光ダイオード
TWI750650B (zh) 用於表面貼裝微型led流體組裝的發光顯示基板及製備方法
JP2023518181A (ja) 電流拡散層を含む多層複合膜を有する発光ダイオードデバイス
CN115210869A (zh) 具有限定的硬掩模开口的发光二极管器件
JP2014525683A (ja) 基板の半導体発光素子への接合方法
TW201913744A (zh) 發光二極體
GB2596570A (en) Light emitting array
WO2023129806A1 (fr) Appareil de test de microstructures
TW201332149A (zh) 於半導體發光裝置上形成厚金屬層
JP7559243B2 (ja) フリップチップマイクロ発光ダイオードを製造する方法
US12100791B2 (en) Method for producing a semiconductor component having an insulating substrate, and semiconductor component having an insulating substrate
US20240097087A1 (en) Method of Transferring Patterned Micro-LED Die onto a Silicon Carrier for Wafer-to-Wafer Hybrid Bonding to a CMOS Backplane

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22917437

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE