WO2023125558A1 - 数据传输的方法、模块、装置、设备及存储介质 - Google Patents

数据传输的方法、模块、装置、设备及存储介质 Download PDF

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Publication number
WO2023125558A1
WO2023125558A1 PCT/CN2022/142438 CN2022142438W WO2023125558A1 WO 2023125558 A1 WO2023125558 A1 WO 2023125558A1 CN 2022142438 W CN2022142438 W CN 2022142438W WO 2023125558 A1 WO2023125558 A1 WO 2023125558A1
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Prior art keywords
target
data packet
storage control
target data
unit
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PCT/CN2022/142438
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English (en)
French (fr)
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蔡凯
田佩佳
张雨生
汪福全
刘明
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声龙(新加坡)私人有限公司
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Publication of WO2023125558A1 publication Critical patent/WO2023125558A1/zh
Priority to US18/358,015 priority Critical patent/US20230367735A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0002—Serial port, e.g. RS232C
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0004—Parallel ports, e.g. centronics

Definitions

  • the present application relates to the technical field of communications, and in particular to a data transmission method, module, device, device, and storage medium.
  • DRAM Dynamic Random Access Memory
  • the transmission bit width of the memory is limited by the hardware structure, and is usually smaller than the transmission bit width of the data packet. Therefore, the efficiency of transmitting data packets is limited by the transmission bit width of the memory, resulting in low efficiency of transmitting data packets.
  • the present application provides a data transmission method, module, device, equipment and storage medium.
  • the present application provides a data transmission method, the method comprising:
  • the target data packet including the address of the target data packet
  • the target parallel-to-serial unit corresponding to the target data packet is determined from the preset N parallel-to-serial units, and the N parallel-to-serial units are respectively connected with the N
  • the storage control units are connected one by one, and the N is a positive integer greater than 1;
  • the target storage control unit Send the target data packet to the target storage control unit through the target parallel-to-serial unit, and store the target data packet in the corresponding storage unit through the target storage control unit, the target storage control unit It is a storage control unit connected with the target parallel-to-serial unit.
  • the target parallel-to-serial unit is used to split the target data packet into multiple sub-packets.
  • the present application provides a data transmission module for performing the above method, including:
  • a transmission unit a write data path interface, N parallel-to-serial units, and N storage control units
  • the input end of the write data path interface is connected to the output end of the transmission unit, and the output end of the write data path interface
  • the input terminals of the N parallel-to-serial units are respectively connected, the output terminals of the N parallel-to-serial units are respectively connected to the input terminals of the N storage control units in one-to-one correspondence, and the N is greater than positive integer of 1;
  • the transmission unit is used to obtain a target data packet, and send the target data packet to the write data path interface, and the target data packet includes an address of the target data packet;
  • the write data path interface is used to determine the target parallel-to-serial unit corresponding to the target data packet from the N parallel-to-serial units according to the address of the target data packet, and write the target data packet to A packet is sent to the target parallel-to-serial unit;
  • the target parallel-to-serial unit is used to send the target data packet to the target storage control unit and split the target data packet into multiple sub-packets.
  • the target storage control unit is the target parallel-to-serial unit. connected storage control unit;
  • the target storage control unit is used for storing the target data packet in a corresponding storage unit.
  • the present application provides a data transmission device, including:
  • an acquisition unit configured to acquire a target data packet to be stored, where the target data packet includes the address of the target data
  • the determining unit is configured to determine the target parallel-to-serial unit corresponding to the target data packet from preset N parallel-to-serial units according to the address of the target data packet, and the N parallel-to-serial units
  • the units are respectively connected to N storage control units one by one, and the N is a positive integer greater than 1;
  • a sending unit configured to send the target data packet to a target storage control unit through the target parallel-to-serial unit, and store the target data packet in a corresponding storage unit through the target storage control unit, so
  • the target storage control unit is a storage control unit connected to the target parallel-to-serial unit.
  • the embodiment of the present application provides a chip, including:
  • a processor and a memory the memory is used to store a computer program, and the processor is used to call and run the computer program stored in the memory to execute the method in the first aspect or its implementation.
  • the embodiment of the present application provides an electronic device, including:
  • a processor and a memory the memory is used to store a computer program, and the processor is used to call and run the computer program stored in the memory to execute the method in the first aspect or its implementation.
  • an embodiment of the present application provides a computer-readable storage medium, which is used to store a computer program, and the computer program causes a computer to execute the method in the first aspect or its implementation manner.
  • a computer program which, when running on a computer, causes the computer to execute the method in the above first aspect or various implementations thereof.
  • Fig. 1 is a schematic structural diagram of a data transmission module provided by the related art
  • FIG. 2 is a schematic structural diagram of a data transmission module provided by an embodiment of the present application.
  • FIG. 3 is a schematic flow diagram of a data transmission method provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a data transmission device provided by an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of an electronic device provided by an embodiment of the present application.
  • the embodiment of the present application relates to the technical field of data transmission.
  • DAG Directed Acyclic Graph
  • the DAG data packet at least includes a data control flow signal, an address of the DAG data packet, and data to be stored.
  • the data control flow signal is used to indicate the time node for sending the DAG data packet, and the address of the DAG data packet is used to determine the corresponding storage unit of the DAG data packet in the memory.
  • Fig. 1 is a data transmission module provided by the related art.
  • a data transmission module 10 provided in the related art includes a transmission unit 100 , a parallel-to-serial unit 101 , a write data path interface 102 , and N storage control units 103 .
  • the algorithm for calculating DAG data determines the bit width of the generated DAG data packet, and the physical structure of the DRAM determines the input bit width of the DRAM. Since the input bit width of the DRAM is smaller than the bit width of the DAG data packet, the data transmission module 10 needs to split the DAG data packet in the DAG data packet into a plurality of sub-components whose bit width is smaller than the input bit width of the DRAM through the parallel-to-serial unit 101.
  • the transmission unit 100 can send a DAG data packet in one clock cycle, since the parallel-to-serial unit 101 can only send one sub-packet in one clock cycle, it takes multiple clock cycles to transmit multiple sub-packets.
  • the parallel-to-serial unit 101 will only receive the next DAG data packet when the transmission of the sub-data packet corresponding to the previous DAG data packet is completed. In this way, the DAG data packet generates data at the output end of the transmission unit 100 Congestion, resulting in low efficiency of data transmission.
  • the bit width of the DAG data packet is 512bit
  • the input bit width of the DRAM is 128bit
  • the parallel-to-serial unit 101 splits the DAG data packet into 4 sub-packets, then the parallel-to-serial unit 101 needs to go through 4 cycles
  • the output terminal of the transmission unit 100 detects that the transmission efficiency of the 512-bit DAG data packet does not exceed 25%.
  • bit width of the DAG data packet refers to the amount of data that the DAG data packet can transmit at one time
  • the input bit width of the DRAM refers to the amount of data that the DRAM can receive at one time
  • the embodiment of the present application sets N parallel-to-serial units, and connects these N parallel-to-serial units with N storage units one by one.
  • the target data to be stored can be The address of the packet, determine the target parallel-to-serial unit corresponding to the target data packet from the above-mentioned N parallel-to-serial units, and send the above-mentioned target data packet to the target storage control unit by the target parallel-to-serial unit, so as to avoid Data packet congestion, thereby improving the transmission efficiency of data packets.
  • FIG. 2 is a schematic structural diagram of a data transmission module 20 provided by the embodiment of the present application. As shown in FIG. Storage control unit 203 .
  • the input end of the write data path interface 201 is connected to the output end of the transmission unit 200, the output end of the write data path interface 201 is respectively connected to the input ends of N parallel-to-serial units 202, and the N parallel-to-serial units 202
  • the output terminals of N are connected to the input terminals of N storage control units 203 in one-to-one correspondence, and N is a positive integer greater than 1.
  • the transmission unit 200 is configured to obtain a target data packet, and send the target data packet to the write data path interface 201, where the target data packet includes an address of the target data packet.
  • the address of the target data packet refers to the address of the target storage unit corresponding to the target data package.
  • each storage control unit manages D storage units.
  • the address range of the target storage unit is between 0 and ( Between D-1) ⁇ N, D is an integer greater than 1, and D is also called the address depth of the storage control unit.
  • the target data packet can be calculated by a central processing unit (Center Processing Unit, CPU), a micro control unit (Micro Control Unit, MCU) or a system on chip (System on Chip, SoC), and can also be obtained from other storage devices.
  • CPU Center Processing Unit
  • MCU Micro Control Unit
  • SoC System on Chip
  • the write data path interface 201 is used to determine the target parallel-to-serial unit corresponding to the target data packet from the N parallel-to-serial units 202 according to the address of the target data packet, and send the target data packet to the target parallel-to-serial unit unit.
  • the write data path interface 201 is specifically used to determine the target parallel-to-serial unit corresponding to the target data packet from the N parallel-to-serial units 202 according to the address of the target data packet may be:
  • the write data path interface 201 first determines the target storage control unit 203 corresponding to the target data packet according to the address of the target data packet and the number of storage control units 203, and then writes the data path interface 201 to connect the parallel switches connected to the target storage control unit.
  • the serial unit 202 is determined as the target parallel-to-serial unit corresponding to the target data packet.
  • the write data path interface 201 determines the target parallel-to-serial unit corresponding to the target data packet from the preset N parallel-to-serial units 202 according to the address of the target data packet may also be:
  • the write data path interface 201 first determines the target storage control unit 203 corresponding to the target data packet according to the address of the target data packet and the address depth of the storage unit, and then the write data path interface 201 converts the parallel-to-serial unit connected to the target storage control unit 202. Determine the target parallel-to-serial conversion unit corresponding to the target data packet. Wherein, the rounding is rounding up or rounding down.
  • the write data path interface 201 is specifically used for:
  • the write data path interface 201 determines the remainder between the address of the target data packet and the number of storage control units 203, and determines the storage control unit 203 identified as the remainder among the N storage control units 203 as the target corresponding to the target data packet storage control unit.
  • N storage control units are sequentially identified as 1, 2, ..., N, the quotient of Add divided by N is K and the remainder is L, N, Add , K and L is an integer, and at this time it can be determined that the storage control unit identified as L among the N storage control units is the target storage control unit corresponding to the target data packet.
  • the write data path interface 201 can also be used to determine the address of the target data packet, round the number of storage control units 203, and identify the storage control unit among the N storage control units 203 as the rounded storage control unit , determined as the target storage control unit corresponding to the target data packet.
  • N storage control units are sequentially identified as 1, 2, ..., N, Add rounds N to K, and N, Add , and K are all integers. At this time, it may be determined that the storage control unit identified as K among the N storage control units is the target storage control unit corresponding to the target data packet.
  • the target parallel-to-serial unit is used to split the target data packet into multiple sub-packets and send the multiple sub-packets to the target storage control unit, and store the target data packet in the corresponding storage unit by the target storage control unit,
  • the target storage control unit is the storage control unit 203 connected to the target parallel-to-serial unit.
  • the write data path interface 201 is specifically configured to determine the quotient between the address of the target data packet and the number of the storage control unit 203 as the storage address of the target data packet in the storage unit.
  • the write data path interface 201 stores the target data packet in the storage unit through the target storage control unit according to the storage address.
  • the address of the target data packet is A dd
  • the quotient of A dd divided by N is K and the remainder is L
  • N, A dd , K and L are all integers.
  • the N storage control unit is identified as L
  • the storage unit with address K in the storage control unit is the storage address of the target data packet in the storage unit.
  • the write data path interface 201 is specifically used to establish other corresponding relationships between the address of the target data packet and the number of storage control units 203, which is not limited in this embodiment of the present application.
  • the target data packet is a DAG data packet.
  • the algorithm for calculating the directed acyclic graph data packet determines that the bit width of the generated directed acyclic graph data packet is 512bit or 1024bit, which is not equal to the input bit width of 64bit or 128bit commonly used by the storage unit, and the directed acyclic graph Data packets are usually larger, so when the target data packet is a directed acyclic graph data packet, it is more suitable to be applied to the above method. Based on this, when the above-mentioned data transmission module is set in the proof-of-work chip, the time spent by the proof-of-work chip in transmitting the directed acyclic graph data packet is reduced, and the loss of computing power is small.
  • the address of the target data packet is randomly generated during the process of generating the target data packet, that is, the address of the target data packet can be issued in real time when calculating the target data packet.
  • the address of the target data packet may also be allocated after the data transmission unit 200 obtains the complete target data packet.
  • the target data packet with the address 0 will hit the storage control unit marked as 1
  • the target data packet with the address 1 will hit the storage control unit marked with 1
  • the target data packet whose address is N-1 will hit the storage control unit marked as N.
  • the addresses of multiple target data packets will not continuously hit the same storage control unit, so that multiple target data packets will not continuously hit the same parallel-to-serial unit, so that multiple parallel-to-serial units can be issued at the same time Subpackets to avoid congestion of target packets.
  • the parallel-to-serial unit 202 is further configured to: split the target data packet into M sub-packets and sequentially send the M sub-packets to the target storage control unit, where M is a positive integer.
  • the parallel-to-serial unit 202 divides the target data packet into M sub-packets, so that the bit width of the sub-packets is less than or equal to the input bit width of the storage unit, and sends them to the target storage control unit sequentially in M times, thereby storing control
  • the input bit width of the unit can be any input bit width, which will not affect the transmission efficiency of the data transmission module.
  • the write data path interface 201 determines the target data packet from the preset N parallel-to-serial units.
  • the parallel-to-serial unit is used as the target parallel-to-serial unit before transmission, and the target data packet is transmitted to the corresponding target parallel-to-serial unit, and each parallel-to-serial unit has a corresponding storage control unit, so First, when multiple target data packets do not hit the same storage control unit, different parallel-to-serial units among the N parallel-to-serial units can simultaneously transmit target data packets to the corresponding storage control unit, greatly improving the transmission efficiency.
  • the bit width of the target data packet is 512bit
  • the input bit width of the storage control unit is 128bit
  • the transmission efficiency of the data packet detected at the output of the transmission unit is 100%
  • the transmission speed is about the data in the related art 4 times that of the transmission module, which can ensure the efficiency of the data transmission module to the greatest extent.
  • the above-mentioned modules may be circuits distributed on the same chip.
  • the data transmission module provided in the embodiment of the present application may be understood as a chip with a specific data transmission function.
  • Each of the above units may also be a program code.
  • the data transmission module provided in this application may be understood as a program code executed by a computer.
  • Fig. 3 is a flow chart of a method for data transmission provided by the embodiment of the present application. As shown in Fig. 3, the method includes:
  • the address of the target data packet may be generated when the target data packet is generated, or may be allocated after the target data packet is obtained.
  • N is a positive integer greater than 1.
  • the target parallel-to-serial unit corresponding to the data packet is determined from the preset N parallel-to-serial units, including the following steps S210 and S220:
  • S210 Determine a target storage control unit corresponding to the target data packet according to the address of the target data packet and the number of storage control units.
  • determining the target storage control unit corresponding to the target data packet includes:
  • the storage control unit identified as L among the N storage control units is the storage control unit corresponding to the target data packet.
  • implementation method of S210 is not limited to the above-mentioned methods, any one can establish a corresponding relationship between the address of the target data packet and the number of storage control units so as to select different storage control units for different target data packets Any method can be used as the implementation method of S210.
  • the storage control unit is the storage control unit corresponding to the target data packet, and [] represents a rounding function.
  • S220 Determine the parallel-to-serial unit connected to the target storage control unit as the target parallel-to-serial unit corresponding to the target data packet.
  • the address of the target data packet is the address corresponding to the target data packet stored in the storage unit via the storage control unit. Since the N parallel-to-serial units are respectively connected to the N storage control units one by one, that is, the storage control unit and the parallel-to-serial One-to-one correspondence between units, the parallel-to-serial unit connected to the target storage control unit can be determined as the target parallel-to-serial unit after determining the target storage control unit corresponding to the target data packet.
  • the target storage control unit is the target parallel-to-serial unit Connected storage control unit.
  • N is a positive integer, and N can be set by the user according to hardware equipment and requirements, so it is called the preset N parallel-to-serial units. Since the target storage unit is connected to the target parallel-to-serial unit one by one, the storage unit corresponding to the target data packet is selected by selecting the storage control unit corresponding to the target storage unit.
  • the target data packet is stored in the corresponding storage unit by the target storage control unit, including:
  • the storage address of the target data packet in the storage unit refers to, since each storage control unit controls and manages D storage units, wherein each storage unit corresponds to an address in the storage control unit, in the target storage control unit, for To determine the storage unit corresponding to the target data packet, it is necessary to determine the storage address of the target data packet in the storage unit.
  • the address of the target data packet is Add
  • the number of target storage control units is N
  • Add ⁇ N K...L
  • Add , K and L Both are integers
  • K ⁇ L at this time, it is determined that K is the storage address of the target data packet in the storage unit.
  • the storage control unit marked as L stores the target data packet in the storage unit with address K.
  • the address of the target data packet is randomly generated during the process of generating the target data packet, that is, the address of the target data packet can be issued in real time when calculating the target data packet.
  • the address of the target data packet may also be allocated after the data transmission unit 200 obtains the complete target data packet.
  • the target data packet with the address 0 will hit the storage control unit marked as 1
  • the target data packet with the address 1 will hit the storage control unit marked with 1
  • the target data packet whose address is N-1 will hit the storage control unit marked as N.
  • the addresses of multiple target data packets will not continuously hit the same storage control unit, so that multiple target data packets will not continuously hit the same parallel-to-serial unit, so that multiple parallel-to-serial units can be issued at the same time Subpackets to avoid congestion of target packets.
  • the target data packet is a DAG data packet.
  • the algorithm for calculating the directed acyclic graph data packet determines that the bit width of the generated directed acyclic graph data packet is 512bit or 1024bit, which is not equal to the input bit width of 64bit or 128bit commonly used by the storage unit, and the directed acyclic graph Data packets are usually larger, so when the target data packet is a directed acyclic graph data packet, it is more suitable to be applied to the above method. Based on this, when the above-mentioned data transmission module is set in the proof-of-work chip, the time spent by the proof-of-work chip in transmitting the directed acyclic graph data packet is reduced, and the loss of computing power is small.
  • the target data packet is sent to the target storage control unit through the target parallel-to-serial unit, including:
  • the target data packet is split into M sub-packets by the target parallel-to-serial unit, so that the bit width of the sub-packets is less than or equal to the input bit width of the storage unit, and sent to the target storage control unit sequentially in M times, thereby
  • the input bit width of the storage control unit can be any input bit width without affecting the transmission efficiency of the data transmission module.
  • the parallel-to-serial unit corresponding to the target data packet is determined as the target parallel-to-serial unit before proceeding Transmission, to transmit the target data packet to the corresponding target parallel-to-serial unit, and each parallel-to-serial unit has a corresponding storage control unit, so that different parallel-to-serial units in the N parallel-to-serial units
  • the serial unit can transmit multiple target data packets to the corresponding storage control unit at the same time, which greatly improves the transmission efficiency.
  • Fig. 3 is only an example of the present application, and should not be construed as a limitation to the present application.
  • FIG. 4 is a schematic structural diagram of a data transmission device provided by an embodiment of the present application. As shown in FIG.
  • the acquiring unit 300 is configured to acquire the target data packet to be stored, and the target data packet includes the address of the target data.
  • the determining unit 301 is used to determine the target parallel-to-serial unit corresponding to the target data packet from the preset N parallel-to-serial units according to the address of the target data packet, and the N parallel-to-serial units are respectively connected with the N storage units.
  • the control units are connected one by one.
  • the sending unit 302 is used to send the target data packet to the target storage control unit through the target parallel-to-serial unit, and store the target data packet in the corresponding storage unit through the target storage control unit.
  • Storage control unit for serial unit connection.
  • the determination unit 301 is specifically configured to determine the target storage control unit corresponding to the target data packet according to the address of the target data packet and the number of storage control units; the parallel-to-serial conversion unit connected to the target storage control unit , which is determined as the target parallel-to-serial unit corresponding to the data packet.
  • the determining unit 301 is specifically configured to determine the remainder between the address of the target data packet and the number of storage control units; and determine the storage control unit identified as the remainder among the N storage control units as the target data packet Corresponding target storage control unit.
  • the sending unit 302 is specifically configured to determine the quotient between the address of the target data packet and the number of storage control units as the storage address of the target data packet in the storage unit; according to the storage address, through the target storage The control unit stores the target data packet in the storage unit.
  • the address of the target data packet is randomly generated during the generation of the target data packet.
  • the target data packet is a DAG data packet.
  • the sending unit 302 is specifically configured to split the target data packet into M sub-packets through the target parallel-to-serial unit; and send the M sub-packets to the target storage control unit sequentially through the target parallel-to-serial unit , M is a positive integer.
  • the device embodiment and the method embodiment may correspond to each other, and similar descriptions may refer to the method embodiment. To avoid repetition, details are not repeated here.
  • the apparatus shown in FIG. 4 can execute the above-mentioned method embodiments, and the aforementioned and other operations and/or functions of the various modules in the apparatus are respectively intended to realize the corresponding method embodiments of the computing device, and for the sake of brevity, are not repeated here. repeat.
  • FIG. 5 is a schematic block diagram of an electronic device provided by an embodiment of the present application.
  • the electronic device may be the above-mentioned file encapsulation device or file decapsulation device, or the electronic device may have the functions of a file encapsulation device and a file decapsulation device.
  • the electronic device 40 may include:
  • Memory 41 and memory 42 the memory 41 is used to store computer programs and transmit the program codes to the memory 42 .
  • the memory 42 can invoke and run computer programs from the memory 41 to implement the methods in the embodiments of the present application.
  • the memory 42 can be used to execute the above-mentioned method embodiments according to the instructions in the computer program.
  • the memory 42 may include but not limited to:
  • DSP Digital Signal Processor
  • ASIC Application Specific Integrated Circuit
  • FPGA Field Programmable Gate Array
  • the memory 41 includes but is not limited to:
  • non-volatile memory can be read-only memory (Read-Only Memory, ROM), programmable read-only memory (Programmable ROM, PROM), erasable programmable read-only memory (Erasable PROM, EPROM), electronically programmable Erase Programmable Read-Only Memory (Electrically EPROM, EEPROM) or Flash.
  • the volatile memory can be Random Access Memory (RAM), which acts as external cache memory.
  • RAM Static Random Access Memory
  • SRAM Static Random Access Memory
  • DRAM Dynamic Random Access Memory
  • Synchronous Dynamic Random Access Memory Synchronous Dynamic Random Access Memory
  • SDRAM double data rate synchronous dynamic random access memory
  • Double Data Rate SDRAM, DDR SDRAM double data rate synchronous dynamic random access memory
  • Enhanced SDRAM, ESDRAM enhanced synchronous dynamic random access memory
  • SLDRAM synchronous connection dynamic random access memory
  • Direct Rambus RAM Direct Rambus RAM
  • the computer program can be divided into one or more modules, and the one or more modules are stored in the memory 41 and executed by the memory 42 to complete the method provided by the present application .
  • the one or more modules may be a series of computer program instruction segments capable of accomplishing specific functions, and the instruction segments are used to describe the execution process of the computer program in the video production device.
  • the electronic device 40 may also include:
  • the transceiver 4, the transceiver 43 can be connected to the memory 42 or the memory 41.
  • the memory 42 can control the transceiver 43 to communicate with other devices, specifically, can send information or data to other devices, or receive information or data sent by other devices.
  • Transceiver 43 may include a transmitter and a receiver.
  • the transceiver 43 may further include antennas, and the number of antennas may be one or more.
  • bus system includes not only a data bus, but also a power bus, a control bus and a status signal bus.
  • the present application also provides a chip, where the chip includes a processor, and the processor is configured to execute the above-mentioned embodiments.
  • the present application also provides a computer storage medium, on which a computer program is stored, and when the computer program is executed by a computer, the computer can execute the methods of the above method embodiments.
  • the embodiments of the present application further provide a computer program product including instructions, and when the instructions are executed by a computer, the computer executes the methods of the foregoing method embodiments.
  • the computer program product includes one or more computer instructions.
  • the computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable device.
  • the computer instructions may be stored in or transmitted from one computer-readable storage medium to another computer-readable storage medium, e.g. (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) to another website site, computer, server or data center.
  • the computer-readable storage medium may be any available medium that can be accessed by a computer, or a data storage device such as a server or a data center integrated with one or more available media.
  • the available medium may be a magnetic medium (such as a floppy disk, a hard disk, or a magnetic tape), an optical medium (such as a digital video disc (digital video disc, DVD)), or a semiconductor medium (such as a solid state disk (solid state disk, SSD)), etc.
  • modules and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are executed by hardware or software depends on the specific application and design constraints of the technical solution. Skilled artisans may use different methods to implement the described functions for each specific application, but such implementation should not be regarded as exceeding the scope of the present application.
  • the disclosed systems, devices and methods may be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of the modules is only a logical function division. In actual implementation, there may be other division methods.
  • multiple modules or components can be combined or can be Integrate into another system, or some features may be ignored, or not implemented.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or modules may be in electrical, mechanical or other forms.
  • a module described as a separate component may or may not be physically separated, and a component displayed as a module may or may not be a physical module, that is, it may be located in one place, or may also be distributed to multiple network units. Part or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. For example, each functional module in each embodiment of the present application may be integrated into one processing module, each module may exist separately physically, or two or more modules may be integrated into one module.

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Abstract

本申请提供了一种数据传输的方法、模块、装置、设备及存储介质，该方法包括：获取待存储的目标数据包，所述目标数据包中包括所述目标数据包的地址；根据所述目标数据包的地址，从预设的N个并行转串行单元中，确定所述目标数据包对应的目标并行转串行单元，所述N个并行转串行单元分别与N个存储控制单元一一连接；通过所述目标并行转串行单元将所述目标数据包发送给目标存储控制单元，并通过所述目标存储控制单元将所述目标数据包存储在对应的存储单元中，所述目标存储控制单元为与所述目标并行转串行单元连接的存储控制单元，所述目标并行转串行单元用于将目标数据包拆分成多个子数据包。

Description

数据传输的方法、模块、装置、设备及存储介质
本申请要求于2021年12月30日提交中国专利局、申请号为202111636129.8、申请名称为“数据传输的方法、模块、装置、设备及存储介质”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及通信技术领域，尤其涉及一种数据传输的方法、模块、装置、设备及存储介质。
背景技术
目前，在存储较大体积的数据时，通常采用存储密度较高的动态随机存取存储器(Dynamic Random Access Memory，DRAM)存储。在传输协议相同的前提下，数据包的传输位宽越大，传输数据包的效率越高。
但是存储器的传输位宽受硬件结构的限制，通常小于数据包的传输位宽。因此，传输数据包的效率受存储器的传输位宽限制，造成数据包的传输效率低。
发明内容
本申请提供一种数据传输的方法、模块、装置、设备及存储介质。
第一方面，本申请提供一种数据传输方法，该方法包括：
获取待存储的目标数据包，所述目标数据包中包括所述目标数据包的地址；
根据所述目标数据包的地址，从预设的N个并行转串行单元中，确定所述目标数据包对应的目标并行转串行单元，所述N个并行转串行单元分别与N个存储控制单元一一连接，所述N为大于1的正整数；
通过所述目标并行转串行单元将所述目标数据包发送给目标存储控制单元，并通过所述目标存储控制单元将所述目标数据包存储在对应的存储单元中，所述目标存储控制单元为与所述目标并行转串行单元连接的存储控制单元。
其中，所述目标并行转串行单元用于将目标数据包拆分成多个子数据包。
第二方面，本申请提供一种数据传输模块，用于执行上述方法，包括：
传输单元、写数据通路接口、N个并行转串行单元以及N个存储控制单元，所述写数据通路接口的输入端与所述传输单元的输出端连接，所述写数据通路接口的输出端与所述N个并行转串行单元的输入端分别连接，所述N个并行转串行单元的输出端与所述N个存储控制单元的输入端分别一一对应连接，所述N为大于1的正整数；
所述传输单元用于获取目标数据包，并将所述目标数据包发送给所述写数据通路接口，所述目标数据包中包括所述目标数据包的地址；
所述写数据通路接口用于根据所述目标数据包的地址，从所述N个并行转串行单元中，确定所述目标数据包对应的目标并行转串行单元，并将所述目标数据包发送给所述目标并行转串行单元；
所述目标并行转串行单元用于将所述目标数据包发送给目标存储控制单元以及将目标数据包拆分成多个子数据包所述目标存储控制单元为与所述目标并行转串行单元连接的存储控制单元；
所述目标存储控制单元用于将所述目标数据包存储在对应的存储单元中。
第三方面，本申请提供一种数据传输的装置，包括：
获取单元，用于获取待存储的目标数据包，所述目标数据包中包括所述目标数据的地址；
确定单元，用于根据所述目标数据包的地址，从预设的N个并行转串行单元中，确定所述目标数据包对应的目标并行转串行单元，所述N个并行转串行单元分别与N个存储控制单元一一连接，所述N为大于1的正整数；
发送单元，用于通过所述目标并行转串行单元将所述目标数据包发送给目标存储控制单元，并通过所述目标存储控制单元将所述目标数据包存储在对应的存储单元中，所述目标存储控制单元为与所述目标并行转串行单元连接的存储控制单元。
第四方面，本申请实施例提供一种芯片，包括：
处理器和存储器，所述存储器用于存储计算机程序，所述处理器用于调用并运行所述存储器中存储的计算机程序，以执行第一方面或其实现方式中的方法。
第五方面，本申请实施例提供一种电子设备，包括：
处理器和存储器，所述存储器用于存储计算机程序，所述处理器用于调用并运行所述存储器中存储的计算机程序，以执行第一方面或其实现方式中的方法。
第六方面，本申请实施例提供一种计算机可读存储介质，其特征在于，用于存储计算机程序，所述计算机程序使得计算机执行第一方面或其实现方式中的方法。
第七方面，提供了一种计算机程序，当其在计算机上运行时，使得计算机执行上述第一方面或其各实现方式中的方法。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为相关技术提供的一种数据传输模块的结构示意图；
图2为本申请实施例提供的一种数据传输模块的结构示意图；
图3为本申请实施例提供的一种数据传输方法的流程示意图；
图4为本申请实施例提供的一种数据传输装置的结构示意图；
图5为本申请实施例提供的一种电子设备的结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
应当理解，本公开的方法实施方式中记载的各个步骤可以按照不同的顺序执行，和/或并行执行。此外，方法实施方式可以包括附加的步骤和/或省略执行示出的步骤。本公开的范围在此方面不受限制。
需要说明的是，本发明的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后 次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的本发明的实施例能够以除了在这里图示或描述的那些以外的顺序实施。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、系统、产品或服务器不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。
本申请实施例涉及数据传输技术领域。
在介绍本申请技术方案之前，下面先对本申请相关知识进行介绍：
有向无环图(Directed Acyclic Graph，DAG)随着技术的发展，DAG数据逐渐增大至超过4GB，且DAG数据随着时间更新，更新周期大约为5.2天，因此对传输DAG数据的效率有较高的要求。
由于DAG数据的体积较大，通常使用DRAM存储DAG数据。在工作量证明芯片计算之前，需要将DAG数据传输到DRAM中。由于DRAM需要不断的刷新来进行周期性的充电以保证DRAM中的数据不丢失，导致DRAM在进行刷新操作时，无法接收数据，即DRAM并非任意时刻都可以接收数据，因此用于传输DAG数据的DAG数据包至少包含数据控制流信号，DAG数据包的地址以及待存储数据。数据控制流信号用于指示发送DAG数据包的时间节点，DAG数据包的地址用于确定DAG数据包在存储器中对应的存储单元。
图1为相关技术提供的一种数据传输模块。如图1所示，相关技术提供的一种数据传输模块10，包括，传输单元100、并行转串行单元101、写数据通路接口102，以及N个存储控制单元103。
计算DAG数据的算法决定生成DAG数据包的位宽，DRAM的物理结构决定DRAM的输入位宽。由于DRAM的输入位宽小于DAG数据包的位宽，数据传输模块10需要通过并行转串行单元101将DAG数据包中的DAG数据包拆分成多个位宽小于DRAM的输入位宽的子数据包，再依次将多个子数据包发送至写数据通路接口101，接着写数据通路接口101按照DAG数据包的地址从N个存储控制单元103中选出目标存储控制单元并将子数据包发送至目标存储控制单元，目标存储控制单元再将DAG数据包存储在对应的存储单元中，以完成DAG数据包的传输。虽然传输单元100在一个时 钟周期内可发送一个DAG数据包，但是由于并行转串行单元101在一个时钟周期内只能发送一个子数据包，因此传输多个子数据包需要历经多个时钟周期，并行转串行单元101只有在将上一个DAG数据包对应的子数据包传输完成的情况下，才会接收下一个DAG数据包，这样一来，DAG数据包在传输单元100的输出端发生数据拥堵，从而造成传输数据的效率较低。
示例的，DAG数据包的位宽是512bit，DRAM的输入位宽是128bit，并行转串行单元101将DAG数据包拆分成4个子数据包，则并行转串行单元101需要历经4个周期发送一个DAG数据包，传输单元100的输出端，监测到512bit的DAG数据包的传输效率不超过百分之25。
其中，DAG数据包的位宽指的是，DAG数据包一次能传输的数据量，DRAM的输入位宽指的是DRAM一次能接收的数据量。
为了解决上述问题，本申请实施例设置N个并行转串行单元，并将这N个并行转串行单元与N个存储单元一一对应连接，在实际使用时，可以根据待存储的目标数据包的地址，从上述N个并行转串行单元中确定目标数据包对应的目标并行转串行单元，并通过该目标并行转串行单元将上述目标数据包发送给目标存储控制单元，以避免数据包拥堵，进而提高数据包的传输效率。
下面通过一些实施例对本申请实施例的技术方案进行详细说明。下面这几个实施例可以相互结合，对于相同或相似的概念或过程可能在某些实施例不再赘述。
图2为本申请实施例提供的一种数据传输模块20的结构示意图，如图2所示，该模块包括：传输单元200、写数据通路接口201、N个并行转串行单元202以及N个存储控制单元203。
其中，写数据通路接口201的输入端与传输单元200的输出端连接，写数据通路接口201的输出端与N个并行转串行单元202的输入端分别连接，N个并行转串行单元202的输出端与N个存储控制单元203的输入端分别一一对应连接，N为大于1的正整数。
传输单元200用于获取目标数据包，并将目标数据包发送给写数据通路接口201，目标数据包中包括目标数据包的地址。
其中，目标数据包的地址指的是目标数据包对应的目标存储单元的地址，示例的，每个存储控制单元管理D个存储单元，在上述情况下，目标存储单元的地址范围在0至(D-1)×N之间，D为大于1的整数，D也称为存储控制单元地址深度。目标数据包可以由中央处理器(Center Processing Unit，CPU)、微控制单元(Micro Control Unit，MCU)或者片上系统(System on Chip，SoC)计算得到，也可以从其他存储设备处获取。
写数据通路接口201用于根据目标数据包的地址，从N个并行转串行单元202中，确定目标数据包对应的目标并行转串行单元，并将目标数据包发送给目标并行转串行单元。
在一些实施例中，写数据通路接口201具体用于根据目标数据包的地址，从N个并行转串行单元202中，确定目标数据包对应的目标并行转串行单元可以是：
写数据通路接口201首先根据目标数据包的地址和存储控制单元203的个数，确定目标数据包对应的目标存储控制单元203，接下来写数据通路接口201将与目标存储控制单元连接的并行转串行单元202，确定为目标数据包对应的目标并行转串行单元。
在另外一些实施例中，写数据通路接口201根据目标数据包的地址，从预设的N个并行转串行单元202中，确定目标数据包对应的目标并行转串行单元还可以是：
写数据通路接口201首先根据目标数据包的地址和存储单元地址深度，确定目标数据包对应的目标存储控制单元203，接下来写数据通路接口201将与目标存储控制单元连接的并行转串行单元202，确定为目标数据包对应的目标并行转串行单元。其中，取整为向上取整或者向下取整。
在一些实施例中，写数据通路接口201具体用于：
写数据通路接口201确定目标数据包的地址与存储控制单元203的个数之间的余数，并将N个存储控制单元203中标识为余数的存储控制单元203，确定为目标数据包对应的目标存储控制单元。
示例的，假设目标数据包的地址为A dd，N个存储控制单元被依次标识为1、2、…、N，A dd除以N的商为K余数为L，N、A dd、K和L均为整数，此时可以确定N个存储控制单元中标识为L的存储控制单元为目标数据包 对应的目标存储控制单元。
在另外一些实施例中，写数据通路接口201还可以用于确定目标数据包的地址对存储控制单元203的个数取整，并将N个存储控制单元203中标识为取整的存储控制单元，确定为目标数据包对应的目标存储控制单元。
示例的，假设目标数据包的地址为A dd，N个存储控制单元被依次标识为1、2、…、N，A dd对N取整为K，N、A dd、K均为整数，此时可以确定N个存储控制单元中标识为K的存储控制单元为目标数据包对应的目标存储控制单元。
目标并行转串行单元用于将目标数据包拆分成多个子数据包以及将多个子数据包发送给目标存储控制单元，并通过目标存储控制单元将目标数据包存储在对应的存储单元中，目标存储控制单元为与目标并行转串行单元连接的存储控制单元203。
在一些实施例中，写数据通路接口201具体用于将目标数据包的地址与存储控制单元203的个数之间的商，确定为目标数据包在存储单元中的存储地址。
写数据通路接口201根据存储地址，通过目标存储控制单元将目标数据包存储在存储单元中。
示例的，目标数据包的地址为A dd，A dd除以N商为K余数为L，N、A dd、K和L均为整数，此时可以确定N个存储控制单元中标识为L的存储控制单元中地址为K的存储单元为目标数据包在存储单元中的存储地址。
在另外一些实施例中，写数据通路接口201具体用于建立目标数据包的地址与存储控制单元203的个数之间的其他对应关系，本申请实施例对此不做限定。
在一些实施例中，目标数据包为有向无环图数据包。计算有向无环图数据包的算法决定了，生成有向无环图数据包的位宽为512bit或者1024bit，与存储单元常用的64bit或者128bit的输入位宽不相等，并且有向无环图数据包通常较大，因此当目标数据包为有向无环图数据包时，更适合应用到上述方法。基于此，当上述数据传输模块设置在工作量证明芯片中时，工作量证明芯片在传输有向无环图数据包的环节所用的时间减少，算力损失小。
在一些实施例中，目标数据包的地址是在生成目标数据包的过程中随机 生成的，即目标数据包的地址可以是在计算目标数据包时实时下发的。目标数据包的地址也可以是数据传输单元200获取完整的目标数据包后再分配的。
示例的，对于已经获取的多个目标数据包，地址为0的目标数据包会命中标识为1的存储控制单元，地址为1的目标数据包会命中标识为1的存储控制单元，依次类推，地址为N-1的目标数据包会命中标识为N的存储控制单元。这样一来，多个目标数据包的地址不会连续命中同一存储控制单元，从而多个目标数据包不会连续命中同一个并行转串行单元，从而多个并行转串行单元可以同时下发子数据包，避免目标数据包的拥堵。
在一些实施例中，并行转串行单元202还用于：将目标数据包拆分成M个子数据包以及将M个子数据包依次发送给目标存储控制单元，M为正整数。
并行转串行单元202通过将目标数据包拆分成M个子数据包，使得子数据包的位宽小于或者等于存储单元的输入位宽，分M次依次发送给目标存储控制单元，从而存储控制单元的输入位宽可以是任意输入位宽，不会影响到数据传输模块的传输效率。
在此基础上，在目标数据包的传输过程中，由于设置了N个并行转串行单元202，写数据通路接口201从预设的N个并行转串行单元中，确定目标数据包对应的并行转串行单元作为目标并行转串行单元之后再进行传输，将目标数据包传输至对对应的目标并行转串行单元，并且每一并行转串行单元均有对应的存储控制单元，这样一来，在多个目标数据包不命中同一个存储控制单元的情况下，N个并行转串行单元中不同的并行转串行单元可以同时向对应的存储控制单元传输目标数据包，大大提升了传输效率。示例的，目标数据包的位宽是512bit，存储控制单元的输入位宽是128bit，则在传输单元输出端监测到数据包的传输效率为百分之100，传输速度约是相关技术中的数据传输模块的4倍，可以最大程度的保证数据传输模块的效率。
在具体实施方式中，上述各模块可以为分布在同一个芯片上的电路，基于此，本申请实施例提供的数据传输模块可以理解为一个具体数据传输功能的芯片。上述各单元也可以为程序代码，基于此，本申请提供的数据传输模块可以理解为由计算机执行的程序代码。
上文对本申请实施例涉及的数据传输模块进行了介绍，在此基础上，下面对本申请提供的数据传输方法进行介绍。
图3为本申请实施例提供一种数据传输的方法流程图，如图3所示，该方法包括：
S100、获取待存储的目标数据包，该目标数据包中包括目标数据包的地址。
其中，目标数据包的地址可以是在生成目标数据包时生成的，也可以是在获取目标数据包之后分配的。
S200、根据目标数据包的地址，从预设的N个并行转串行单元中，确定目标数据包对应的目标并行转串行单元，N个并行转串行单元分别与N个存储控制单元一一连接，N为大于1的正整数。
在一些实施例中，S200中根据目标数据包的地址，从预设的N个并行转串行单元中，确定数据包对应的目标并行转串行单元，包括如下步骤S210和S220：
S210、根据目标数据包的地址和存储控制单元的个数，确定目标数据包对应的目标存储控制单元。
在一些实施例中，S210中根据目标数据包的地址和存储控制单元的个数，确定目标数据包对应的目标存储控制单元，包括：
S211、确定目标数据包的地址与存储控制单元的个数之间的余数。
S212、将N个存储控制单元中标识为余数的存储控制单元，确定为目标数据包对应的目标存储控制单元。
假设目标数据包的地址为A dd，目标存储控制单元依次标识为1、2、…、N，，A dd÷N＝K…L，n、A dd、K和L均为整数，此时确定N个存储控制单元中标识为L的存储控制单元为目标数据包对应的存储控制单元。
需要理解的是，S210的实现方法并不仅仅限于上述方法，任意一种能够建立目标数据包的地址与存储控制单元的个数之间对应关系以对于不同的目标数据包选择不同的存储控制单元的方法均可作为S210的实现方法。
示例的，假设目标数据包的地址为A dd，目标存储控制单元依次标识为1、2、…、N，[A dd÷N]＝K，此时确定N个存储控制单元中标识为K的存储 控制单元为目标数据包对应的存储控制单元，[]代表取整函数。
S220、将目标存储控制单元连接的并行转串行单元，确定为目标数据包对应的目标并行转串行单元。
目标数据包的地址为目标数据包经由存储控制单元存储在存储单元中对应的地址，由于N个并行转串行单元分别与N个存储控制单元一一连接，即存储控制单元与并行转串行单元一一对应，确定了目标数据包对应的目标存储控制单元即可确定与目标存储控制单元连接的并行转串行单元为目标并行转串行单元。
S300、通过目标并行转串行单元将目标数据包发送给目标存储控制单元，并通过目标存储控制单元将目标数据包存储在对应的存储单元中，目标存储控制单元为与目标并行转串行单元连接的存储控制单元。
其中，N为正整数，N可以由用户根据硬件设备和需求设定，故称为预设的N个并行转串行单元。由于目标存储单元与目标并行转串行单元一一连接，因此，通过选择与目标存储单元对应的存储控制单元，选择目标数据包对应的存储单元。
在一些实施例中，S300中通过目标存储控制单元将目标数据包存储在对应的存储单元中，包括：
S310、将目标数据包的地址与存储控制单元的个数之间的商，确定为目标数据包在存储单元中的存储地址。
S320、根据存储地址，通过目标存储控制单元将目标数据包存储在存储单元中。
目标数据包在存储单元中的存储地址指的是，由于每个存储控制单元控制管理D个存储单元，其中每个存储单元在存储控制单元中对应的一个地址，在目标存储控制单元中，为了确定目标数据包对应的存储单元，需要确定目标数据包在存储单元中的存储地址。示例的，假设每个存储控制单元控制管理D个存储单元，目标数据包的地址为A dd，目标存储控制单元的个数为N，A dd÷N＝K…L，A dd、K和L均为整数，且K＜L，此时确定K为目标数据包在存储单元中存储地址。接着标识为L的存储控制单元将目标数据包存储在地址为K的存储单元中。
在一些实施例中，目标数据包的地址是在生成目标数据包的过程中随机 生成的，即目标数据包的地址可以是在计算目标数据包时实时下发的。目标数据包的地址也可以是数据传输单元200获取完整的目标数据包后再分配的。
示例的，对于已经获取的多个目标数据包，地址为0的目标数据包会命中标识为1的存储控制单元，地址为1的目标数据包会命中标识为1的存储控制单元，依次类推，地址为N-1的目标数据包会命中标识为N的存储控制单元。这样一来，多个目标数据包的地址不会连续命中同一存储控制单元，从而多个目标数据包不会连续命中同一个并行转串行单元，从而多个并行转串行单元可以同时下发子数据包，避免目标数据包的拥堵。
在一些实施例中，目标数据包为有向无环图数据包。计算有向无环图数据包的算法决定了，生成有向无环图数据包的位宽为512bit或者1024bit，与存储单元常用的64bit或者128bit的输入位宽不相等，并且有向无环图数据包通常较大，因此当目标数据包为有向无环图数据包时，更适合应用到上述方法。基于此，当上述数据传输模块设置在工作量证明芯片中时，工作量证明芯片在传输有向无环图数据包的环节所用的时间减少，算力损失小。
在一些实施例中，S300中通过目标并行转串行单元将目标数据包发送给目标存储控制单元，包括：
S301、通过目标并行转串行单元将目标数据包拆分成M个子数据包，使得子数据包的位宽小于或者等于存储单元的输入位宽，分M次依次发送给目标存储控制单元，从而存储控制单元的输入位宽可以是任意输入位宽，不会影响到数据传输模块的传输效率。S302、通过目标并行转串行单元将M个子数据包依次发送给目标存储控制单元，M为正整数。
在此基础上，在目标数据包的传输过程中，由于是从预设的N个并行转串行单元中，确定目标数据包对应的并行转串行单元作为目标并行转串行单元之后再进行传输，将目标数据包传输至对对应的目标并行转串行单元，并且每一并行转串行单元均有对应的存储控制单元，这样一来，N个并行转串行单元中不同的并行转串行单元可以同时向对应的存储控制单元传输多个目标数据包，大大提升了传输效率。
应理解，图3仅为本申请的示例，不应理解为对本申请的限制。
以上结合附图详细描述了本申请的优选实施方式，但是，本申请并不限 于上述实施方式中的具体细节，在本申请的技术构思范围内，可以对本申请的技术方案进行多种简单变型，这些简单变型均属于本申请的保护范围。例如，在上述具体实施方式中所描述的各个具体技术特征，在不矛盾的情况下，可以通过任何合适的方式进行组合，为了避免不必要的重复，本申请对各种可能的组合方式不再另行说明。又例如，本申请的各种不同的实施方式之间也可以进行任意组合，只要其不违背本申请的思想，其同样应当视为本申请所公开的内容。
图4为本申请实施例提供一种数据传输装置的结构示意图，如图4所示，本申请实施例提供一种数据传输装置30，包括：获取单元300、确定单元301以及发送单元302。
获取单元300用于获取待存储的目标数据包，目标数据包中包括目标数据的地址。
确定单元301用于根据目标数据包的地址，从预设的N个并行转串行单元中，确定目标数据包对应的目标并行转串行单元，N个并行转串行单元分别与N个存储控制单元一一连接。
发送单元302用于通过目标并行转串行单元将目标数据包发送给目标存储控制单元，并通过目标存储控制单元将目标数据包存储在对应的存储单元中，目标存储控制单元为与目标并行转串行单元连接的存储控制单元。
在一些实施例中，确定单元301具体用于根据目标数据包的地址和存储控制单元的个数，确定目标数据包对应的目标存储控制单元；将与目标存储控制单元连接的并行转串行单元，确定为数据包对应的目标并行转串行单元。
在一些实施例中，确定单元301具体用于确定目标数据包的地址与存储控制单元的个数之间的余数；将N个存储控制单元中标识为余数的存储控制单元，确定为目标数据包对应的目标存储控制单元。
在一些实施例中，发送单元302具体用于将目标数据包的地址与存储控制单元的个数之间的商，确定为目标数据包在存储单元中的存储地址；根据存储地址，通过目标存储控制单元将目标数据包存储在存储单元中。
在一些实施例中，目标数据包的地址是在生成目标数据包的过程中随机 生成的。
在一些实施例中，目标数据包为有向无环图数据包。
在一些实施例中，发送单元302具体用于通过目标并行转串行单元将目标数据包拆分成M个子数据包；通过目标并行转串行单元将M个子数据包依次发送给目标存储控制单元，M为正整数。
应理解的是，装置实施例与方法实施例可以相互对应，类似的描述可以参照方法实施例。为避免重复，此处不再赘述。具体地，图4所示的装置可以执行上述方法的实施例，并且装置中的各个模块的前述和其它操作和/或功能分别为了实现计算设备对应的方法实施例，为了简洁，在此不再赘述。
图5是本申请实施例提供的电子设备的示意性框图，该电子设备可以为上述的文件封装设备、或文件解封装设备，或者该电子设备具有文件封装设备和文件解封装设备的功能。
如图5所示，该电子设备40可包括：
存储器41和存储器42，该存储器41用于存储计算机程序，并将该程序代码传输给该存储器42。换言之，该存储器42可以从存储器41中调用并运行计算机程序，以实现本申请实施例中的方法。
例如，该存储器42可用于根据该计算机程序中的指令执行上述方法实施例。
在本申请的一些实施例中，该存储器42可以包括但不限于：
通用处理器、数字信号处理器(Digital Signal Processor，DSP)、专用集成电路(Application Specific Integrated Circuit，ASIC)、现场可编程门阵列(Field Programmable Gate Array，FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等等。
在本申请的一些实施例中，该存储器41包括但不限于：
易失性存储器和/或非易失性存储器。其中，非易失性存储器可以是只读存储器(Read-Only Memory，ROM)、可编程只读存储器(Programmable ROM，PROM)、可擦除可编程只读存储器(Erasable PROM，EPROM)、电可擦除可编程只读存储器(Electrically EPROM，EEPROM)或闪存。易失性存储器可以是随机存取存储器(Random Access Memory，RAM)，其用作外部高 速缓存。通过示例性但不是限制性说明，许多形式的RAM可用，例如静态随机存取存储器(Static RAM，SRAM)、动态随机存取存储器(Dynamic RAM，DRAM)、同步动态随机存取存储器(Synchronous DRAM，SDRAM)、双倍数据速率同步动态随机存取存储器(Double Data Rate SDRAM，DDR SDRAM)、增强型同步动态随机存取存储器(Enhanced SDRAM，ESDRAM)、同步连接动态随机存取存储器(synch link DRAM，SLDRAM)和直接内存总线随机存取存储器(Direct Rambus RAM，DR RAM)。
在本申请的一些实施例中，该计算机程序可以被分割成一个或多个模块，该一个或者多个模块被存储在该存储器41中，并由该存储器42执行，以完成本申请提供的方法。该一个或多个模块可以是能够完成特定功能的一系列计算机程序指令段，该指令段用于描述该计算机程序在该视频制作设备中的执行过程。
如图4所示，该电子设备40还可包括：
收发器4，该收发器43可连接至该存储器42或存储器41。
其中，存储器42可以控制该收发器43与其他设备进行通信，具体地，可以向其他设备发送信息或数据，或接收其他设备发送的信息或数据。收发器43可以包括发射机和接收机。收发器43还可以进一步包括天线，天线的数量可以为一个或多个。
应当理解，该视频制作设备中的各个组件通过总线系统相连，其中，总线系统除包括数据总线之外，还包括电源总线、控制总线和状态信号总线。
本申请还提供了一种芯片，所述芯片包括处理器，所述处理器用于执行上述实施例。
本申请还提供了一种计算机存储介质，其上存储有计算机程序，该计算机程序被计算机执行时使得该计算机能够执行上述方法实施例的方法。或者说，本申请实施例还提供一种包含指令的计算机程序产品，该指令被计算机执行时使得计算机执行上述方法实施例的方法。
当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。该计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行该计算机程序指令时，全部或部分地产生按照本申请实施例该的流程或功能。该计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。 该计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，该计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如同轴电缆、光纤、数字用户线(digital subscriber line，DSL))或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。该计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可用介质集成的服务器、数据中心等数据存储设备。该可用介质可以是磁性介质(例如，软盘、硬盘、磁带)、光介质(例如数字视频光盘(digital video disc，DVD))、或者半导体介质(例如固态硬盘(solid state disk，SSD))等。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的模块及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，该模块的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个模块或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或模块的间接耦合或通信连接，可以是电性，机械或其它的形式。
作为分离部件说明的模块可以是或者也可以不是物理上分开的，作为模块显示的部件可以是或者也可以不是物理模块，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部模块来实现本实施例方案的目的。例如，在本申请各个实施例中的各功能模块可以集成在一个处理模块中，也可以是各个模块单独物理存在，也可以两个或两个以上模块集成在一个模块中。
以上内容，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护 范围应以该权利要求的保护范围为准。

Claims (17)

  1. 一种数据传输的方法，其特征在于，包括：
    获取待存储的目标数据包，所述目标数据包中包括所述目标数据包的地址；
    根据所述目标数据包的地址，从预设的N个并行转串行单元中，确定所述目标数据包对应的目标并行转串行单元，所述N个并行转串行单元分别与N个存储控制单元一一连接，所述N为大于1的正整数；
    通过所述目标并行转串行单元将所述目标数据包发送给目标存储控制单元，并通过所述目标存储控制单元将所述目标数据包存储在对应的存储单元中，所述目标存储控制单元为与所述目标并行转串行单元连接的存储控制单元；
    其中，所述目标并行转串行单元用于将目标数据包拆分成多个子数据包。
  2. 根据权利要求1所述的方法，其特征在于，所述根据所述目标数据包的地址，从预设的N个并行转串行单元中，确定所述数据包对应的目标并行转串行单元，包括：
    根据所述目标数据包的地址和存储控制单元的个数，确定所述目标数据包对应的目标存储控制单元；
    将与所述目标存储控制单元连接的并行转串行单元，确定为所述数据包对应的目标并行转串行单元。
  3. 根据权利要求2所述的方法，其特征在于，所述根据所述目标数据包的地址和存储控制单元的个数，确定所述目标数据包对应的目标存储控制单元，包括：
    确定所述目标数据包的地址与所述存储控制单元的个数之间的余数；
    将所述N个存储控制单元中标识为所述余数的存储控制单元，确定为所述目标数据包对应的目标存储控制单元。
  4. 根据权利要求2所述的方法，其特征在于，所述通过所述目标存储控制单元将所述目标数据包存储在对应的存储单元中，包括：
    将所述目标数据包的地址与所述存储控制单元的个数之间的商，确定为所述目标数据包在所述存储单元中的存储地址；
    根据所述存储地址，通过所述目标存储控制单元将所述目标数据包存储在所述存储单元中。
  5. 根据权利要求1-4任一项所述的方法，其特征在于，所述目标数据包为有向无环图数据包。
  6. 根据权利要求1-3任一项所述的方法，其特征在于，所述通过所述目标并行转串行单元将所述目标数据包发送给目标存储控制单元，包括：
    通过所述目标并行转串行单元将所述目标数据包拆分成M个子数据包；
    通过所述目标并行转串行单元将所述M个子数据包依次发送给所述目标存储控制单元，所述M为正整数。
  7. 一种数据传输模块，其特征在于，包括：传输单元、写数据通路接口、N个并行转串行单元以及N个存储控制单元；所述写数据通路接口的输入端与所述传输单元的输出端连接，所述写数据通路接口的输出端与所述N个并行转串行单元的输入端分别连接，所述N个并行转串行单元的输出端与所述N个存储控制单元的输入端分别一一对应连接，所述N为大于1的正整数；
    所述传输单元用于获取目标数据包，并将所述目标数据包发送给所述写数据通路接口，所述目标数据包中包括所述目标数据包的地址；
    所述写数据通路接口用于根据所述目标数据包的地址，从所述N个并行转串行单元中，确定所述目标数据包对应的目标并行转串行单元，并将所述目标数据包发送给所述目标并行转串行单元；
    所述目标并行转串行单元用于将所述目标数据包发送给目标存储控制单元，以及将目标数据包拆分成多个子数据包，所述目标存储控制单元为与所述目标并行转串行单元连接的存储控制单元；
    所述目标存储控制单元用于将所述目标数据包存储在对应的存储单元中。
  8. 根据权利要求7所述的数据传输模块，其特征在于，所述写数据通路接口，具体用于根据所述目标数据包的地址和存储控制单元的个数，确定所述目标数据包对应的目标存储控制单元；并将与所述目标存储控制单元连接的并行转串行单元，确定为所述目标数据包对应的目标并行转串行单元。
  9. 根据权利要求8所述的数据传输模块，其特征在于，所述写数据通 路接口，具体用于确定所述目标数据包的地址与所述存储控制单元的个数之间的余数；并将所述N个存储控制单元中标识为所述余数的存储控制单元，确定为所述目标数据包对应的目标存储控制单元。
  10. 根据权利要求8所述的数据传输模块，其特征在于，所述写数据通路接口，具体用于将所述目标数据包的地址与所述存储控制单元的个数之间的商，确定为所述目标数据包在所述存储单元中的存储地址；并根据所述存储地址，通过所述目标存储控制单元将所述目标数据包存储在所述存储单元中。
  11. 根据权利要求7-10任一项所述的数据传输模块，其特征在于，所述目标数据包为有向无环图数据包。
  12. 根据权利要求7所述的数据传输模块，其特征在于，所述目标并行转串行单元，具体用于将所述目标数据包拆分成M个子数据包，并将所述M个子数据包依次发送给所述目标存储控制单元，所述M为正整数。
  13. 一种数据传输的装置，其特征在于，包括：
    获取单元，用于获取待存储的目标数据包，所述目标数据包中包括所述目标数据的地址；
    确定单元，用于根据所述目标数据包的地址，从预设的N个并行转串行单元中，确定所述目标数据包对应的目标并行转串行单元，所述N个并行转串行单元分别与N个存储控制单元一一连接，所述N为大于1的正整数；
    发送单元，用于通过所述目标并行转串行单元将所述目标数据包发送给目标存储控制单元，并通过所述目标存储控制单元将所述目标数据包存储在对应的存储单元中，所述目标存储控制单元为与所述目标并行转串行单元连接的存储控制单元。
  14. 一种芯片，其特征在于，包括：
    处理器和存储器，所述存储器用于存储计算机程序，所述处理器用于调用并运行所述存储器中存储的计算机程序，以执行权利要求1至6中任一项所述的方法。
  15. 一种电子设备，其特征在于，包括：
    处理器和存储器，所述存储器用于存储计算机程序，所述处理器用于调用并运行所述存储器中存储的计算机程序，以执行权利要求1至6中任一项 所述的方法。
  16. 一种计算机可读存储介质，其特征在于，用于存储计算机程序，所述计算机程序使得计算机执行如权利要求1至6中任一项所述的方法。
  17. 一种计算机程序，其特征在于，当其在计算机上运行时，使得计算机执行如权利要求1至6中任一项所述的方法。
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