WO2018041074A1 - 一种内存设备的访问方法、装置和系统 - Google Patents

一种内存设备的访问方法、装置和系统 Download PDF

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Publication number
WO2018041074A1
WO2018041074A1 PCT/CN2017/099331 CN2017099331W WO2018041074A1 WO 2018041074 A1 WO2018041074 A1 WO 2018041074A1 CN 2017099331 W CN2017099331 W CN 2017099331W WO 2018041074 A1 WO2018041074 A1 WO 2018041074A1
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Prior art keywords
buffer
data
memory
controller
request
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PCT/CN2017/099331
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English (en)
French (fr)
Inventor
卢天越
阮元
陈明宇
陈少杰
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华为技术有限公司
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Priority to EP17845376.7A priority Critical patent/EP3470971B1/en
Publication of WO2018041074A1 publication Critical patent/WO2018041074A1/zh
Priority to US16/289,134 priority patent/US20190196989A1/en

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    • G06—COMPUTING; CALCULATING OR COUNTING
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    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
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    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1642—Handling requests for interconnection or transfer for access to memory bus based on arbitration with request queuing
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    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F16/00—Information retrieval; Database structures therefor; File system structures therefor
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    • G06F16/24—Querying
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    • G11C7/1063—Control signal output circuits, e.g. status or busy flags, feedback command signals

Definitions

  • the embodiments of the present invention relate to the field of computers, and in particular, to a method, device, and system for accessing a memory device.
  • the memory system is one of the most important components of a computer system, while the traditional memory system uses the Double Data Rate (DDR) protocol for data interaction.
  • DDR Double Data Rate
  • the synchronous DDR protocol uses a fixed read and write latency, and the latency, granularity, and order of the memory access are fixed. Therefore, in the synchronous DDR protocol, only the data content, the request address, and the like need to be transmitted to complete the memory access operation.
  • Asynchronous memory access is the memory protocol used to solve this problem.
  • each memory access uses a different memory access delay, so not only the data content and the request address are transmitted, but also additional delay identifiers, access granularity, request identifiers, and the like. The transmission of this information requires a large amount of bus bandwidth, which will increase the load on the memory system.
  • the present invention discloses a method, apparatus and system for accessing a memory device to implement asynchronous access to a memory device.
  • the present application provides an access system for a memory device, the system includes a memory controller and a memory device, the memory device includes a media controller, a memory, and a buffer, and the media controller is configured to receive multiple accesses of the memory controller.
  • the request, and the data requested by each access request are read from the memory and written to the buffer.
  • the memory controller sends at least one access request to the media controller, it is used to send a query request to the media controller, and the query request is used to query whether there is data writing in the buffer, and the media controller is configured to determine the buffer according to the query request. Whether there is data writing in the medium, in the case of determining that there is already data writing in the buffer, the media controller is also used to send the data written in the buffer to the memory controller.
  • the memory controller actively sends a query request to the media controller, and accesses the memory device without adding an additional signal line. After receiving the query request, if the media controller determines that there is data writing in the buffer, the media controller can treat the query request as a read instruction to the buffer and return the data written in the buffer to the memory. Controller.
  • the media controller is further configured to send a response message to the memory controller, where the response message is used to indicate the buffer.
  • the data write status is the existing data write
  • the memory controller is further configured to trigger the read buffer request according to the reply message, and send the read buffer request to the media controller, and the read buffer request is used in the read buffer Data that has been written
  • the media controller is further configured to receive the read buffer request, and read the data written in the buffer according to the read buffer request, and trigger the sending the cache to the memory controller The operation of the data written in the device.
  • the query request is used to query whether there is data write in the buffer, and the memory controller uses the read buffer to request read operation of the buffer, thereby further reducing the complexity of the storage protocol.
  • the response message can carry the data in the buffer, and the memory controller can trigger the read buffer request according to the amount of data in the buffer. For example, if a read buffer can only read a fixed size of data, if the response message indicates that there are currently M data in the buffer, the memory controller can trigger M read buffer requests, wherein one data refers to The data that can be requested by one access request.
  • the memory controller is specifically configured to send a query request to the media controller according to a preset query period.
  • the preset query period may be dynamically adjusted according to the busyness of the interconnected channel between the memory controller and the memory device. For example, when the bus or channel is busy, the preset query period may be increased. Therefore, the sending frequency of the query request is reduced, and the occupation of the bus or the channel is reduced; when the bus or the channel is relatively idle, the preset query period can be reduced, thereby increasing the sending frequency of the query request, and the memory controller can be implemented as soon as possible. Read the access data.
  • the multiple access requests sent by the memory controller are divided into at least two priorities, and the memory device includes At least two buffers, each buffer corresponding to one priority, the query period of the access request is determined according to the priority of the access request, and the access requests of different priorities correspond to different query periods.
  • the access request of the computer system can be divided into multiple priorities, and the access requests of different priorities can be managed by setting multiple buffers in the memory device, and each buffer corresponds to one priority access request.
  • the query period of the corresponding query request is determined according to the priority of the access request, and the contradiction between the return time of the data and the occupation of the interconnected channel can be reasonably compromised. For a high priority access request, the query period for sending a query request can be smaller, thereby ensuring that important data is preferentially returned to the memory controller.
  • the query request sent by the memory controller to the media controller further carries the indication information of the buffer
  • the indication information of the buffer is used to indicate the buffer that the query request is queried.
  • the memory controller When querying the data write status of a specific buffer, the memory controller needs to carry the indication information of the queried buffer in the query request.
  • the indication message may be specifically address information of the buffer, or address information of a status register of a data write status of the buffer.
  • the memory controller in order to ensure normal data communication, before the memory controller sends the query request to the media controller, Used to determine that the interconnect channel between the memory controller and the media controller is idle.
  • the query request is sent when the interconnect channel is idle, which can avoid the influence of the query request on other normal read and write operations.
  • the memory device further includes a status register, where the status register is used to record a data write status of the buffer;
  • the media controller is specifically configured to: read a data write status of the buffer recorded by the status register, and determine whether there is any buffer in the buffer according to the data write status of the buffer. Data is written.
  • the media controller After the media controller writes the data to be accessed to the buffer, it updates the status register and clears the status register after reading the value in the status register.
  • the data controller may still have an out-of-order sequence in the asynchronous memory access mode, and the media controller further And when the data written in the buffer is sent to the memory controller, the identifier information is sent to the memory controller, where the identifier information is used to indicate an access request corresponding to the sent data.
  • the identifier information may be a request ID, and the request ID may be carried in an access request sent by the memory controller, or a synchronous request counter may be maintained on both sides of the memory controller and the media controller, and the value of the request counter is used. Indicates the request ID.
  • the present application provides an access method of a memory device, where the memory device includes a media controller, a memory, and a buffer, where the media controller is configured to receive multiple access requests of the memory controller, and request each access request The data is read from the memory and written to the buffer.
  • the method includes: the memory controller sends at least one access request to the media controller; the memory controller sends a query request to the media controller, and the query request is used to query whether the buffer is in the buffer There is data write; the memory controller receives the data that has been written in the buffer sent by the media controller.
  • the memory controller actively sends a query request to the media controller, and accesses the memory device without adding an additional signal line.
  • the query request can be regarded as a read instruction to the buffer. If data is written in the buffer, the memory controller can directly receive the data written in the buffer sent by the media controller.
  • the method further includes: the memory controller receiving the response message from the media controller, and the response message is used by The data write status of the indication buffer is written to the existing data; the memory controller sends a read buffer request to the media controller according to the response message, and the read buffer request is used to read the data written in the buffer.
  • the query request is used to query whether there is data write in the buffer, and the memory controller uses the read buffer to request read operation of the buffer, thereby further reducing the complexity of the storage protocol.
  • the response message can carry the data in the buffer, and the memory controller can trigger the read buffer request according to the amount of data in the buffer.
  • the memory controller sends the query request to the media controller, including: the memory controller according to the preset query The cycle sends a query request to the media controller.
  • the preset query period may be dynamically adjusted according to the busyness of the interconnected channel between the memory controller and the memory device. For example, when the bus or channel is busy, the preset query period may be increased. Therefore, the sending frequency of the query request is reduced, and the occupation of the bus or the channel is reduced; when the bus or the channel is relatively idle, the preset query period can be reduced, thereby increasing the sending frequency of the query request, and the memory controller can be implemented as soon as possible. Read the access data.
  • the multiple access requests sent by the memory controller are divided into at least two priorities, and the memory device includes At least two buffers, each buffer corresponding to one priority, the query period of the access request is determined according to the priority of the access request, and the access requests of different priorities correspond to different query periods.
  • the access request of the computer system can be divided into multiple priorities, and the access requests of different priorities can be managed by setting multiple buffers in the memory device, and each buffer corresponds to one priority access request.
  • the query period of the corresponding query request is determined according to the priority of the access request, and the contradiction between the return time of the data and the occupation of the interconnected channel can be reasonably compromised.
  • the query request sent by the memory controller to the media controller further carries the indication information of the buffer
  • the indication information of the buffer is used to indicate the buffer that the query request is queried.
  • the memory controller When querying the data write status of a specific buffer, the memory controller needs to carry the indication information of the queried buffer in the query request.
  • the indication message may be specifically address information of the buffer, or address information of a status register of a data write status of the buffer.
  • the method before the memory controller sends the query request to the media controller, to ensure normal data communication, the method also includes the memory controller determining that the interconnect channel between the memory controller and the media controller is idle.
  • the query request is sent when the interconnect channel is idle, which can avoid the influence of the query request on other normal read and write operations.
  • the second aspect the second possible implementation manner, An access request corresponding to the received data.
  • the identifier information may be a request ID, and the request ID may be carried in an access request sent by the memory controller, or a synchronous request counter may be maintained on both sides of the memory controller and the media controller, and the value of the request counter is used. Indicates the request ID.
  • the present application provides a readable medium, including executing instructions, when the processor of the memory controller executes an execution instruction, the memory controller performs any of the possible implementations of the second aspect or the second aspect The method in the way.
  • the present application provides a memory controller, including: a processor, a memory, and a bus; a memory for storing execution instructions, a processor and a memory connected by a bus, and a processor performing memory storage when the memory controller is running Executing instructions to cause the memory controller to perform the method of any of the possible implementations of the second aspect or the second aspect.
  • the present application provides an access method of a memory device, where the memory device includes a media controller, a memory, and a buffer, where the media controller is configured to receive multiple access requests of the memory controller, and request each access request The data is read from the memory and written to the buffer, the method comprising: the media controller receiving at least one access request from the memory controller; the media controller receiving the query request from the memory controller, the query request is used to query the buffer Whether there is data writing in the medium; the media controller determines whether there is data writing in the buffer according to the query request; in the case that it is determined that the data is written in the buffer, the media controller sends the buffer to the memory controller. The data written.
  • the media controller implements an access operation to the memory device by receiving a query request sent by the memory controller without adding an additional signal line. After receiving the query request, if the media controller determines that there is data writing in the buffer, the media controller can treat the query request as a read instruction to the buffer and return the data written in the buffer to the memory. Controller.
  • the query sent by the memory controller to the media controller further carries the indication information of the buffer, where the indication information of the buffer is used to indicate the buffer that is queried by the query request, and the memory controller is querying the data of the specific buffer.
  • the indication information of the queried buffer needs to be carried in the query request.
  • the indication message may be specifically address information of the buffer, or address information of a status register of a data write status of the buffer.
  • the method further includes: the media controller sends a response message to the memory controller, and the response message Used to indicate that the data write status of the buffer is an existing data write; the media controller receives a read buffer request from the memory controller, and the read buffer request is used to read the data written in the buffer.
  • the query request is used to query whether there is data write in the buffer, and the read buffer request is used to implement a read operation on the buffer, thereby further reducing the complexity of the storage protocol.
  • the response message can carry the data in the buffer, and the memory controller can trigger the read buffer request according to the amount of data in the buffer. For example, if a read buffer request can only read a fixed size of data, if the response message indicates that there are currently M data in the buffer, the memory controller can trigger M read buffer requests, one of which is data Refers to the data that can be requested by a single access request.
  • the memory device further includes a status register, where the status register is used to record the data write status of the buffer
  • the media controller determines whether the buffer has data to be written, including: the media controller reads the data write status of the buffer recorded by the status register, and determines whether data is written in the buffer according to the data write status of the buffer. .
  • the media controller After the media controller writes the data to be accessed to the buffer, it updates the status register and clears the status register after reading the value in the status register.
  • the method further includes: the media controller sends the identifier information to the memory controller, where the identifier information is used An access request corresponding to the transmitted data is indicated.
  • the identifier information may be a request ID, and the request ID may be carried in an access request sent by the memory controller, or a synchronous request counter may be maintained on both sides of the memory controller and the media controller, and the value of the request counter is used. Indicates the request ID.
  • the present application provides a readable medium, including executing instructions, when the processor of the media controller executes an execution instruction, the media controller performs any of the possible implementations of the fifth aspect or the fifth aspect. The method in the way.
  • the present application provides a media controller, including: a processor, a memory, and a bus; a memory for storing execution instructions, a processor and a memory connected by a bus, and a processor performing memory storage when the media controller is running Executing instructions to cause the media controller to perform the method of any of the possible implementations of the fifth aspect or the fifth aspect.
  • the application provides an access device for a memory device, where the memory device includes a media controller, a memory, and a buffer, where the media controller is configured to receive multiple access requests of the device, and request each access request
  • the data is read from the memory and written to the buffer
  • the device comprises: a sending unit, configured to send at least one access request to the media controller; the sending unit is further configured to send a query request to the media controller, and the query request is used for querying the cache Whether there is data writing in the device; the receiving unit is configured to receive the data written in the buffer sent by the media controller.
  • the receiving unit is further configured to receive a response message from the media controller, where the response message is used to indicate the buffer The data writing state; the sending unit is further configured to send a read buffer request to the media controller according to the response message, and the read buffer request is used to read the data written in the buffer.
  • the sending unit when the query request is sent to the media controller, the sending unit is specifically configured to perform the preset query.
  • the cycle sends a query request to the media controller.
  • the multiple access requests of the device are divided into at least two priorities, and the memory device includes at least two Each buffer corresponds to a priority level, and the query period of the access request is determined according to the priority of the access request, and the access requests of different priorities correspond to different query periods.
  • the query request sent by the sending unit to the media controller further carries the indication information of the buffer, and the cache The indication information of the device is used to indicate the buffer that the query request is queried.
  • the device further includes a determining unit, where the sending unit is configured to send the query request to the media controller Determine that the interconnect channel between the memory controller and the media controller is idle.
  • the receiving unit is further configured to receive the identifier information sent by the media controller, where the identifier information is used to indicate The access request corresponding to the data received by the receiving unit.
  • the eighth aspect is the device implementation manner of the memory controller corresponding to the method of the second aspect, so the description in any of the possible implementation manners of the second aspect or the second aspect is applicable to any of the eighth aspect or the eighth aspect. The implementation of this will not be repeated here.
  • the present application provides an access device for a memory device, wherein the memory device includes a device, a memory, and a buffer, where the device is configured to receive multiple access requests of the memory controller, and each access request The requested data is read from the memory and written to the buffer, the device comprising: a receiving unit, configured to receive at least one access request from the memory controller; the receiving unit is further configured to receive a query request from the memory controller, query The request is used to query whether there is data writing in the buffer; the determining unit is configured to determine whether there is data writing in the buffer according to the query request; and the sending unit, in the case that the determining unit determines that the data is already written in the buffer The sending unit is configured to send the data written in the buffer to the memory controller.
  • the query request further carries the indication information of the buffer, where the indication information of the buffer is used to indicate the buffer that is queried by the query request, and the memory controller needs to query the query when querying the data write status of the specific buffer.
  • the indication information of the queried buffer is carried in the middle.
  • the indication message may be specifically address information of the buffer, or address information of a status register of a data write status of the buffer.
  • the sending unit is further configured to use the memory
  • the controller sends a response message, the response message is used to indicate that the data write status of the buffer is an existing data write;
  • the receiving unit is further configured to receive a read buffer request from the memory controller, and the read buffer request is used to read the cache. The data that has been written in the device.
  • the memory device further includes a status register, where the status register is used to record the data write status of the buffer;
  • the determining unit is specifically configured to read the data writing state of the buffer recorded by the status register, and determine whether there is data writing in the buffer according to the data writing state of the buffer.
  • the sending unit is further configured to send the identifier information to the memory controller, where the identifier information is used to indicate an access request corresponding to the data sent by the sending unit.
  • the ninth aspect is the device implementation manner of the media controller corresponding to the method of the fifth aspect, so the description in any one of the possible implementation manners of the fifth aspect or the fifth aspect is applicable to any of the ninth aspect or the ninth aspect. The implementation of this will not be repeated here.
  • the present application provides a memory device, where the memory device includes a memory, a buffer, and the device in any one of the possible implementations of the ninth or the ninth aspect.
  • the memory controller actively sends a query request to the media controller, and implements the memory device without adding an additional signal line. Access operation.
  • the embodiment of the present invention implements access to the hybrid memory system by using less signaling, and because the query request can be implemented by using the read instruction in the storage protocol, the embodiment of the present invention has various storage protocols. Better compatibility.
  • FIG. 1 is a schematic diagram of a logical structure of a computer system
  • FIGS. 2(a) and 2(b) are schematic diagrams showing the logical structure of a memory device according to an embodiment of the invention.
  • FIG. 3 is a schematic diagram of a logical structure of a computer system
  • FIG. 4 is a schematic flow chart of a method for accessing a memory device according to an embodiment of the invention.
  • FIG. 5 is a timing diagram of a memory device access method according to an embodiment of the invention.
  • FIG. 6 is a timing diagram of a method for accessing a memory device according to an embodiment of the invention.
  • FIG. 7 is a timing diagram of a memory device access method according to an embodiment of the invention.
  • FIG. 8 is a timing diagram of a method for accessing a memory device according to an embodiment of the invention.
  • FIG. 9 is a timing diagram of a memory device access method according to an embodiment of the invention.
  • FIG. 10 is a timing diagram of a memory device access method according to an embodiment of the invention.
  • FIG. 11 is a schematic flowchart of a method for accessing a memory device according to an embodiment of the invention.
  • FIG. 12 is a timing diagram of a memory device access method according to an embodiment of the invention.
  • FIG. 13 is a schematic structural diagram of hardware of a memory access device according to an embodiment of the invention.
  • FIG. 14 is a schematic diagram showing the logical structure of a memory controller according to an embodiment of the invention.
  • FIG. 15 is a schematic diagram showing the logical structure of a memory controller according to an embodiment of the invention.
  • FIG. 16 is a schematic diagram showing the logical structure of a medium controller according to an embodiment of the invention.
  • DDR Double Data Rate
  • NVDIMMs non-volatile dual in-line memory modules
  • DRAM Integrated dynamic random access memory
  • non-volatile memory chips the traditional DDR protocol can not meet the requirements of the system.
  • the memory controller accesses the memory device not only to transmit the address information of the data, but also to transmit additional delay identifiers and other additional information. For example, the length information of the request packet, the request identification number, etc.; or an additional signal line needs to be added between the memory controller and the memory device, and the memory device actively pushes the access request to the memory controller through the additional signal line. status.
  • the memory controller queries the status of the access request by sending a query instruction to the memory device, and can access the different delayed memory medium without modifying the traditional storage protocol (eg, DDR).
  • DDR traditional storage protocol
  • the system 100 includes one or more processors 102, a memory controller 104, and a memory device 108.
  • the processor 102, the memory controller 104, and the memory device 108 may be on the same motherboard, but the invention is not limited thereto.
  • memory device 108 can be remote memory and memory controller 104 is interconnected with memory device 108 via a network protocol.
  • the processor 102 can be a general-purpose central processing unit (CPU), a microprocessor, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA). Or one or more integrated circuits, the embodiment of the present invention does not limit the specific implementation form of the processor 102.
  • CPU central processing unit
  • ASIC application specific integrated circuit
  • FPGA field programmable gate array
  • the memory controller 104 is responsive to access requests from the processor 102 and communicates with the memory device 108 via the interconnect channel 106, which may be a bus or other connection.
  • the embodiment of the present invention does not limit the connection manner between the memory controller 104 and the memory device 108.
  • the two may also be connected by wireless, or the memory device 108 is a remote memory, and between the memory controller 104 and the memory device 108. It is also possible to connect through various network protocols.
  • the memory device 108 can support multiple storage protocols, such as the double data rate fourth generation (DDR4) protocol and the additional protocol.
  • DDR4 double data rate fourth generation
  • the embodiment of the present invention does not limit the storage protocol supported by the memory device 108. .
  • Memory device 108 includes media controller 110 and memory 112.
  • the media controller 110 is configured to interact with the memory controller 104 and manage access operations to the memory device 108.
  • the memory 112 includes a memory chip 114 and a memory chip 116 for storing data required by the processor 102 of the system 100.
  • the memory chip 114 and the memory chip 116 may be the same storage medium or different storage medium, for example, in a hybrid memory system.
  • the memory device includes different storage media.
  • the memory chip 114 and the memory 116 can be various types of non-volatile memory (NVM) or dynamic random access memory (DRAM).
  • NVM non-volatile memory
  • DRAM dynamic random access memory
  • the memory chip 114 and the memory chip 116 may be flash memory, ferroelectric random-access memory (FeTRAM), nanowire-based random storage, or various types of DRAM.
  • FIG. 1 illustrates that memory 112 includes memory chip 114 and memory chip 116
  • embodiments of the present invention do not limit the number of memory chips in memory 112, which may include more or less
  • the memory chip of the present invention does not limit the storage medium used by the memory chip.
  • FIG. 2(a) is a schematic diagram of the architecture of a memory device 108 according to an embodiment of the invention, and FIG. 2(a) shows other details of the memory device 108.
  • the memory device 108 also includes a buffer 118 and a memory interface 120.
  • Media controller 110, memory 112, buffer 118 and memory interface 120 can be connected by an interconnect bus.
  • the buffer 118 is used to cache the data stored in the memory 112. Specifically, after receiving the access request, the media controller 110 first reads the data to be accessed from the memory 112, and then writes the data to be accessed into the buffer 118, and then After receiving a new instruction sent by the memory controller, such as a query request or a read buffer request in the following description, the data to be accessed in the buffer 118 is returned to the memory controller 104.
  • the buffer 118 may be a first input first output (FIFO).
  • the media controller 110 After receiving the instruction sent by the memory controller 104, the media controller 110 stores the FIFO in the order in which the FIFO is written. The data is returned to the memory controller side.
  • FIFO first input first output
  • the memory device 108 can specifically include a read buffer for buffering data written to the memory 112 and a read buffer for buffering data read from the memory 112, which is not limited.
  • the buffer 118 in the embodiment of the present invention is a read buffer unless otherwise stated.
  • buffers 118 there may be multiple buffers 118 in the memory device 108.
  • Different buffers 118 may correspond to different access requests or corresponding access requests of different priorities.
  • an access request of a computer system can be divided into multiple priorities, and an access request for important data has a higher priority than an access request for general data.
  • the management of access requests of different priorities may be implemented by setting a plurality of buffers 118 in the memory device, each access request corresponding to a different buffer according to different priorities.
  • the description is made by one of the buffers 118, but it should be understood that the embodiment of the present invention does not limit the number of the buffers 118.
  • the memory interface 120 is used to interface with the interconnect channel 106 to enable interaction between the memory controller 104 and the media controller 110.
  • the memory device 108 further includes a status register 122 for recording the data write status of the buffer 118. More specifically, if there are multiple buffers 118, for example, different priority access requests correspond to different buffers 118, each buffer 118 may have a status register 122 to record its data write status, for convenience of description.
  • the embodiment of the present invention is represented by a set of buffers 118 and status registers 122, but it should be understood that the embodiment of the present invention does not limit the number of buffers 118 and status registers 122.
  • the status register 122 can store one bit of a binary bit, and can record two states of “0” or “1”. For example, the “0” state can be used to indicate that no data is written in the buffer 118, and “1” is used. The state indicates that the buffer 118 has data to be written, and the media controller 110 determines whether there is data writing in the buffer 118 by the status bit in the status register 122.
  • the status register 122 can store multiple bit binary bits and can record multiple states. For example, if the storage register 122 can record 3 bit binary bits, then 8 states can be recorded. If a fixed size of data to be accessed can be requested for each access request, each time a piece of data to be accessed is written to the buffer 118, the media controller 110 pairs the status register 122 by adding the value of the status register 122 to the status register 122. Update. For example, if the original value of the status register 122 is "0", the "0" status indicates that there is no data write in the buffer 118.
  • the value of the status register 122 can be set to "1", indicating that a piece of data to be accessed is written to the buffer 118, if the value in the status register 122 is If it is not "0", for example, it is "2”, it indicates that there are already 2 data to be accessed written in the buffer 118, and the media controller 110 adds 1 to the value in the status register 122 to become "3", indicating that the buffer is cached.
  • the device 118 has new data to be accessed, and there are 3 data to be accessed in the current buffer 118.
  • each access request can read a 64 Bytes of data to be accessed.
  • the media controller 110 writes a 64 Bytes-sized data to be accessed to the buffer 118 according to the access request, the value in the status register 122 is incremented by one to indicate that there is a A new piece of data is written to the buffer.
  • one piece of data or one piece of data to be accessed is data requested to be read by one access request.
  • FIG. 2(a) and FIG. 2(b) are merely schematic architectural diagrams of the memory device 108.
  • the memory device 108 may include more or fewer components. Not limited.
  • the memory controller 104 further includes a first request counter 124, and the memory device includes a second request counter 126.
  • the first request counter 124 is used to mark an access request sent by the memory controller 104 to the memory device 108. For example, each time the memory controller 104 sends an access request, the first request counter 124 is incremented by 1, and the first request counter is used. The value of 106 marks the transmitted access request as the request ID.
  • the second request counter 126 is synchronized with the first request counter 106 for marking the access request received by the memory device 108. For example, each time the media controller 108 receives an access request, the second request counter 126 is incremented by one. The value of the second request counter 126 marks the received access request as the request ID.
  • the media controller 110 maintains the correspondence between the access request and the access data.
  • the request ID of the access request corresponding to the access data is carried, thereby identifying the order of the access data.
  • the memory controller 104 adjusts the order in which the data is accessed based on the request ID.
  • the request counter can be zeroed back, that is, the value in the request counter is reset to zero.
  • the embodiment of the present invention does not limit the counting manner of the first request counter 124 and the second request counter 126.
  • the first request counter 124 and the second request counter 126 may also mark the access request in a manner of minus one.
  • the memory controller 104 and the media controller 110 described in the embodiments of the present invention may be implemented by hardware logic coding, such as an ASIC or an FPGA.
  • the memory controller 104 and the media controller 110 described in the embodiments of the present invention may also be implemented by a readable storage medium storing instructions executed by a computer.
  • the readable storage medium may be a read only memory (ROM), a static storage device, a dynamic storage device or a random access memory (RAM), or the like, or other type suitable for storing computer executable instructions.
  • ROM read only memory
  • RAM random access memory
  • Read the media may be downloadable computer instructions that may be transferred from a remote computer (eg, a server) to a requesting computer (eg, a client) over a network transmission.
  • FIG. 4 is a schematic flowchart of a method for accessing a memory device according to an embodiment of the present invention. As shown in FIG. 4, the method includes:
  • S402 The memory controller triggers an access request and sends the access request to the media controller.
  • the memory controller sends at least one access request to the media controller, wherein each access request carries address information of the requested data to be accessed in a memory of the memory device.
  • the access request can be triggered by the memory controller after the memory controller receives the access instruction sent by the processor.
  • the address information of the data to be accessed may be physical address information of the data to be accessed in the memory
  • the access instruction sent by the processor carries the virtual address information of the data to be accessed
  • the memory controller is further configured to use the virtual address and the physical
  • the mapping relationship of the addresses converts the virtual address information of the data to be accessed into physical address information.
  • mapping between the virtual address and the physical address may be maintained by the media controller, and the address information carried in the access request may also be the virtual address information of the data to be accessed.
  • the size of the data to be accessed that can be read by each access request may be a fixed value, that is, each access request may read a fixed amount of data to be accessed, for example, an access request may read 64 Bytes.
  • the data If the size of the data to be accessed that can be requested by each access request is a fixed value, the address information of the data to be accessed in the access request may be the first address of the memory device to be accessed.
  • the embodiment of the present invention does not define the form of the address information of the access request and the data to be accessed.
  • S404 The media controller receives the access request, reads the to-be-accessed data from the memory according to the access request, and writes the to-be-accessed data into the buffer.
  • the media controller After receiving each access request, the media controller reads the data to be accessed from the memory according to the address information carried therein, and writes the data to the buffer. When the data to be accessed is written into the buffer, the data is in the ready state, indicating that it can be read by the memory controller. When the media controller receives the instruction of the read buffer from the memory controller, the buffer can be written in the buffer. The incoming data is returned to the memory controller.
  • the time required by the media controller to read and write the data to be accessed from the memory to the buffer is opaque to the memory controller, that is, the memory controller cannot determine that the media controller completes this.
  • the memory controller needs to actively send a new instruction to query whether there is data writing in the buffer.
  • S406 The memory controller sends a query request to the media controller, and the query request is used to query whether there is data writing in the buffer.
  • the embodiment of the present invention is applicable to a scenario in which an access delay of a memory medium is uncertain when performing memory access.
  • an access delay of a memory medium is uncertain when performing memory access.
  • a fixed delay is used in a hybrid memory system.
  • the DDR protocol obviously cannot meet the requirements of the system. Since the memory controller is uncertain of the access delay of the data to be accessed, it is impossible to determine the time point at which the data to be accessed is written to the buffer, so it is necessary to query the buffer to see if any data is written in the buffer.
  • the media controller may send a query request to the media controller according to a preset query period.
  • the preset query period can also be dynamically adjusted according to the busyness of the interconnected channel between the memory controller and the memory device. For example, when the bus or channel is busy, the preset query period can be increased, thereby reducing Query the sending frequency of the request, reduce the occupation of the bus or channel; when the bus or channel is relatively idle, the preset query period can be reduced, thereby increasing the sending frequency of the query request, and the memory controller can access the data as soon as possible. Read.
  • the preset query period may also be determined according to the priority of the access request.
  • the multiple access requests sent by the memory controller are divided into at least two priorities, and the memory device includes at least two buffers, and each buffer corresponds to one type.
  • Priority the query period of the access request is determined according to the priority of the access request, and the access requests of different priorities do not correspond. The same query cycle.
  • the access request of the computer system can be divided into multiple priorities, and the access requests of different priorities can be managed by setting multiple buffers in the memory device, and each buffer corresponds to one priority access request. For higher priority buffers, more frequent query requests can be used to guarantee operational delays for high priority access requests.
  • the memory controller may further send a query instruction to the media controller after determining that the interconnect channel between the memory controller and the memory device is in an idle state.
  • step S404 and step S406 are in no particular order.
  • the media controller may have read the data requested by the access request from the memory.
  • the buffer is written out and written, or the data requested by the access request has not been written to the buffer.
  • step S408 The media controller receives the query request and determines whether there is data writing in the buffer. If it is determined that the buffer has not yet written data, step S410 is performed. If it is determined that the buffer has data written, step S412 is performed.
  • the media controller can record the data write status of the buffer by maintaining the remaining space in the buffer. If the size of the remaining space is the same as the buffer storage space, it indicates that the current buffer has no data write; if the remaining space is less than The storage space of the buffer indicates that the current buffer has data to be written. The size of the data written in the buffer is the difference between the storage space of the buffer and the remaining space. More specifically, the media controller can maintain the remaining space of the buffer by maintaining the form of a writable address bit of the buffer.
  • the media controller can also record the data write status of the buffer through the status register. After the media controller writes the data to be accessed to the buffer, it updates the status register, which is used to record the data write status of the buffer. After receiving the query request, the media controller reads the data write status of the buffer recorded in the status register, and determines whether data is written in the buffer according to the data write status of the buffer.
  • the query request may be a read command of the read status register, which carries the address of the status register, so that the query request can be implemented by the read instruction supported by each storage protocol, so that the query request can be compatible with various storage protocols.
  • the media controller After the media controller reads the data in the status register, it clears the status register.
  • the query request sent by the memory controller to the media controller further carries the indication information of the buffer, and the indication information of the buffer is used to indicate the buffer that is queried by the query request.
  • the memory controller needs to carry the indication information of the queried buffer in the query request.
  • the indication message may be specifically address information of the buffer, or address information of a status register of a data write status of the buffer.
  • the media controller does not respond to the query request of the memory controller or sends an indication message to the internal control controller, where the indication message is used to indicate that no data is written in the buffer.
  • the media controller may not respond to the query request, or send an indication message to the memory controller, indicating the message. There is no data in the indication buffer.
  • the memory controller may repeatedly send the message to the media controller.
  • the detailed policy refers to S406, and details are not described herein again.
  • S412 The media controller sends the data written in the buffer to the memory controller.
  • the media controller sends the data written in the buffer. Give it to the memory controller.
  • the access delay of the storage medium is uncertain
  • the synchronous storage protocol using the fixed delay DDR protocol obviously cannot meet the requirements of the system, and the memory controller sends the access request to the media controller because of the access delay.
  • the media controller can not actively return data to the memory controller without receiving an explicit instruction.
  • the memory controller needs to send a query instruction to the media controller to read the buffer. data.
  • the query instruction has two functions, one function is to query the data write status of the buffer, and the other function is to implement the data write in the buffer.
  • FIG. 5 is a schematic timing diagram of a memory device access flow according to an embodiment of the present invention.
  • the enable signal is active at a low level, and when the enable signal is at a low level, the clock rises.
  • the media controller receives an access request from the memory controller, wherein the access request carries the data A to be accessed at the address A of the memory device; when the enable signal is at another low level, the media controller receives the rising edge of the clock
  • the query request from the memory controller the media controller queries the buffer according to the query request. If the data A has been written to the write buffer at this time, the media controller returns the data A to the memory controller in response to the query request.
  • the media controller before the media controller sends the to-be-accessed data in the buffer to the memory controller, the media controller sends a response message to the memory controller, where the response message is used to indicate the data of the buffer.
  • the write status is the existing data write.
  • the memory controller triggers a read buffer request based on the reply message and sends a read buffer request to the media controller, and the read buffer request is used to read the data written in the buffer.
  • the media controller is further configured to receive a read buffer request sent by the memory controller, read the data written in the buffer according to the read buffer request, and trigger an operation of sending the data written in the buffer to the memory controller. .
  • the query request is used to query whether there is data write in the buffer, and the read buffer request is used to implement a read operation on the buffer, thereby further reducing the complexity of the storage protocol.
  • the read buffer request is specifically a read command to the buffer, and carries the address information of the buffer. After receiving the read buffer request, the media controller triggers step S412.
  • the response message is used to indicate that the data is written in the buffer. More specifically, the response message may also indicate the number of data to be accessed in the buffer, that is, the response message message also carries the number of copies of the data to be accessed in the buffer.
  • the read buffer request may carry the quantity information of the data in the request read buffer, and the quantity information is generated according to the data M.
  • a read buffer request can only read one piece of data to be accessed in the buffer, that is, it can only read the access data of an access request, such as fixed data of 64 Bytes in size
  • the memory controller can refer to the medium according to the response message.
  • the controller sends M read buffer requests to read all the data in the buffer. After receiving the M read buffer requests, the media controller returns the data to be accessed in the buffer to the memory controller.
  • M is a positive integer greater than zero.
  • FIG. 6 is a schematic timing diagram of a memory device access flow according to an embodiment of the present invention.
  • the media controller queries whether there is data in the buffer, if there is data.
  • Write send a response message to the memory controller, the response message carries the data write status of the buffer, as shown in Figure 6, the media controller responds to the query request and sends the value "1" to the memory controller side, the value " 1" is used to indicate the current buffer There is data writing.
  • the value "1" can be used to indicate that there is a piece of data in the current buffer, and the memory controller sends a read buffer request to the media controller according to the response message, wherein the read buffer requests To read the data in the buffer, the media controller sends the data A to the memory controller according to the read buffer request.
  • query requests can be implemented with new access requests.
  • the media controller fetches the data A indicated by address A from the memory and writes it to the buffer, and then the memory controller sends an access request for reading address B.
  • the access request of the read address B can simultaneously implement the function of the query instruction.
  • the media controller After receiving the access request of the read address B, the media controller reads the data B indicated by the address B from the memory according to the access request of the read address B. Write to the buffer, and query the data write status of the buffer according to the access request of the read address B, and directly return the data A to the memory controller or send a response message to the memory controller.
  • the number of signaling interactions between the memory controller and the media controller is reduced, thereby reducing the load pressure on the communication bus or channel.
  • FIG. 7 and FIG. 8 The schematic timing diagram is shown in FIG. 7 and FIG. 8.
  • the media controller receives the access request of the read address B, if the data A has been written in the buffer, the media controller directly puts the buffer into the buffer. Data A is returned to the memory controller.
  • the media controller receives the access request of the read address B, if the data A has been written in the buffer, the media controller sends a response message to the memory controller, and the memory controller sends a response message to the media controller according to the response message. Sending a read buffer request, the media controller returns data A to the memory controller based on the read buffer request.
  • FIG. 7 and FIG. 8 refers to FIG. 5 and FIG. 6, and details are not described herein again.
  • the media controller records the data write status of the buffer through the status register.
  • the schematic timing diagram is shown in FIG. 9 and FIG. 10.
  • the query request also carries the address information of the status register, and the query request carries the address of the status register.
  • the media controller reads the status according to the address information of the status register. The value in the register, if the value is "0", indicates that the current buffer has no data to write; if the value is not "0", it indicates that the current buffer has data to be written. Further, the media controller can also determine the amount of data written in the buffer according to a specific value in the status register.
  • a read command of the memory controller to the buffer can only read one data to be accessed in the buffer, and the memory system treats the query request as a read command to the buffer. , which saves the number of interactions between the memory controller and the media controller.
  • the media controller can directly send the to-be-accessed data to the memory controller. If M is a positive integer greater than 1, the media controller can cache according to the query instruction.
  • the first data to be accessed written in the device is sent to the memory controller side. For example, if the buffer is a FIFO, the media controller sends a to-be-accessed data of the first queue to the memory controller, and The memory controller sends a response message indicating the amount of data to be accessed remaining in the buffer. After the memory controller receives the response message, it only needs to send M-1 read buffer requests to the media controller, and the media controller receives the M-1 read buffer. After the request, the remaining M-1 pieces of data to be accessed in the buffer are returned to the memory controller.
  • the data to be accessed may be out of order, and the media controller sends the data written in the buffer to the memory controller to the memory controller.
  • the identifier information is used to indicate an access request corresponding to the data sent by the media controller, that is, the identifier information is used to indicate a correspondence between the data to be accessed and the access request.
  • the identifier information may be carried in the data sent by the media controller, and sent to the memory controller at the same time, and the identification information of the data and the data may be sent alternately. It should be understood that the embodiment of the present invention does not identify the data and the data. The method of sending is limited.
  • the embodiment of the present invention uses the request ID to identify the data to be accessed each time it is returned.
  • the request ID of the access request corresponding to the to-be-accessed data is also returned to the memory controller, thereby implementing the out-of-order return of the data.
  • the memory controller may send the request ID corresponding to the access request to the media controller together when sending the access request.
  • the request ID may be recorded in a synchronous manner between the memory controller and the media controller, that is, each party has a request counter, and the request ID of the access request is recorded by the value of the request counter.
  • the memory controller sends an access request
  • the first request counter on the memory controller side is automatically incremented by one
  • each time the media controller receives a request the second request counter on the media controller side is automatically incremented by one, and when the data to be accessed is returned, the request is received.
  • the ID is passed along with the data to be accessed to the memory controller. Since the order of sending and receiving of the access request must be consistent, the two parties implement the synchronization of the request ID, thereby implementing the out-of-order return of the memory access request.
  • the detailed description of the request counter has been described above and will not be described here.
  • the memory controller actively sends a query request to the media controller, and the pair is implemented without adding an additional signal line. Access operation of the memory device.
  • the embodiment of the present invention implements access to the hybrid memory system by using less signaling, and because the query request can be implemented by using the read instruction in the storage protocol, the embodiment of the present invention has various storage protocols. Better compatibility.
  • FIG. 11 is a specific memory device according to an embodiment of the invention.
  • a schematic flow diagram of the method, as shown in FIG. 11, the method includes:
  • S1102 The memory controller triggers the first read instruction and sends the first read instruction to the media controller.
  • the first read command carries the address information of the data to be accessed in the memory device, and the data to be accessed that the first read command can read is a fixed size, for example, 64 Bytes.
  • the size of the access data is 64 Bytes, but it should be understood that the embodiment of the present invention does not limit the size of a piece of data to be accessed.
  • the memory controller adds 1 to the first request counter on the memory controller side, and uses the value in the first request counter after adding 1 as the request ID of the access request to identify the first read. instruction.
  • the media controller receives the first read instruction, and reads 64 bytes of the to-be-accessed data from the memory of the memory device according to the address information carried by the first read instruction, and writes the to-be-accessed data into the buffer.
  • the media controller After receiving the first read command, the media controller adds 1 to the second request counter on the media controller side, thereby maintaining synchronization with the first request counter on the memory controller side, and using the value of the request counter after adding 1 as the Visit please
  • the requested ID is used to identify the first read instruction. More specifically, the media controller maintains the correspondence between the data to be accessed and the first read command, that is, records the request ID corresponding to each data to be accessed, so as to achieve out-of-order return of data.
  • the data write status may be a specific value indicating the number of copies of the data to be accessed in the current buffer. After the media controller writes the data to be accessed to the buffer, the value in the status register is incremented by one.
  • S1108 The memory controller triggers a second read command and sends a second read command to the media controller.
  • the second read command carries an address of the status register for reading the data write status of the buffer recorded in the status register.
  • the media controller receives the second read command and reads the status register according to the address of the status register carried in the second read command.
  • the media controller After the media controller reads the value N in the status register, it clears the status register.
  • the media controller sends the value N in the status register to the memory controller, and the value N in the status register is used to indicate the number N of the data to be accessed in the current buffer.
  • Step S1114 After receiving the value N in the status register sent by the media controller, the memory controller determines whether N is greater than 0. If N is 0, it indicates that there is no data to be accessed in the current buffer, and the memory controller returns Step S1108: Re-send the second read command to the media controller according to a certain policy; if N is greater than 0, the memory controller performs step S1116.
  • S1116 The memory controller triggers a third read command and sends a third read command to the media controller.
  • the third read command carries the address information of the buffer, and is used to read the to-be-accessed data in the buffer.
  • the third read command further carries the quantity indication information of the data to be read, and the quantity indication information is generated according to the data N;
  • the read command can only read one piece of data to be accessed, and the memory controller sends N third read instructions to the memory controller, and each third read command is used to read a 64 Bytes size of the data to be accessed.
  • the media controller receives the third read command, and reads the to-be-accessed data in the buffer according to the address information of the buffer carried by the third read command.
  • the buffer can be a FIFO. If each third read instruction can only read one piece of data to be accessed, each third read instruction reads a piece of data to be accessed at the beginning of the FIFO queue. N pieces of third read instructions can read the first N pieces of data to be accessed from the buffer.
  • S1120 The media controller sends N pieces of to-be-read data read from the buffer to the memory controller.
  • each of the to-be-accessed data carries a request ID corresponding thereto to indicate a request sequence of the data to be accessed.
  • the memory controller receives N pieces of to-be-accessed data sent by the media controller, and sends the N pieces of to-be-accessed data to the processor.
  • the memory controller may also perform the chaos according to the request ID in the data to be accessed before sending the to-be-accessed data to the processor.
  • the data to be accessed returned by the sequence is rearranged to ensure the correctness and integrity of the data.
  • FIG. 11 is a specific implementation of the embodiment of FIG. 3.
  • the specific description of the embodiment of FIG. 3 is applicable to the embodiment of the present invention, and details are not described herein again.
  • FIG. 12 is a timing diagram of a method for accessing a memory device in the embodiment of FIG. 11.
  • the media controller when the enable signal is low, the media controller receives a first read command on a rising edge of the clock, and the first read command carries Address A of the data A to be accessed; when another low level of the enable signal, the media controller receives the second read command sent by the memory controller on the rising edge of the clock, and the second read command carries the address information of the status register.
  • the media controller will read the value in the status register and return the value "1" to the memory controller.
  • the value "1" is used to indicate that the current buffer has a data to be accessed; when the enable signal is at a lower level, The media controller receives a third read command from the memory controller on the rising edge of the clock, the third read command carries the address information of the buffer, the media controller reads the buffer, and returns the data A in the buffer to the memory. Controller.
  • device 1300 includes a processor 1302, a memory 1304, a communication interface 1306, and a bus 1308.
  • the processor 1302, the memory 1304, and the communication interface 1306 implement a communication connection with each other through the bus 1308.
  • the processor 1302 is a control center of the device 1300, and is configured to execute related programs to implement the technical solutions provided by the embodiments of the present invention.
  • the processor 1302 can employ a general-purpose central processing unit, a microprocessor, an application-specific integrated circuit, or one or more integrated circuits for executing related programs to implement the technical solutions provided by the embodiments of the present invention.
  • Memory 1304 can be a read only memory, a static storage device, a dynamic storage device, or a random access memory.
  • the program code for implementing the technical solution provided by the embodiment of the present invention is stored in the memory 1304 and executed by the processor 1302.
  • the memory 1304 can be integrated with or integrated with the processor 1302 or can be one or more memory units independent of the processor 1302.
  • Communication interface 1306 implements communication between device 1300 and other devices or communication networks using transceivers such as, but not limited to, transceivers.
  • Bus 1308 can include a path for communicating information between various components of device 1300, such as processor 1302, memory 1304, and communication interface 1306.
  • the metering device 1300 shown in FIG. 13 only shows the processor 1302, the memory 1304, the communication interface 1306, and the bus 1308, in a specific implementation process, those skilled in the art will appreciate that the device 1300 also includes an implementation. Other devices necessary for normal operation. At the same time, those skilled in the art will appreciate that device 1300 may also include hardware devices that implement other additional functions, depending on the particular needs. Moreover, those skilled in the art will appreciate that device 1300 may also only include the components necessary to implement embodiments of the present invention, and does not necessarily include all of the devices shown in FIG.
  • FIG. 13 and the foregoing description are applicable to various memory controllers or media controllers provided by the embodiments of the present invention, and are suitable for performing the access methods of various memory devices provided by the embodiments of the present invention.
  • FIG. 14 is a schematic diagram showing the logical structure of a memory controller for implementing access to a memory device, the memory device including a media controller, a memory, and a buffer, as shown in FIG.
  • the controller includes a transmitting unit 1402 and a receiving unit 1404, where
  • the sending unit 1402 is configured to send at least one access request to the media controller.
  • the sending unit 1402 is further configured to send a query request to the media controller, where the query request is used to query whether there is data writing in the buffer.
  • the sending unit 1402 can be configured by the processor 1302, the memory 1304 shown in FIG.
  • the communication interface 1306 is implemented, and more specifically, the execution instructions in the memory 1304 can be executed by the processor 1302 to cause the communication interface to perform the functions of the transmitting unit 1402.
  • the sending unit 1402 may send the query request to the media controller according to a preset query period, and the preset query period may be determined according to the priority of the access request, and the access request of the memory controller may be divided.
  • the memory device includes at least two buffers, each buffer corresponding to one priority, and the query period of the access request is determined according to the priority of the access request, and the access requests of different priorities correspond to different query periods. .
  • the query request sent by the sending unit to the media controller further carries the indication information of the buffer, and the indication information of the buffer is used to indicate the buffer that is queried by the query request.
  • the memory controller further includes a determining unit 1406.
  • the determining unit 1406 is configured to determine that the interconnect channel between the memory controller and the media controller is in an idle state.
  • the determining unit may be implemented by the processor 1302 and the memory 1304 shown in FIG. 13, and more specifically, the executing instruction in the memory 1304 may be executed by the processor 1302 to determine the memory controller and the media controller. The interconnection channel between them is idle.
  • the receiving unit 1404 is configured to receive data that has been written in a buffer sent by the media controller.
  • the receiving unit 1404 can be implemented by the processor 1302, the memory 1304 and the communication interface 1306 shown in FIG. 13, and more specifically, the execution instruction in the memory 1304 can be executed by the processor 1302 to enable the communication interface. The function of the receiving unit 1404 is performed.
  • the receiving unit 1404 is further configured to receive a response message from the media controller, where the response message is used to indicate that the data write status of the buffer is an existing data write;
  • the sending unit 1402 is further configured to send a read buffer request to the media controller according to the response message, and the read buffer request is used to read the data written in the buffer.
  • the receiving unit 1404 is further configured to receive the identifier information sent by the media controller, where the identifier information is used to indicate an access request corresponding to the data received by the receiving unit 1404.
  • the embodiment of the present invention is an apparatus embodiment of a memory controller, and the feature description of the embodiment of FIG. 1 to FIG. 12 is applicable to the embodiment of the present invention, and details are not described herein again.
  • FIG. 16 is a schematic diagram showing the logical structure of a media controller for implementing access to a memory device, the memory device including the media controller, the memory, and the buffer, and the media controller for receiving according to the receiving
  • Each access request of the memory controller writes data stored in the memory requested by each access request to the buffer, as shown in FIG. 16, the memory controller includes a receiving unit 1602, a determining unit 1604, and Sending unit 1606, wherein
  • the receiving unit 1602 is configured to receive at least one access request from the memory controller.
  • the receiving unit 1602 can be implemented by the processor 1302, the memory 1304 and the communication interface 1306 shown in FIG. 13, and more specifically, the execution instruction in the memory 1304 can be executed by the processor 1302 to enable the communication interface. The function of the receiving unit 1602 is performed.
  • the receiving unit 1602 is further configured to receive a query request from the memory controller, where the query request is used to query whether there is data writing in the buffer.
  • the determining unit 1604 is configured to determine, according to the query request, whether there is data writing in the buffer.
  • the determining unit may be implemented by the processor 1302 and the memory 1304 shown in FIG. 13, and more specifically, the executing instruction in the memory 1304 may be executed by the processor 1302 to determine the buffer according to the query request. Is there any data to write?
  • the sending unit 1606 is configured to, when the determining unit 1604 determines that data has been written in the buffer, the sending unit 1606 is configured to send the data written in the buffer to the memory controller.
  • the sending unit 1606 can be implemented by the processor 1302, the memory 1304 and the communication interface 1306 shown in FIG. 13, and more specifically, the execution instruction in the memory 1304 can be executed by the processor 1302 to enable the communication interface. The function of the transmitting unit 1606 is performed.
  • the sending unit 1606 is further configured to send a response message to the memory controller, where the response message is used to indicate that the data write status of the buffer is written to the existing data.
  • the receiving unit 1602 is further configured to receive a read buffer request from the memory controller, and the read buffer request is used to read the data written in the buffer.
  • the memory device further includes a status register, where the status register is used to record the data write status of the buffer; the determining unit 1604 is specifically configured to read the data write status of the buffer recorded by the status register, and according to the data of the buffer. Write status to determine if there is data write in the buffer.
  • the sending unit 1606 is further configured to send the identifier information to the memory controller, where the identifier information is used to indicate an access request corresponding to the data sent by the sending unit 1606.
  • the embodiment of the present invention is an apparatus embodiment of the medium controller, and the feature description of the embodiment of the present invention is applicable to the embodiment of the present invention, and details are not described herein again.
  • the disclosed systems, devices, and methods may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the modules is only a logical function division, and may be implemented in another manner, for example, multiple modules or components may be combined or may be Integrate into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or module, and may be electrical, mechanical or otherwise.
  • the modules described as separate components may or may not be physically separated.
  • the components displayed as modules may or may not be physical modules, that is, may be located in one place, or may be distributed to multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional module in each embodiment of the present invention may be integrated into one processing module, or each module may exist physically separately, or two or more modules may be integrated into one module.
  • the above integrated modules can be implemented in the form of hardware or in the form of hardware plus software function modules.
  • the above-described integrated modules implemented in the form of software function modules can be stored in a computer readable storage medium.
  • the software functional modules described above are stored in a storage medium and include instructions for causing a computer device (which may be a personal computer, server, or network device, etc.) to perform some of the steps of the methods described in various embodiments of the present invention.
  • the foregoing storage medium includes: a removable hard disk, a read only memory, a random access memory, a magnetic disk, or an optical disk, and the like, which can store program codes.

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Abstract

本发明实施例提供了一种内存设备的访问方法、装置和系统，实现了对内存设备的异步访问。该系统包含内存控制器和内存设备，内存设备包含介质控制器、存储器和缓存器；介质控制器用于根据接收到的内存控制器的每个访问请求，将每个访问请求所请求的保存在存储器中的数据写入缓存器；内存控制器，用于在向介质控制器发送至少一个访问请求之后，向介质控制器发送查询请求，查询请求用于查询缓存器中是否有数据写入；介质控制器，还用于根据查询请求，确定缓存器中是否有数据写入，若确定缓存器中已有数据写入，向内存控制器发送缓存器中已写入的数据。

Description

一种内存设备的访问方法、装置和系统 技术领域
本发明实施例涉及计算机领域，尤其涉及一种内存设备的方法访问方法、装置和系统。
背景技术
内存系统是计算机系统中最重要的组成部分之一，而传统的内存系统使用同步双倍数据速率(Double Data Rate，DDR)协议进行数据交互。同步DDR协议使用固定的读写延迟，而且访存的延迟、粒度、顺序都是固定的。因此同步DDR协议中只需要传输数据内容、请求地址等数据即可完成访存动作。
随着不同内存介质的出现，同步DDR协议已经不能适应所有的内存介质，特别是混合内存系统。由于混合内存系统中不同的内存介质具有不同的访存延迟，使用固定延迟的DDR协议显然无法满足系统的要求。异步访存就是为了解决这一问题而使用的内存协议。在异步访存中，每次内存访问使用不同的访存延迟，因此不仅要传输数据内容和请求地址，还需要传输额外的延迟标识、访问粒度、请求标识等信息。而传输这些信息需要占用大量的总线带宽，会加大对内存系统的负荷。
发明内容
有鉴于此，本发明公开了一种内存设备的方法访问方法、装置和系统，以实现对内存设备的异步访问。
第一方面，本申请提供了一种内存设备的访问系统，该系统包含内存控制器和内存设备，内存设备包含介质控制器、存储器和缓存器，介质控制器用于接收内存控制器的多个访问请求，以及将每个访问请求所请求的数据从存储器中读出并写入缓存器。内存控制器在向介质控制器发送至少一个访问请求之后，用于向介质控制器发送查询请求，查询请求用于查询缓存器中是否有数据写入，介质控制器用于根据查询请求，确定缓存器中是否有数据写入，在确定缓存器中已有数据写入的情况下，介质控制器还用于向内存控制器发送缓存器中已写入的数据。
在内存设备的存储介质的访问时延不同的场景中，通过内存控制器向介质控制器主动发送查询请求，在不增加额外信号线的情况下，实现对内存设备的访问操作。介质控制器在接收到查询请求后，若确定缓存器中有数据写入，则介质控制器可以将查询请求当做一次对缓存器的读指令，并将缓存器中已写入的数据返回给内存控制器。
结合第一方面，在第一方面第一种可能的实现方式中，介质控制器确定缓存器中已有数据写入之后，还用于向内存控制器发送应答消息，应答消息用于指示缓存器的数据写入状态为已有数据写入；内存控制器还用于根据应答消息触发读缓存器请求，并将读缓存器请求发送给介质控制器，读缓存器请求用于读取缓存器中已写入的数据；介质控制器还用于接收该读缓存器请求，并根据读缓存器请求读取缓存器中已写入的数据,并触发所述向所述内存控制器发送所述缓存器中写入的数据的操作。
查询请求用于查询缓存器中是否有数据写入，内存控制器使用读缓存器请求实现对缓存器的读操作，从而可以进一步降低存储协议的复杂度。具体的，应答消息里可以携带缓存器中数据的多少，内存控制器可以根据缓存器中数据的多少触发读缓存器请求。例如，如果一次读缓存器只能读取固定大小的一份数据，若应答消息指示缓存器中当前有M份数据，则内存控制器可以触发M条读缓存器请求，其中，一份数据指一次访问请求可以请求的数据。
结合第一方面或第一方面以上任一种可能的实现方式，在第一方面第二种可能的实现方式中，内存控制器具体用于按照预设的查询周期向介质控制器发送查询请求。
更具体的，该预设的查询周期还可以根据内存控制器和内存设备之间互连的通道的忙碌程度进行动态调整，例如，当总线或通道比较忙碌时，可以增大预设的查询周期，从而减小查询请求的发送频率，减少对总线或者通道的占用；当总线或者通道比较空闲时，可以减少预设的查询周期，从而增大查询请求的发送频率，可以尽快的实现内存控制器对待访问数据的读取。
结合第一方面或第一方面以上任一种可能的实现方式，在第一方面第三种可能的实现方式中，内存控制器发送的多个访问请求分为至少两种优先级，内存设备包含至少两个缓存器，每个缓存器对应一种优先级，访问请求的查询周期根据访问请求的优先级确定，不同优先级的访问请求对应不同的查询周期。
计算机系统的访问请求可以分为多个优先级，可以通过在内存设备中设置多个缓存器的形式实现对不同优先级的访问请求的管理，每个缓存器对应一个优先级的访问请求。根据访问请求的优先级确定对应查询请求的查询周期，可以合理的折中数据的返回时间和对互联通道的占用之间的矛盾。对于优先级高的访问请求，发送查询请求的查询周期可以更小，从而保证重要数据优先返回给内存控制器。
结合第一方面或第一方面以上任一种可能的实现方式，在第一方面第四种可能的实现方式中，内存控制器向介质控制器发送的查询请求中还携带缓存器的指示信息，缓存器的指示信息用于指示查询请求所查询的缓存器。
内存控制器在查询特定缓存器的数据写入状态时，需要在查询请求中携带所查询的缓存器的指示信息。该指示消息可以具体为缓存器的地址信息，或者记录缓存器的数据写入状态的状态寄存器的地址信息等。
结合第一方面或第一方面以上任一种可能的实现方式，在第一方面第五种可能的实现方式中，为了保证正常的数据通信，内存控制器向介质控制器发送查询请求之前，还用于确定内存控制器与介质控制器之间的互联通道处于空闲状态。
在互联通道处于空闲的时候才发送查询请求，可以避免查询请求对其他正常的读写操作的影响。
结合第一方面或第一方面以上任一种可能的实现方式，在第一方面第六种可能的实现方式中，内存设备还包含状态寄存器，状态寄存器用于记录缓存器的数据写入状态；当确定缓存器是否有数据写入时，介质控制器具体用于：读取状态寄存器记录的缓存器的数据写入状态，并根据所述缓存器的数据写入状态，确定缓存器中是否有数据写入。
介质控制器将待访问数据写入缓存器后，会更新状态寄存器，并在读取出状态寄存器中数值后，对状态寄存器进行清零操作。
结合第一方面或第一方面以上任一种可能的实现方式，在第一方面第七种可能的实现方式中，由于异步访存方式中，待访问数据返回可能存在乱序，介质控制器还用于在向内存控制器发送缓存器中写入的数据时，向内存控制器发送标识信息，标识信息用于指示发送的数据对应的访问请求。
具体的，该标识信息可以为请求ID，可以在内存控制器发送的访问请求中携带请求ID，也可以在内存控制器和介质控制器两侧各维护一个同步的请求计数器，使用请求计数器的值表示请求ID。
第二方面，本申请提供了一种内存设备的访问方法，内存设备包含介质控制器、存储器和缓存器，介质控制器用于接收内存控制器的多个访问请求，以及将每个访问请求所请求的数据从存储器中读出并写入缓存器，该方法包括：内存控制器向介质控制器发送至少一个访问请求；内存控制器向介质控制器发送查询请求，查询请求用于查询缓存器中是否有数据写入；内存控制器接收介质控制器发送的缓存器中已写入的数据。
在内存设备的存储介质的访问时延不同的场景中，通过内存控制器向介质控制器主动发送查询请求，在不增加额外信号线的情况下，实现对内存设备的访问操作。且查询请求可以当做一次对缓存器的读指令，若缓存器中有数据写入，则内存控制器可以直接接收到介质控制器发送的缓存器中已写入的数据。
结合第二方面，在第二方面第一种可能的实现方式中，内存控制器向介质控制器发送查询请求之后，该方法还包括：内存控制器接收来自介质控制器的应答消息，应答消息用于指示缓存器的数据写入状态为已有数据写入；内存控制器根据应答消息，向介质控制器发送读缓存器请求，读缓存器请求用于读取缓存器中已写入的数据。
查询请求用于查询缓存器中是否有数据写入，内存控制器使用读缓存器请求实现对缓存器的读操作，从而可以进一步降低存储协议的复杂度。具体的，应答消息里可以携带缓存器中数据的多少，内存控制器可以根据缓存器中数据的多少触发读缓存器请求。
结合第二方面或第二方面以上任一种可能的实现方式，在第二方面第二种可能的实现方式中，内存控制器向介质控制器发送查询请求包括：内存控制器按照预设的查询周期向介质控制器发送查询请求。
更具体的，该预设的查询周期还可以根据内存控制器和内存设备之间互连的通道的忙碌程度进行动态调整，例如，当总线或通道比较忙碌时，可以增大预设的查询周期，从而减小查询请求的发送频率，减少对总线或者通道的占用；当总线或者通道比较空闲时，可以减少预设的查询周期，从而增大查询请求的发送频率，可以尽快的实现内存控制器对待访问数据的读取。
结合第二方面或第二方面以上任一种可能的实现方式，在第二方面第三种可能的实现方式中，内存控制器发送的多个访问请求分为至少两种优先级，内存设备包含至少两个缓存器，每个缓存器对应一种优先级，访问请求的查询周期根据访问请求的优先级确定，不同优先级的访问请求对应不同的查询周期。
计算机系统的访问请求可以分为多个优先级，可以通过在内存设备中设置多个缓存器的形式实现对不同优先级的访问请求的管理，每个缓存器对应一个优先级的访问请求。根据访问请求的优先级确定对应查询请求的查询周期，可以合理的折中数据的返回时间和对互联通道的占用之间的矛盾。
结合第二方面或第二方面以上任一种可能的实现方式，在第二方面第四种可能的实现方式中，内存控制器向介质控制器发送的查询请求中还携带缓存器的指示信息，缓存器的指示信息用于指示查询请求所查询的缓存器。
内存控制器在查询特定缓存器的数据写入状态时，需要在查询请求中携带所查询的缓存器的指示信息。该指示消息可以具体为缓存器的地址信息，或者记录缓存器的数据写入状态的状态寄存器的地址信息等。
结合第二方面或第二方面以上任一种可能的实现方式，在第二方面第五种可能的实现方式中，为了保证正常的数据通信，内存控制器向介质控制器发送查询请求之前，该方法还包括：内存控制器确定内存控制器与介质控制器之间的互联通道处于空闲状态。
在互联通道处于空闲的时候才发送查询请求，可以避免查询请求对其他正常的读写操作的影响。
结合第二方面或第二方面以上任一种可能的实现方式，在第二方面第六种可能的实现方式中，该方法还包括：内存控制器接收介质控制器发送的标识信息，标识信息用于指示接收的数据对应的访问请求。
具体的，该标识信息可以为请求ID，可以在内存控制器发送的访问请求中携带请求ID，也可以在内存控制器和介质控制器两侧各维护一个同步的请求计数器，使用请求计数器的值表示请求ID。
第三方面，本申请提供了一种可读介质，包括执行指令，当内存控制器的处理器执行执行指令时，该内存控制器器执行第二方面或第二方面的任一种可能的实现方式中的方法。
第四方面，本申请提供了一种内存控制器，包括：处理器、存储器和总线；存储器用于存储执行指令，处理器与存储器通过总线连接，当内存控制器运行时，处理器执行存储器存储的执行指令，以使内存控制器执行第二方面或第二方面的任一种可能的实现方式中的方法。
第五方面，本申请提供了一种内存设备的访问方法，内存设备包含介质控制器、存储器和缓存器，介质控制器用于接收内存控制器的多个访问请求，以及将每个访问请求所请求的数据从存储器中读出并写入缓存器，该方法包括：介质控制器接收来自内存控制器的至少一个访问请求；介质控制器接收来自内存控制器的查询请求，查询请求用于查询缓存器中是否有数据写入；介质控制器根据查询请求，确定缓存器中是否有数据写入；在确定缓存器中已有数据写入的情况下，介质控制器向内存控制器发送缓存器中已写入的数据。
在内存设备的存储介质的访问时延不同的场景中，介质控制器通过接收内存控制器主动发送的查询请求，在不增加额外信号线的情况下，实现对内存设备的访问操作。介质控制器在接收到查询请求后，若确定缓存器中有数据写入，则介质控制器可以将查询请求当做一次对缓存器的读指令，并将缓存器中已写入的数据返回给内存控制器。
可选的，内存控制器向介质控制器发送的查询请求中还携带缓存器的指示信息，缓存器的指示信息用于指示查询请求所查询的缓存器，内存控制器在查询特定缓存器的数据写入状态时，需要在查询请求中携带所查询的缓存器的指示信息。该指示消息可以具体为缓存器的地址信息，或者记录缓存器的数据写入状态的状态寄存器的地址信息等。
结合第五方面，在第五方面第一种可能的实现方式中，介质控制器确定缓存器中已有数据写入之后，该方法还包括：介质控制器向内存控制器发送应答消息，应答消息用于指示缓存器的数据写入状态为已有数据写入；介质控制器接收来自内存控制器的读缓存器请求，读缓存器请求用于读取缓存器中已写入的数据。
查询请求用于查询缓存器中是否有数据写入，读缓存器请求用于实现对缓存器的读操作，从而可以进一步降低存储协议的复杂度。具体的，应答消息里可以携带缓存器中数据的多少，内存控制器可以根据缓存器中数据的多少触发读缓存器请求。例如，如果一次读缓存器请求只能读取固定大小的一份数据，若应答消息指示缓存器中当前有M份数据，则内存控制器可以触发M条读缓存器请求，其中，一份数据指一次访问请求可以请求的数据。
结合第五方面或第五方面以上任一种可能的实现方式，在第五方面第二种可能的实现方式中，内存设备还包含状态寄存器，状态寄存器用于记录缓存器的的数据写入状态；介质控制器确定缓存器是否有数据写入包括：介质控制器读取状态寄存器记录的缓存器的数据写入状态，并根据缓存器的数据写入状态，确定缓存器中是否有数据写入。
介质控制器将待访问数据写入缓存器后，会更新状态寄存器，并在读取出状态寄存器中数值后，对状态寄存器进行清零操作。
结合第五方面或第五方面以上任一种可能的实现方式，在第五方面第三种可能的实现方式中，该方法还包括：介质控制器向内存控制器发送标识信息，标识信息用于指示该发送的数据对应的访问请求。
具体的，该标识信息可以为请求ID，可以在内存控制器发送的访问请求中携带请求ID，也可以在内存控制器和介质控制器两侧各维护一个同步的请求计数器，使用请求计数器的值表示请求ID。
第六方面，本申请提供了一种可读介质，包括执行指令，当介质控制器的处理器执行执行指令时，该介质控制器器执行第五方面或第五方面的任一种可能的实现方式中的方法。
第七方面，本申请提供了一种介质控制器，包括：处理器、存储器和总线；存储器用于存储执行指令，处理器与存储器通过总线连接，当介质控制器运行时，处理器执行存储器存储的执行指令，以使介质控制器执行第五方面或第五方面的任一种可能的实现方式中的方法。
第八方面，本申请提供了一种内存设备的访问装置，内存设备包含介质控制器、存储器和缓存器，介质控制器用于接收该装置的多个访问请求，以及将每个访问请求所请求的数据从存储器中读出并写入缓存器，该装置包括：发送单元，用于向介质控制器发送至少一个访问请求；发送单元还用于向介质控制器发送查询请求，查询请求用于查询缓存器中是否有数据写入；接收单元，用于接收介质控制器发送的缓存器中已写入的数据。
结合第八方面，在第八方面第一种可能的实现方式中，发送单元向介质控制器发送查询请求之后，接收单元还用于接收来自介质控制器的应答消息，应答消息用于指示缓存器的数据写入状态；发送单元还用于根据应答消息，向介质控制器发送读缓存器请求，读缓存器请求用于读取缓存器中已写入的数据。
结合第八方面或第八方面以上任一种可能的实现方式，在第八方面第二种可能的实现方式中，当向介质控制器发送查询请求时，发送单元具体用于按照预设的查询周期向介质控制器发送查询请求。
结合第八方面或第八方面以上任一种可能的实现方式，在第八方面第三种可能的实现方式中，该装置的多个访问请求分为至少两种优先级，内存设备包含至少两个缓存器，每个缓存器对应一种优先级，访问请求的查询周期根据访问请求的优先级确定，不同优先级的访问请求对应不同的查询周期。
结合第八方面或第八方面以上任一种可能的实现方式，在第八方面第四种可能的实现方式中，发送单元向介质控制器发送的查询请求中还携带缓存器的指示信息，缓存器的指示信息用于指示查询请求所查询的缓存器。
结合第八方面或第八方面以上任一种可能的实现方式，在第八方面第五种可能的实现方式中，装置还包含确定单元，发送单元向介质控制器发送查询请求之前，确定单元用于确定内存控制器与介质控制器之间的互联通道处于空闲状态。
结合第八方面或第八方面以上任一种可能的实现方式，在第八方面第六种可能的实现方式中，接收单元还用于接收介质控制器发送的标识信息，该标识信息用于指示接收单元接收的数据对应的访问请求。
第八方面为第二方面方法对应的内存控制器的装置实现方式，所以第二方面或第二方面任一种可能的实现方式中的描述对应适用于第八方面或第八方面任一种可能的实现方式，在此不再赘述。
第九方面，本申请提供了一种内存设备的访问装置，其特征在于，内存设备包含装置、存储器和缓存器，该装置用于接收内存控制器的多个访问请求，以及将每个访问请求所请求的数据从存储器中读出并写入缓存器，该装置包括：接收单元，用于接收来自内存控制器的至少一个访问请求；接收单元还用于接收来自内存控制器的查询请求，查询请求用于查询缓存器中是否有数据写入；确定单元，用于根据查询请求，确定缓存器中是否有数据写入；发送单元，在确定单元确定缓存器中已有数据写入的情况下，发送单元用于向内存控制器发送缓存器中已写入的数据。
可选的，查询请求中还携带缓存器的指示信息，缓存器的指示信息用于指示查询请求所查询的缓存器，内存控制器在查询特定缓存器的数据写入状态时，需要在查询请求中携带所查询的缓存器的指示信息。该指示消息可以具体为缓存器的地址信息，或者记录缓存器的数据写入状态的状态寄存器的地址信息等。
结合第九方面或第九方面以上任一种可能的实现方式，在第九方面第二种可能的实现方式中，确定单元确定缓存器中已有数据写入之后，发送单元还用于向内存控制器发送应答消息，应答消息用于指示缓存器的数据写入状态为已有数据写入；接收单元还用于接收来自内存控制器的读缓存器请求，读缓存器请求用于读取缓存器中已写入的数据。
结合第九方面或第九方面以上任一种可能的实现方式，在第九方面第二种可能的实现方式中，内存设备还包含状态寄存器，状态寄存器用于记录缓存器的数据写入状态；确定单元具体用于读取状态寄存器记录的缓存器的数据写入状态，并根据缓存器的数据写入状态，确定缓存器中是否有数据写入。
结合第九方面或第九方面以上任一种可能的实现方式，在第九方面第三种可能的实 现方式中，发送单元还用于向内存控制器发送标识信息，标识信息用于指示发送单元发送的数据对应的访问请求。
第九方面为第五方面方法对应的介质控制器的装置实现方式，所以第五方面或第五方面任一种可能的实现方式中的描述对应适用于第九方面或第九方面任一种可能的实现方式，在此不再赘述。
第十方面，本申请提供了一种内存设备，内存设备包含存储器、缓存器和第九方面或第九方面任一种可能的实现方式中的的装置。
根据本发明公开的技术方案，在内存设备的存储介质的访问时延不同的场景中，通过内存控制器向介质控制器主动发送查询请求，在不增加额外信号线的情况下，实现对内存设备的访问操作。相对于异步协议，本发明实施例使用更少的信令，实现了对混合内存系统的访问，而且因为查询请求可以使用存储协议中的读指令来实现，本发明实施例对各种存储协议有较好的兼容性。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为一种计算机系统的逻辑结构示意图；
图2(a)和图2(b)为依据本发明一实施例的内存设备的逻辑结构示意图；
图3为一种计算机系统的逻辑结构示意图；
图4为依据本发明一实施例的内存设备访问方法的流程示意图；
图5为依据本发明一实施例的内存设备访问方法的时序示意图；
图6为依据本发明一实施例的内存设备访问方法的时序示意图；
图7为依据本发明一实施例的内存设备访问方法的时序示意图；
图8为依据本发明一实施例的内存设备访问方法的时序示意图；
图9为依据本发明一实施例的内存设备访问方法的时序示意图；
图10为依据本发明一实施例的内存设备访问方法的时序示意图；
图11为依据本发明一实施例的内存设备访问方法的流程示意图；
图12为依据本发明一实施例的内存设备访问方法的时序示意图；
图13为依据本发明一实施例的内存访问装置的硬件结构示意图；
图14为依据本发明一实施例的内存控制器的逻辑结构示意图；
图15为依据本发明一实施例的内存控制器的逻辑结构示意图；
图16为依据本发明一实施例的介质控制器的逻辑结构示意图。
具体实施方式
下面将结合附图，对本发明实施例进行描述。
在进行内存访问时，对于不确定内存介质的访问时延的情况，例如，在混合内存系统中，由于混合内存系统中不同的内存介质具有不同的访存延迟，使用固定延迟的同步 双倍数据速率(Double Data Rate，DDR)协议显然无法满足系统的要求，更具体的，对于非易失性双列直插内存模块(non-volatile dual in-line memory module，NVDIMM)，由于其中集成了动态随机存取存储器(dynamic random access memory，DRAM)和非易失性内存芯片，传统的DDR协议无法满足系统的要求。
如果采用异步访存协议，由于每次内存访问的延时可能不同，则内存控制器对内存设备进行访问时，不仅要传输数据的地址信息，还需要传输额外的延时标识以及其他额外信息，例如请求包的长度信息、请求标识号等；或者需要通过增加在内存控制器和内存设备之间增加额外的信号线，由内存设备通过这条额外的信号线主动向内存控制器推送访问请求的状态。
本发明旨在解决上述的一些问题。根据本发明实施例，内存控制器通过向内存设备发送查询指令来查询访问请求的状态，可以在不修改传统存储协议(例如，DDR)的情况下，实现对不同延迟的内存介质的访问。
图1为依据本发明一实施例的的计算机系统100的架构示意图，系统100包括一个或多个处理器102，内存控制器104和内存设备108。在具体实现过程中，处理器102，内存控制器104和内存设备108可以处于同一块主板上，但本发明对此并不进行限定。例如内存设备108可以为远端内存，内存控制器104通过网络协议与内存设备108互联。
处理器102可以可以采用通用的中央处理器(Central Processing Unit，CPU)，微处理器，应用专用集成电路(Application Specific Integrated Circuit，ASIC)，现场可编程门阵列(Field Programmable Gate Array，FPGA)，或者一个或多个集成电路，本发明实施例并不对处理器102的具体实现形式进行限定。
内存控制器104用于响应来自处理器102的访问请求，并通过互联通道106与内存设备108进行通信，其中，互联通道106可以为总线或其他连接方式。本发明实施例并不对内存控制器104与内存设备108的连接方式进行限定，例如，二者还可以通过无线连接，或者内存设备108是一个远端内存，内存控制器104与内存设备108之间也可以通过各种网络协议进行连接。
其中，内存设备108可以支持多种存储协议，例如双倍数据速率第四代(Double Data Rate Fourth Generat1n，DDR4)协议和附加协议等，本发明实施例并不对内存设备108支持的存储协议进行限定。
内存设备108包含介质控制器110和存储器112。介质控制器110用于与内存控制器104交互和管理对内存设备108的访问操作。
存储器112包含存储芯片114和存储芯片116，用于存储系统100的处理器102需要的数据，存储芯片114和存储芯片116可以是相同的存储介质或者不同的存储介质，例如在混合内存系统中，内存设备包含不同的存储介质，存储芯片114和存储器116可以为各类非易失存储器(Non-VolatiIe Memory，NVM)或动态随机存取存储器(Dynamic Random Access Memory，DRAM)等。具体的，存储芯片114和存储芯片116可以为闪存(Flash)存储、铁电随机存储(ferroelectric random-access memory，FeTRAM)、基于纳米线的随机存储或各类DRAM等。
应理解，虽然图1示出存储器112包含存储芯片114和存储芯片116，但本发明实施例并不对存储器112中的存储芯片的数目进行限制，存储器112可以包含更多或者更少 的存储芯片，本发明实施例也不对存储芯片采用的存储介质进行限定。
图2(a)为依据本发明一实施例的一种内存设备108的架构示意图，图2(a)展示了内存设备108的其他细节。
如图2(a)所示，内存设备108还包含缓存器118和内存接口120。介质控制器110，存储器112，缓存器118和内存接口120可以通过互联总线相连。
缓存器118用于缓存存储器112存储的数据，具体的，介质控制器110接收到访问请求后，会先将待访问数据从存储器112读出，然后将待访问数据写入缓存器118，然后在接收到内存控制器发送的新的指令后，例如以下描述中的查询请求或读缓存器请求，将缓存器118中的待访问数据返回给内存控制器104。
更具体的，缓存器118可以为一个先入先出队列(First Input First Output，FIFO)，介质控制器110接收到内存控制器104发送的指令后，按照写入该FIFO的顺序将该FIFO中存储的数据返回给内存控制器侧。
应理解，内存设备108可以具体包含读缓存器和写缓存器，写缓存器用于缓存向存储器112写入的数据，读缓存器用于缓存从存储器112内读出的数据，本发明对此并不限定。为了描述方便，除非另有说明，本发明实施例中的缓存器118为读缓存器。
另外，在内存设备108中可以有多个缓存器118，不同的缓存器118可以对应不同的访问请求，或者对应不同优先级的访问请求。例如，计算机系统的访问请求可以分为多个优先级，对重要数据的访问请求的优先级高于对一般数据的访问请求的优先级。可以通过在内存设备中设置多个缓存器118的形式实现对不同优先级的访问请求的管理，每个访问请求依据不同的优先级，对应不同的缓存器。为了描述方便，在本发明实施例中，以其中的一个缓存器118进行描述，但应理解，本发明实施例并不对缓存器118的数量进行限定。
内存接口120用于与互联通道106连接，从而实现内存控制器104与介质控制器110之间的交互。
可选的，如图2(b)所示，内存设备108还包含状态寄存器122，状态寄存器122用于记录缓存器118的数据写入状态。更具体的，如果有多个缓存器118，例如，不同的优先级的访问请求对应不同的缓存器118，则每一个缓存器118可以有一个状态寄存器122记录其数据写入状态，为了描述方便，本发明实施例以其中的一组缓存器118和状态寄存器122进行表述，但应了解，本发明实施例并不对缓存器118和状态寄存器122的数目进行限定。
可选的，状态寄存器122可以存储一位二进制的比特位，可以记录“0”或“1”两种状态，例如，可以用“0”状态表示缓存器118中没有数据写入，用“1”状态表示缓存器118有数据写入，则介质控制器110通过状态寄存器122中的状态位来判断缓存器118中是否有数据写入。
可选的，状态寄存器122可以存储多位二进制比特位，可以记录多种状态，例如，如果存储寄存器122可以记录3位二进制比特位，则可以记录8种状态。如果每次访问请求可以请求一份固定大小的待访问数据，则每将一份待访问数据写入缓存器118后，介质控制器110通过将状态寄存器122的数值加1的形式对状态寄存器122进行更新。例如，如果状态寄存器122的原数值为“0”，“0”状态表示缓存器118中没有数据写 入，则介质控制器110将待访问数据写入缓存器118后，可以将状态寄存器122的值置为“1”，表示有一份待访问数据被写入缓存器118，如果状态寄存器122中数值不为“0”，例如为“2”，则表明缓存器118中已经有2份待访问数据写入，则介质控制器110将状态寄存器122中数值加1，变为“3”，表示缓存器118有新的待访问数据写入，当前缓存器118中有3份待访问数据。
例如，每一个访问请求可以读取64Bytes的一份待访问数据，介质控制器110根据访问请求将64Bytes大小的待访问数据写入缓存器118后，会将状态寄存器122中数值加1，表示有一份新的数据被写入缓存器。
为了描述方便，除非另有说明，在本发明实施例中，一份数据或一份待访问数据为一次访问请求所请求读取的数据。
应理解，图2(a)和图2(b)仅仅是内存设备108的示例性架构示意图，在具体实现过程中，内存设备108可以包含更多或者更少的组件，本发明实施例对此并不进行限定。
例如，在本发明实施例的一种更具体的实现方式中，如图3所示，内存控制器104还包含第一请求计数器124，内存设备包含第二请求计数器126。
其中，第一请求计数器124用于对内存控制器104发送给内存设备108的访问请求进行标记，例如，内存控制器104每发送一个访问请求，第一请求计数器124加1，并用第一请求计数器106的数值作为请求ID对发送的访问请求进行标记。第二请求计数器126与第一请求计数器106保持同步，用于对内存设备108接收到的访问请求进行标记，例如，介质控制器108每接收一个访问请求，第二请求计数器126加1，并用第二请求计数器126的数值作为请求ID对接收的访问请求进行标记。
介质控制器110会维护访问请求与访问数据之间的对应关系，当向内存控制器104返回访问数据时，会携带访问数据对应的访问请求的请求ID，以此对访问数据的顺序进行标识。内存控制器104根据请求ID对访问数据的顺序进行调整。
当第一请求计数器124和第二请求计数器126的数值达到能支持的最大值的时候，可以对请求计数器进行回零操作，即重新将请求计数器中的数值置为0。而且本发明实施例并不对第一请求计数器124和第二请求计数器126的计数方式进行限定，例如，第一请求计数器124和第二请求计数器126还可以按照减1的方式对访问请求进行标记。
本发明实施例所描述的内存控制器104和介质控制器110可以通过硬件逻辑编码实现，例如ASIC或者FPGA等。
本发明实施例所描述的内存控制器104和介质控制器110也可以通过通过存储有计算机执行指令的可读存储介质来实现。该可读存储介质可以为只读存储器(Read Only Memory，ROM)，静态存储设备，动态存储设备或者随机存取存储器(Random Access Memory，RAM)等或适合于存储计算机执行指令的其它类型的可读媒介。例如，本发明实施例可以为可下载计算机指令，可以通过网络传输从远程计算机(例如，服务器)传递到请求计算机(例如，客户端)。
图4为依据本发明一实施例的一种内存设备的访问方法的示意性流程图，如图4所示，该方法包括：
S402：内存控制器触发访问请求，并将访问请求发送给介质控制器。
具体的，内存控制器向介质控制器发送至少一条访问请求，其中，每条访问请求携带所请求的待访问数据在内存设备的存储器中的地址信息。
访问请求可以在内存控制器接收到处理器发送的访问指令后，由内存控制器触发。
更具体的，待访问数据的地址信息可以为待访问数据在存储器中的物理地址信息，处理器发送的访问指令中携带待访问数据的虚拟地址信息，内存控制器还用于根据虚拟地址与物理地址的映射关系，将待访问数据的虚拟地址信息转换为物理地址信息。
在具体实现中，也可以由介质控制器维护虚拟地址与物理地址的映射关系，则访问请求中携带的地址信息也可以为待访问数据的虚拟地址信息。
具体实现过程中，每次访问请求能够读取的待访问数据的大小可以是一个固定的数值，即每次访问请求可以读取一份固定大小的待访问数据，例如一次访问请求可以读取64Bytes的数据。如果每次访问请求能够请求的待访问数据大小为一个固定值，则访问请求中的待访问数据的地址信息可以为待访问数据在内存设备的首地址。
应理解，本发明实施例并不对访问请求和待访问数据的地址信息的形式进行限定。
S404：介质控制器接收访问请求，根据访问请求将待访问数据从存储器中读出，并将待访问数据写入缓存器。
介质控制器接收到每条访问请求后，根据其中携带的地址信息将待访问数据从存储器中读出，并写入缓存器。当待访问数据被写入缓存器后，则数据为ready状态，表示可以被内存控制器读取，当介质控制器从内存控制器接收到读缓存器的指令后，可以将缓存器中已写入的数据返回给内存控制器。
因为不同存储介质的访问时延不同，介质控制器将待访问数据从存储器中读出并写入缓存器这一过程需要的时间对内存控制器不透明，即内存控制器无法确定介质控制器完成这一过程的时间，内存控制器需要主动发送新的指令来查询缓存器中是否有数据写入。
S406：内存控制器向介质控制器发送查询请求，查询请求用于查询缓存器中是否有数据写入。
本发明实施例适用于进行内存访问时，不确定内存介质的访问时延的场景，例如，在混合内存系统中，由于混合内存系统中不同的内存介质具有不同的访存延迟，使用固定延迟的DDR协议显然无法满足系统的要求。由于内存控制器不确定待访问数据的访问时延，无法确定待访问数据被写入缓存器的时间点，所以要通过查询请求，查询缓存器中是否有数据被写入。
具体的，介质控制器可以按照预设的查询周期向介质控制器发送查询请求。
该预设的查询周期还可以根据内存控制器和内存设备之间互连的通道的忙碌程度进行动态调整，例如，当总线或通道比较忙碌时，可以增大预设的查询周期，从而减小查询请求的发送频率，减少对总线或者通道的占用；当总线或者通道比较空闲时，可以减少预设的查询周期，从而增大查询请求的发送频率，可以尽快的实现内存控制器对待访问数据的读取。
该预设的查询周期还可以根据访问请求的优先级进行确定，内存控制器发送的多个访问请求分为至少两种优先级，内存设备包含至少两个缓存器，每个缓存器对应一种优先级，访问请求的查询周期根据访问请求的优先级确定，不同优先级的访问请求对应不 同的查询周期。
计算机系统的访问请求可以分为多个优先级，可以通过在内存设备中设置多个缓存器的形式实现对不同优先级的访问请求的管理，每个缓存器对应一个优先级的访问请求。对于优先级高的缓存器，可以使用更频繁的查询请求来保证高优先级访问请求的操作延迟。
可选的，为了保证正常的数据通信，内存控制器还可以在确定内存控制器与内存设备之间的互联通道处于空闲状态后，向介质控制器发送查询指令。
应理解，本发明实施例中部分步骤不分先后顺序，例如步骤S404与步骤S406不分先后顺序，内存控制器发送查询请求时，介质控制器可能已经将访问请求所请求的数据从存储器中读出并写入了缓存器，或者尚未将访问请求所请求的数据写入缓存器。
S408：介质控制器接收查询请求，并确定缓存器中是否有数据写入，如果确定缓存器还没有数据写入，则执行步骤S410，如果确定缓存器已经有数据写入，则执行步骤S412。
介质控制器可以通过维护缓存器中的剩余空间的形式来记录缓存器的数据写入状态，如果剩余空间的大小与缓存器存储空间相同，则表明当前缓存器没有数据写入；如果剩余空间小于缓存器的存储空间，则表明当前缓存器有数据写入，缓存器中已写入的数据的大小为缓存器的存储空间与剩余空间的差值。更具体的，介质控制器可以通过维护缓存器的可写地址位的形式来维护缓存器的剩余空间。
介质控制器还可以通过状态寄存器来记录缓存器的数据写入状态。介质控制器将待访问数据写入缓存器后，会更新状态寄存器，状态寄存器用于记录缓存器的数据写入状态。介质控制器接收到查询请求后，读取状态寄存器记录的缓存器的数据写入状态，并根据缓存器的数据写入状态，确定所述缓存器中是否有数据写入
查询请求可以为读状态寄存器的读指令，其中携带有状态寄存器的地址，以此可以通过各存储协议支持的读指令来实现查询请求，从而可以实现查询请求与各种存储协议的兼容。
介质控制器读取状态寄存器中的数据后，对状态寄存器进行清零操作。
内存控制器向介质控制器发送的查询请求中还携带缓存器的指示信息，缓存器的指示信息用于指示查询请求所查询的缓存器。内存控制器在查询特定缓存器的数据写入状态时，需要在查询请求中携带所查询的缓存器的指示信息。该指示消息可以具体为缓存器的地址信息，或者记录缓存器的数据写入状态的状态寄存器的地址信息等。
S410：介质控制器不响应内存控制器的查询请求或者向内控控制器发送指示消息，该指示消息用于指示缓存器中没有数据写入。
因为内存介质的访问时延不确定，可能内存控制器发送查询指令时，缓存器中还没有数据写入，则介质控制器可以不响应查询请求，或者向内存控制器发送指示消息，指示消息用于指示缓存器中没有数据。
如果内存控制器在固定时间内没有收到介质控制器的响应或者收到介质控制器发送的用于指示缓存器中没有数据的指示消息，则内存控制器可以一定的策略重复向介质控制器发送查询请求，详细策略参照S406，在此不再赘述。
S412：介质控制器向内存控制器发送缓存器中已写入的数据。
在确定缓存器中已经有数据写入的情况下，介质控制器将缓存器中已写入的数据发 送给内存控制器。
在本发明实施例中，因为存储介质的访问时延不确定，使用固定延迟的DDR协议等同步存储协议显然无法满足系统的要求，内存控制器向介质控制器发送访问请求后，因为访问时延不确定，介质控制器在没有收到明确指令，不能主动将数据返回给内存控制器，为了确定待访问数据的状态，需要内存控制器向介质控制器发送查询指令，才能读取缓存器中的数据。
在本发明实施例的一种具体的实现方式中，查询指令有两个功能，一个功能是查询缓存器的数据写入状态，另一个功能是在缓存器中有数据写入的情况下，实现对缓存器的读操作。介质控制器在接收到查询请求后，若确定缓存器中有数据写入，则介质控制器可以将查询请求当做一次对缓存器的读指令，并将缓存器中已写入的数据返回给内存控制器。
图5为依据本发明一实施例的一种内存设备访问流程的示意性时序图，如图5所示，使能信号在低电平时为有效，当使能信号处于低电平时，在时钟上升沿，介质控制器接收来自内存控制器的访问请求，其中访问请求携带待访问数据A在内存设备的地址A；当使能信号处于另外一个低电平时，在时钟的上升沿，介质控制器接收来自内存控制器的查询请求，介质控制器根据查询请求查询缓存器，如果此时数据A已经被写入写缓存器，则介质控制器响应查询请求，将数据A返回给内存控制器。
在本发明实施例的另一种具体的实现方式中，介质控制器向内存控制器发送缓存器中的待访问数据之前，还向内存控制器发送应答消息，应答消息用于指示缓存器的数据写入状态为已有数据写入。内存控制器根据应答消息，触发读缓存器请求，并将读缓存器请求发送给介质控制器，读缓存器请求用于读取缓存器中已写入的数据。介质控制器还用于接收内存控制器发送的读缓存器请求，根据读缓存器请求读取缓存器中已写入的数据，并触发向内存控制器发送缓存器中已写入的数据的操作。
查询请求用于查询缓存器中是否有数据写入，读缓存器请求用于实现对缓存器的读操作，从而可以进一步降低存储协议的复杂度。
读缓存器请求具体为对缓存器的一次读指令，携带有缓存器的地址信息。介质控制器接收到读缓存器请求后，触发步骤S412。
应答消息用于指示缓存器中有数据写入，更具体的，应答消息中还可以指示缓存器中待访问数据的数量，即应答消息消息中还携带有缓存器中待访问数据的份数M，则读缓存器请求中可以携带请求读取缓存器中数据的数量信息，该数量信息根据数据M产生。
如果一个读缓存器请求只能读取缓存器中的一份待访问数据，即只能读取一个访问请求的待访问数据，例如64Bytes大小的固定数据，则内存控制器可以根据应答消息向介质控制器发送M条读缓存器请求，从而实现对缓存器中所有数据的读取，介质控制器接收到M条读缓存器请求后，将缓存器中的待访问数据返回给内存控制器。其中，M为大于0的正整数。
图6为依据本发明一实施例的一种内存设备访问流程的示意性时序图，如图6所示，介质控制器接收到查询请求后，查询缓存器中是否有数据写入，如果有数据写入，则向内存控制器发送应答消息，应答消息携带缓存器的数据写入状态，如图6所示，介质控制器响应查询请求，将数值“1”发送给内存控制器侧，数值“1”用于指示当前缓存器 有数据写入，更具体的，数值“1”可以用于表示当前缓存器中有一份数据，则内存控制器根据应答消息，向介质控制器发送读缓存器请求，其中，读缓存器请求用于读取缓存器中的数据，介质控制器根据读缓存器请求将数据A发送给内存控制器。
在本发明实施例的另一种具体的实现方式中，因为访问请求不能直接使介质控制器返回该访问请求所请求的待访问数据，借助于访问请求的这一特性，为了减少内存控制器与介质控制器之间的交互次数，查询请求可以用新的访问请求来实现。
例如，内存控制器发送读地址A的访问请求之后，介质控制器将地址A指示的数据A从存储器中取出，并写入了缓存器，随后内存控制器又发送了一条读地址B的访问请求，则读地址B的访问请求可以同时实现查询指令的功能，介质控制器接收到读地址B的访问请求之后，会根据读地址B的访问请求将地址B指示的数据B从存储器中读出，写入缓存器，并根据读地址B的访问请求查询缓存器的数据写入状态，并直接向内存控制器返回数据A或者向内存控制器发送应答消息。
通过这样的实现方式，减小了内存控制器与介质控制器之间进行交互的信令数目，从而减小了对通信总线或者通道的负载压力。
示意性时序图如图7和图8所示，图7中，介质控制器接收到读地址B的访问请求之后，如果缓存器中已经有数据A写入，则介质控制器直接将缓存器中的数据A返回给内存控制器。图8中，介质控制器接收到读地址B的访问请求之后，如果缓存器中已经有数据A写入，则介质控制器向内存控制器发送应答消息，内存控制器根据应答消息向介质控制器发送读缓存器请求，介质控制器根据读缓存器请求将数据A返回给内存控制器。图7和图8的具体实现参照图5和图6，在此不再赘述。
在本发明实施例的另一种具体的实现方式中，介质控制器通过状态寄存器来记录缓存器的数据写入状态。示意性时序图如图9和图10所示，查询请求还携带状态寄存器的地址信息，查询请求携带状态寄存器的地址，介质控制器接收到查询请求后，根据状态寄存器的地址信息去读取状态寄存器中的数值，如果数值为“0”，则表明当前缓存器没有数据写入；如果数值不为“0”，则表明当前缓存器已经有数据写入。进一步的，介质控制器还可以根据状态寄存器中的具体数值来判断缓存器中被写入数据的数量。
图9中，如果状态寄存器的值不为“0”，则介质控制器直接将状态寄存器中的数据返回给内存控制器。图10中，如果状态寄存器的值不为“0”，则介质控制器将状态寄存器中的数据返回给内存控制器。图9和图10的具体实现参照图5和图6，在此不再赘述。
在本发明实施例另一种实现方式中，内存控制器对缓存器的的一条读指令只能读取缓存器中的一份待访问数据，内存系统将查询请求当做一次对缓存器的读指令，从而节省了内存控制器与介质控制器之间交互的次数。
具体的，若缓存器中只有一份待访问数据，则介质控制器可以直接将该待访问数据发送给内存控制器，若M为大于1的正整数，则介质控制器可以根据查询指令将缓存器中的最先被写入的一份待访问数据发送给内存控制器侧，例如，缓存器为一个FIFO，则介质控制器将队列首的一份待访问数据发送给内存控制器，并向内存控制器发送应答消息，应答消息中指示缓存器剩余的待访问数据的数量。则内存控制器接收到应答消息后，只需向介质控制器发送M-1条读缓存器请求即可，介质控制器接收到M-1条读缓存器请 求后，将缓存器中剩余的M-1条待访问数据返回给内存控制器。
在本发明实施例中，由于异步访存方式中，待访问数据返回可能存在乱序，介质控制器在向所述内存控制器发送所述缓存器中写入的数据时，还向内存控制器发送标识信息，该标识信息用于指示介质控制器发送的数据对应的访问请求，即标识信息用于指示待访问数据与访问请求的对应关系。
具体的，标识信息可以携带在介质控制器发送的数据内，同时发送给内存控制器，也可以将数据和数据的标识信息交替发送，应理解，本发明实施例并不对数据和数据的标识信息的发送方式进行限定。
具体的，本发明实施例使用请求ID以标识每次返回的待访问数据。介质控制器在向内存控制器发送待访问数据时，还将待访问数据对应的访问请求的请求ID一并返回给内存控制器，从而实现数据的乱序返回。
具体实现过程中，内存控制器可以在发送访问请求时，将访问请求对应的请求ID一起发送给介质控制器。
本发明实施例还可以采用内存控制器与介质控制器双方同步的方式记录请求ID，即双方各有一个请求计数器，用请求计数器的值记录访问请求的请求ID。内存控制器每发送一个访问请求，内存控制器侧的第一请求计数器自动加1；介质控制器每接收一个请求，介质控制器侧的第二请求计数器自动加1，返回待访问数据时，请求ID伴随待访问数据一起传给内存控制器。由于访问请求的发送与接收的顺序一定一致，所以双方实现了请求ID的同步，从而实现了访存请求的乱序返回。请求计数器的详细说明前文已有描述，在此不再赘述。
根据本发明实施例公开的技术方案，在内存设备的存储介质的访问时延不同的场景中，通过内存控制器向介质控制器主动发送查询请求，在不增加额外信号线的情况下，实现对内存设备的访问操作。相对于异步协议，本发明实施例使用更少的信令，实现了对混合内存系统的访问，而且因为查询请求可以使用存储协议中的读指令来实现，本发明实施例对各种存储协议有较好的兼容性。
本发明实施例中，为了兼容存储协议，访问请求、查询请求和读缓存器请求都可以使用存储协议中的读指令来实现，图11为依据本发明一实施例的一种具体的内存设备的方法的流程性示意图，如图11所示，该方法包括：
S1102：内存控制器触发第一读指令，并将第一读指令发送给介质控制器。
其中，第一读指令携带待访问数据在内存设备的地址信息，该第一读指令可以读取的一份待访问数据为固定大小，例如64Bytes，为了表述方便，在以下描述中，一份待访问数据的大小为64Bytes，但应理解，本发明实施例并不对一份待访问数据的大小进行限定。
内存控制器发送第一读指令后，对内存控制器侧的第一请求计数器加1，并用加1后的第一请求计数器内的数值作为该访问请求的请求ID，用于标识该第一读指令。
S1104：介质控制器接收第一读指令，并根据第一读指令携带的地址信息，从内存设备的存储器中读出64Bytes大小的待访问数据，并将该待访问数据写入缓存器。
介质控制器接收到第一读指令后，对介质控制器侧的第二请求计数器加1，以此与内存控制器侧的第一请求计数器保持同步，并用加1后的请求计数器的数值作为该访问请 求的请求ID，用于标识该第一读指令。更具体的，介质控制器会维护待访问数据与第一读指令的对应关系，即记录每一份待访问数据对应的请求ID，以实现数据的乱序返回。
S1106：介质控制器将待访问数据写入缓存器后，更新状态寄存器记录的缓存器的数据写入状态。
该数据写入状态可以为具体数值，用于指示当前缓存器中待访问数据的份数。介质控制器将待访问数据写入缓存器后，将状态寄存器内的数值加1。
S1108：内存控制器触发第二读指令，并将第二读指令发送给介质控制器。
具体的，第二读指令携带状态寄存器的地址，用于读取状态寄存器中记录的缓存器的数据写入状态。
S1110：介质控制器接收第二读指令，并根据第二读指令中携带的状态寄存器的地址读取状态寄存器。
介质控制器读取状态寄存器中的数值N后，将状态寄存器清零。
S1112：介质控制器将状态寄存器中的数值N发送给内存控制器，状态寄存器中的数值N用于表示当前缓存器中的待访问数据的份数N。
S1114：内存控制器接收到介质控制器发送的状态寄存器中的数值N后，判断N是否大于0，如果N为0，则表明当前缓存器中还没有待访问数据写入，则内存控制器返回步骤S1108，按照一定的策略重新向介质控制器发送第二读指令；如果N大于0，则内存控制器执行步骤S1116。
S1116：内存控制器触发第三读指令，并将第三读指令发送到介质控制器。
其中，第三读指令携带缓存器的地址信息，用于读取缓存器中的待访问数据。
具体的，如果一条第三读指令可以读取多份待访问数据，则第三读指令中还携带待读取的数据的数量指示信息，该数量指示信息根据数据N产生；如果每一条第三读指令只能读取一份待访问数据，则内存控制器向内存控制器发送N条第三读指令，每一条第三读指令用于读取一份64Bytes大小的待访问数据。
S1118：介质控制器接收第三读指令，并根据第三读指令携带的缓存器的地址信息读取缓存器中的待访问数据。
具体的，缓存器可以为一个FIFO，如果每一条第三读指令只能读取一份待访问数据，则每一个第三读指令读取处于FIFO队列首的一份待访问数据。N条第三读指令可以从缓存器中读取前N份待访问数据。
S1120：介质控制器向内存控制器发送从缓存器中读取的N份待访问数据。
具体的，每一份待访问数据中携带与其对应的请求ID，以指示待访问数据的请求顺序。
S1122:内存控制器接收介质控制器发送的N份待访问数据，并将该N份待访问数据发送给处理器。
具体的，因为每份待访问数据都携带对其对应的第一读指令的请求ID，内存控制器在将待访问数据发送给处理器之前，还可以根据待访问数据中的请求ID，对乱序返回的待访问数据进行重排，从而保证数据的正确性和完整性。
图11实施例为图3实施例的一种具体的实现方式，图3实施例的具体描述适用于本发明实施例，在此不再赘述。
图12为图11实施例的内存设备访问方法的时序示意图，如图12所示，当使能信号为低电平时，介质控制器在时钟的上升沿接收第一读指令，第一读指令携带待访问数据A的地址A；在使能信号的另一个低电平时，介质控制器在时钟的上升沿接收到内存控制器发送的第二读指令，第二读指令携带状态寄存器的地址信息，介质控制器将读取状态寄存器中数值，并将数值“1”返回给内存控制器，数值“1”用于指示当前缓存器有一份待访问数据；在使能信号的再一个低电平时，介质控制器在时钟的上升沿接收到来自内存控制器的第三读指令，第三读指令携带缓存器的地址信息，介质控制器读取缓存器，并将缓存器中的数据A返回给内存控制器。
本发明实施例所描述的内存控制器或介质控制器的硬件结构可以通过如图13所示的装置1300来实现。如图13所示，装置1300包括处理器1302、存储器1304、通信接口1306和总线1308。其中，处理器1302、存储器1304和通信接口1306通过总线1308实现彼此之间的通信连接。
处理器1302是装置1300的控制中心，用于执行相关程序，以实现本发明实施例所提供的技术方案。处理器1302可以采用通用的中央处理器，微处理器，专用集成电路，或者一个或多个集成电路，用于执行相关程序，以实现本发明实施例所提供的技术方案。
存储器1304可以是只读存储器，静态存储设备，动态存储设备或者随机存取存储器。在通过软件或者固件来实现本发明实施例提供的技术方案时，用于实现本发明实施例提供的技术方案的程序代码保存在存储器1304中，并由处理器1302来执行。存储器1304可以与处理器1302集成在一起或集成在处理器1302的内部，也可以是独立于处理器1302的一个或多个存储单元。
通信接口1306使用例如但不限于收发器一类的收发装置，来实现装置1300与其他设备或通信网络之间的通信。
总线1308可包括一通路，在装置1300各个部件(例如处理器1302、存储器1304和通信接口1306)之间传送信息。
应注意，尽管图13所示的计装置1300仅仅示出了处理器1302、存储器1304、通信接口1306以及总线1308，但是在具体实现过程中，本领域的技术人员应当明白，装置1300还包含实现正常运行所必须的其他器件。同时，根据具体需要，本领域的技术人员应当明白，装置1300还可包含实现其他附加功能的硬件器件。此外，本领域的技术人员应当明白，装置1300也可仅仅包含实现本发明实施例所必须的器件，而不必包含图13中所示的全部器件。
图13所示的硬件结构以及上述描述适用于本发明实施例所提供的各种内存控制器或介质控制器，适用于执行本发明实施例所提供的各种内存设备的访问方法。
图14为依据本发明一实施例的内存控制器的逻辑结构示意图，该内存控制器用于实现对内存设备的访问，内存设备包含介质控制器、存储器和缓存器，如图14所示，该内存控制器包括发送单元1402和接收单元1404，其中，
发送单元1402用于向介质控制器发送至少一个访问请求。
发送单元1402还用于向所述介质控制器发送查询请求，所述查询请求用于查询所述缓存器中是否有数据写入。
在具体实现过程中，发送单元1402可以由图13所示的处理器1302，存储器1304 和通信接口1306来实现，更具体的，可以由处理器1302执行存储器1304中的执行指令，以使通信接口执行发送单元1402的功能。
具体实现过程中，发送单元1402可以按照预设的查询周期向介质控制器发送所述查询请求，且该预设的查询周期可以根据访问请求的优先级进行确定，内存控制器的访问请求可以分为至少两种优先级，内存设备包含至少两个缓存器，每个缓存器对应一种优先级，访问请求的查询周期根据访问请求的优先级确定，不同优先级的访问请求对应不同的查询周期。
发送单元向介质控制器发送的查询请求中还携带缓存器的指示信息，缓存器的指示信息用于指示查询请求所查询的缓存器。
如图15所示，该内存控制器还包含确定单元1406，发送单元1402向介质控制器发送查询请求之前，确定单元1406用于确定内存控制器与介质控制器之间的互联通道处于空闲状态。
在具体实现过程中，确定单元可以由图13所示的处理器1302和存储器1304来实现，更具体的，可以由处理器1302执行存储器1304中的执行指令，以确定内存控制器与介质控制器之间的互联通道处于空闲状态。
接收单元1404用于接收介质控制器发送的缓存器中已写入的数据。
在具体实现过程中，接收单元1404可以由图13所示的处理器1302，存储器1304和通信接口1306来实现，更具体的，可以由处理器1302执行存储器1304中的执行指令，以使通信接口执行接收单元1404的功能。
可选的，发送单元1402向介质控制器发送查询请求之后，接收单元1404还用于接收来自介质控制器的应答消息，应答消息用于指示缓存器的数据写入状态为已有数据写入；发送单元1402还用于根据应答消息，向介质控制器发送读缓存器请求，读缓存器请求用于读取缓存器中已写入的数据。
接收单元1404还用于接收介质控制器发送的标识信息，该标识信息用于指示接收单元1404接收的数据对应的访问请求。
本发明实施例是内存控制器的装置实施例，图1至图12实施例部分的特征描述，适用于本发明实施例，在此不再赘述。
图16为依据本发明一实施例的介质控制器的逻辑结构示意图，该介质控制器用于实现对内存设备的访问，内存设备包含该介质控制器、存储器和缓存器，介质控制器用于根据接收到的内存控制器的每个访问请求，将每个访问请求所请求的保存在该存储器中的数据写入该缓存器，如图16所示，该内存控制器包括接收单元1602，确定单元1604和发送单元1606，其中，
接收单元1602用于接收来自内存控制器的至少一个访问请求。
在具体实现过程中，接收单元1602可以由图13所示的处理器1302，存储器1304和通信接口1306来实现，更具体的，可以由处理器1302执行存储器1304中的执行指令，以使通信接口执行接收单元1602的功能。
接收单元1602还用于接收来自内存控制器的查询请求，查询请求用于查询缓存器中是否有数据写入。
确定单元1604，用于根据查询请求，确定缓存器中是否有数据写入。
在具体实现过程中，确定单元可以由图13所示的处理器1302和存储器1304来实现，更具体的，可以由处理器1302执行存储器1304中的执行指令，以根据查询请求，确定缓存器中是否有数据写入。
发送单元1606，在确定单元1604确定缓存器中已有数据写入的情况下，发送单元1606用于向内存控制器发送缓存器中已写入的数据。
在具体实现过程中，发送单元1606可以由图13所示的处理器1302，存储器1304和通信接口1306来实现，更具体的，可以由处理器1302执行存储器1304中的执行指令，以使通信接口执行发送单元1606的功能。
可选的，确定单元1604确定缓存器中已有数据写入之后，发送单元1606还用于向内存控制器发送应答消息，应答消息用于指示缓存器的数据写入状态为已有数据写入；接收单元1602还用于接收来自内存控制器的读缓存器请求，读缓存器请求用于读取缓存器中已写入的数据。
可选的，内存设备还包含状态寄存器，状态寄存器用于记录缓存器的数据写入状态；确定单元1604具体用于读取状态寄存器记录的缓存器的数据写入状态，并根据缓存器的数据写入状态，确定缓存器中是否有数据写入。
发送单元1606还用于向内存控制器发送标识信息，标识信息用于指示发送单元1606发送的数据对应的访问请求。
本发明实施例是介质控制器的装置实施例，图1至图12实施例部分的特征描述，适用于本发明实施例，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统，设备和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述模块的划分，仅仅为一种逻辑功能划分，实现时可以有另外的划分方式，例如多个模块或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或模块的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的模块可以是或者也可以不是物理上分开的，作为模块显示的部件可以是或者也可以不是物理模块，即可以位于一个地方，或者也可以分布到多个网络模块上。可以根据实际的需要选择其中的部分或者全部模块来实现本实施例方案的目的。
另外，在本发明各个实施例中的各功能模块可以集成在一个处理模块中，也可以是各个模块单独物理存在，也可以两个或两个以上模块集成在一个模块中。上述集成的模块既可以采用硬件的形式实现，也可以采用硬件加软件功能模块的形式实现。
上述以软件功能模块的形式实现的集成的模块，可以存储在一个计算机可读取存储介质中。上述软件功能模块存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本发明各个实施例所述方法的部分步骤。而前述的存储介质包括：移动硬盘、只读存储器、随机存取存储器、磁碟或者光盘等各种可以存储程序代码的介质。
最后应说明的是：以上实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的保护范围。

Claims (31)

  1. 一种内存设备的访问系统，其特征在于，所述系统包含内存控制器和内存设备，所述内存设备包含介质控制器、存储器和缓存器；
    所述介质控制器，用于接收所述内存控制器的多个访问请求，以及将每个访问请求所请求的数据从所述存储器中读出并写入所述缓存器；
    所述内存控制器，在向所述介质控制器发送至少一个访问请求之后，用于向所述介质控制器发送查询请求，所述查询请求用于查询所述缓存器中是否有数据写入；
    所述介质控制器，还用于根据所述查询请求，确定所述缓存器中是否有数据写入，在所述缓存器中已有数据写入的情况下，还用于向所述内存控制器发送所述缓存器中已写入的数据。
  2. 根据权利要求1所述的系统，其特征在于，所述介质控制器确定所述缓存器中已有数据写入之后，还用于：
    向所述内存控制器发送应答消息，所述应答消息用于指示所述缓存器的数据写入状态为已有数据写入；
    则，所述内存控制器，还用于根据所述应答消息，向所述介质控制器发送读缓存器请求，所述读缓存器请求用于读取所述缓存器中已写入的数据；
    所述介质控制器，还用于接收所述内存控制器发送的所述读缓存器请求，根据所述读缓存器请求触发所述向所述内存控制器发送所述缓存器中已写入的数据的操作。
  3. 根据权利要求1或2所述的系统，其特征在于，所述内存控制器具体用于：
    按照预设的查询周期向所述介质控制器发送所述查询请求。
  4. 根据权利要求3所述的系统，其特征在于，所述内存控制器发送的多个访问请求包含至少两种优先级，所述内存设备包含至少两个缓存器，每个缓存器对应一种优先级；
    所述预设的查询周期根据所述访问请求的优先级确定，不同优先级的访问请求对应不同的查询周期。
  5. 根据权利要求1-4任一项所述的系统，其特征在于，所述内存控制器向所述介质控制器发送的所述查询请求中还携带缓存器的指示信息，所述缓存器的指示信息用于指示所述查询请求所查询的缓存器。
  6. 根据权利要求1或2所述的系统，其特征在于，所述内存控制器向所述介质控制器发送查询请求之前，还用于确定所述内存控制器与所述介质控制器之间的互联通道处于空闲状态。
  7. 根据权利要求1-6任一项所述的系统，其特征在于，所述内存设备还包含状态寄存器，所述状态寄存器用于记录所述缓存器的数据写入状态；
    所述介质控制器具体用于：读取所述状态寄存器记录的所述缓存器的数据写入状态，并根据所述缓存器的数据写入状态，确定所述缓存器中是否有数据写入。
  8. 根据权利要求1-7任一项所述的系统，其特征在于，所述介质控制器还用于在向所述内存控制器发送所述缓存器中写入的数据时，向所述内存控制器发送标识信息，所述标识信息用于指示所述发送的数据对应的访问请求。
  9. 一种内存设备的访问方法，其特征在于，所述内存设备包含介质控制器、存储 器和缓存器，所述介质控制器用于接收内存控制器的多个访问请求，以及将所述每个访问请求所请求的数据从所述存储器中读出并写入所述缓存器，所述方法包括：
    所述内存控制器向所述介质控制器发送至少一个访问请求；
    所述内存控制器向所述介质控制器发送查询请求，所述查询请求用于查询所述缓存器中是否有数据写入；
    所述内存控制器接收所述介质控制器发送的所述缓存器中已写入的数据。
  10. 根据权利要求9所述的方法，其特征在于，所述内存控制器向所述介质控制器发送查询请求之后，所述方法还包括：
    所述内存控制器接收来自所述介质控制器的应答消息，所述应答消息用于指示所述缓存器的数据写入状态为已有数据写入；
    所述内存控制器根据所述应答消息，向所述介质控制器发送读缓存器请求，所述读缓存器请求用于读取所述缓存器中已写入的数据。
  11. 根据权利要求9或10所述的方法，其特征在于，所述内存控制器向所述介质控制器发送查询请求包括：
    所述内存控制器按照预设的查询周期向所述介质控制器发送所述查询请求。
  12. 根据权利要求11所述的方法，其特征在于，所述内存控制器发送的多个访问请求包含至少两种优先级，所述内存设备包含至少两个缓存器，每个缓存器对应一种优先级；
    所述预设的查询周期根据所述访问请求的优先级确定，不同优先级的访问请求对应不同的查询周期。
  13. 根据权利要求9-12任一项所述的方法，其特征在于，所述内存控制器向所述介质控制器发送的所述查询请求中还携带缓存器的指示信息，所述缓存器的指示信息用于指示所述查询请求所查询的缓存器。
  14. 根据权利要求9或10所述的方法，其特征在于，所述内存控制器向所述介质控制器发送查询请求之前，所述方法还包括：所述内存控制器确定所述内存控制器与所述介质控制器之间的互联通道处于空闲状态。
  15. 根据权利要求9-14任一项所述的方法，其特征在于，所述方法还包括：所述内存控制器接收介质控制器发送的标识信息，所述标识信息用于指示所述接收的数据对应的访问请求。
  16. 一种内存设备的访问方法，其特征在于，所述内存设备包含介质控制器、存储器和缓存器，所述介质控制器，用于接收所述内存控制器的多个访问请求，以及将每个访问请求所请求的数据从所述存储器中读出并写入所述缓存器，所述方法包括：
    所述介质控制器接收来自所述内存控制器的至少一个访问请求；
    所述介质控制器接收来自所述内存控制器的查询请求，所述查询请求用于查询所述缓存器中是否有数据写入；
    所述介质控制器根据所述查询请求，确定所述缓存器中是否有数据写入；在所述缓存器中已有数据写入的情况下，所述介质控制器向所述内存控制器发送所述缓存器中已写入的数据。
  17. 根据权利要求16所述的方法，其特征在于，所述介质控制器确定所述缓存器中已有数据写入之后，所述方法还包括：
    所述介质控制器向所述内存控制器发送应答消息，所述应答消息用于指示所述缓存器的数据写入状态为已有数据写入；
    所述介质控制器接收来自所述内存控制器的读缓存器请求，所述读缓存器请求用于读取所述缓存器中已写入的数据。
  18. 根据权利要求16或17所述的方法，其特征在于，所述内存设备还包含状态寄存器，所述状态寄存器用于记录所述缓存器的数据写入状态；
    所述介质控制器确定所述缓存器是否有数据写入包括：所述介质控制器读取所述状态寄存器记录的所述缓存器的数据写入状态，并根据所述缓存器的数据写入状态，确定所述缓存器中是否有数据写入。
  19. 根据权利要求16-18任一项所述的方法，其特征在于，所述方法还包括：所述介质控制器向所述内存控制器发送标识信息，所述标识信息用于指示所述发送的数据对应的访问请求序。
  20. 一种内存设备的访问装置，其特征在于，所述内存设备包含介质控制器、存储器和缓存器，所述介质控制器用于接收所述装置的多个访问请求，以及将所述每个访问请求所请求的数据从所述存储器中读出并写入所述缓存器，所述装置包括：
    发送单元，用于向所述介质控制器发送至少一个访问请求；
    所述发送单元还用于向所述介质控制器发送查询请求，所述查询请求用于查询所述缓存器中是否有数据写入；
    接收单元，用于接收所述介质控制器发送的所述缓存器中已写入的数据。
  21. 根据权利要求20所述的装置，其特征在于，所述发送单元向所述介质控制器发送查询请求之后，所述接收单元还用于接收来自所述介质控制器的应答消息，所述应答消息用于指示所述缓存器的数据写入状态为已有数据写入；
    所述发送单元还用于根据所述应答消息，向所述介质控制器发送读缓存器请求，所述读缓存器请求用于读取所述缓存器中已写入的数据。
  22. 根据权利要求20或21所述的装置，其特征在于，当向所述介质控制器发送查询请求时，所述发送单元具体用于按照预设的查询周期向所述介质控制器发送所述查询请求。
  23. 根据权利要求22所述的装置，其特征在于，所述装置的多个访问请求包含至少两种优先级，所述内存设备包含至少两个缓存器，每个缓存器对应一种优先级；
    所述预设的查询周期根据所述访问请求的优先级确定，不同优先级的访问请求对应不同的查询周期。
  24. 根据权利要求20-23任一项所述的装置，其特征在于，所述查询请求中还携带缓存器的指示信息，所述缓存器的指示信息用于指示所述查询请求所查询的缓存器。
  25. 根据权利要求20或22所述的装置，其特征在于，所述装置还包含确定单元，所述发送单元向所述介质控制器发送查询请求之前，所述确定单元用于确定所述内存控制器与所述介质控制器之间的互联通道处于空闲状态。
  26. 根据权利要求20-25任一项所述的装置，其特征在于，所述接收单元还用于接收介质控制器发送的标识信息，所述标识信息用于指示所述接收单元接收的数据对应的访问请求。
  27. 一种内存设备的访问装置，其特征在于，所述内存设备包含所述装置、存储器 和缓存器，所述装置用于接收所述内存控制器的多个访问请求，以及将每个访问请求所请求的数据从所述存储器中读出并写入所述缓存器，所述装置包括：
    接收单元，用于接收来自所述内存控制器的至少一个访问请求；
    所述接收单元还用于接收来自所述内存控制器的查询请求，所述查询请求用于查询所述缓存器中是否有数据写入；
    确定单元，用于根据所述查询请求，确定所述缓存器中是否有数据写入；
    发送单元，在所述确定单元确定所述缓存器中已有数据写入的情况下，所述发送单元用于向所述内存控制器发送所述缓存器中已写入的数据。
  28. 根据权利要求27所述的装置，其特征在于，所述确定单元确定所述缓存器中已有数据写入之后，
    所述发送单元还用于向所述内存控制器发送应答消息，所述应答消息用于指示所述缓存器的数据写入状态为已有数据写入；
    所述接收单元还用于接收来自所述内存控制器的读缓存器请求，所述读缓存器请求用于读取所述缓存器中已写入的数据。
  29. 根据权利要求27或28所述的装置，其特征在于，所述内存设备还包含状态寄存器，所述状态寄存器用于记录所述缓存器的数据写入状态；
    所述确定单元具体用于读取所述状态寄存器记录的所述缓存器的数据写入状态，并根据所述缓存器的数据写入状态，确定所述缓存器中是否有数据写入。
  30. 根据权利要求27-29任一项所述的装置，其特征在于，所述发送单元还用于向所述内存控制器发送标识信息，所述标识信息用于指示所述发送单元发送的数据对应的访问请求。
  31. 一种内存设备，所述内存设备包含存储器、缓存器和权利要求27-30任一项所述的装置。
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