WO2023125332A1 - 数据传输电路、方法和芯片 - Google Patents

数据传输电路、方法和芯片 Download PDF

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Publication number
WO2023125332A1
WO2023125332A1 PCT/CN2022/141656 CN2022141656W WO2023125332A1 WO 2023125332 A1 WO2023125332 A1 WO 2023125332A1 CN 2022141656 W CN2022141656 W CN 2022141656W WO 2023125332 A1 WO2023125332 A1 WO 2023125332A1
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WIPO (PCT)
Prior art keywords
data
clock
module
data transmission
clock information
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PCT/CN2022/141656
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English (en)
French (fr)
Inventor
王鹏
沈桢
葛雄强
张国明
李峰
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苏州兆芯半导体科技有限公司
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Publication of WO2023125332A1 publication Critical patent/WO2023125332A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/16—Circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements

Definitions

  • the present application relates to communication technology, in particular to a data transmission circuit, method and chip.
  • Clock data is the basis of communication between chips.
  • the existing radio frequency chip and baseband chip communicate, usually the chips of both sides of the communication multiplex a phase-locked loop, and the clock data is transmitted between the chips by connecting an additional clock line to realize Both clocks are synchronized.
  • the present application provides a data transmission circuit, method and chip, which can reduce the difficulty of board placement and power consumption.
  • the present application provides a data transmission circuit, including: a first data receiving module and a clock data providing module, the first data receiving module includes a clock data recovery module, and the clock data providing module and the clock data recovery module are connected; the first The data receiving module is used to receive the first data sent from the second data sending module in other data transmission circuits; the clock data recovery module is used to recover the first clock information corresponding to other data transmission circuits from the first data; The clock data providing module is configured to calibrate the second clock information corresponding to the clock data providing module according to the first clock information, so that the data transmission circuit analyzes the first data according to the calibrated second clock information.
  • the first data receiving module also includes an analog front end, a sampler, a serial-to-parallel conversion module, and a clock recovery unit; wherein,
  • the first end of the sampler is respectively connected to the serial-to-parallel conversion module and the clock recovery unit, and the second end of the sampler is connected to the analog front end; the analog front end is used to process the amplitude and quality of the first data to obtain the second data;
  • the sampler is used to sample the second data according to the second clock information to obtain a sampling result;
  • the serial-to-parallel conversion module is used to convert the sampling result from a serial format to a parallel format to obtain a third data
  • it also includes a first data sending module, the first data sending module is connected to the clock data providing module, and the first data sending module is used to carry the third clock information provided by the clock data providing module in the third data and send it to The second data receiving module in other data transmission circuits.
  • the first data sending module includes a parallel-to-serial conversion module and a driver connected to each other; the parallel-to-serial conversion module is used to convert the received fourth data from a parallel format to a serial format to obtain fifth data, and Sending the fifth data to the driver; the driver is used to drive the fifth data, so that the first data sending module sends the fifth data to the second data receiving module in other data transmission circuits.
  • the controller also includes a controller and a digital physical layer PHYD; the first end of the PHYD is connected to the controller through a high-speed serial computer expansion bus standard PCIe physical layer interface PIPE, and the second end of the PHYD is connected to the serial-to-parallel conversion module; the PHYD , used to decode the third data to obtain the sixth data, and send the sixth data to the controller; the controller is used to process the sixth data according to the preset first protocol; the controller also uses Generate the seventh data according to the preset second protocol, and send the seventh data to the PHYD; the PHYD is also used to encode the seventh data to obtain the fourth data, and send the fourth data to the parallel-serial conversion module .
  • the present application provides a data transmission method applied to the data transmission circuit provided in the first aspect, the method includes: receiving first data sent by other data transmission circuits; recovering other data from the first data transmitting the first clock information corresponding to the circuit; according to the first clock information, calibrating the second clock information corresponding to the clock data providing module in the data transmission circuit, and analyzing the first data according to the calibrated second clock information.
  • recovering the first clock information corresponding to other data transmission circuits from the first data includes: recovering from the first data the first clock information corresponding to other data transmission circuits through a clock data recovery module in the data transmission circuit. clock information.
  • the method further includes: acquiring second clock information; carrying the second clock information in the third data and sending it to a second data receiving module in other data transmission circuits.
  • the first data includes a first field and a second field, the first field is used to indicate that the first data includes the first clock information; the second field is used to indicate the first clock information.
  • the present application provides a data transmission system, including the data transmission circuit provided in the first aspect and other data transmission circuits.
  • the present application provides a chip, including the data transmission circuit provided in the first aspect.
  • the data transmission circuit, method and chip provided by this application include: a first data receiving module and a clock data providing module, the first data receiving module includes a clock data recovery module, and the clock data providing module and the clock data recovery module are connected; the first The data receiving module is used to receive the first data sent from the second data sending module in other data transmission circuits; the clock data recovery module is used to recover the first clock information corresponding to other data transmission circuits from the first data; The clock data providing module is used to calibrate the second clock information corresponding to the clock data providing module according to the first clock information, so that the data transmission circuit can analyze the first data according to the calibrated second clock information.
  • the receiving end can recover the clock of the sending end from the received data, so that the clock of the receiving end and the sending end are consistent, and there is no need to connect the clock line between the receiving end and the sending end, which reduces the cost of the board. It improves the anti-interference ability of the clock data; on the other hand, the data transmission circuit can be tested through the excitation source without building a complete communication architecture between the RF chip and the baseband chip, which reduces the difficulty of testing and improves the reliability of the data transmission circuit. Testability.
  • FIG. 1 is a schematic structural diagram of a data transmission system provided by the present application.
  • FIG. 2 is a schematic diagram of a data transmission circuit provided by the present application.
  • FIG. 3 is a schematic diagram of another data transmission circuit provided by the present application.
  • FIG. 4 is a schematic diagram of another data transmission circuit provided by the present application.
  • FIG. 5 is a sequence diagram of a PIPE interface provided by the present application.
  • Figure 6 is a 128B130B encoding format provided by the present application.
  • Fig. 7 is a kind of data frame format that the present application provides
  • FIG. 8 is a schematic flowchart of a data transmission method provided by the present application.
  • FIG. 9 is a schematic flowchart of another data transmission method provided by the present application.
  • FIG. 10 is a schematic structural diagram of a data transmission system provided by the present application.
  • FIG. 1 is a schematic structural diagram of a data transmission system provided by the present application.
  • PLL Phase Locked Loop
  • additional clock lines need to be connected between chips to transmit clocks, and clock data requires high anti-interference ability, so higher requirements are put forward for board placement and clock sources.
  • transmitting clock data between chips will also increase chip power consumption.
  • a chip without a phase-locked loop needs to be tested separately, all the test work cannot be completed normally due to the lack of common clock supply.
  • the present invention provides a kind of data transmission circuit on the basis of combining conventional circuit, and it is provided with phase-locked loop in chip and clock recovery module (Clock Data Recovery, CDR) is provided in its receiving module.
  • CDR Phase Data Recovery
  • the receiving module recovers the clock data corresponding to the sending end from the received data through the clock recovery module, and calibrates the clock data generated by its PLL according to the recovered clock data, so that its clock is consistent with the sending end Consistent, so that the received data can be collected and analyzed;
  • the clock data generated by its PLL is added to the data packet and sent to the receiving end, so that it can be consistent with the sending end clock through clock recovery.
  • the clock data can be generated inside the data transmission circuit.
  • the data transmission circuit can be tested through the excitation source, and there is no need to build a complete communication architecture between the RF chip and the baseband chip, which reduces the difficulty of testing and improves data quality. Testability of transmission circuits.
  • Fig. 2 is a schematic diagram of a data transmission circuit provided by the present application. As shown in Fig. 2, the circuit includes:
  • the first data receiving module 21 and the clock data providing module 22 are identical to each other.
  • the first data receiving module 21 includes a clock data recovery module 211 .
  • the clock data supply module 22 is connected to the clock data recovery module 211 .
  • the clock data recovery module 211 is a CDR module.
  • the clock data providing module 22 is a PLL.
  • the first data receiving module 21 is configured to receive the first data sent from the second data sending module in other data transmission circuits.
  • the second data sending module may be a data sending module in a baseband chip; when the first data receiving module is a data receiving module in a baseband chip, the second The second data sending module may be a data sending module in the radio frequency chip.
  • the clock data recovery module 211 is configured to recover first clock information corresponding to other data transmission circuits from the first data.
  • the clock data providing module 22 is configured to calibrate the second clock information corresponding to the clock data providing module 22 according to the first clock information, so that the data transmission circuit analyzes the first data according to the calibrated second clock information.
  • the data transmission circuit provided by this application receives the first data sent from the second data transmission module in other data transmission circuits through the first data receiving module; recovers other data transmission circuits from the first data through the clock data recovery module Corresponding first clock information; and through the clock data providing module, calibrate the second clock information corresponding to the clock data providing module according to the first clock information, so that the data transmission circuit analyzes the first data according to the calibrated second clock information , on the one hand, it realizes that during the communication process, the receiving end can recover the clock of the sending end from the received data, so that the clocks of the receiving end and the sending end are consistent, and there is no need to connect the clock between the receiving end and the sending end line, which reduces the difficulty of board placement, improves the anti-interference ability of clock data, and reduces power consumption; on the other hand, the data transmission circuit can be tested through the excitation source, without the need to build a complete communication architecture between the RF chip and the baseband chip. The test difficulty is reduced, and the testability of the data transmission circuit is
  • FIG. 3 is a schematic diagram of another data transmission circuit provided by the present application. As shown in FIG. 3, the circuit is based on the circuit shown in the above-mentioned implementation, and the first data receiving module 21 also includes an analog front end 212, a sampler 213, and a serial-to-parallel conversion module 214.
  • the first end of the sampler 213 is respectively connected to the clock data recovery module 211 and the serial-to-parallel conversion module 214 ; the second end of the sampler 213 is connected to the analog front end 212 .
  • the analog front end 212 is configured to process the amplitude and quality of the first data to obtain the second data.
  • the analog front end optimizes the amplitude and quality of the first data by adjusting the signal amplitude and signal quality of the first data.
  • the sampler 213 is configured to sample the second data according to the second clock information to obtain a sampling result.
  • a serial-to-parallel conversion module 214 configured to convert the sampling result from a serial format to a parallel format to obtain third data.
  • the clock data recovery module can analyze the data related to the clock from the received first data, thereby recovering the first clock corresponding to other data transmission circuits information; further, enabling the receiving end to sample the converted parallel data through the recovered first clock data, so as to realize data transmission between the sending end and the receiving end.
  • FIG. 4 is a schematic diagram of another data transmission circuit provided by the present application. As shown in FIG. 4 , this circuit is based on the circuit shown in the above implementation, and the data transmission circuit also includes a first data sending module 23 .
  • the first data sending module 23 is connected to the clock data providing module 22 .
  • the first data sending module 23 is configured to carry the third clock information provided by the clock data providing module 22 in the third data and send it to the second data receiving module in other data transmission circuits.
  • the first data sending module 23 includes a parallel-to-serial conversion module 231 and a driver 232 connected to each other.
  • the parallel-to-serial conversion module 231 is configured to convert the received fourth data from a parallel format into a serial format to obtain fifth data, and send the fifth data to the driver 232 .
  • the driver 232 is used to drive the fifth data, so that the first data sending module sends the fifth data to the second data receiving module in other data transmission circuits.
  • the data transmission circuit further includes a controller 24 and a digital physical layer PHYD25.
  • the first end of PHYD25 is connected with controller 24 by high-speed serial computer expansion bus standard (peripheral component interconnect express, PCIe) physical layer PIPE interface, and the second end of PHYD25 is respectively connected with the serial-to-parallel conversion module in the first data receiving module 21 214. Connect to the parallel-to-serial conversion module 231 in the first data sending module 23.
  • PCIe peripheral component interconnect express
  • FIG. 5 is a timing diagram of a PIPE interface provided by this application
  • FIG. 6 is a 128B130B encoding format provided by this application.
  • the PIPE interface may use a signal transmission mode of scramble+128B130B encoding. Therefore, by means of signal scramble, DC balance can be realized for a long time during high-speed data transmission.
  • 128B130B encoding every 128 bits of data is inserted into a 2-bit syncheader, and the syncheader is used to inform the receiving end whether it is data information or control information, which facilitates subsequent data analysis.
  • the bandwidth utilization rate of this encoding method can reach 98.46%, and it has a higher performance at the same rate. bandwidth.
  • FIG. 7 is a data frame format provided by the present application, and the digital frame format can be applied to a PIPE interface.
  • the data frame format includes a DIFF-Z field 71 , a DIFF-N field 72 , a DIFF-P field 73 , a training field 74 , a Sync field 75 and a data field 76 .
  • DIFF-Z represents the high-impedance state on the line 71; the high-speed data transmitted by the DIFF-N field 72 is all "0"; the high-speed data transmitted by the DIFF-P field 73 is all "1", and the length is 4 blocks;
  • the high-speed data transmitted by the Training field 74 is a 0101 sequence, which is used for clock data recovery at the receiving end, and has a length of 11 blocks;
  • the Sync field 75 transmits the Electrical Idle Exit Ordered Set (EIEOS), which is used for Block alignment , indicating the beginning of the data field 76, with a length of 1 block.
  • EIEOS Electrical Idle Exit Ordered Set
  • a block represents 8*16bit; the content transmitted in the data field is data, and its length is adjustable.
  • PHYD25 configured to decode the third data to obtain sixth data, and send the sixth data to the controller.
  • the PHYD is used for encoding and decoding parallel data, synchronizing data packets, and adjusting switching timing of analog circuits.
  • the PHYD25 is configured to process the parallel data sent by the serial-to-parallel conversion module 214 and send it to the controller 24 .
  • the controller 24 is configured to process the sixth data according to a preset first protocol.
  • the controller 24 is further configured to generate seventh data according to a preset second protocol, and send the seventh data to the PHYD.
  • the PHYD is further configured to encode the seventh data to obtain the fourth data, and send the fourth data to the parallel-to-serial conversion module 231 .
  • the third clock information provided by the clock data supply module is carried in the third data and sent to other data transmission circuits through the first data sending module
  • the second data receiving module enables it to recover the clock of the sending end according to the received data.
  • Fig. 8 is a schematic flow chart of a data transmission method provided by the present application, the method is applied to the data transmission circuit provided in any of the above embodiments, as shown in Fig. 8, the method includes:
  • the first clock information is recovered by analyzing relevant fields in the first data.
  • the second clock information corresponding to the clock data providing module in the data transmission circuit is calibrated, so that the clock data in the data transmission circuit is consistent with the first clock data, and then the data transmission
  • the circuit can sample and analyze the first data according to the calibrated second clock information.
  • the data transmission method provided by this application receives the first data sent by other data transmission circuits; recovers the first clock information corresponding to other data transmission circuits from the first data; and calibrates the clock information in the data transmission circuit according to the first clock information
  • the clock data provides the second clock information corresponding to the module, and analyzes the first data according to the calibrated second clock information.
  • the receiving end can recover the The clock at the sending end, so that the clock at the receiving end is consistent with the clock at the sending end.
  • the source tests the data transmission circuit without building a complete communication architecture between the RF chip and the baseband chip, which reduces the difficulty of testing and improves the testability of the data transmission circuit.
  • Fig. 9 is a schematic flowchart of another data transmission method provided by the present application, which is applied to the data transmission circuit provided in any of the above-mentioned embodiments.
  • Fig. 9 is based on the embodiment shown in Fig. Recovering the first clock information corresponding to other data transmission circuits from the data is further described in detail, as shown in Figure 9, the method includes:
  • S901. Receive first data sent by other data transmission circuits.
  • first data and the third data have a similar data frame structure, and the specific frame structure description will be further described in detail below, and will not be repeated here.
  • the third data includes the first field and the second field.
  • the first field includes first clock information corresponding to other data transmission circuits.
  • the second field identifies the beginning of the data field in the first data.
  • the first field is a training field, and this field is used to recover clock data of the sending end.
  • the high-speed data transmitted in this field may be a 0101 sequence, and the length of this field is 11 blocks, wherein one block includes 8*16 bits.
  • the second field is a Sync field
  • the Sync field is located between the training field and the data field, and this field is used to mark the end of the field related to clock recovery and the start of the data field.
  • the content of the Sync field transmission can be an Electrical Idle Exit Ordered Set (EIEOS) command, such as FF00, or other data that will not conflict with the data in data, and its specific length can be 1 block.
  • EIEOS Electrical Idle Exit Ordered Set
  • the first data may further include a third field and a fourth field, wherein the fourth field is located between the third field and the first field.
  • the fourth field is opposite to the data transmitted by the third field, and the transition of data between the third field and the fourth field represents the start of data transmission.
  • the third field is the first DIFF-N field, and the high-speed data transmitted in the first DIFF-N field is all 0s.
  • the fourth field is the DIFF-P field, and the high-speed data transmitted in this field is all 1s, and the length of the DIFF-P field is 4 blocks, and one block includes 8*16 bits.
  • the first data may further include a fifth field and a sixth field, wherein the fifth field is located between the second field and the sixth field.
  • the fifth field is a data field, including the target data to be transmitted.
  • the sixth field is used to indicate that the data transmission is stopped.
  • the fifth field is a data field, and its specific length can be configured according to actual conditions.
  • the sixth field is the second DIFF-N field.
  • the high-speed data transmitted in the second DIFF-N field is all 0, indicating the end of data transmission.
  • the specific length can be configured according to the actual situation.
  • it also includes: modifying the proportional relationship between the length of the second field and the length of the fifth field according to the amount of communication data.
  • the circuit when the amount of communication data is relatively large, it can be set to normal mode, and the circuit is in consistent transmission mode, that is, the data field is longer; when the amount of communication data is relatively small, it can be set to burst mode, that is, the data field is longer, Send data intermittently. Since the high-speed data transmitted in the DIFF-N field is all 0, the power consumption is low. Through the burst mode, not only real-time transmission is completed, no storage circuit is required, but also power consumption can be saved.
  • DIFF-P Before judging that valid high-speed data is to be transmitted, first transmit a section of DIFF-P, and the analog circuit at the receiving end will automatically determine that this signal is a start signal, thereby starting all related circuits to enter the normal working mode, and then sequentially sending Training
  • the frame is used for clock recovery, and EIEOS is sent to indicate the beginning of a packet of data data.
  • DIFF-N When a packet of data transmission ends and continues to transmit all 0 signals (DIFF-N), the receiving circuit will turn off the relevant high-speed circuit after detecting DIFF-N and enter a low power consumption state.
  • the ratio of Data and DIFF-N can vary with the size of the data packet to find the optimal duty cycle to achieve the transmission with the lowest power consumption.
  • a seventh field is further included, the seventh field is located before the third field, and the seventh field represents a high-impedance state.
  • the data transmission method provided by this application recovers the first clock information corresponding to other data transmission circuits from the first data through the clock data recovery module in the data transmission circuit.
  • the clock of the sending end can be quickly recovered from the received data, the stability of the clock data signal can be improved, and the efficiency of data collection can be improved.
  • FIG. 10 is a schematic structural diagram of a data transmission system provided by the present application. As shown in FIG. 10 , the system includes a first data transmission circuit 101 and a second data transmission circuit 102 .
  • the sending end of the first data transmission circuit 101 is connected with the receiving end of the second data transmission circuit 102; the receiving end of the first data transmission circuit 101 is connected with the sending end of the second data transmission circuit 102, thereby realizing the first data transmission circuit 101 and the data transmission between the second data transmission circuit 102.
  • the first data transmission circuit 101 is a radio frequency circuit, which includes a 4-way data sending module and a 3-way data receiving module.
  • the second data transmission circuit 102 is a baseband circuit, which includes a 3-way data sending module and a 4-way data receiving module.
  • Communication between the first data transmission circuit 101 and the second data transmission circuit 102 is based on a high-speed serial communication system (SerDes).
  • SerDes serial communication system
  • the data transmission system provided by the present application can execute the data transmission method provided by the above-mentioned embodiments, and its content and effects can be referred to the above-mentioned circuit embodiments, which will not be repeated here.
  • the present application also provides a chip, including the data transmission circuit provided by any one of the above embodiments.
  • the chip provided by this application includes any kind of data transmission circuit provided in the above-mentioned embodiments, and its content and effects can refer to the above-mentioned circuit embodiments, and will not be repeated here.
  • An embodiment of the present application provides a computer-readable storage medium, wherein computer-executable instructions are stored in the computer-readable storage medium, and the foregoing data transmission method is implemented when the computer-executable instructions are executed by a processor.
  • An embodiment of the present application further provides a computer program product, including a computer program, and when the computer program is executed by a processor, the above data transmission method can be implemented.
  • the aforementioned program can be stored in a readable memory.
  • the program executes the steps comprising the above-mentioned method embodiments; and the aforementioned memory (storage medium) includes: read-only memory (read-only memory, ROM), RAM, flash memory, hard disk, solid-state hard disk, magnetic tape (magnetic tape), floppy disk (floppy disk), optical disc (optical disc) and any combination thereof.
  • Embodiments of the present application are described with reference to flowcharts and/or block diagrams of methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each procedure and/or block in the flowchart and/or block diagram, and a combination of procedures and/or blocks in the flowchart and/or block diagram can be realized by computer program instructions. These computer program instructions may be provided to a general purpose computer, special purpose computer, embedded processor, or processing unit of other programmable data processing equipment to produce a machine such that the instructions executed by the processing unit of the computer or other programmable data processing equipment produce a An apparatus for realizing the functions specified in one or more procedures of the flowchart and/or one or more blocks of the block diagram.
  • These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing apparatus to operate in a specific manner, such that the instructions stored in the computer-readable memory produce an article of manufacture comprising instruction means, the instructions
  • the device realizes the function specified in one or more procedures of the flowchart and/or one or more blocks of the block diagram.
  • the term “include” and its variants may mean non-limiting inclusion; the term “or” and its variants may mean “and/or”.
  • the terms “first”, “second”, etc. in this application are used to distinguish similar objects, and not necessarily used to describe a specific order or sequence.
  • “plurality” means two or more.
  • “And/or” describes the association relationship of associated objects, indicating that there may be three types of relationships, for example, A and/or B may indicate: A exists alone, A and B exist simultaneously, and B exists independently.
  • the character “/” generally indicates that the contextual objects are an "or” relationship.

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Abstract

本申请提供的数据传输电路、方法和芯片，该电路包括：第一数据接收模块和时钟数据提供模块，第一数据接收模块中包括时钟数据恢复模块，时钟数据提供模块和时钟数据恢复模块连接；第一数据接收模块，用于接收从其他数据传输电路中的第二数据发送模块发送的第一数据；时钟数据恢复模块，用于从第一数据中恢复出其他数据传输电路对应的第一时钟信息；时钟数据提供模块，用于根据第一时钟信息校准时钟数据提供模块对应的第二时钟信息，以使数据传输电路根据校准后的第二时钟信息对第一数据进行解析。该电路能够降低了置板难度，提高了时钟数据的抗干扰能力，以及降低测试难度，提高了数据传输电路的可测性。

Description

数据传输电路、方法和芯片
本申请要求于2021年12月31日提交中国专利局、申请号为2021116753006、申请名称为“数据传输电路、方法和芯片”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及通信技术，尤其涉及一种数据传输电路、方法和芯片。
背景技术
随着集成电路技术的发展，芯片被广泛应用。时钟数据是芯片之间通信的基础，现有的射频芯片和基带芯片通信时，通常是通信双方的芯片复用一个锁相环，芯片之间通过连接额外的时钟线来传输时钟数据，以实现双方时钟同步。
然而，由于时钟数据需要较高的抗干扰能力，因此对于置板要求较高，置板难度较大，且芯片功耗较大。
发明内容
本申请提供一种数据传输电路、方法和芯片，能够降低置板难度和功耗。
一方面，本申请提供一种数据传输电路，包括：第一数据接收模块和时钟数据提供模块，第一数据接收模块中包括时钟数据恢复模块，时钟数据提供模块和时钟数据恢复模块连接；第一数据接收模块，用于接收从其他数据传输电路中的第二数据发送模块发送的第一数据；时钟数据恢复模块，用于从第一数据中恢复出其他数据传输电路对应的第一时钟信息；时钟数据提供模块，用于根据第一时钟信息校准时钟数据提供模块对应的第二时钟信息，以使数据传输电路根据校准后的第二时钟信息对第一数据进行解析。
可选地，第一数据接收模块中还包括模拟前端、采样器、串并转换模块和时钟恢复单元；其中，
采样器的第一端分别于串并转换模块和时钟恢复单元连接，采样器的第二端与模拟前端连接；模拟前端，用于对第一数据的幅度和质量进行处理，得到第二数据；采样器， 用于根据第二时钟信息，对第二数据进行采样，得到采样结果；串并转换模块，用于将采样结果由串行格式转换为并行格式，得到第三数据
可选地，还包括第一数据发送模块，第一数据发送模块和时钟数据提供模块连接，第一数据发送模块用于将时钟数据提供模块提供的第三时钟信息携带在第三数据中发送至其他数据传输电路中的第二数据接收模块。
可选地，第一数据发送模块包括互相连接的并串转换模块和驱动器；并串转换模块，用于将接收到的第四数据，由并行格式转换为串行格式，得到第五数据，并将第五数据发送至驱动器；驱动器，用于为第五数据提供驱动，以使第一数据发送模块将第五数据发送至其他数据传输电路中的第二数据接收模块。
可选地，还包括控制器和数字物理层PHYD；PHYD的第一端与控制器通过高速串行计算机扩展总线标准PCIe物理层接口PIPE连接，PHYD的第二端与串并转换模块连接；PHYD，用于对第三数据进行解码处理，得到第六数据，并将第六数据发送至控制器；控制器，用于根据预设的第一协议对第六数据进行处理；控制器，还用于根据预设的第二协议生成第七数据，并向PHYD发送第七数据；PHYD，还用于对第七数据进行编码处理，得到第四数据，并将第四数据发送至并串转换模块。
第二方面，本申请提供了一种数据传输方法，应用于如第一方面提供的数据传输电路，该方法包括：接收其他数据传输电路发送的第一数据；从第一数据中恢复出其他数据传输电路对应的第一时钟信息；根据第一时钟信息，校准数据传输电路中的时钟数据提供模块对应的第二时钟信息，并根据校准后的第二时钟信息对第一数据进行解析。
可选地，从第一数据中恢复出其他数据传输电路对应的第一时钟信息，包括：通过数据传输电路中的时钟数据恢复模块，从第一数据中恢复出其他数据传输电路对应的第一时钟信息。
可选地，方法还包括：获取第二时钟信息；将第二时钟信息携带在第三数据中发送给其他数据传输电路中的第二数据接收模块。
可选地，第一数据中包括第一字段和第二字段，第一字段用于指示第一数据中包括第一时钟信息；第二字段用于指示第一时钟信息。
第三方面，本申请提供了一种数据传输系统，包括如第一方面所提供的数据传输电路和其他数据传输电路。
第四方面，本申请提供了一种芯片，包括如第一方面所提供的数据传输电路。
本申请提供的数据传输电路、方法和芯片，包括：第一数据接收模块和时钟数据提供模块，第一数据接收模块中包括时钟数据恢复模块，时钟数据提供模块和时钟数据恢复模 块连接；第一数据接收模块，用于接收从其他数据传输电路中的第二数据发送模块发送的第一数据；时钟数据恢复模块，用于从第一数据中恢复出其他数据传输电路对应的第一时钟信息；时钟数据提供模块，用于根据第一时钟信息校准时钟数据提供模块对应的第二时钟信息，以使数据传输电路根据校准后的第二时钟信息对第一数据进行解析，其一方面，实现了在通讯过程中，接收端能够从所接收到的数据中，恢复出发送端的时钟，从而使接收端与发送端的时钟一致，接收端和发送端之间，不需要连接时钟线，降低了置板难度，提高了时钟数据的抗干扰能力；另一方面，可以通过激励源对数据传输电路进行测试，无需搭建完整的射频芯片与基带芯片的通信架构，降低了测试难度，提高了数据传输电路的可测性。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本申请的实施例，并与说明书一起用于解释本申请的原理。
图1为本申请提供的一种数据传输系统的结构示意图；
图2为本申请提供的一种数据传输电路的示意图；
图3为本申请提供的另一种数据传输电路的示意图；
图4为本申请提供的又一种数据传输电路的示意图；
图5为本申请提供的一种PIPE接口的时序图；
图6为本申请提供的一种128B130B编码格式；
图7为本申请提供的一种数据帧格式；
图8为本申请提供的一种数据传输方法的流程示意图；
图9为本申请提供的另一种数据传输方法的流程示意图；
图10为本申请提供的一种数据传输系统的结构示意图。
通过上述附图，已示出本申请明确的实施例，后文中将有更详细的描述。这些附图和文字描述并不是为了通过任何方式限制本申请构思的范围，而是通过参考特定实施例为本领域技术人员说明本申请的概念。
具体实施方式
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中 所描述的实施方式并不代表与本申请相一致的所有实施方式。相反，它们仅是与如所附权利要求书中所详述的、本申请的一些方面相一致的装置和方法的例子。
随着集成电路技术的发展，芯片被广泛应用。时钟数据是芯片之间通信的基础，图1为本申请提供的一种数据传输系统的结构示意图，如图1所示，现有技术中的射频芯片和基带芯片通信之间过程中，两方芯片复用一个锁相环(Phase Locked Loop，PLL)。因此，芯片之间需要连接额外的时钟线，来传输时钟，又有时钟数据需要较高的抗干扰能力，因此对于置板以及时钟源提出了较高的要求。而且，在芯片之间传输时钟数据，还会增加芯片功耗。此外，当需要对没有锁相环的芯片单独测试时，由于没有时钟共给，无法正常完成所有测试工作。
针对这些缺点，本发明在结合以往电路的基础上，提供了一种数据传输电路，其在芯片中设置锁相环以及在其接收模块中设置时钟恢复模块(Clock Data Recovery，CDR)。当接收数据时，接收模块通过时钟恢复模块从接收到的数据中恢复得到发送端对应的时钟数据，并根据恢复得到的时钟数据对其PLL产生的时钟数据进行校准，从而使其时钟与发送端一致，从而可以采集、解析所接收到的数据；当发送数据时，将其PLL产生的时钟数据添加到数据包中发送给接收端，以使其通过时钟恢复，与发送端时钟达成一致。基于此，芯片之间不需要连接时钟线，从而降低了置板难度，无需芯片之间发送时钟数据，还可以降低芯片功耗。此外，该数据传输电路内部可以产生时钟数据，对其进行测试时，可以通过激励源对数据传输电路进行测试，无需搭建完整的射频芯片与基带芯片的通信架构，降低了测试难度，提高了数据传输电路的可测性。
图2为本申请提供的一种数据传输电路的示意图，如图2所示，该电路包括：
第一数据接收模块21和时钟数据提供模块22。
第一数据接收模块21中包括时钟数据恢复模块211。
时钟数据提供模块22和时钟数据恢复模块211连接。
示例性的，时钟数据恢复模块211为CDR模块。时钟数据提供模块22为PLL。
第一数据接收模块21，用于接收从其他数据传输电路中的第二数据发送模块发送的第一数据。
示例性的，第一数据接收模块为射频芯片中的数据接收模块时，第二数据发送模块可以是基带芯片中的数据发送模块；第一数据接收模块为基带芯片中的数据接收模块时，第二数据发送模块可以是射频芯片中的数据发送模块。
时钟数据恢复模块211，用于从第一数据中恢复出其他数据传输电路对应的第一时钟信息。
时钟数据提供模块22，用于根据第一时钟信息校准时钟数据提供模块22对应的第二时钟信息，以使数据传输电路根据校准后的第二时钟信息对第一数据进行解析。
本申请提供的数据传输电路，通过第一数据接收模块接收从其他数据传输电路中的第二数据发送模块发送的第一数据；通过时钟数据恢复模块，从第一数据中恢复出其他数据传输电路对应的第一时钟信息；并通过时钟数据提供模块，根据第一时钟信息校准时钟数据提供模块对应的第二时钟信息，以使数据传输电路根据校准后的第二时钟信息对第一数据进行解析，一方面，实现了在通讯过程中，接收端能够从所接收到的数据中，恢复出发送端的时钟，从而使接收端与发送端的时钟一致，接收端和发送端之间，不需要连接时钟线，降低了置板难度，提高了时钟数据的抗干扰能力，降低了功耗；另一方面，可以通过激励源对数据传输电路进行测试，无需搭建完整的射频芯片与基带芯片的通信架构，降低了测试难度，提高了数据传输电路的可测性。
图3为本申请提供的另一种数据传输电路的示意图，如图3所示，该电路在上述实施所示电路的基础上，第一数据接收模块21中，还包括模拟前端212、采样器213、和串并转换模块214。
采样器213的第一端分别与时钟数据恢复模块211和串并转换模块214连接；采样器213的第二端与模拟前端212连接。
模拟前端212，用于对第一数据的幅度和质量进行处理，得到第二数据。
示例性的，模拟前端通过调整第一数据的信号幅度以及信号质量，对第一数据的幅度和质量进行优化处理。
采样器213，用于根据第二时钟信息，对第二数据进行采样，得到采样结果。
串并转换模块214，用于将采样结果由串行格式转换为并行格式，得到第三数据。
本申请提供的数据传输电路，在上述实施例的基础上，时钟数据恢复模块，能够从接收到的第一数据中解析出与时钟相关的数据，从而恢复出其他数据传输电路对应的第一时钟信息；进一步，使接收端能够通过恢复出的第一时钟数据，对转换得到的并行数据进行采样，实现发送端与接收端的数据传输。
图4为本申请提供的又一种数据传输电路的示意图，如图4所示，该电路在上述实施所示电路的基础上，该数据传输电路还包括第一数据发送模块23。
第一数据发送模块23和时钟数据提供模块22连接。
第一数据发送模块23，用于将时钟数据提供模块22提供的第三时钟信息携带在第三数据中发送至其他数据传输电路中的第二数据接收模块。
可选地，如图4所示，该第一数据发送模块23中，包括互相连接的并串转换模块231 和驱动器232。
并串转换模块231，用于将接收到的第四数据，由并行格式转换为串行格式，得到第五数据，并将第五数据发送至驱动器232。
驱动器232，用于为第五数据提供驱动，以使第一数据发送模块将第五数据发送至其他数据传输电路中的第二数据接收模块。
可选地，如图4所示，该数据传输电路，还包括控制器24和数字物理层PHYD25。
PHYD25的第一端与控制器24通过高速串行计算机扩展总线标准(peripheral component interconnect express，PCIe)物理层PIPE接口连接，PHYD25的第二端分别与第一数据接收模块21中的串并转换模块214、第一数据发送模块23中的并串转换模块231连接。
可选地，图5为本申请提供的一种PIPE接口的时序图，图6为本申请提供的一种128B130B编码格式，PIPE接口可使用了scramble+128B130B编码的信号传输方式。从而可以，借助信号的scramble可以实现高速数据传输过程中较长时间的直流平衡。128B130B编码，每128比特数据插入2比特的syncheader，利用syncheader告知接收端是数据信息还是控制信息，方便后续的数据解析，这种编码方式带宽利用率可以达到98.46％，相同速率下具有更高的带宽。
可选地，图7为本申请提供的一种数据帧格式，该数字帧格式可以应用于PIPE接口。如图7所示，该数据帧格式包括DIFF-Z字段71、DIFF-N字段72、DIFF-P字段73training字段74、Sync字段75和data字段76。
其中，DIFF-Z代表线71上为高阻态；DIFF-N字段72传输的高速数据为全“0”；DIFF-P字段73传输的高速数据为全“1”，长度为4个block；Training字段74传输的高速数据为0101序列，用于接收端的时钟数据恢复，长度为11个block；Sync字段75传输的是电气空闲退出命令集(Electrical Idle Exit Ordered Set，EIEOS)，用于Block alignment，表示data字段76的开始，长度为1个block。其中，一个block表示8*16bit；data字段传输的内容为数据，其长度可调。
PHYD25，用于对第三数据进行解码处理，得到第六数据，并将第六数据发送至控制器。
示例性的，PHYD用于对并行数据进行编、解码，数据包的同步，以及调节模拟电路的开关时序。
PHYD25，用于对串并转换模块214输送的并行数据进行处理后，发送至控制器24。
控制器24，用于根据预设的第一协议对第六数据进行处理。
控制器24，还用于根据预设的第二协议生成第七数据，并向PHYD发送第七数据。
PHYD，还用于对第七数据进行编码处理，得到第四数据，并将第四数据发送至并串转换模块231。
本申请提供的数据传输电路，在上述实施例的基础上，进一步的，通过第一数据发送模块将时钟数据提供模块提供的第三时钟信息携带在第三数据中发送至其他数据传输电路中的第二数据接收模块，使其能够根据接收到的数据，恢复出发送端的时钟。
图8为本申请提供的一种数据传输方法的流程示意图，该方法应用于上述任一实施例提供的数据传输电路，如图8所示，该方法包括：
S801、接收其他数据传输电路发送的第一数据。
S802、从第一数据中恢复出其他数据传输电路对应的第一时钟信息。
具体的，通过解析第一数据中的相关字段，恢复出第一时钟信息。
S803、根据第一时钟信息，校准数据传输电路中的时钟数据提供模块对应的第二时钟信息，并根据校准后的第二时钟信息对第一数据进行解析。
具体的，根据通过时钟恢复得到的第一时钟信息，校准数据传输电路中的时钟数据提供模块对应的第二时钟信息，使数据传输电路中的时钟数据与第一时钟数据一致，进而使数据传输电路能够根据校准后的第二时钟信息对第一数据进行采样、解析。
本申请提供的数据传输方法，通过接收其他数据传输电路发送的第一数据；从第一数据中恢复出其他数据传输电路对应的第一时钟信息；根据第一时钟信息，校准数据传输电路中的时钟数据提供模块对应的第二时钟信息，并根据校准后的第二时钟信息对第一数据进行解析，一方面，实现了在通讯过程中，接收端能够从所接收到的数据中，恢复出发送端的时钟，从而使接收端与发送端的时钟一致，接收端和发送端之间，不需要连接时钟线，降低了置板难度，提高了时钟数据的抗干扰能力；另一方面，可以通过激励源对数据传输电路进行测试，无需搭建完整的射频芯片与基带芯片的通信架构，降低了测试难度，提高了数据传输电路的可测性。
图9为本申请提供的另一种数据传输方法的流程示意图，该方法应用于上述任一实施例提供的数据传输电路，图9在图8所示实施例的基础上，对如何从第一数据中恢复出其他数据传输电路对应的第一时钟信息做了进一步的详细说明，如图9所示，该方法包括：
S901、接收其他数据传输电路发送的第一数据。
可以理解的是，第一数据和第三数据具有相似的数据帧结构，其具体帧结构描述，在下文做进一步详细说明，在此不做赘述。
S902、通过数据传输电路中的时钟数据恢复模块，从第一数据中恢复出其他数据传输 电路对应的第一时钟信息。
S903、根据第一时钟信息，校准数据传输电路中的时钟数据提供模块对应的第二时钟信息，并根据校准后的第二时钟信息对第一数据进行解析。
可选地，还包括：
S904、获取第二时钟信息。
S905、将第二时钟信息携带在第三数据中发送给其他数据传输电路中的第二数据接收模块。
可选地，第三数据中包括第一字段和第二字段。
第一字段，包括其他数据传输电路对应的第一时钟信息。
第二字段，标识第一数据中，数据字段的开始。
示例性的，第一字段为training字段，该字段用于恢复发送端的时钟数据。该字段传输的高速数据可以为0101序列，该字段的长度为11个block，其中，1个block包括8*16bit。
第二字段为Sync字段，Sync字段位于training字段和数据data字段之间，该字段用于标识与时钟恢复相关的字段的结束，以及data字段的开始。Sync字段传输对内容可以是电动空闲退出命令集(Electrical Idle Exit Ordered Set，EIEOS)命令，例如FF00，也可以是其他不会以data中的数据冲突的数据，其具体长度可以是1个block。
可选地，第一数据还可以包括第三字段和第四字段，其中第四字段位于第三字段和第一字段之间。
第四字段与第三字段所传输的数据相反，第三字段到第四字段之间数据的跳变，表征数据传输的起始。
示例性的，第三字段为第一DIFF-N字段，第一DIFF-N字段传输的高速数据为全0。第四字段为DIFF-P字段，该字段传输的高速数据为全1，DIFF-P字段的长度为4个block，其中，1个block包括8*16bit。
可选地，第一数据还可以包括第五字段和第六字段，其中第五字段位于第二字段和第六字段之间。
第五字段，为数据字段，包括传输的目标数据。
第六字段，用于表示数据传输停止。
示例性的，第五字段为data字段，其具体长度可根据实际进行配置。第六字段为第二DIFF-N字段，第二DIFF-N字段传输的高速数据为全0，表示数据传输结束，其具体长度可根据实际进行配置。
可选地，还包括：根据通信数据量，修改第二字段的长度与第五字段的长度的比例关 系。
示例性的，当通信数据量比较大时，可以设置成常规模式，电路处于一致传输模式，即data字段较长；当通信数据量比较小时，可以设置成突发模式，即data字段较长，间歇性发送数据，由于DIFF-N字段传输的高速数据为全0，功耗较低，通过突发模式，不仅完成实时传输，不需要任何的存储电路，还可以节省功耗。
示例性的，在判断要传输有效的高速数据之前，先传输一段DIFF-P，接收端模拟电路自动会判断出此信号是启动信号，从而启动所有相关电路进入正常工作模式，接下来依次发送Training帧用于时钟恢复，发送EIEOS用于表示一包数据data的开始。当一包数据传输结束后继续传输全0信号(DIFF-N)，接收端电路检测到DIFF-N后会关闭相关高速电路，进入低功耗状态。Data和DIFF-N的比例可以随着数据包的大小变化，找到最优占空比实现最低功耗的传输。
可选地，还包括第七字段，第七字段位于第三字段之前，第七字段表示高阻态。
本申请提供的数据传输方法，在上述方法实施例的基础上，通过数据传输电路中的时钟数据恢复模块，从第一数据中恢复出其他数据传输电路对应的第一时钟信息，能够根据接收端能够从所接收到的数据中，快速恢复出发送端的时钟，提高时钟数据信号的稳定性，提高数据采集效率。
本申请还提供了一种数据传输系统的结构示意图，该系统包括如上述任一实施例所提供的数据传输电路和其他数据传输电路。图10为本申请提供的一种数据传输系统的结构示意图，如图10所示，该系统包括第一数据传输电路101和第二数据传输电路102。
第一数据传输电路101的发送端与第二数据传输电路102的接收端连接；第一数据传输电路101的接收端与第二数据传输电路102的发送端连接，从而实现了第一数据传输电路101和第二数据传输电路102之间的数据传输。
示例性的，第一数据传输电路101，为射频电路，其包括4路数据发送模块和3路数据接收模块。
第二数据传输电路102，为基带电路，其包括3路数据发送模块和4路数据接收模块。
第一数据传输电路101和第二数据传输电路102之间基于高速串口通信系统(SerDes)进行通信。
本申请提供的数据传输系统能够执行上述实施例提供的数据传输方法，其内容和效果可参考上述电路实施例部分，对此不再赘述。
本申请还提供了一种芯片，包括如上述任一实施例所提供的数据传输电路。
本申请提供的芯片包括如上述实施例中提供的任意一种数据传输电路，其内容和效果 可参考上述电路实施例部分，对此不再赘述。
本申请实施例提供一种计算机可读存储介质，计算机可读存储介质中存储有计算机执行指令，当计算机执行指令被处理器执行时实现上述数据传输方法。
本申请实施例还提供一种计算机程序产品，包括计算机程序，该计算机程序被处理器执行时，可实现上述数据传输方法。
实现上述各方法实施例的全部或部分步骤可以通过程序指令相关的硬件来完成。前述的程序可以存储于一可读取存储器中。该程序在执行时，执行包括上述各方法实施例的步骤；而前述的存储器(存储介质)包括：只读存储器(read-only memory，ROM)、RAM、快闪存储器、硬盘、固态硬盘、磁带(magnetic tape)、软盘(floppy disk)、光盘(optical disc)及其任意组合。
本申请实施例是参照根据本申请实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理单元以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理单元执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
显然，本领域的技术人员可以对本申请实施例进行各种改动和变型而不脱离本申请的精神和范围。这样，倘若本申请实施例的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。
在本申请中，术语“包括”及其变形可以指非限制性的包括；术语“或”及其变形可以指“和/或”。本本申请中术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。本申请中，“多个”是指两个或两个以上。“和/或”，描 述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。字符“/”一般表示前后关联对象是一种“或”的关系。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本申请的其它实施方案。本申请旨在涵盖本申请的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本申请的一般性原理并包括本申请未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本申请的真正范围和精神由下面的权利要求书指出。
应当理解的是，本申请并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本申请的范围仅由所附的权利要求书来限制。

Claims (10)

  1. 一种数据传输电路，其特征在于，包括：第一数据接收模块和时钟数据提供模块，所述第一数据接收模块中包括时钟数据恢复模块，所述时钟数据提供模块和所述时钟数据恢复模块连接；
    所述第一数据接收模块，用于接收从其他数据传输电路中的第二数据发送模块发送的第一数据；
    所述时钟数据恢复模块，用于从所述第一数据中恢复所述其他数据传输电路对应的第一时钟信息；
    所述时钟数据提供模块，用于根据所述第一时钟信息校准所述时钟数据提供模块对应的第二时钟信息，以使所述数据传输电路根据校准后的第二时钟信息对所述第一数据进行解析。
  2. 根据权利要求1所述的电路，其特征在于，所述第一数据接收模块中还包括模拟前端、采样器、串并转换模块；其中，所述采样器的第一端分别于所述串并转换模块和所述时钟恢复单元连接，所述采样器的第二端与所述模拟前端连接；
    所述模拟前端，用于对所述第一数据的幅度和质量进行处理，得到第二数据；
    所述采样器，用于根据所述第二时钟信息，对所述第二数据进行采样，得到采样结果；
    所述串并转换模块，用于将所述采样结果由串行格式转换为并行格式，得到第三数据。
  3. 根据权利要求2所述的电路，其特征在于，还包括第一数据发送模块，所述第一数据发送模块和所述时钟数据提供模块连接；
    所述第一数据发送模块，用于将所述时钟数据提供模块提供的第三时钟信息携带在第三数据中发送至所述其他数据传输电路中的第二数据接收模块。
  4. 根据权利要求2或3所述的电路，其特征在于，所述第一数据发送模块，包括相互连接的并串转换模块和驱动器；
    所述并串转换模块，用于将接收到的第四数据，由并行格式转换为串行格式，得到第五数据，并将所述第五数据发送至所述驱动器；
    所述驱动器，用于为所述第五数据提供驱动，以使所述第一数据发送模块将所述第五数据发送至所述其他数据传输电路中的第二数据接收模块。
  5. 根据权利要求4所述的电路，其特征在于，还包括控制器和数字物理层PHYD；
    所述PHYD的第一端与所述控制器通过高速串行计算机扩展总线标准PCIe物理层接口PIPE连接，所述PHYD的第二端分别与所述串并转换模块、所述并串转换模块连接；
    所述PHYD，用于对所述第三数据进行解码处理，得到第六数据，并将所述第六数据发送至所述控制器；
    所述控制器，用于根据预设的第一协议对所述第六数据进行处理；
    所述控制器，还用于根据预设的第二协议生成第七数据，并向所述PHYD发送所述第七数据；
    所述PHYD，还用于对所述第七数据进行编码处理，得到所述第四数据，并将所述第四数据发送至所述并串转换模块。
  6. 一种数据传输方法，其特征在于，应用于数据传输电路，所述方法包括：
    接收其他数据传输电路发送的第一数据；
    从所述第一数据中恢复所述其他数据传输电路对应的第一时钟信息；
    根据所述第一时钟信息，校准所述数据传输电路中的时钟数据提供模块对应的第二时钟信息，并根据校准后的第二时钟信息对所述第一数据进行解析。
  7. 根据权利要求6所述的方法，其特征在于，所述从所述第一数据中恢复所述其他数据传输电路对应的第一时钟信息，包括：
    通过所述数据传输电路中的时钟数据恢复模块，从所述第一数据中恢复所述其他数据传输电路对应的第一时钟信息。
  8. 根据权利要求6或7所述的方法，其特征在于，所述方法还包括：
    获取所述第二时钟信息；
    将所述第二时钟信息携带在第三数据中发送给所述其他数据传输电路中的第二数据接收模块。
  9. 根据权利要求6或7所述的方法，其特征在于，所述第一数据中包括第一字段和第二字段，所述第一字段用于指示所述第一数据中包括第一时钟信息；所述第二字段用于指示所述第一时钟信息。
  10. 一种数据传输芯片，其特征在于，包括如权利要求1-5任一项所述的数据传输电路。
PCT/CN2022/141656 2021-12-31 2022-12-23 数据传输电路、方法和芯片 WO2023125332A1 (zh)

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101686120A (zh) * 2008-09-26 2010-03-31 大唐移动通信设备有限公司 一种实现时钟同步的装置及方法
CN107547188A (zh) * 2017-08-02 2018-01-05 北京东土军悦科技有限公司 一种时钟恢复方法及装置
WO2020151698A1 (zh) * 2019-01-22 2020-07-30 华为技术有限公司 驱动器和数据传输方法
CN113406993A (zh) * 2021-07-16 2021-09-17 盛立安元科技(杭州)股份有限公司 基于恢复时钟的fpga芯片时钟域同步方法及相关设备
CN113810319A (zh) * 2021-11-17 2021-12-17 伟恩测试技术(武汉)有限公司 时钟数据发送电路、接收电路、恢复电路和方法
CN114337708A (zh) * 2021-12-31 2022-04-12 苏州兆芯半导体科技有限公司 数据传输电路、方法和芯片

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7295644B1 (en) * 2003-07-14 2007-11-13 Marvell International Ltd. Apparatus for clock data recovery
CN103716060B (zh) * 2014-01-15 2016-05-25 英特格灵芯片(天津)有限公司 时钟数据恢复电路
KR102403623B1 (ko) * 2017-08-18 2022-05-30 삼성전자주식회사 클록 신호들 사이의 스큐를 조절하도록 구성되는 전자 회로

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101686120A (zh) * 2008-09-26 2010-03-31 大唐移动通信设备有限公司 一种实现时钟同步的装置及方法
CN107547188A (zh) * 2017-08-02 2018-01-05 北京东土军悦科技有限公司 一种时钟恢复方法及装置
WO2020151698A1 (zh) * 2019-01-22 2020-07-30 华为技术有限公司 驱动器和数据传输方法
CN113406993A (zh) * 2021-07-16 2021-09-17 盛立安元科技(杭州)股份有限公司 基于恢复时钟的fpga芯片时钟域同步方法及相关设备
CN113810319A (zh) * 2021-11-17 2021-12-17 伟恩测试技术(武汉)有限公司 时钟数据发送电路、接收电路、恢复电路和方法
CN114337708A (zh) * 2021-12-31 2022-04-12 苏州兆芯半导体科技有限公司 数据传输电路、方法和芯片

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