WO2011060669A1 - 一种串行和解串行的方法及装置 - Google Patents
一种串行和解串行的方法及装置 Download PDFInfo
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- WO2011060669A1 WO2011060669A1 PCT/CN2010/077346 CN2010077346W WO2011060669A1 WO 2011060669 A1 WO2011060669 A1 WO 2011060669A1 CN 2010077346 W CN2010077346 W CN 2010077346W WO 2011060669 A1 WO2011060669 A1 WO 2011060669A1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
- H04L25/40—Transmitting circuits; Receiving circuits
Definitions
- the present invention relates to serial communication technologies, and in particular, to a serial and deserialization method and apparatus. Background technique
- serial communication technology-serializer/deserializer (SERDES) technology is gradually replacing the traditional parallel interface technology, and has become popular. High-speed interface technology.
- SERDES technology is a time division multiplexing and point-to-point communication technology.
- multi-channel, ie multi-channel low-speed parallel signals are converted into high-speed serial signals according to a certain protocol or framing method, and passed through optical fiber or The other media sends out, and the receiving end converts the received high-speed serial signal into a low-speed parallel signal.
- the signal sent by the transmitting end carries a frame indication signal required for serial-to-parallel conversion, and is used for receiving, by the receiving end, a frame header of the serial signal, and the receiving end is configured according to a protocol or a framing method according to the transmitting end.
- the frame header of the serial signal is solved, and then the bit is decomposed according to the frame header, and the parallel signals corresponding to the respective channels are solved.
- This point-to-point serial communication technology makes full use of the high capacity of the current transmission medium and high processing speed of the chip, and thus is widely used in industries such as communication and industrial design.
- the N is the number of channels, N > 2, and is usually an even number; the N: 1 can be: 8: 1, or 10: 1, or 16: 1 for 8 channels, or 10 channels, or Inter-conversion of low-speed parallel signals and high-speed serial signals of 16 channels.
- the chip A chip with SERDES function produced by the manufacturer can only meet the serial-to-parallel conversion of a fixed-ratio data link, and does not support serial-to-parallel conversion of other ratio data links.
- a chip with a certain SERDES function is For serial-to-parallel conversion of 8:1 data link, if the user wants to change the 8-channel parallel signal to 10-channel parallel signal, he can only re-purchase the 10:1 SERDES function chip, the original 8:1 SERDES function. The chip can no longer be used. It can be seen that the existing SERDES function chip can be used in a flexible range, and the user's consumption cost is high.
- the main object of the present invention is to provide a serial and deserialization method and device, which can realize mutual conversion of parallel signals and serial signals of different channel numbers in a field programmable gate array (FPGA) module. Reduce the cost of users' consumption.
- FPGA field programmable gate array
- the present invention provides a serial and deserialization method, the method comprising:
- the frame format for encoding the serial data is set by using the number of channels N as a variable; the local receiving end locates the received serial data out of the frame header according to the set frame format, and converts the serial data into N-bit parallel data; Parsing the parallel data according to the set frame format to obtain the link state, and outputting N-bit parallel data;
- the local transmitting end encodes the local parallel data according to the set frame format, and outputs parallel data corresponding to the frame format according to the link state parsed by the local receiving end; converts the parallel data into serial data, and uses the multiplied high-speed clock Output serial data.
- the method further includes: extracting a clock in the serial data sent by the other party, and using the serial data as a sample clock for serial data to parallel data. Conversion.
- the method further includes: adjusting the local clock with reference to the other clock to ensure that the local clock is synchronized with the other clock.
- the local N-bit parallel data and the four-bit control domain data are converted into serial data, the clock is multiplied to N+4 times of the local parallel data clock, and the serial data corresponding to the high-speed clock is transmitted to the other party.
- the present invention also provides a serial and deserialization device, the device comprising: a setting module, a frame serial transfer module, a frame format decoding module, a frame format encoding module, a frame parallel-to-serial module, and a clock multiplying module; ,
- the setting module is configured to set a frame format for encoding serial data by using a channel number N as a variable;
- the frame serial transfer module is configured to locate the received serial data out of the frame header according to a frame format set by the setting module, and convert the serial data into N-bit parallel data and send the data to the frame format decoding module;
- the frame format decoding module is configured to parse the parallel data according to the frame format set by the setting module to obtain a link state, notify the frame format encoding module, and output N-bit parallel data;
- the frame format encoding module is configured to encode the local parallel data according to a frame format set by the setting module, output parallel data corresponding to the frame format according to the link state parsed by the frame format decoding module, and send the data to the frame and the serial-to-serial module;
- the frame parallel-to-serial module is configured to convert parallel data into serial data, and output serial data by using a multi-clocked high-speed clock;
- the clock multiplying module is configured to multiply the local clock into a high-speed clock and send it to the frame and to the serial module.
- the device further includes a clock recovery module, configured to extract a clock in the serial data sent by the other party, and send the signal to the frame serial transfer module;
- the frame serial transfer module is specifically configured to convert the serial data into N-bit parallel data according to the set frame format by using a clock in the serial data.
- the apparatus further includes a clock adjustment module, configured to adjust the local clock to synchronize with the counterpart clock with reference to the counterpart clock before outputting the N-bit parallel data by the frame format decoding module.
- the serial and deserialization method and apparatus set a frame format for encoding serial data with a channel number N as a variable; the local receiving end locates the received serial data according to the set frame format. Head, and serial data is converted into N-bit parallel data; the local receiving end parses the parallel data according to the set frame format to obtain the link state, and outputs N-bit parallel data; the local transmitting end presses the local parallel data according to the set frame format Encoding is performed, and parallel data corresponding to the frame format is output according to the link state parsed by the local receiving end; the local transmitting end converts the parallel data into serial data, and outputs the serial data by using the multiplied high-speed clock.
- the invention sets the channel number N as a variable for realizing the serial and de-serialization process, and can realize the mutual conversion between the parallel signal and the serial signal of different channel numbers, thereby saving the developer's research and development cost and further reducing the user. Cost of consumption.
- the present invention can monitor any data received when parsing the parallel data to obtain the link state, thereby achieving the effect of monitoring the link state between the peer and the local, and facilitating the maintenance of the link in time.
- 1 is a schematic diagram showing an implementation process of serial data to parallel data conversion in the serial and de-serial method of the present invention
- FIG. 2 is a schematic flow chart showing the process of converting parallel data to serial data in the serial and de-serial method of the present invention
- FIG. 3 is a schematic structural diagram of a device for serial and deserialization according to the present invention. detailed description
- the basic idea of the present invention is: setting a frame format for encoding serial data by using the number of channels N as a variable; the local receiving end positions the received serial data out of the frame header according to the set frame format, And converting the serial data into N-bit parallel data, parsing the parallel data according to the set frame format to obtain a link state, and outputting N-bit parallel data;
- the local transmitting end encodes the local parallel data according to the set frame format, and outputs parallel data corresponding to the frame format according to the link state parsed by the local receiving end; converts the parallel data into serial data, and uses the multiplied high-speed clock Output serial data.
- the N is the number of channels, N > 2;
- the frame format for encoding the serial data includes: a positioning frame, a data frame, and an error frame; correspondingly, the link state may be: a reset start , receiving a positioning frame, receiving a data frame, and receiving an error frame.
- FIG. 1 is a schematic flow chart showing the implementation of serial data to parallel data conversion in the serial and de-serial method of the present invention, such as As shown in Figure 1, the process includes the following steps:
- Step 101 Set a frame format for encoding the serial data by using the number of channels N as a variable.
- the FPGA module sets a frame format for encoding the serial data by using the channel number N as a variable, where the pair of serial data is
- the various frames are composed of a data field and a control domain, wherein the control domain, that is, the control signal is four bits, and the data field is N bits.
- Each frame contains N + 4 bits, so it can be calculated that the transmission rate of serial data is N + 4 times of parallel data.
- the positioning frame is as shown in Table 1:
- positioning frame A is a signal having the same frequency as the parallel data and having a duty ratio of 50%.
- frame B is the same frequency as the parallel data, and the duty ratio is not 50% but the high level is one bit higher than the low level.
- the '7' indicates that the bit is inverted, and the four data frames are used for alternate transmission of data, preventing the problem that the receiving end cannot recover the clock when the data is continuously 0 or consecutively 1.
- the "X" represents 0 or 1; the one to eight represent the types of error frames, that is, there are eight types.
- the transmitting end of the other party first transmits the serial data in the frame format as the positioning frame A, and the phase locked loop is in a stable state, and then transmits the serial data in the format of the positioning frame B, that is, when the local receiving end determines the frame header
- the pre-position transmission frame format is the serial data of the positioning frame A.
- the serial data of the frame format is the positioning frame B is sent to the other party to notify the other party that the process of the framing header has been completed, the phase locked loop After being stabilized again, the serial data of the frame format is transmitted.
- serial data of the frame format of the error frame may be transmitted due to the failure.
- Step 102 The local receiving end locates the received serial data out of the frame header according to the set frame format.
- the receiving end of the local FPGA module locates the received serial data according to the frame format that has been set, and the three frame formats set in step 101 can be seen, only the other party sends the positioning. At the time of the frame, it is possible to determine where the frame header is in the data stream. Because when the other party sends the positioning frame, there is only one falling edge and one rising edge in the data stream, and for the positioning frames of the two formats, the position of the rising edge is fixed in the second and third bits of the control field. In the present invention, the position of the rising edge is used for frame positioning, and the frame header is located at the position of the third bit after the rising edge. If the frame header is not located, the local receiver will continue to look for the rising edge of the serial data until the frame header is located.
- the present invention further comprises extracting a clock in the serial data sent by the other party as a sample clock of the serial data for converting the serial data to the parallel data.
- the clock is the clock of the other party.
- Step 103 The local receiving end converts the serial data into N-bit parallel data.
- the serially received serial data is converted into N-bit parallel data according to the set frame format by using the clock in the serial data, that is, the conversion Data consisting of N-bit parallel data and four-bit control domain data.
- the N: 1 data link string is first determined before establishing the link between the two parties.
- the specific value of N is converted, and then the conversion between the serial data and the parallel data is performed to establish a link between the two parties.
- Step 104 The local receiving end parses the parallel data according to the set frame format to obtain a link state, and notifies the local transmitting end, and then outputs N-bit parallel data.
- the receiving end of the local FPGA module parses the data composed of the converted N-bit parallel data and the four-bit control domain data to obtain the current link state and notify the local transmitting end, for example: if N-bit parallel data and The frame format corresponding to the data composed of the four-bit control domain data is a data frame, and the current link state is: receiving the data frame, and then outputting N-bit parallel data; if the data consisting of N-bit parallel data and four-bit control domain data If the corresponding frame format is a positioning frame, the current link state is: receiving the positioning frame, and then outputting N-bit parallel data; if the frame format corresponding to the data composed of the N-bit parallel data and the four-bit control domain data is an error frame, The current link state is: After receiving the error frame, the N-bit parallel data is output; before the link is established, the current link state is: After the reset starts, the local sender sends a positioning frame to the other party to start the link. In addition, when the local receiver receives the error frame
- the output parallel data is not all valid data.
- the output parallel data is valid data, and if the positioning frame is received, the data corresponding to the positioning frame does not include the data to be transmitted.
- the data information is therefore not valid data; if an error frame is received, the data information corresponding to the error frame is an error message, and the transmission is proved to be an error code, and thus is not valid data.
- the local clock needs to be adjusted with reference to the other clock to ensure that the local clock is synchronized with the other clock.
- the process if an error frame is received, the process returns to step 102 to re-establish the link between the local and the other party, and the effect of monitoring the link state is maintained, so that the link between the local and the other party can be maintained in time.
- Step 201 The local sending end encodes the local parallel data according to the set frame format. Specifically, the sending end of the local FPGA module analyzes the local N-bit parallel data and the four-bit control domain data according to the local receiving end. The three frame formats corresponding to the state are encoded.
- Step 202 Output parallel data of a corresponding frame format according to the link state obtained by the local receiving end.
- the transmitting end in the local FPGA module sends the parallel data in different frame formats according to the link state obtained by the local receiving end parsing the parallel data in step 104, if the current link state is the start of the reset or if the chain obtained by parsing the parallel data is obtained
- the parallel data of the positioning frame format is output; if the link state obtained by parsing the parallel data is the received data frame, the parallel data of the data frame format is output, so that the local and the other party establish two-way in both directions.
- the link between the people is the link state obtained by the local receiving end parsing the parallel data in step 104, if the current link state is the start of the reset or if the chain obtained by parsing the parallel data is obtained
- the parallel data of the positioning frame format is output; if the link state obtained by parsing the parallel data is the received data frame, the parallel data of the data frame format is output, so that the local and the other party establish two-way in both directions. The link between the people.
- the transmit frame format is parallel data of the positioning frame A; when the phase-locked loop of the receiving end is in a stable state and on the link
- the transmission frame format is parallel data of the positioning frame B; when the parsed link state is the received data frame, the parallel data of the frame format is transmitted.
- the serial and deserialized method of the present invention is mainly used for the link between the local and the other party.
- the establishment process therefore, the format of the data frame sent by the local transmitting end to the other party should correspond to the format of the data frame received by the local receiving end, so as to establish a link between the two parties.
- Step 203 The local transmitting end converts the parallel data into serial data, and outputs the serial data by using the multiplied high speed clock;
- the transmitting end of the local FPGA module converts the local N-bit parallel data and the four-bit control domain data into serial data, and multiplies the clock to a local parallel data clock N+4 times the high-speed clock, and then the high speed
- the serial data corresponding to the clock is transmitted to the other party.
- 3 is a schematic structural diagram of a device for serial and deserialization according to the present invention. As shown in FIG.
- the device includes: a setting module, a frame serial conversion module, a frame format decoding module, a frame format encoding module, a frame and a serial-to-serial module, and The clock multiplying module, each of the above modules is integrated in a field programmable gate array (FPGA) module except the clock multiplying module, wherein the frame serial transfer module and the frame format decoding module are located at the receiving end, and the frame format encoding a module, a frame-and-serial module, and a clock multiplier module are located at the transmitting end;
- FPGA field programmable gate array
- the setting module is configured to set a frame format for encoding serial data by using a channel number N as a variable;
- the frame serial transfer module is configured to locate the received serial data out of the frame header according to a frame format set by the setting module, and convert the serial data into N-bit parallel data and send the data to the frame format decoding module;
- the frame format decoding module is configured to parse the parallel data according to the frame format set by the setting module to obtain a link state, notify the frame format encoding module, and output N-bit parallel data;
- the frame format encoding module is configured to encode the local parallel data according to a frame format set by the setting module, output parallel data corresponding to the frame format according to the link state parsed by the frame format decoding module, and send the data to the frame and the serial-to-serial module;
- the frame parallel-to-serial module is configured to convert parallel data into serial data, and output serial data by using a multi-clocked high-speed clock;
- the clock multiplying module is configured to multiply the local clock into a high-speed clock and send it to the frame and to the serial module.
- the device further includes a clock recovery module, configured to extract a clock in the serial data sent by the other party, and send the signal to the frame serial transfer module; correspondingly, the frame serial transfer module is specifically used in the serial data.
- the clock converts the serial data into N-bit parallel data according to the set frame format.
- the apparatus further includes a clock adjustment module for outputting N-bit parallel in the frame format decoding module Before the data, the local clock is adjusted to synchronize with the other party's clock with reference to the other party's clock.
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Description
一种串行和解串行的方法 ^置 技术领域
本发明涉及串行通信技术, 尤其涉及一种串行和解串行的方法及装置。 背景技术
随着通信技术的发展, 人们对信息流量的需求不断增长, 而传统的并 行接口技术则成为进一步提高数据传输速率的瓶颈。 随着芯片处理速度的 提高和高速光纤通信技术的发展及广泛运用, 串行通信技术——串行器 /解 串行器( SERDES )技术正逐步取代传统的并行接口技术, 并成为目前流行 的高速接口技术。
SERDES 技术是一种时分多路复用、 及点对点的通信技术, 在发送端 将多路、 即多通道的低速并行信号按一定的协议或者成帧方法转换成高速 串行信号, 并经过光纤或其它媒体发送出去, 接收端把接收到的高速串行 信号转换成低速并行信号。 其中, 所述发送端发送的信号中携带串并转换 中所需的帧指示信号, 用于接收端解出串行信号的帧头, 所述接收端根据 发送端所依据的协议或者成帧方法首先解出串行信号的帧头, 然后根据帧 头按比特进行分解, 解出对应各个通道的并行信号。 这种点对点的串行通 信技术充分利用了目前传输媒体的高容量及芯片处理速度高等特点, 因而, 广泛应用在通信和工业设计等行业中。
目前, 很多芯片制造商已研制出多种实现 SERDES功能的芯片, 用于 N: 1比值不同的数据链路的串并转换, 即: 用于通道数不同的低速并行信 号与高速串行信号的相互转换。 其中, 所述 N为通道数, N > 2, 通常为偶 数; 所述 N: 1可为: 8 : 1、 或 10: 1、 或 16: 1等, 用于 8通道、 或 10 通道、 或 16通道等的低速并行信号与高速串行信号的相互转换。 但是芯片
制造商所生产的具备 SERDES功能的某一芯片只能满足某一固定比值的数 据链路的串并转换, 不支持其它比值的数据链路的串并转换, 例如, 某一 SERDES功能的芯片被用于 8: 1的数据链路的串并转换, 若用户想将 8通 道并行信号改为 10通道并行信号,则只能重新购买 10: 1的 SERDES功能 的芯片, 原 8 : 1 的 SERDES 功能的芯片则无法再被利用, 可见, 现有 SERDES功能的芯片可适用范围不够灵活, 用户的消费成本艮高。 发明内容
有鉴于此, 本发明的主要目的在于提供一种串行和解串行的方法及装 置, 可在现场可编程门阵列 (FPGA )模块中实现不同通道数的并行信号与 串行信号的相互转换, 降低用户的消费成本。
为达到上述目的, 本发明的技术方案是这样实现的:
本发明提供了一种串行和解串行的方法, 该方法包括:
以通道数 N为变量设置对串行数据进行编码的帧格式; 本地接收端根 据已设置的帧格式将接收到的串行数据定位出帧头,并将串行数据转换成 N 位并行数据; 根据已设置的帧格式解析并行数据得到链路状态, 并输出 N 位并行数据;
本地发送端将本地并行数据按设置的帧格式进行编码, 根据本地接收 端解析所得的链路状态输出对应帧格式的并行数据; 将并行数据转换成串 行数据, 并利用倍频后的高速时钟输出串行数据。
其中, 所述将接收到的串行数据定位出帧头之前, 进一步包括: 提取 对方所发的串行数据中的时钟, 作为串行数据的釆样时钟, 用于串行数据 向并行数据的转换。
其中, 所述输出 N位并行数据之前, 进一步包括: 参照对方时钟对本 地时钟进行调节, 保证本地时钟与对方时钟同步。
其中, 所述将并行数据转换成串行数据, 并利用倍频后的高速时钟输
出串行数据, 具体为:
将本地 N位并行数据和四位控制域数据转换成串行数据, 将时钟倍频 为本地并行数据时钟的 N+4倍, 并将所述高速时钟对应的串行数据传输给 对方。
本发明还提供了一种串行和解串行的装置, 该装置包括: 设置模块、 帧串转并模块、 帧格式解码模块、 帧格式编码模块、 帧并转串模块和时钟 倍频模块; 其中,
所述设置模块, 用于以通道数 N为变量设置对串行数据进行编码的帧 格式;
所述帧串转并模块, 用于根据设置模块设置的帧格式将接收到的串行 数据定位出帧头, 并将串行数据转换成 N位并行数据并发送到帧格式解码 模块;
所述帧格式解码模块, 用于根据设置模块设置的帧格式解析并行数据 得到链路状态并通知帧格式编码模块, 并输出 N位并行数据;
所述帧格式编码模块, 用于将本地并行数据按设置模块设置的帧格式 进行编码, 根据帧格式解码模块解析所得的链路状态输出对应帧格式的并 行数据并发送到帧并转串模块;
所述帧并转串模块, 用于将并行数据转换成串行数据, 并用倍频后的 高速时钟输出串行数据;
所述时钟倍频模块, 用于将本地时钟倍频为高速时钟, 并发送到帧并 转串模块。
其中, 该装置进一步包括时钟恢复模块, 用于提取对方所发的串行数 据中的时钟, 并发送到帧串转并模块;
相应的, 所述帧串转并模块, 具体用于利用串行数据中的时钟, 根据 已设置的帧格式将串行数据转换成 N位并行数据。
该装置进一步包括时钟调节模块, 用于帧格式解码模块输出 N位并行 数据之前, 参照对方时钟调节本地时钟与对方时钟同步。
本发明提供的串行和解串行的方法及装置, 以通道数 N为变量设置对 串行数据进行编码的帧格式; 本地接收端根据已设置的帧格式将接收到的 串行数据定位出帧头, 并将串行数据转换成 N位并行数据; 本地接收端根 据已设置的帧格式解析并行数据得到链路状态, 并输出 N位并行数据; 本 地发送端将本地并行数据按设置的帧格式进行编码, 根据本地接收端解析 所得的链路状态输出对应帧格式的并行数据; 本地发送端将并行数据转换 成串行数据, 并利用倍频后的高速时钟输出串行数据。 本发明将通道数 N 设为变量用于串行和解串行流程的实现过程中, 可实现不同通道数的并行 信号与串行信号间的相互转换, 可节约开发商的研发成本, 进而降低用户 的消费成本。
此外, 本发明在解析并行数据得到链路状态时, 可实现对接收到的任 何数据进行监控, 从而达到监控对方与本地间的链路状态的效果, 便于及 时维护链路。 附图说明
图 1 为本发明串行和解串行方法中串行数据向并行数据转换的实现流 程示意图;
图 2为本发明串行和解串行方法中并行数据向串行数据转换的实现流 程示意图;
图 3为本发明串行和解串行的装置结构示意图。 具体实施方式
本发明的基本思想是: 以通道数 N为变量设置对串行数据进行编码的 帧格式; 本地接收端根据已设置的帧格式将接收到的串行数据定位出帧头,
并将串行数据转换成 N位并行数据, 根据已设置的帧格式解析并行数据得 到链路状态, 并输出 N位并行数据;
本地发送端将本地并行数据按设置的帧格式进行编码, 根据本地接收 端解析所得的链路状态输出对应帧格式的并行数据; 将并行数据转换成串 行数据, 并利用倍频后的高速时钟输出串行数据。
本发明中, 所述 N为通道数, N > 2; 所述对串行数据进行编码的帧格 式包括: 定位帧、 数据帧和错误帧; 相应的, 所述链路状态可为: 复位开 始、 收到定位帧、 收到数据帧和收到错误帧等。
下面结合附图及具体实施例对本发明作进一步详细说明。
本发明所述串行和解串行的方法主要在现场可编程门阵列 (FPGA )模 块中进行, 图 1 为本发明串行和解串行方法中串行数据向并行数据转换的 实现流程示意图, 如图 1所示, 该流程包括以下步骤:
步骤 101: 以通道数 N为变量设置对串行数据进行编码的帧格式; 具体的, FPGA模块以通道数 N为变量设置对串行数据进行编码的帧 格式, 这里, 所述对串行数据进行编码的帧格式有三种类型, 包括: 定位 帧、 数据帧和错误帧, 各种帧由数据域和控制域组成, 其中, 所述控制域, 即控制信号为四位, 数据域为 N位, 每帧包含 N+4个比特, 因此可算出串 行数据的传输速率是并行数据的 N+4倍。
下面列表分别详细描述所述三种帧格式, 所述定位帧如表 1所示:
表 1
如表 1所示, 本发明中所述定位帧有两种, 为定位帧 A和定位帧 B, 可看出, 定位帧 A是与并行数据频率相同且占空比为 50%的信号, 定位帧
B是与并行数据频率相同, 占空比不为 50%而是高电平比低电平多一位的 信号。
所述数据帧共有四种, 如表 2所示:
表 2
这里, 所述 '7" 表示比特取反, 四种数据帧用于数据的交替传输, 防 止数据连续为 0或连续为 1时, 接收端不能恢复时钟的问题。
所述错误帧共有八种, 如表 3所示:
表 3
其中, 所述 "X" 表示 0或 1; 所述一至八表示错误帧的种类, 即共有 八种。
本发明中, 对方的发送端首先发送帧格式为定位帧 A的串行数据, 锁 相环处于稳定状态后发送格式为定位帧 B的串行数据, 也就是说, 当本地 接收端确定帧头位置前发送帧格式为定位帧 A的串行数据, 当帧头的位置 确定后向对方发送帧格式为定位帧 B的串行数据, 以通知对方本地已完成 定帧头的过程, 锁相环再次稳定后发送帧格式为数据帧的串行数据, 在发 送帧格式为数据帧的串行数据过程中, 由于故障可能会发送帧格式为错误 帧的串行数据。
步骤 102:本地接收端根据已设置的帧格式将接收到的串行数据定位出 帧头;
具体的, 本地 FPGA模块中的接收端根据已设置的帧格式将接收到的 串行数据定位出帧头, 这里, 由步骤 101 中所设置的三种帧格式可看出, 只有在对方发送定位帧的时候, 才能确定帧头在数据流的什么位置。 因为 在对方发送定位帧的时候, 数据流中只有一个下降沿和一个上升沿, 且对 于两种格式的定位帧来说, 其上升沿的位置都固定在控制域的第二和第三 比特之间, 本发明就是利用这个上升沿的位置来进行帧定位的, 帧头就位 于这个上升沿后面的第三个比特的位置。 如果帧头没有定位, 则本地接收 端就会不断查找串行数据的上升沿, 直到帧头被定位。
进一步地, 在定位帧头之前, 本发明还包括提取对方所发的串行数据 中的时钟, 作为串行数据的釆样时钟, 用于串行数据向并行数据的转换。 其中, 所述时钟, 即对方的时钟。
步骤 103: 本地接收端将串行数据转换成 N位并行数据;
具体为: 本地 FPGA模块中的接收端将串行数据的帧头定位后, 利用 串行数据中的时钟将后续接收到的串行数据按已设置的帧格式转换成 N位 并行数据, 即转换成 N位并行数据和四位控制域数据组成的数据。
本发明中 ,在建立双方的链路之前首先确定所述 N: 1数据链路的串并
转换中 N的具体数值, 之后再进行所述串行数据和并行数据之间的相互转 换以便建立双方的链路。
步骤 104:本地接收端根据已设置的帧格式解析并行数据得到链路状态 并通知本地发送端, 之后输出 N位并行数据;
具体为: 本地 FPGA模块中的接收端对转换成的 N位并行数据和四位 控制域数据组成的数据进行解析,得到当前的链路状态并通知本地发送端, 例如: 如果 N位并行数据和四位控制域数据组成的数据对应的帧格式为数 据帧, 则当前的链路状态为: 收到数据帧, 之后输出 N位并行数据; 如果 N位并行数据和四位控制域数据组成的数据对应的帧格式为定位帧, 则当 前的链路状态为: 收到定位帧, 之后输出 N位并行数据; 如果 N位并行数 据和四位控制域数据组成的数据对应的帧格式为错误帧, 则当前的链路状 态为: 收到错误帧, 之后输出 N位并行数据; 在双方链路建立之前, 当前 的链路状态为: 复位开始, 本地发送端会向对方发送定位帧开始建立链路, 此外, 当本地接收端收到错误帧后, 也将返回复位开始状态重新建立链路。
这里, 所述输出的并行数据不全为有效数据, 只有链路状态为收到数 据帧时, 输出的并行数据为有效数据, 而如果接收到定位帧, 则定位帧对 应的数据中不包含要传输的数据信息, 因此不是有效数据; 如果接收到错 误帧, 则错误帧对应的数据信息为错误信息, 证明传输的为误码, 因此不 是有效数据。
进一步地, 在输出 N位并行数据之前, 需参照对方时钟对本地时钟进 行调节, 保证本地时钟与对方时钟同步。
本发明中, 如果收到错误帧, 则返回步骤 102, 重新建立本地与对方的 链路, 达到了一直监控链路状态的效果, 便于及时维护本地与对方间的链 路。
图 2为本发明串行和解串行方法中并行数据向串行数据转换的实现流
程示意图;
步骤 201: 本地发送端将本地并行数据按设置的帧格式进行编码; 具体为: 本地 FPGA模块中的发送端将本地的 N位并行数据和四位控 制域数据按本地接收端解析所得的链路状态对应的三种帧格式进行编码。
步骤 202:根据本地接收端解析所得的链路状态输出对应帧格式的并行 数据;
这里, 本地 FPGA模块中的发送端根据步骤 104中本地接收端解析并 行数据得到的链路状态, 发送不同帧格式的并行数据, 如果当前的链路状 态为复位开始或如果解析并行数据得到的链路状态为收到定位帧时, 则输 出定位帧格式的并行数据; 如果解析并行数据得到的链路状态为收到数据 帧时, 则输出数据帧格式的并行数据, 以便本地和对方双向建立两者之间 的链路。 更具体的, 当解析所得的链路处于复位开始状态或接收端的锁相 环处于稳定状态之前, 发送帧格式为定位帧 A的并行数据; 当接收端的锁 相环处于稳定状态后且在链路处于收到数据帧之前时, 发送帧格式为定位 帧 B的并行数据; 当解析所得的链路状态为收到数据帧时, 则发送帧格式 为数据帧的并行数据。
这里, 所述本地发送端以本地接收端解析所得的链路状态为依据输出 对应帧格式的并行数据的原因为: 本发明串行和解串行的方法主要用于本 地与对方之间链路的建立过程, 因此, 本地发送端向对方发送的数据帧格 式应与本地接收端接收的数据帧格式相呼应, 以便双方之间链路的建立。
步骤 203: 本地发送端将并行数据转换成串行数据, 并利用倍频后的高 速时钟输出串行数据;
具体为: 本地 FPGA模块中的发送端将本地 N位并行数据和四位控制 域数据转换成串行数据, 并将时钟倍频为本地并行数据时钟 N+4倍的高速 时钟, 之后将该高速时钟对应的串行数据传输给对方。
图 3为本发明串行和解串行的装置结构示意图, 如图 3所示, 该装置 包括: 设置模块、 帧串转并模块、 帧格式解码模块、 帧格式编码模块、 帧 并转串模块和时钟倍频模块, 上述各模块除时钟倍频模块外, 均集成于现 场可编程门阵列 (FPGA )模块中, 所述帧串转并模块和帧格式解码模块位 于接收端, 所述帧格式编码模块、 帧并转串模块和时钟倍频模块位于发送 端; 其中,
所述设置模块, 用于以通道数 N为变量设置对串行数据进行编码的帧 格式;
所述帧串转并模块, 用于根据设置模块设置的帧格式将接收到的串行 数据定位出帧头, 并将串行数据转换成 N位并行数据并发送到帧格式解码 模块;
所述帧格式解码模块, 用于根据设置模块设置的帧格式解析并行数据 得到链路状态并通知帧格式编码模块, 并输出 N位并行数据;
所述帧格式编码模块, 用于将本地并行数据按设置模块设置的帧格式 进行编码, 根据帧格式解码模块解析所得的链路状态输出对应帧格式的并 行数据并发送到帧并转串模块;
所述帧并转串模块, 用于将并行数据转换成串行数据, 并利用倍频后 的高速时钟输出串行数据;
所述时钟倍频模块, 用于将本地时钟倍频为高速时钟, 并发送到帧并 转串模块。
该装置进一步包括时钟恢复模块, 用于提取对方所发的串行数据中的 时钟, 并发送到帧串转并模块; 相应的, 所述帧串转并模块, 具体用于利 用串行数据中的时钟, 根据已设置的帧格式将串行数据转换成 N位并行数 据。
该装置进一步包括时钟调节模块, 用于帧格式解码模块输出 N位并行
数据之前, 参照对方时钟调节本地时钟与对方时钟同步。
以上所述, 仅为本发明的较佳实施例而已, 并非用于限定本发明的保 护范围, 凡在本发明的精神和原则之内所作的任何修改、 等同替换和改进 等, 均应包含在本发明的保护范围之内。
Claims
1、 一种串行和解串行的方法, 其特征在于, 该方法包括:
以通道数 N为变量设置对串行数据进行编码的帧格式; 本地接收端根 据已设置的帧格式将接收到的串行数据定位出帧头,并将串行数据转换成 N 位并行数据; 根据已设置的帧格式解析并行数据得到链路状态, 并输出 N 位并行数据;
本地发送端按设置的帧格式对本地并行数据进行编码, 根据本地接收 端解析所得的链路状态输出对应帧格式的并行数据; 将并行数据转换成串 行数据, 并利用倍频后的高速时钟输出串行数据。
2、 根据权利要求 1所述的串行和解串行的方法, 其特征在于, 所述将 接收到的串行数据定位出帧头之前, 该方法进一步包括: 提取对方所发的 串行数据中的时钟, 作为串行数据的釆样时钟。
3、 根据权利要求 1或 2所述的串行和解串行的方法, 其特征在于, 所 述输出 N位并行数据之前, 该方法进一步包括: 参照对方时钟对本地时钟 进行调节, 保证本地时钟与对方时钟同步。
4、 根据权利要求 1或 2所述的串行和解串行的方法, 其特征在于, 所 述将并行数据转换成串行数据, 并利用倍频后的高速时钟输出串行数据, 为:
将本地 N位并行数据和四位控制域数据转换成串行数据, 将时钟倍频 为本地并行数据时钟的 N+4倍, 并将所述高速时钟对应的串行数据传输给 对方。
5、 一种串行和解串行的装置, 其特征在于, 该装置包括: 设置模块、 帧串转并模块、 帧格式解码模块、 帧格式编码模块、 帧并转串模块和时钟 倍频模块; 其中,
所述设置模块, 用于以通道数 N为变量, 设置对串行数据进行编码的 帧格式;
所述帧串转并模块, 用于根据设置模块设置的帧格式, 将接收到的串 行数据定位出帧头, 并将串行数据转换成 N位并行数据并发送到帧格式解 码模块;
所述帧格式解码模块, 用于根据设置模块设置的帧格式, 解析并行数 据得到链路状态并通知帧格式编码模块, 并输出 N位并行数据;
所述帧格式编码模块, 用于将本地并行数据按设置模块设置的帧格式 进行编码, 根据帧格式解码模块解析所得的链路状态, 输出对应帧格式的 并行数据并发送到帧并转串模块;
所述帧并转串模块, 用于将并行数据转换成串行数据, 并用倍频后的 高速时钟输出串行数据;
所述时钟倍频模块, 用于将本地时钟倍频为高速时钟, 并发送到帧并 转串模块。
6、 根据权利要求 5所述的串行和解串行的装置, 其特征在于, 该装置 进一步包括时钟恢复模块, 用于提取对方所发的串行数据中的时钟, 并发 送到帧串转并模块;
相应的, 所述帧串转并模块, 具体用于利用串行数据中的时钟, 根据 已设置的帧格式将串行数据转换成 N位并行数据。
7、 根据权利要求 5或 6所述的串行和解串行的装置, 其特征在于, 该 装置进一步包括时钟调节模块, 用于帧格式解码模块输出 N位并行数据之 前, 参照对方时钟调节本地时钟与对方时钟同步。
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CN1571412A (zh) * | 2004-05-13 | 2005-01-26 | 中兴通讯股份有限公司 | 一种基带数据传输的装置及其帧同步方法 |
CN1798117A (zh) * | 2004-12-22 | 2006-07-05 | 华为技术有限公司 | 高速串行信号同步方法及同步电路 |
CN101573903A (zh) * | 2006-11-08 | 2009-11-04 | 菲尼萨公司 | 用于在光电设备中使用的串化器/解串器 |
CN101706763A (zh) * | 2009-11-20 | 2010-05-12 | 中兴通讯股份有限公司 | 一种串行和解串行的方法及装置 |
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