WO2023125047A1 - 带隙基准电压校准方法 - Google Patents

带隙基准电压校准方法 Download PDF

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WO2023125047A1
WO2023125047A1 PCT/CN2022/139327 CN2022139327W WO2023125047A1 WO 2023125047 A1 WO2023125047 A1 WO 2023125047A1 CN 2022139327 W CN2022139327 W CN 2022139327W WO 2023125047 A1 WO2023125047 A1 WO 2023125047A1
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bandgap reference
reference voltage
temperature
calibration
trimming code
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PCT/CN2022/139327
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English (en)
French (fr)
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董彭
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思瑞浦微电子科技(上海)有限责任公司
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Publication of WO2023125047A1 publication Critical patent/WO2023125047A1/zh

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
    • G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/30—Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities

Definitions

  • the invention relates to the field of integrated circuits, in particular to a bandgap reference voltage calibration method.
  • the traditional "single-point calibration” calibrates the first-order temperature coefficient (TC) error by calibrating the absolute voltage of the bandgap reference voltage V_BG at room temperature.
  • TC temperature coefficient
  • the purpose of the present invention is to provide a bandgap reference voltage calibration method, which can calibrate the temperature coefficient error of the whole system and has high precision.
  • an embodiment of the present invention provides a bandgap reference voltage calibration method, the calibration method is based on a bandgap reference circuit, the bandgap reference circuit includes a first-order calibration module, a higher-order calibration module, an absolute A value voltage calibration module and a reference buffer, the first-order calibration module can perform a first-order calibration through the trimming code D to obtain a bandgap reference voltage V BG , and through a high-order calibration module, an absolute value voltage calibration module and a reference buffer Obtain the reference output voltage V REF ; the calibration method includes:
  • a second trimming code D cal for calibrating the temperature coefficient error is obtained, and a corresponding first bandgap reference voltage V BG_CP is obtained at the same time.
  • the first trimming code D raw is obtained by performing single-point calibration on the first-order calibration module in cooperation with the preset bandgap reference voltage V BG .
  • the temperature coefficient error is specifically: Wherein, V REF_H is the first reference output voltage obtained at the first temperature TH , and V REF_L is the second reference output voltage obtained at the second temperature T L.
  • the obtaining of the second trimming code D cal for calibrating the temperature coefficient error is specifically:
  • k is Boltzmann's constant
  • q is electron charge
  • N is the number ratio of transistor Q2 to transistor Q1 in the first-order calibration module.
  • the calibration method also includes:
  • the second bandgap reference voltage V BG_FT is obtained according to the second trimming code D cal ;
  • the third trimming code D trim is obtained.
  • the calibration method further includes: performing absolute value voltage calibration at the second temperature T L .
  • the calibration method further includes: configuring a high-order trimming code at the first temperature TH .
  • the first temperature TH is higher than the second temperature T L .
  • Fig. 1 is a circuit schematic diagram of a bandgap reference circuit
  • FIG. 2 is a flowchart of a method for calibrating a bandgap reference voltage according to an embodiment of the present invention.
  • a bandgap reference circuit includes a first-order calibration module 10, a high-order calibration module TCC trim, an absolute value voltage calibration module Voltage trim and a reference buffer buffer.
  • the first-order calibration module 10 can adjust the code by trimming D performs first-order temperature coefficient error calibration to obtain the bandgap reference voltage V BG , and obtains the reference output voltage V REF through the high-order calibration module TCC trim, the absolute value voltage calibration module Voltage trim and the reference buffer buffer buffer.
  • the first-order calibration module 10 includes a resistor R1A, a resistor R1B, an adjustable resistor R2, an operational amplifier opamp, a PNP transistor Q1, a PNP transistor Q2 and a PMOS transistor M1.
  • the source of the PMOS transistor M1 is connected to the power supply Vdd, the drain of the PMOS transistor M1 is connected to the high-order calibration module TCC trim, one end of the resistor R1A, and one end of the resistor R1B, and the gate of the PMOS transistor M1 is connected to the output of the operational amplifier opamp.
  • the other end of the resistor R1A is connected to the negative input terminal of the operational amplifier opamp and the emitter of the PNP transistor Q1
  • the other end of the resistor R1B is connected to the positive input terminal of the operational amplifier opamp and one end of the adjustable resistor R2
  • the other end of the adjustable resistor R2 is connected to
  • the emitter of the PNP transistor Q2 the collector of the PNP transistor Q2 are connected to the collector of the PNP transistor Q1 and connected to the power supply Vss.
  • the high-order calibration module TCC trim is also connected to the positive input terminal of the reference buffer buffer through the absolute value voltage calibration module Voltage trim, and the negative input terminal of the reference buffer buffer is connected to the output terminal of the reference buffer buffer.
  • the first-order calibration module 10 outputs the bandgap reference voltage V BG after the first-order temperature coefficient error calibration, and the high-order calibration module TCC trim performs high-order curvature calibration on the bandgap reference voltage V BG to output the voltage VTCC, and the voltage VTCC is determined by the absolute value Voltage trim is calibrated by the voltage calibration module to obtain a voltage VA, and finally the voltage VA passes through a reference buffer buffer to obtain a reference output voltage V REF .
  • Calibration method comprises:
  • the first testing stage may be selected as a wafer testing stage, and the second testing stage may be selected as a post-packaging testing stage.
  • the first temperature TH is higher than the second temperature T L .
  • the first temperature T H is selected as a high temperature state
  • the second temperature T L is selected as a normal temperature state.
  • the temperature ranges of the first temperature TH and the second temperature T L are not specifically limited. The greater the difference between the first temperature TH and the second temperature T L , the more conducive to calibration accuracy, thereby achieving the purpose of high precision and low cost.
  • the first temperature TH may be 100°C ⁇ 125°C
  • the second temperature T L may be 25°C ⁇ 5°C.
  • the second temperature T L may also be as low as -40° C., but the cost of testing at this low temperature is relatively high.
  • the high-order trimming code is configured to perform high-order calibration on the bandgap reference voltage V BG through the high-order calibration module TCC trim.
  • This high-level calibration is generally done through experiments before step S 1 , so as to eliminate the influence of the high-level temperature coefficient error on the reference output voltage V REF to the greatest possible extent, and avoid impact on the accuracy of subsequent tests (ie, two-point calibration).
  • the absolute voltage calibration is performed through the absolute voltage calibration module Voltage trim.
  • step S1 the first trimming code D raw is obtained by performing a single-point calibration on the first-order calibration module in cooperation with the preset bandgap reference voltage V BG .
  • the bandgap reference voltage in the bandgap reference circuit Among them, V BE1 is the negative temperature coefficient voltage, and ⁇ V BE is the PTAT (proportional to absolute temperature) voltage.
  • the above single-point calibration can be understood as that the absolute voltage value and first-order temperature coefficient error of the bandgap reference voltage V BG can be adjusted by adjusting the resistance of the adjustable resistor R2.
  • step S1 the temperature coefficient error is specifically: Wherein, V BEF_H is the first reference output voltage obtained at the first temperature TH , and V REF_L is the second reference output voltage obtained at the second temperature T L.
  • V RFF_H the corresponding first reference output voltage obtained at the first temperature TH
  • V REF_L the second reference output voltage obtained at the second temperature T L.
  • step S2 assuming that the correction code D is equal to the second correction code D cal , the above temperature coefficient error can be calibrated out, so that the second correction code D cal for calibrating the temperature coefficient error can be obtained, specifically:
  • f -1 is expressed as the inverse function of f
  • the function f is determined by the calibration network that calibrates the resistance of the adjustable resistor R2
  • V REF and V BG are preset values
  • k is the Boltzmann constant
  • q is the electron
  • N is the ratio of the number of transistors Q2 and transistors Q1 in the first-order calibration module.
  • This mapping relationship reflects the relationship that the temperature coefficient error from the first test stage to the second test stage is calibrated by the change of the bandgap reference voltage V BG at normal temperature. To the value to be trimmed by another trimming code D.
  • the mapping relationship is related to the size and mode of the packaging material, and is obtained through experimental statistics.
  • the third trimming code D trim is used to trim the temperature coefficient error that affects the reference output voltage V REF caused by environmental changes corresponding to the first stage to the second stage.
  • the first stage is the wafer stage
  • the second stage is the packaging stage. Factors such as packaging stress during the packaging stage will cause changes in the temperature coefficient error, thereby affecting the reference output voltage V REF of the wafer.
  • the third trimming code D trim is used to trim the temperature coefficient error.

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Abstract

一种带隙基准电压校准方法，基于带隙基准电路实现；校准方法包括：在第一测试阶段，获取在第一温度和第二温度下且修调码为第一修调码时所对应的温度系数误差（S1）；获得校准温度系数误差的第二修调码，同时获得对应的第一带隙基准电压（S2）。根据带隙基准电压校准方法，先在第一测试阶段的第一温度下进行"单点校准"，再在第二测试阶段的第二温度下进行"两点校准"，从而只需两个测试温度点，无需多次迭代。对封装等应力影响的检测和调整，充分考虑到基准输出电压从第一测试阶段至第二测试阶段的变化从而加以校准。

Description

带隙基准电压校准方法
本发明要求2021年12月31日向中国专利局提交的申请号为202111671626.1、发明名称为“带隙基准电压校准方法”的中国专利申请的优先权，该申请的全部内容通过引用结合在本文中。
技术领域
本发明关于集成电路领域，特别是关于一种带隙基准电压校准方法。
背景技术
传统的“单点校准”均是通过校准常温下带隙基准电压V_BG的绝对电压来校准一阶温度系数(TC)误差。但是对于高精度的基准reference，如温度系数(TC)＜3ppm的基准，由于运算放大器opamp的失调电压Vos、三极管的基极电阻和基极电流、三极管的early效应、基准缓冲器的失调电压Vos等均贡献一部分温度系数误差，所以“单点校准“(即只在一个温度点下做测量和校准)已难以达到需要的TC精度。
公开于该背景技术部分的信息仅仅旨在增加对本发明的总体背景的理解，而不应当被视为承认或以任何形式暗示该信息构成已为本领域一般技术人员所公知的现有技术。
发明内容
本发明的目的在于提供一种带隙基准电压校准方法，其能够校准整个系统的温度系数误差，精度高。
为实现上述目的，本发明的实施例提供了一种带隙基准电压校准方法，所述校准方法基于带隙基准电路实现，所述带隙基准电路包括一阶校准模块、高阶校准模块、绝对值电压校准模块和基准缓冲器，所述一阶校准模块能够通过修调码D进行一阶校准以获得带隙基准电压V BG，并通过高阶校准模块、绝对值电压校准模块和基准缓冲器获得基准输出电压V REF；所述校准方法包括：
获取在第一温度T H和第二温度T L下且修调码D为第一修调码D raw时所对应的温度系数误差；
获得校准所述温度系数误差的第二修调码D cal，同时获得对应的第一带隙基准电压V BG_CP。
在本发明的一个或多个实施方式中，所述第一修调码D raw通过预设带隙基准电压V BG配合对所述一阶校准模块进行单点校准获得。
在本发明的一个或多个实施方式中，所述温度系数误差具体为：
Figure PCTCN2022139327-appb-000001
其中，V REF_H为在第一温度T H下获取的第一基准输出电压，V REF_L为在第二温度T L下获取的第二基准输出电压。
在本发明的一个或多个实施方式中，所述获得校准所述温度系数误差的第二修调码D cal具体为：
Figure PCTCN2022139327-appb-000002
其中，k为玻尔兹曼常数，q为电子电荷量，N为一阶校准模块内三极管Q2与三极管Q1的个数比例。
在本发明的一个或多个实施方式中，所述校准方法还包括：
在第二温度T L下，根据第二修调码D cal获得第二带隙基准电压V BG_FT；
根据第二带隙基准电压V BG_FT和第一带隙基准电压V BG_CP的变化与所需调节的修调码值ΔD的映射关系，获得第三修调码D trim。
在本发明的一个或多个实施方式中，所述第二带隙基准电压V BG_FT和第一带隙基准电压V BG_CP的变化与所需调节的修调码值ΔD之间的映射关系具体为：ΔD＝g(ΔV BG)，其中，ΔV BG＝VB G_FT-V BG_CP。
在本发明的一个或多个实施方式中，所述获得第三修调码D trim具体为：D trim＝D cal+ΔD。
在本发明的一个或多个实施方式中，所述校准方法还包括：在第二温度T L下，进行绝对值电压校准。
在本发明的一个或多个实施方式中，所述校准方法还包括：在第一温度T H下，配置高阶修调码。
在本发明的一个或多个实施方式中，所述第一温度T H高于第二温度T L。
与现有技术相比，根据本发明实施方式的带隙基准电压校准方法，先在第一测试 阶段的第一温度T H下进行“单点校准”，再在第一测试阶段的第二温度T L下进行“两点校准”，从而只需两个测试温度点，无需多次迭代，就能算出相当精准的修调码，显著提高了校准的精度，具有高精度、低成本的优势。基于最终基准输出电压V REF的“两点校准”，可以校准整个系统的温度系数误差，达到“单点校准”难以达到的精度的效果。对封装等应力影响的检测和调整，充分考虑到基准输出电压V REF从第一测试阶段至第二测试阶段的变化从而加以校准，具有很强的工程实施性。
附图说明
图1是一种带隙基准电路的电路原理图；
图2是根据本发明一实施方式的带隙基准电压校准方法的流程图。
具体实施方式
下面结合附图，对本发明的具体实施方式进行详细描述，但应当理解本发明的保护范围并不受具体实施方式的限制。
除非另有其它明确表示，否则在整个说明书和权利要求书中，术语“包括”或其变换如“包含”或“包括有”等等将被理解为包括所陈述的元件或组成部分，而并未排除其它元件或其它组成部分。
实施例1
如图1所示，一种带隙基准电路，包括一阶校准模块10、高阶校准模块TCC trim、绝对值电压校准模块Voltage trim和基准缓冲器buffer，一阶校准模块10能够通过修调码D进行一阶温度系数误差校准以获得带隙基准电压V BG，并通过高阶校准模块TCC trim、绝对值电压校准模块Voltage trim和基准缓冲器buffer获得基准输出电压V REF。
具体的，一阶校准模块10包括电阻R1A、电阻R1B、可调电阻R2、运算放大器opamp、PNP三极管Q1、PNP三极管Q2和PMOS管M1。
PMOS管M1的源极连接电源Vdd，PMOS管M1的漏极连接高阶校准模块TCC trim以及电阻R1A的一端以及电阻R1B的一端，PMOS管M1的栅极连接运算放大器opamp的输出端。电阻R1A的另一端连接运算放大器opamp的负极输入端和PNP三极管Q1的发射极，电阻R1B的另一端连接运算放大器opamp的正极输入端和可调电阻R2的一端，可调电阻R2的另一端连接PNP三极管Q2的发射极，PNP三极管 Q2的集电极和PNP三极管Q1的集电极相连且连接电源Vss。
高阶校准模块TCC trim同时通过绝对值电压校准模块Voltage trim与基准缓冲器buffer的正极输入端连接，基准缓冲器buffer的负极输入端与基准缓冲器buffer的输出端连接。
一阶校准模块10输出一阶温度系数误差校准后的带隙基准电压V BG，高阶校准模块TCC trim对带隙基准电压V BG做高阶的曲率校准后输出电压VTCC，电压VTCC经绝对值电压校准模块Voltage trim校准后得到电压VA，最后电压VA通过基准缓冲器buffer后获得基准输出电压V REF。
如图2所示，一种带隙基准电压校准方法，该方法基于上述带隙基准电路实现；校准方法包括：
在第一测试阶段：
S1、获取在第一温度T H和第二温度T L下且修调码D为第一修调码D raw时所对应的温度系数误差。
S2、获得校准温度系数误差的第二修调码D cal，同时获得对应的第一带隙基准电压V BG_CP。
在第二测试阶段：
S3、在第二温度T L下，根据第二修调码D cal获得第二带隙基准电压V BG_FT。
S4、根据第二带隙基准电压V BG_FT和第一带隙基准电压V BG_CP的变化与所需调节的修调码值ΔD之间的映射关系，获得第三修调码D trim。
在本实施例中，第一测试阶段可以选择为晶圆测试阶段，第二测试阶段可以选择为封装后测试阶段。第一温度T H高于第二温度T L。第一温度T H选择为高温状态，第二温度T L选择为常温状态。第一温度T H和第二温度T L的温度范围不做具体的限定，第一温度T H和第二温度T L相差越大，越有利于校准精度，从而达到高精度、低成本的目的。优选地，第一温度T H可以为100℃～125℃，第二温度T L可以为25℃±5℃。另外，第二温度T L也可以为-40℃的低温，但该低温下的测试成本偏高。
另外，在第一温度T H下，配置高阶修调码以通过高阶校准模块TCC trim对带隙基准电压V BG进行高阶校准。该高阶校准一般在步骤S 1前通过实验等方式完成，最大可 能消除高阶温度系数误差对基准输出电压V REF的影响，避免对后续的各测试(即两点校准)的精度产生影响。
同时，在第二测试阶段且在第二温度T L下，第二带隙基准电压V BG_FT校准完毕后，通过绝对值电压校准模块Voltage trim进行绝对值电压校准。
具体的，在步骤S1中，第一修调码D raw通过预设带隙基准电压V BG配合对一阶校准模块进行单点校准获得。
结合图1所示，带隙基准电路中的带隙基准电压
Figure PCTCN2022139327-appb-000003
其中，V BE1为负温度系数电压，ΔV BE为PTAT(与绝对温度成正比关系)电压。上述单点校准可以理解为，可以通过调节可调电阻R2的阻值来调整带隙基准电压V BG的绝对电压值和一阶温度系数误差。
在上述公式中，
Figure PCTCN2022139327-appb-000004
可以通过校准网络的修调码D来调整，设其函数关系为
Figure PCTCN2022139327-appb-000005
Figure PCTCN2022139327-appb-000006
则
Figure PCTCN2022139327-appb-000007
其中k为玻尔兹曼常数，q为电子电荷量，N为PNP三极管Q2与PNP三极管Q1的个数比例，皆为常数。所以在预设带隙基准电压V BG的情况下，获得对应的第一修调码D raw。基于
Figure PCTCN2022139327-appb-000008
的一阶温度系数误差校准，参数皆为物理参数，与所用工艺无关，具有很强的工艺性。
在步骤S1中，温度系数误差具体为：
Figure PCTCN2022139327-appb-000009
其中，V BEF_H为在第一温度T H下获取的第一基准输出电压，V REF_L为在第二温度T L下获取的第二基准输出电压。本实施例中，在确定第一修调码D raw之后，在第一温度T H下，通过上述带隙基准电路能够测得对应的第一基准输出电压V RFF_H，在第二温度T L下，通过上述带隙基准电路能够测得对应的第二基准输出电压V REF_L，从而能够算出温度系数误差。
在步骤S2中，假设修调码D等于第二修调码D cal时，能够校准掉上述温度系数误差，从而能够获得校准温度系数误差的第二修调码D cal，具体为：
Figure PCTCN2022139327-appb-000010
其中，f -1表示为f的反函数，函数f由校准可调电阻R2的阻值的校准网络决定，V REF和V BG为预设的值，k为玻尔兹曼常数，q为电子电荷量，N为一阶校准模块内三极管Q2与三极管Q1的个数比例。不难发现，当V REF_H等于V REF_L时，第一修调码D raw等于第二修调码D cal。当V REF_H接近V REF_L时，第一修调码D raw接近理想的修调码D。
在步骤S3中，第二带隙基准电压V BG_FT和第一带隙基准电压V BG_CP的变化与所需调节的修调码值ΔD的映射关系具体为：ΔD＝g(ΔV BG)，其中，ΔV BG＝V BG_FT-V BG_CP。该映射关系反应了从第一测试阶段到第二测试阶段的温度系数误差由常温下带隙基准电压V BG的变化来校准的关系，修调码值ΔD即为从一个修调码D修调到另一个修调码D所要修调的值。该映射关系与封装材料大小和方式等有关，均由实验统计所得。
在步骤S3中，获得第三修调码D trim具体为：D trim＝D cal+ΔD。第三修调码D trim用于修调从第一阶段到第二阶段所对应的环境变化等因素导致的对基准输出电压V REF产生影响的温度系数误差。本实施方式中，第一阶段为晶圆阶段，第二阶段为封装阶段，封装阶段时的封装应力等因素会导致温度系数误差产生变化，从而对晶圆的基准输出电压V REF产生影响，通过第三修调码D trim以修调该温度系数误差。
前述对本发明的具体示例性实施方案的描述是为了说明和例证的目的。这些描述并非想将本发明限定为所公开的精确形式，并且很显然，根据上述教导，可以进行很多改变和变化。对示例性实施例进行选择和描述的目的在于解释本发明的特定原理及其实际应用，从而使得本领域的技术人员能够实现并利用本发明的各种不同的示例性实施方案以及各种不同的选择和改变。本发明的范围意在由权利要求书及其等同形式所限定。

Claims (10)

  1. 一种带隙基准电压校准方法，其特征在于，所述校准方法基于带隙基准电路实现，所述带隙基准电路包括一阶校准模块、高阶校准模块、绝对值电压校准模块和基准缓冲器，所述一阶校准模块能够通过修调码D进行一阶校准以获得带隙基准电压V BG，并通过高阶校准模块、绝对值电压校准模块和基准缓冲器获得基准输出电压V REF；所述校准方法包括：
    在第一测试阶段：
    获取在第一温度T H和第二温度T L下且修调码D为第一修调码D raw时所对应的温度系数误差；
    获得校准所述温度系数误差的第二修调码D cal，同时获得对应的第一带隙基准电压V BG_CP。
  2. 如权利要求1所述的带隙基准电压校准方法，其特征在于，所述第一修调码D raw通过预设带隙基准电压V BG配合对所述一阶校准模块进行单点校准获得。
  3. 如权利要求1所述的带隙基准电压校准方法，其特征在于，所述温度系数误差具体为：
    Figure PCTCN2022139327-appb-100001
    其中，V REF_H为在第一温度T H下获取的第一基准输出电压，V REF_L为在第二温度T L下获取的第二基准输出电压。
  4. 如权利要求3所述的带隙基准电压校准方法，其特征在于，所述获得校准所述温度系数误差的第二修调码D cal具体为：
    Figure PCTCN2022139327-appb-100002
    其中，k为玻尔兹曼常数，q为电子电荷量，N为一阶校准模块内三极管Q2与三极管Q1的个数比例。
  5. 如权利要求1所述的带隙基准电压校准方法，其特征在于，所述校准方法还包括：
    在第二测试阶段：
    在第二温度T L下，根据第二修调码D cal获得第二带隙基准电压V BG_FT；
    根据第二带隙基准电压V BG_FT和第一带隙基准电压V BG_CP的变化与所需调节的修调码值ΔD的映射关系，获得第三修调码D trim。
  6. 如权利要求5所述的带隙基准电压校准方法，其特征在于，所述第二带隙基准电压V BG_FT和第一带隙基准电压V BG_CP的变化与所需调节的修调码值ΔD之间的映射关系具体为：ΔD＝g(ΔV BG)，其中，ΔV BG＝V BG_FT-V BG_CP。
  7. 如权利要求5所述的带隙基准电压校准方法，其特征在于，所述获得第三修调码D trim具体为：D trim＝D cal+ΔD。
  8. 如权利要求5所述的带隙基准电压校准方法，其特征在于，所述校准方法还包括：在第二温度T L下，进行绝对值电压校准。
  9. 如权利要求1所述的带隙基准电压校准方法，其特征在于，所述校准方法还包括：在第一温度T H下，配置高阶修调码。
  10. 如权利要求1所述的带隙基准电压校准方法，其特征在于，所述第一温度T H高于第二温度T L。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117270621A (zh) * 2023-11-23 2023-12-22 上海芯炽科技集团有限公司 一种低温漂带隙基准电路的单温度校准结构

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114296504B (zh) * 2021-12-31 2023-06-02 思瑞浦微电子科技(上海)有限责任公司 带隙基准电压校准方法
CN114740941B (zh) * 2022-05-05 2023-12-19 芯海科技（深圳）股份有限公司 带隙基准电路、集成电路和电子设备
CN117232565A (zh) * 2023-11-15 2023-12-15 合肥美镓传感科技有限公司 传感器补偿方法、装置、系统及电子设备

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060043957A1 (en) * 2004-08-30 2006-03-02 Carvalho Carlos M Resistance trimming in bandgap reference voltage sources
US20080074172A1 (en) * 2006-09-25 2008-03-27 Analog Devices, Inc. Bandgap voltage reference and method for providing same
CN101630176A (zh) * 2009-07-28 2010-01-20 中国科学院微电子研究所 低电压cmos带隙基准电压源
CN202120153U (zh) * 2011-05-31 2012-01-18 比亚迪股份有限公司 一种带隙基准电压产生电路
CN104298294A (zh) * 2013-07-19 2015-01-21 中国科学院上海微系统与信息技术研究所 带有修调的高阶曲率补偿基准电压源
CN108664069A (zh) * 2017-03-31 2018-10-16 上海东软载波微电子有限公司 带隙基准电路的校准方法及装置
CN110262614A (zh) * 2019-07-15 2019-09-20 中国科学院上海微系统与信息技术研究所 一种基准电压温度系数修调方法、装置及终端
CN114296504A (zh) * 2021-12-31 2022-04-08 思瑞浦微电子科技(上海)有限责任公司 带隙基准电压校准方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7839202B2 (en) * 2007-10-02 2010-11-23 Qualcomm, Incorporated Bandgap reference circuit with reduced power consumption
US7888991B2 (en) * 2009-03-23 2011-02-15 Micron Technology, Inc. Clock distribution network
US7932772B1 (en) * 2009-11-02 2011-04-26 Delphia Technologies, Inc. Curvature-compensated band-gap voltage reference circuit
CN103744464B (zh) * 2013-12-20 2015-07-29 中国科学院微电子研究所 一种具有电流补偿的带隙基准电路
US9804614B2 (en) * 2015-05-15 2017-10-31 Dialog Semiconductor (Uk) Limited Bandgap reference circuit and method for room temperature trimming with replica elements
CN108681359B (zh) * 2018-05-22 2020-02-18 电子科技大学 一种高精度低失调的带隙基准电压电路
CN109725672B (zh) * 2018-09-05 2023-09-08 南京浣轩半导体有限公司 一种带隙基准电路及高阶温度补偿方法

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060043957A1 (en) * 2004-08-30 2006-03-02 Carvalho Carlos M Resistance trimming in bandgap reference voltage sources
US20080074172A1 (en) * 2006-09-25 2008-03-27 Analog Devices, Inc. Bandgap voltage reference and method for providing same
CN101630176A (zh) * 2009-07-28 2010-01-20 中国科学院微电子研究所 低电压cmos带隙基准电压源
CN202120153U (zh) * 2011-05-31 2012-01-18 比亚迪股份有限公司 一种带隙基准电压产生电路
CN104298294A (zh) * 2013-07-19 2015-01-21 中国科学院上海微系统与信息技术研究所 带有修调的高阶曲率补偿基准电压源
CN108664069A (zh) * 2017-03-31 2018-10-16 上海东软载波微电子有限公司 带隙基准电路的校准方法及装置
CN110262614A (zh) * 2019-07-15 2019-09-20 中国科学院上海微系统与信息技术研究所 一种基准电压温度系数修调方法、装置及终端
CN114296504A (zh) * 2021-12-31 2022-04-08 思瑞浦微电子科技(上海)有限责任公司 带隙基准电压校准方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117270621A (zh) * 2023-11-23 2023-12-22 上海芯炽科技集团有限公司 一种低温漂带隙基准电路的单温度校准结构
CN117270621B (zh) * 2023-11-23 2024-02-13 上海芯炽科技集团有限公司 一种低温漂带隙基准电路的单温度校准结构

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