WO2023123809A1 - 一种太阳能电池及其制备方法 - Google Patents

一种太阳能电池及其制备方法 Download PDF

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WO2023123809A1
WO2023123809A1 PCT/CN2022/092291 CN2022092291W WO2023123809A1 WO 2023123809 A1 WO2023123809 A1 WO 2023123809A1 CN 2022092291 W CN2022092291 W CN 2022092291W WO 2023123809 A1 WO2023123809 A1 WO 2023123809A1
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doped layer
layer
dopant
doped
semiconductor substrate
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PCT/CN2022/092291
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French (fr)
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李中兰
鲁伟明
李华
靳玉鹏
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泰州隆基乐叶光伏科技有限公司
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Priority to EP22913105.7A priority Critical patent/EP4418332A1/en
Priority to AU2022425791A priority patent/AU2022425791A1/en
Publication of WO2023123809A1 publication Critical patent/WO2023123809A1/zh

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Definitions

  • the present disclosure relates to the technical field of solar cells, in particular to a solar cell and a preparation method thereof.
  • the photoelectric conversion efficiency of the back-contact solar cell is higher because there is no electrode shielding on the front.
  • a p-type region and an n-type region are arranged on different regions on the back of the back contact battery, and then a positive electrode and a negative electrode are respectively arranged thereon.
  • this kind of battery with no shielding on the front not only has high conversion efficiency, but also looks more beautiful.
  • the assembly with all back electrodes is easier to assemble.
  • IBC battery is one of the technical directions to realize high-efficiency crystalline silicon battery at present.
  • the preparation method is also relatively complicated. Generally, at least two patternings are required to complete the patterning of the p-type region and the n-type region, so the cost is relatively high.
  • the present disclosure proposes a solar cell and a manufacturing method thereof, which can complete the preparation of doped semiconductors in two regions only by patterning once. Moreover, in the doped region prepared by the method, both poles are passivated contact structures, the passivation effect is good, and the recombination rate of the metal region is greatly reduced, thereby improving the efficiency of the battery.
  • the present disclosure provides a method for preparing a solar cell, comprising the following steps:
  • the first doped layer has a first dopant and a second dopant
  • the third doped layer has a first dopant and a second dopant
  • the conductivity type of the first doped layer is opposite to that of the second doped layer
  • the conductivity type of at least a part of the third doped layer is the same as that of the first doped layer.
  • a first semiconductor layer is formed on the first surface of the semiconductor substrate, and then a first dopant is diffused into the first semiconductor layer, thereby forming a first doped layer, or a first doped layer is formed on the first surface of the semiconductor substrate.
  • a first doped layer is formed by in-situ doping;
  • a first auxiliary layer is formed on the surface of the first doped layer facing away from the semiconductor substrate, and then part of the first auxiliary layer and the first doped layer are etched away to complete the patterning, leaving a part of the first auxiliary layer. a doped layer.
  • a second doped layer is formed by in-situ doping
  • the heat treatment is laser treatment or heat treatment
  • the conductivity type of the region directly irradiated by the laser light is the same as that of the first doped layer.
  • a region of the same conductivity type as that of the first doped layer penetrates through the third doped layer along the thickness direction.
  • a second semiconductor layer is formed on the surface of the first doped layer away from the semiconductor substrate and the first surface of the semiconductor substrate not covering the first doped layer,
  • the second dopant is diffused into the second semiconductor layer, and due to the high temperature, the first dopant in the first doped layer will also diffuse to all the layers above it.
  • the second semiconductor layer located above the first doped layer is the third doped layer, and the second semiconductor layer located on the first surface of the semiconductor substrate is the second doped layer .
  • the conductivity of at least a part of the region is the same as that of the first doped layer.
  • the peak doping concentration of the first dopant in the first doped layer is 1 ⁇ 10 19 -5 ⁇ 10 21 atoms/cm 3 .
  • the doping concentration of the first dopant is greater than the doping concentration of the second dopant
  • the doping concentration of the first dopant is greater than the doping concentration of the second dopant in at least a part of the region.
  • the peak doping concentration of the first dopant in the first doped layer is 1 ⁇ 10 19 -3 ⁇ 10 21 atoms/cm 3 ;
  • the peak doping concentration of the second dopant is 1 ⁇ 10 19 to 3 ⁇ 10 19 atoms/cm 3 ;
  • the peak doping concentration of the first dopant in at least a part of the third doped layer is 1 ⁇ 10 20 -5 ⁇ 10 20 atoms/cm 3 .
  • the heating peak temperature of the heat treatment is above 850° C., preferably above 900° C., more preferably 1000° C.; at the peak temperature, the heating time is above 10 min.
  • the first dopant and the second dopant located in the first doped layer and the third doped layer diffuse into the semiconductor substrate Inside, thereby forming the third doped region;
  • the second dopant located in the second doped layer is diffused into the semiconductor substrate, thereby forming a fourth doped region
  • the peak doping concentration of the first dopant is 1 ⁇ 10 18 to 3 ⁇ 10 21 atoms/cm 3
  • the peak doping concentration of the second dopant is The impurity concentration is 1 ⁇ 10 17 ⁇ 3 ⁇ 10 19 atoms/cm 3 ;
  • the peak doping concentration of the second dopant is 1 ⁇ 10 18 -3 ⁇ 10 19 atoms/cm 3 .
  • the first dopant is a Group VA element or a Group IIIA element
  • the second dopant is a Group VA element or a Group IIIA element.
  • the first dopant is A Group VA element
  • the second dopant is a Group IIIA element.
  • first doped layer, the second doped layer and the third doped layer are all doped polysilicon layers, microcrystalline silicon layers or amorphous silicon layers.
  • the present disclosure provides a solar cell, including a semiconductor substrate, a first doped layer and a second doped layer on a first surface of the semiconductor substrate, and a side of the first doped layer away from the semiconductor substrate The surface has a third doped layer,
  • the first doped layer has a first dopant and a second dopant
  • the third doped layer has a first dopant and a second dopant
  • the conductivity type of at least a part of the region in the third doped layer is the same as that of the first doped layer;
  • the conductivity type of the first doped layer is opposite to that of the second doped layer.
  • the thickness of the first doped layer is 50-300 nm
  • the third doped layer and the second doped layer have the same thickness, which is less than or equal to 150 nm.
  • the conductivity type of all regions in the third doped layer is the same as that of the first doped layer.
  • the conductivity of at least a part of the region is the same as that of the The conductivity types of the first doped layers are the same.
  • the thickness of the third doped layer is 30nm ⁇ d ⁇ 150nm
  • a region of the same conductivity type as the first doped layer penetrates the first doped layer along the thickness direction.
  • the doping concentration of the first dopant increases first from the side surface away from the semiconductor substrate to the doping concentration of the side surface close to the semiconductor substrate.
  • the doping concentration of the second dopant decreases gradually.
  • the doping concentration of the second dopant is the same from the side surface away from the semiconductor substrate to the doping concentration of the side surface close to the semiconductor substrate.
  • the doping concentration of the first dopant gradually increases from the side surface away from the semiconductor substrate to the doping concentration of the side surface close to the semiconductor substrate. big;
  • the doping concentration of the second dopant is the same from the side surface away from the semiconductor substrate to the doping concentration of the side surface close to the semiconductor substrate.
  • the third doped layer not only covers the surface of the first doped layer facing away from the semiconductor substrate, but also covers the side surface of the first doped layer close to the second doped layer, and covers The third doped layer on the side of the first doped layer is in contact with the second doped layer.
  • the solar cell further includes a first interface layer, and the first interface layer is located between the semiconductor substrate and the first doped layer;
  • the second interface layer extends from the surface of the first doped layer away from the first interface layer to its side, and continues to extend and extend to cover the semiconductor substrate. Covering a portion of the first doped layer, and the second doped layer and the third doped layer are respectively disposed on one side surface of the second interface layer;
  • a back passivation layer is further included, and the back passivation layer covers the third doped layer and the second doped layer.
  • the width of the first doped layer is the same as that of the third doped layer, and there is an isolation region between the first doped layer and the third doped layer and the second doped layer.
  • first interface layer is also included, and the first interface layer is located between the semiconductor substrate and the first doped layer;
  • the second interface layer is located between the first doped layer and the third doped layer and between the second doped layer and the semiconductor substrate;
  • a back passivation layer is further included, and the back passivation layer covers the third doped layer, the isolation region and the second doped layer.
  • the first electrode is in contact with a region of the third doped layer having the same conductivity type as the first doped layer through the back passivation layer; the first electrode The second electrode is in contact with the second doped layer through the back passivation layer.
  • the solar cell is prepared by the aforementioned method.
  • the solar cell provided by the present disclosure only needs to be patterned once, that is, the preparation of doped semiconductors in two regions can be completed. Moreover, in the doped region prepared by the method, both poles are passivated contact structures, the passivation effect is good, and the recombination rate of the metal region is greatly reduced, thereby improving the efficiency of the battery. Moreover, this back-contact preparation method only requires one high-temperature heat treatment, which reduces thermal damage caused by high-temperature heat treatment.
  • FIG. 1 is a schematic structural diagram of a solar cell provided by the present disclosure.
  • FIG. 2 is a schematic structural diagram of a solar cell provided by the present disclosure.
  • the present disclosure provides two kinds of solar cells, specifically as follows:
  • the first type of solar cell includes a semiconductor substrate 1, which is divided into a first region and a second region on one side of the semiconductor substrate 1, and a part of the semiconductor substrate 1 in the first region
  • the side surface is provided with the first interface layer 2, the first doped layer 3, the second interface layer 4 and the third doped layer 5 in sequence, and the same side surface of the semiconductor substrate 1 in the second region is provided with the second interface layer in sequence.
  • the second interface layer 4 extends from one side surface of the first doped layer 3 to its side surface, and covers the semiconductor substrate 1 in the second region, so
  • the third doped layer 5 not only covers the second interface layer 4 located on the side of the first doped layer 3 away from the semiconductor substrate 1, but also covers its side close to the second doped layer 6, extending
  • the third doped layer 5 to this side is in contact with said second doped layer 6 .
  • a rear passivation layer 7 covering the third doped layer 5 and the second doped layer 6 is also provided on the surface of the third doped layer 5 away from the second interface layer 4, and is located on the third doped layer 5.
  • a first electrode 8 passing through the back passivation layer 7 and in contact with the third doped layer 5 is also disposed on the back passivation layer 7 above the doped layer 5 .
  • the conductivity type of the first doped layer 3 is opposite to that of the second doped layer 6 .
  • the conductivity in at least a part of the region of the third doped layer 5 is the same as that of the first doped layer 3, and in the third doped layer 5, the conductivity type is the same as that of the first doped layer 3
  • the region of the first conductivity type is the region of the first conductivity type, and the region of the same conductivity type as the second doped layer is the second conductivity type region.
  • the first electrode 8 is in contact with the region of the first conductivity type in the third doped layer 5, and the first electrode is connected to the first doped layer 3 through the region of the first conductivity type.
  • a second electrode 9 passing through the back passivation layer 7 and in contact with the second doped layer 6 is also disposed on the back passivation layer 7 above the second doped layer 6 .
  • the first electrode 8 and the second electrode 9 can be gold, silver or aluminum.
  • the semiconductor substrate 1 is a silicon substrate or a germanium substrate.
  • the semiconductor substrate 1 can be p-type or n-type.
  • the conductivity type can be obtained by testing such as ECV, or by using a pn pen test.
  • Doping concentration can be tested using the ECV method.
  • the doping elements in the first doped layer, the second doped layer, the third doped region and the fourth doped region can be characterized by STEM or by SIMS.
  • the first interface layer 2 may be one or more of an oxide layer, a nitride layer, a carbide layer, and a hydrogenated amorphous silicon layer
  • the oxide layer includes: silicon oxide, nitrogen
  • the nitride layer includes: silicon nitride, aluminum nitride , one or more of TiN, TiCN
  • the carbides include: SiC, SiCN, etc.
  • the first interface layer 2 may be a tunneling oxide layer with a thickness of 0.5-5 nm, such as 0.5 nm, 1 nm, 1.5 nm, 2 nm, 2.5 nm, 3 nm, 3.5 nm, 4 nm, 4.5 nm or 5nm.
  • the second interface layer 4 may be one or more of an oxide layer, a nitride layer, a carbide layer, and a hydrogenated amorphous silicon layer
  • the oxide layer includes: silicon oxide, nitrogen
  • the nitride layer includes: silicon nitride, aluminum nitride , one or more of TiN, TiCN
  • the carbides include: SiC, SiCN, etc.
  • silicon oxide with a thickness of 0.5-5 nm, for example, 0.5 nm, 1 nm, 1.5 nm, 2 nm, 2.5 nm, 3 nm, 3.5 nm, 4 nm, 4.5 nm or 5 nm.
  • a front passivation layer and an anti-reflection layer are sequentially provided on the surface of the semiconductor substrate 1 away from the first interface layer 2, and the front passivation layer may be silicon nitride, silicon oxide , silicon oxynitride, aluminum oxide, silicon carbide, and amorphous silicon.
  • the first doped layer 3 may be a doped amorphous silicon layer, a microcrystalline silicon layer, a polysilicon layer, nano-silicon or one or more mixtures thereof, preferably a doped amorphous silicon layer.
  • amorphous silicon does not need to be annealed separately, and can be annealed in the subsequent various doping or heating processes, and relatively speaking, the process time will be saved.
  • the thickness of the first doped layer 3 is 50-300nm, such as 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 110nm, 120nm, 130nm, 140nm, 150nm, 160nm, 170nm, 180nm, 190nm, 200nm, 210nm, 220nm, 230nm, 240nm, 250nm, 260nm, 270nm, 280nm, 290nm or 300nm.
  • the second doped layer 6 can be a doped amorphous silicon layer, a doped microcrystalline silicon layer, a polysilicon layer, nano-silicon or one or more mixtures thereof, preferably doped amorphous silicon layer, because the preparation temperature of amorphous silicon is lower, relatively speaking, the process time will be saved, and the thickness of the second doped layer 6 is less than or equal to 150nm, for example, it can be 15nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm , 80nm, 90nm, 100nm, 110nm, 120nm, 130nm, 140nm or 150nm.
  • the third doped layer 5 can be doped amorphous silicon layer, microcrystalline silicon layer, polysilicon layer, nano-silicon or one or more mixtures thereof, preferably, the third doped
  • the layer 5 and the second doped layer 6 are of the same substance, and the thickness of the third doped layer 5 is less than or equal to 150 nm.
  • it may be 15nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 110nm, 120nm, 130nm, 140nm or 150nm.
  • the third doped layer 5 and the second doped layer 6 have the same thickness.
  • the first dopant layer 3 has a first dopant and a second dopant, and the peak dopant concentration of the first dopant is greater than the peak dopant concentration of the second dopant. impurity concentration;
  • the third doped layer 5 has a first dopant and a second dopant
  • the peak doping concentration of the first dopant in at least part of the region of the third doped layer 5 is greater than the peak doping concentration of the second dopant, so at least part of the third doped layer 5
  • the conductivity in the region is the same as that of the first doped layer 3 .
  • the second doped layer 6 is n-type.
  • the second doped layer 6 is p-type.
  • the p-type conductive dopant is generally IIIA group elements, such as gallium Ga, or boron B .
  • the n-type dopant is generally VA element, such as phosphorus P element.
  • the peak doping concentration of the first dopant is 1 ⁇ 10 19 to 3 ⁇ 10 21 atoms/cm 3 , for example, 1 ⁇ 10 19 atoms/cm 3 cm 3 , 2 ⁇ 10 19 atoms/cm 3 , 3 ⁇ 10 19 atoms/cm 3 , 4 ⁇ 10 19 atoms/cm 3 , 5 ⁇ 10 19 atoms/cm 3 , 6 ⁇ 10 19 atoms/cm 3 , 7 ⁇ 10 19 atoms/cm 3 , 8 ⁇ 10 19 atoms/cm 3 , 9 ⁇ 10 19 atoms/cm 3 , 1 ⁇ 10 20 atoms/cm 3 , 2 ⁇ 10 20 atoms/cm 3 , 3 ⁇ 10 20 atoms/cm 3 3 , 4 ⁇ 10 20 atoms/cm 3 , 5 ⁇ 10 20 atoms/cm 3 , 6 ⁇ 10 20 atoms/cm 3 , 7 ⁇ 10 20 atoms/cm 3 , 8
  • the peak doping concentration of the second dopant is 1 ⁇ 10 19 to 3 ⁇ 10 19 atoms/cm 3 , for example, 1 ⁇ 10 19 atoms/cm 3 , 2 ⁇ 10 19 atoms/cm 3 or 3 ⁇ 10 19 atoms/cm 3 .
  • the peak doping concentration of the first dopant in at least some regions is 1 ⁇ 10 20 -5 ⁇ 10 20 atoms/cm 3 , for example, 1 ⁇ 10 20 atoms/cm 3 . cm 3 , 2 ⁇ 10 20 atoms/cm 3 , 3 ⁇ 10 20 atoms/cm 3 , 4 ⁇ 10 20 atoms/cm 3 or 5 ⁇ 10 20 atoms/cm 3 .
  • the first dopant is a Group VA element or a Group IIIA element, preferably a Group VA element
  • the second dopant is a Group VA element or a Group IIIA element, preferably Group IIIA elements.
  • the first dopant is phosphorus, gallium or boron, preferably phosphorus
  • the second dopant is phosphorus, gallium or boron, preferably boron.
  • a dopant is a substance that is doped by a dopant, for example, when the dopant is POCl 3 , the dopant is phosphorus.
  • Phosphorus-containing dopants generally include: POCl 3 (generally used in thermal diffusion), PH 3 (phosphine, used in ion implantation, or in-situ doping, etc.), phosphorus-containing silicon oxide (APCVD method doping )wait.
  • Boron-containing dopants generally include: BBr 3 , BCl 3 (both BBr 3 and BCl 3 are used for thermal diffusion), B 2 H 6 (diborane is generally used for in-situ doping or ion implantation).
  • the doping concentration of the first dopant ranges from one side surface away from the semiconductor substrate 1 to one side surface close to the semiconductor substrate 1
  • the doping concentration first increases and then decreases; the doping concentration of the second dopant decreases gradually.
  • the doping concentration of the second dopant is equal from the side surface away from the semiconductor substrate 1 to the doping concentration of the side surface close to the semiconductor substrate 1;
  • the doping concentration of the first dopant is from the side surface far away from the first doped layer 3 to the side surface close to the first doped layer 3
  • the doping concentration of the second dopant increases gradually; the doping concentration of the second dopant is the same from the side surface away from the semiconductor substrate 1 to the side surface close to the semiconductor substrate 1 .
  • the concentration of the first dopant is greater than the concentration of the second dopant, and the entire third dopant
  • the conductivity type of the doped layer 5 is the same as that of the first doped layer 3 .
  • the concentration of part of the first dopant is greater than the concentration of the second dopant, and part of the third doped layer 5 in this part
  • the conductivity type is the same as that of the first doped layer 3 , the concentration of part of the first dopant is smaller than that of the second dopant, and the conductivity type of this part is opposite to that of the first doped layer 3 .
  • the thickness d of the third doped layer 5 is between 30nm-150nm, in the third doped layer 5, in the area close to the first doped layer 3, at least part of the area
  • the conductivity is the same as the conductivity type of the first doped layer 3 , and the first electrode penetrates the back passivation layer 7 into the third doped layer and contacts the region of the first conductivity type.
  • the thickness of the third doped layer 5 is 30nm ⁇ d ⁇ 150nm
  • the region of the same conductivity type as the first doped layer 3 penetrates through the thickness direction
  • the first electrode is in direct contact with the region of the first conductivity type through the back passivation layer.
  • the first dopant or the first dopant and the second dopant pass through the first dopant
  • the interface layer 2 enters into the semiconductor substrate 1 to form a third doped region 11, that is, the third doped region 11 contains the first dopant or the first dopant and the second dopant.
  • the second dopant penetrates the second interface layer 4 into the semiconductor substrate 1 to form a fourth doped region 12 , that is, the fourth doped region 12 contains the second dopant.
  • the semiconductor substrate 1 only has the third doped region 11 .
  • the semiconductor substrate 1 has a fourth doped region 12 in it.
  • the semiconductor substrate 1 contains both the third doped region 11 and the fourth doped region 12 .
  • the preparation method of the first solar cell comprises the steps of:
  • Step 1 providing a semiconductor substrate 1;
  • Step 2 forming a first doped layer 3 on the first surface of the semiconductor substrate 1;
  • Step 3 Patterning the first doped layer 3, thereby retaining part of the first doped layer 3;
  • Step 4 Form a third doped layer 5 on the surface of the first doped layer 3 facing away from the semiconductor substrate 1 through heat treatment, and form a third doped layer 5 on the surface of the semiconductor substrate 1 that does not cover the first doped layer 3 On one surface, a second doped layer 6 is formed,
  • the first doped layer 3 has a first dopant and a second dopant
  • the third doped layer 5 has a first dopant and a second dopant
  • the conductivity type of the first doped layer 3 is opposite to that of the second doped layer 6;
  • the conductivity type of at least a part of the third doped layer 5 is the same as that of the first doped layer 3 .
  • step 2 use LPCVD to form a first interface layer 2 on one side of the semiconductor substrate 1 at a temperature of 400-700° C., on the side of the first interface layer 2 away from the semiconductor substrate 1
  • the first doped layer 3 is formed by in-situ doping LPCVD.
  • step 2 using LPCVD to form a first interface layer 2 on one side of the semiconductor substrate 1 at a temperature of 400-700° C., on the side of the first interface layer 2 away from the semiconductor substrate 1 A first semiconductor layer is formed on the surface, and the first dopant is doped into the first semiconductor layer by diffusion, thereby forming the first doped layer 3 .
  • the first semiconductor layer may be a polycrystalline silicon layer, a microcrystalline silicon layer or an amorphous silicon layer.
  • the peak doping concentration of the first dopant in the first doped layer 3 is 1 ⁇ 10 19 -5 ⁇ 10 21 atoms/cm 3 .
  • Step 3 a first auxiliary layer is formed on the surface of the first doped layer 3 facing away from the semiconductor substrate 1, and then the first auxiliary layer and the first doped layer 3 above the second region are engraved etch away to complete the patterning, leaving only the first doped layer 3 in the first region.
  • the first auxiliary layer may be a dielectric film such as silicon oxide or silicon nitride.
  • the aforementioned silicon oxide film formed upon doping with phosphorus may be used as the first auxiliary layer.
  • the first auxiliary layer is patterned, for example, using etching paste to print patterns to remove the first auxiliary layer, the first doped layer 3 and the first interface layer 2 outside the first region, or using a short pulse laser to remove The first auxiliary layer, the first doped layer 3 and the first interface layer 2 outside the first region.
  • an alkaline solution is used to remove the first doped layer 3 and the first interface layer 2 outside the first region, and the same alkaline solution is used to form a textured surface on the surface of the semiconductor substrate 1 in the second region structure.
  • the lye is used to complete the patterning of the first doped layer 3 in the first region, and at the same time complete the texture preparation of the second region.
  • the IBC preparation process is greatly simplified, and the currently commonly used single-side texturing process can be dispensed with.
  • Method 1 First, double-sided polishing of the silicon wafer, and then prepare the first auxiliary layer on one side, and then remove the first auxiliary layer after the texturing is completed.
  • Method 2 firstly polish both sides of the silicon wafer, then prepare the first auxiliary layer on one side, then polish on one side, and then remove the first auxiliary layer.
  • the existing two single-side texturing methods are relatively complicated, and the single-side texturing process must be completed at the very beginning of the battery manufacturing process. It takes at least four steps to complete.
  • the suede surface may be damaged in the subsequent normal battery preparation process, which reduces the antireflection effect of the suede surface of the battery.
  • the second interface layer 4 may be formed first, and the second interface layer 4 not only covers the first doped layer but faces away from the semiconductor substrate. one side surface and the side surface of the semiconductor substrate, and also cover the first surface of the semiconductor substrate not covered by the first doped layer.
  • in-situ doping LPCVD is used to form the second doped layer 6 on the surface of the second interface layer 4 away from the semiconductor substrate 1 and the first doped layer 3, and the in-situ doped Miscellaneous refers to the simultaneous completion of deposition of amorphous silicon doping.
  • the heat treatment is laser treatment or heat treatment.
  • the region directly irradiated by the laser is the first conductivity type region (the The region of the first conductivity type runs through the third doped layer 5) along the thickness direction, its conductivity type is the same as that of the first doped layer 3, and the doping concentration of the first dopant is greater than that of the second dopant Doping concentration of dopant.
  • the power of laser treatment is greater than 5W, preferably 5W-30W, and the heating effect is better. If the wavelength is longer than 500nm, you can use green laser: wavelength 532nm; yellow laser: wavelength 589nm; red laser: wavelength 635nm, wavelength 660nm, wavelength 660nm, wavelength 670nm, wavelength 671nm; infrared laser: wavelength 808nm, wavelength 914nm, wavelength 946nm , Wavelength 980nm, Wavelength 1047nm, Wavelength 1053nm, Wavelength 1064nm, Wavelength 1320nm, Wavelength 1342nm.
  • a second semiconductor layer is formed on the surface of the second interface layer 4 facing away from the semiconductor substrate 1 and the first doped layer 3, and the second doped layer is The dopant diffuses into the second semiconductor layer, and due to the high temperature, the first dopant in the first doped layer 3 will also diffuse into the second semiconductor layer above it, so that the The second semiconductor layer above the first doped layer 3 is the third doped layer 5 , and the second semiconductor layer on the first surface of the semiconductor substrate 1 is the second doped layer 6 .
  • the conductivity of at least a part of the region is the same as that of the first doped layer 3 .
  • the peak doping concentration of the first dopant in the first doped layer 3 is 1 ⁇ 10 19 to 3 ⁇ 10 21 atoms/cm 3
  • the peak doping concentration of the second dopant is 1 ⁇ 10 19 to 3 ⁇ 10 19 atoms/cm 3 .
  • the peak doping concentration of the first dopant in a partial region of the third doped layer 5 is 1 ⁇ 10 20 -5 ⁇ 10 20 atoms/cm 3
  • the peak doping concentration of the second dopant is 1 ⁇ 10 20 atoms/cm 3 . 10 19 to 3 ⁇ 10 19 atoms/cm 3 .
  • the peak doping concentration of the second dopant in the second doped layer 6 is 1 ⁇ 10 19 -3 ⁇ 10 19 atoms/cm 3 .
  • the heating peak temperature of the heat treatment is above 850°C, preferably above 900°C, more preferably 1000°C, such as 850°C, 900°C, 1000°C, 1100°C, 1200°C, etc.;
  • the heating time is more than 10 minutes, preferably more than 30 minutes, for example, it can be 10 minutes, 20 minutes, 30 minutes, 40 minutes, 50 minutes, 60 minutes and so on.
  • the second semiconductor layer may be a polycrystalline silicon layer, a microcrystalline silicon layer or an amorphous silicon layer. Due to the high peak temperature of the heat treatment, the amorphous silicon or microcrystalline silicon in the second semiconductor layer will be converted into polysilicon, so that the electrical conductivity of the second semiconductor layer can be improved.
  • the solution used to remove the oxide film layer contains fluorine element, specifically, a solution containing HF or NH 4 F, etc. may be used. removing the oxide film layer.
  • the method also includes the steps of:
  • Step 5 Form a back passivation layer 7 on the surface of the third doped layer 5 and the second doped layer 6 facing away from the second interface layer 4, and at the same time, form a back passivation layer 7 on the semiconductor substrate 1 facing away from the first interface layer 4.
  • One side surface of the interface layer 2 forms a front passivation layer.
  • Step 6 forming a first electrode 8 penetrating through the back passivation layer 7 above the third doped layer 5 , and at the same time, forming a penetrating through the back passivation layer above the second doped layer 6 7 of the second electrode 9 .
  • the electrodes there are various methods for forming the electrodes, which can be directly coated on the back passivation layer 7 with a fire-through paste, and then undergo heat treatment so that the electrode paste passes through the back passivation layer 7 and the third doped layer 5 And the second doped layer 6 forms a contact. It is also possible to open holes on the back passivation layer 7 first, and then use methods such as electrode paste, laser transfer printing, electroplating, electroless plating, light-induced electroplating, or physical vapor deposition such as evaporation and sputtering to form electrodes. Obviously, one or a combination of the above methods can also be used to form electrodes.
  • the preparation method of the first solar cell comprises the steps of:
  • Step 1 providing a semiconductor substrate 1;
  • Step 2 forming a first doped layer 3 on the first surface of the semiconductor substrate 1;
  • the first interface layer 2 is formed on one side of the semiconductor substrate 1 by LPCVD at a temperature of 400-700° C.
  • Bit doping LPCVD forms the first doped layer 3 .
  • step 2 using LPCVD to form a first interface layer 2 on one side of the semiconductor substrate 1 at a temperature of 400-700° C., on the side of the first interface layer 2 away from the semiconductor substrate 1 A first semiconductor layer is formed on the surface, and the first dopant is doped into the first semiconductor layer by diffusion, thereby forming the first doped layer 3 .
  • the first semiconductor layer may be a polycrystalline silicon layer, a microcrystalline silicon layer or an amorphous silicon layer.
  • the peak doping concentration of the first dopant in the first doped layer 3 is 1 ⁇ 10 19 -5 ⁇ 10 21 atoms/cm 3 .
  • Step 3 Patterning the first doped layer 3, thereby retaining part of the first doped layer 3;
  • a first auxiliary layer is formed on the surface of the first doped layer 3 facing away from the semiconductor substrate 1, and then the first auxiliary layer and the first doped layer 3 above the second region are etched away. , so as to complete the patterning, leaving only the first doped layer 3 in the first region.
  • the first auxiliary layer may be a dielectric film such as silicon oxide or silicon nitride.
  • the aforementioned silicon oxide film formed upon doping with phosphorus may be used as the first auxiliary layer.
  • the first auxiliary layer is patterned, for example, using etching paste to print patterns to remove the first auxiliary layer, the first doped layer 3 and the first interface layer 2 outside the first region, or using a short pulse laser to remove The first auxiliary layer, the first doped layer 3 and the first interface layer 2 outside the first region.
  • an alkaline solution is used to remove the first doped layer 3 and the first interface layer 2 outside the first region, and the same alkaline solution is used to form a textured surface on the surface of the semiconductor substrate 1 in the second region structure.
  • the lye is used to complete the patterning of the first doped layer 3 in the first region, and at the same time complete the texture preparation of the second region.
  • the IBC preparation process is greatly simplified, and the currently commonly used single-side texturing process can be dispensed with.
  • Method 1 First, double-sided polishing of the silicon wafer, and then prepare the first auxiliary layer on one side, and then remove the first auxiliary layer after the texturing is completed.
  • Method 2 firstly polish both sides of the silicon wafer, then prepare the first auxiliary layer on one side, then polish on one side, and then remove the first auxiliary layer.
  • the existing two single-side texturing methods are relatively complicated, and the single-side texturing process must be completed at the very beginning of the battery manufacturing process. It takes at least four steps to complete.
  • the suede surface may be damaged in the subsequent normal battery preparation process, which reduces the antireflection effect of the suede surface of the battery.
  • Step 4 Form a third doped layer 5 on the surface of the first doped layer 3 facing away from the semiconductor substrate 1 through heat treatment, and form a third doped layer 5 on the surface of the semiconductor substrate 1 that does not cover the first doped layer 3 On one surface, a second doped layer 6 is formed.
  • the first doped layer 3 has a first dopant and a second dopant
  • the third doped layer 5 has a first dopant and a second dopant
  • the conductivity type of the first doped layer 3 is opposite to that of the second doped layer 6;
  • the conductivity type of at least a part of the third doped layer 5 is the same as that of the first doped layer 3 .
  • the second interface layer 4 can also be formed first, and the second interface layer 4 not only covers a part of the first doped layer away from the semiconductor substrate.
  • the second doped layer 6 is formed by in-situ doping LPCVD on the surface of the second interface layer 4 facing away from the semiconductor substrate 1 and the first doped layer 3 . Then heat-treat the second doped layer 6 above the first doped layer 3, so that the first dopant in the first doped layer 3 diffuses into the second doped layer 6 thereon , the second dopant in the second doped layer 6 above the first doped layer will also diffuse into the first doped layer 3, so that the second doped layer above the first doped layer 3
  • the doped layer 6 is transformed into the third doped layer 5 ; the second doped layer 6 not covering the first surface of the first doped layer 3 is still the second doped layer 6 .
  • the heat treatment is laser treatment or heat treatment.
  • the region directly irradiated by the laser is the first conductivity type region (the The region of the first conductivity type runs through the third doped layer 5) along the thickness direction, its conductivity type is the same as that of the first doped layer 3, and the doping concentration of the first dopant is greater than that of the second dopant Doping concentration of dopant.
  • the power of laser treatment is greater than 5W, preferably 5W-30W, and the heating effect is better.
  • green laser wavelength 532nm; yellow laser: wavelength 589nm; red laser: wavelength 635nm, wavelength 660nm, wavelength 660nm, wavelength 670nm, wavelength 671nm; infrared laser: wavelength 808nm, wavelength 914nm, wavelength 946nm , Wavelength 980nm, Wavelength 1047nm, Wavelength 1053nm, Wavelength 1064nm, Wavelength 1320nm, Wavelength 1342nm.
  • a second semiconductor layer is formed on the surface of the second interface layer 4 away from the semiconductor substrate 1 and the first doped layer 3, and the second doped layer is The dopant diffuses into the second semiconductor layer, and due to the high temperature, the first dopant in the first doped layer 3 will also diffuse into the second semiconductor layer above it, so that The second semiconductor layer above the first doped layer 3 is the third doped layer 5 , and the second semiconductor layer on the first surface of the semiconductor substrate 1 is the second doped layer 6 .
  • the conductivity of at least a part of the region is the same as that of the first doped layer 3 .
  • the peak doping concentration of the first dopant in the first doped layer 3 is 1 ⁇ 10 19 to 3 ⁇ 10 21 atoms/cm 3
  • the peak doping concentration of the second dopant is 1 ⁇ 10 19 ⁇ 3 ⁇ 10 19 atoms/cm 3 .
  • the peak doping concentration of the first dopant in a partial region of the third doped layer 5 is 1 ⁇ 10 20 -5 ⁇ 10 20 atoms/cm 3
  • the peak doping concentration of the second dopant is 1 ⁇ 10 20 atoms/cm 3 . 10 19 to 3 ⁇ 10 19 atoms/cm 3 .
  • the peak doping concentration of the second dopant in the second doped layer 6 is 1 ⁇ 10 19 -3 ⁇ 10 19 atoms/cm 3 .
  • the heating peak temperature under the heat treatment or heating conditions is above 850°C, preferably above 900°C, more preferably 1000°C, for example, it can be 850°C, 900°C, 1000°C, 1100°C, 1200°C °C, etc.; at the peak temperature, the heating time is 10 min or more, preferably 30 min or more, for example, 10 min, 20 min, 30 min, 40 min, 50 min, 60 min, etc.
  • the second semiconductor layer may be a polycrystalline silicon layer, a microcrystalline silicon layer or an amorphous silicon layer. Due to the high peak temperature of the heat treatment, the amorphous silicon or microcrystalline silicon in the second semiconductor layer will be converted into polysilicon, so that the electrical conductivity of the second semiconductor layer can be improved.
  • the solution used to remove the oxide film layer contains fluorine element, specifically, a solution containing HF or NH 4 F, etc. may be used. removing the oxide film layer.
  • Step 5 Form a back passivation layer 7 on the surface of the third doped layer 5 and the second doped layer 6 facing away from the second interface layer 4, and at the same time, form a back passivation layer 7 on the semiconductor substrate 1 facing away from the first interface layer 4.
  • One side surface of the interface layer 2 forms a front passivation layer.
  • Step 6 forming a first electrode 8 penetrating through the back passivation layer 7 above the third doped layer 5 , and at the same time, forming a penetrating through the back passivation layer above the second doped layer 6 7 of the second electrode 9 .
  • the electrodes there are various methods for forming the electrodes, which can be directly coated on the back passivation layer 7 with a fire-through paste, and then undergo heat treatment so that the electrode paste passes through the back passivation layer 7 and the third doped layer 5 And the second doped layer 6 forms a contact. It is also possible to open holes on the back passivation layer 7 first, and then use methods such as electrode paste, laser transfer printing, electroplating, electroless plating, light-induced electroplating, or physical vapor deposition such as evaporation and sputtering to form electrodes. Obviously, one or a combination of the above methods can also be used to form electrodes.
  • the second type of solar cell includes a semiconductor substrate 1, which is divided into a first region and a second region with intervals on one side of the semiconductor substrate 1, and the semiconductor substrate in the first region
  • a first interface layer 2 a first doped layer 3, a second interface layer 4, and a third doped layer 5 are sequentially provided on one side surface of the semiconductor substrate 1, and the same side surface of the semiconductor substrate 1 in the second region is sequentially
  • a second interface layer 4 and a second doped layer 6 are provided.
  • a groove is formed on the surface of the semiconductor substrate 1 of the doped layer 6, the second interface layer 4, and the side of the second doped layer 6 close to the first doped layer 3, and the groove is an isolation region 10.
  • a backside passivation layer 7 covering the third doped layer 5 , the isolation region 10 and the second doped layer 6 is also provided on the surface of the third doped layer 5 away from the second interface layer 4 .
  • the back passivation layer 7 above the third doped layer 5 is also provided with a first electrode 8 passing through the back passivation layer 7 and in contact with the third doped layer 5, located on the second A second electrode 9 passing through the back passivation layer 7 and in contact with the second doped layer 6 is also disposed on the back passivation layer 7 above the doped layer 6 .
  • the difference between the second type of solar cell and the first type of solar cell is only that there is an isolation region 10 between the first region and the second region in the second type of solar cell, and there is only a rear passivation layer in the isolation region 10 7 (the third doped layer 5 is not in contact with the second doped layer 6), so the semiconductor substrate 1, the first interface layer 2, the second interface layer 4, the first doped layer 3, The second doped layer 6, the third doped layer 5, the back passivation layer 7, and the first electrode 8 and the second electrode 9 can refer to the first solar cell,
  • the depth h of the isolation region 10 is 300nm-1 ⁇ m, such as 300nm, 400nm, 500nm, 600nm, 700nm, 800nm, 900nm or 1 ⁇ m.
  • the width w of the isolation region 10 is 10-200 ⁇ m, preferably 30-100 ⁇ m. For example, it may be 10 ⁇ m, 20 ⁇ m, 30 ⁇ m, 40 ⁇ m, 50 ⁇ m, 60 ⁇ m, 70 ⁇ m, 80 ⁇ m, 90 ⁇ m, 100 ⁇ m, 110 ⁇ m, 120 ⁇ m, 130 ⁇ m, 140 ⁇ m, 150 ⁇ m, 160 ⁇ m, 170 ⁇ m, 180 ⁇ m, 190 ⁇ m or 200 ⁇ m.
  • the rear passivation layer 7 located at the isolation region 10 is conformal to the isolation region 10 .
  • the isolation region 10 is used to isolate the p-type and n-type semiconductor regions, so as to prevent electric leakage, and prevent the breakdown of lateral pn junctions to cause heat generation and the like.
  • the first doped region since the first doped region has both p-type doping and n-type doping, the existence of the isolation region 10 is more important.
  • the thickness of the back passivation layer 7 on the first doped layer 3 , the isolation region 10 and the second doped layer 6 is equal.
  • a second method for preparing a solar cell comprising the steps of:
  • Step 1 providing a semiconductor substrate 1;
  • Step 2 forming a first doped layer 3 on one side surface of the semiconductor substrate 1;
  • Step 3 Patterning the first doped layer 3, thereby retaining part of the first doped layer 3;
  • Step 4 Form a third doped layer 5 on the surface of the first doped layer 3 facing away from the semiconductor substrate 1 through heat treatment, and form a third doped layer 5 on the surface of the semiconductor substrate 1 that does not cover the first doped layer 3 On one surface, a second doped layer 6 is formed;
  • Step 5 Form a second auxiliary layer on the surface of the third doped layer 5 and the second doped layer 6 facing away from the second interface layer 4 respectively, close to the third doped layer 5 and the second The junction of the doped layer 6 is not covered by the second auxiliary layer.
  • Step 6 Etching away the third doped layer 5 and the second doped layer 6 that do not cover the second auxiliary layer, thereby exposing the semiconductor substrate 1 (the exposed semiconductor substrate 1 is called an isolation region 10), the The third doped layer 5, the second interface layer 4, the first doped layer 3 and the first interface layer 2 are close to the side of the isolation region 10, the surface of the semiconductor substrate 1 of the isolation region 10, the second interface layer 4, the second interface layer 2 An isolation region 10 is formed on the side of the second doped layer 6 close to the isolation region 10 .
  • the first doped layer 3 has a first dopant and a second dopant
  • the third doped layer 5 has a first dopant and a second dopant
  • the conductivity type of the first doped layer 3 is opposite to that of the second doped layer 6;
  • the conductivity type of at least a part of the third doped layer 5 is the same as that of the first doped layer.
  • LPCVD is used to form the first interface layer 2 on one side of the semiconductor substrate 1 at a temperature of 400-700°C.
  • the first doped layer 3 is formed on the surface of the first interface layer 2 facing away from the semiconductor substrate 1 by in-situ doping LPCVD.
  • a first semiconductor layer is formed on the surface of the first interface layer 2 facing away from the semiconductor substrate 1, and the first dopant is doped into the first semiconductor layer. , thereby forming the first doped layer 3 .
  • the first semiconductor layer may be a polycrystalline silicon layer, a microcrystalline silicon layer or an amorphous silicon layer.
  • the peak doping concentration of the first dopant in the first doped layer 3 is 1 ⁇ 10 19 -5 ⁇ 10 21 atoms/cm 3 .
  • Step 3 a first auxiliary layer is formed on the surface of the first doped layer 3 facing away from the semiconductor substrate 1, and then the first auxiliary layer and the first doped layer 3 above the second region are engraved etch away to complete the patterning, leaving only the first doped layer 3 in the first region.
  • the first auxiliary layer may be a dielectric film such as silicon oxide or silicon nitride.
  • the aforementioned silicon oxide film formed upon doping with phosphorus may be used as the first auxiliary layer.
  • the first auxiliary layer is patterned, for example, using etching paste to print patterns to remove the first auxiliary layer, the first doped layer 3 and the first interface layer 2 outside the first region, or using a short pulse laser to remove The first auxiliary layer, the first doped layer 3 and the first interface layer 2 outside the first region.
  • an alkaline solution is used to remove the first doped layer 3 and the first interface layer 2 outside the first region, and the same alkaline solution is used to form a textured surface on the surface of the semiconductor substrate 1 in the second region structure.
  • the lye is used to complete the patterning of the first doped layer 3 in the first region, and at the same time complete the texture preparation of the second region.
  • the IBC preparation process is greatly simplified, and the currently commonly used single-side texturing process can be dispensed with.
  • Method 1 First, double-sided polishing of the silicon wafer, and then prepare the first auxiliary layer on one side, and then remove the first auxiliary layer after the texturing is completed.
  • Method 2 firstly polish both sides of the silicon wafer, then prepare the first auxiliary layer on one side, then polish on one side, and then remove the first auxiliary layer.
  • the existing two single-side texturing methods are relatively complicated, and the single-side texturing process must be completed at the very beginning of the battery manufacturing process. It takes at least four steps to complete.
  • the suede surface may be damaged in the subsequent normal battery preparation process, which reduces the antireflection effect of the suede surface of the battery.
  • the second interface layer 4 may be formed first, and the second interface layer 4 not only covers the first doped layer but faces away from the semiconductor substrate. one side surface and the side surface of the semiconductor substrate, and also cover the first surface of the semiconductor substrate not covered by the first doped layer.
  • in-situ doping LPCVD is used to form the second doped layer 6 on the surface of the second interface layer 4 away from the semiconductor substrate 1 and the first doped layer 3, and the in-situ doped Miscellaneous refers to the simultaneous completion of deposition of amorphous silicon doping.
  • the heat treatment is laser treatment or heat treatment.
  • the region directly irradiated by the laser is the first conductivity type region (the The region of the first conductivity type runs through the third doped layer 5) along the thickness direction, its conductivity type is the same as that of the first doped layer 3, and the doping concentration of the first dopant is greater than that of the second dopant Doping concentration of dopant.
  • the power of laser treatment is greater than 5W, preferably 5W-30W, and the heating effect is better.
  • green laser wavelength 532nm; yellow laser: wavelength 589nm; red laser: wavelength 635nm, wavelength 660nm, wavelength 660nm, wavelength 670nm, wavelength 671nm; infrared laser: wavelength 808nm, wavelength 914nm, wavelength 946nm , Wavelength 980nm, Wavelength 1047nm, Wavelength 1053nm, Wavelength 1064nm, Wavelength 1320nm, Wavelength 1342nm.
  • a second semiconductor layer is formed on the surface of the second interface layer 4 facing away from the semiconductor substrate 1 and the first doped layer 3, and the second doped layer is The dopant diffuses into the second semiconductor layer, and due to the high temperature, the first dopant in the first doped layer 3 will also diffuse into the second semiconductor layer above it, so that the The second semiconductor layer above the first doped layer 3 is the third doped layer 5 , and the second semiconductor layer on the first surface of the semiconductor substrate 1 is the second doped layer 6 .
  • the conductivity of at least a part of the region is the same as that of the first doped layer 3 .
  • the peak doping concentration of the first dopant in the first doped layer 3 is 1 ⁇ 10 19 to 3 ⁇ 10 21 atoms/cm 3
  • the peak doping concentration of the second dopant is 1 ⁇ 10 19 ⁇ 3 ⁇ 10 19 atoms/cm 3 .
  • the peak doping concentration of the first dopant in a partial region of the third doped layer 5 is 1 ⁇ 10 20 -5 ⁇ 10 20 atoms/cm 3
  • the peak doping concentration of the second dopant is 1 ⁇ 10 20 atoms/cm 3 . 10 19 to 3 ⁇ 10 19 atoms/cm 3 .
  • the peak doping concentration of the second dopant in the second doped layer 6 is 1 ⁇ 10 19 -3 ⁇ 10 19 atoms/cm 3 .
  • the heating peak temperature under the heat treatment or heating conditions is above 850°C, preferably above 900°C, more preferably 1000°C, for example, it can be 850°C, 900°C, 1000°C, 1100°C, 1200°C °C, etc.; at the peak temperature, the heating time is 10 min or more, preferably 30 min or more, for example, 10 min, 20 min, 30 min, 40 min, 50 min, 60 min, etc.
  • the second semiconductor layer may be a polycrystalline silicon layer, a microcrystalline silicon layer or an amorphous silicon layer. Due to the high peak temperature of the heat treatment, the amorphous silicon or microcrystalline silicon in the second semiconductor layer will be converted into polysilicon, so that the electrical conductivity of the second semiconductor layer can be improved.
  • the solution used to remove the oxide film layer contains fluorine element, specifically, a solution containing HF or NH 4 F, etc. may be used. removing the oxide film layer.
  • the second auxiliary layer may be a dielectric film such as silicon oxide or silicon nitride.
  • step six the third doped layer 5 , the second doped layer 6 and the second interface layer 4 thereunder are removed by using etching slurry or laser.
  • the isolation region 10 when removing the third doped layer 5, the second doped layer 6 and the second interface layer 4 below it, part of the semiconductor substrate 1 below the second interface layer 4 can be further removed, thereby deepening the isolation region 10 The deeper the isolation zone 10 is, the better the isolation effect will be. Because in general, a certain amount of dopants in the first semiconductor layer or the second semiconductor layer will pass through the interface layer and come into the semiconductor substrate, so the doping in the semiconductor substrate 1 is also as described above, there will be The risk of electric leakage or breakdown heating, so the isolation region 10 extends into the semiconductor substrate 1 can reduce the risk of leakage or breakdown heating.
  • the second auxiliary layer is removed.
  • the method also includes the steps of:
  • Step 7 Form a back passivation layer 7 on the surface of the third doped layer 5 and the second doped layer 6 facing away from the second interface layer 4, and at the same time, form a back passivation layer 7 on the semiconductor substrate 1 facing away from the first One side surface of the interface layer 2 forms a front passivation layer.
  • Step 8 Form a first electrode 8 penetrating through the back passivation layer 7 above the third doped layer 5, and at the same time, form a penetrating through the back passivation layer above the second doped layer 6 7 of the second electrode 9 .
  • the electrodes there are various methods for forming the electrodes, which can be directly coated on the back passivation layer 7 with a fire-through paste, and then undergo heat treatment so that the electrode paste passes through the back passivation layer 7 and the third doped layer 5 And the second doped layer 6 forms a contact. It is also possible to open holes on the back passivation layer 7 first, and then use methods such as electrode paste, laser transfer printing, electroplating, electroless plating, light-induced electroplating, or physical vapor deposition such as evaporation and sputtering to form electrodes. Obviously, one or a combination of the above methods can also be used to form electrodes.
  • a second method for preparing a solar cell comprising the steps of:
  • Step 1 providing a semiconductor substrate 1;
  • Step 2 forming a first doped layer 3 on one side surface of the semiconductor substrate 1;
  • LPCVD is used to form the first interface layer 2 on one side of the semiconductor substrate 1 at a temperature of 400-700°C.
  • the first doped layer 3 is formed on the surface of the first interface layer 2 away from the semiconductor substrate 1 by in-situ doping LPCVD.
  • a first semiconductor layer is formed on the surface of the first interface layer 2 facing away from the semiconductor substrate 1, and the first dopant is doped into the first semiconductor layer. , thereby forming the first doped layer 3 .
  • the first semiconductor layer may be a polycrystalline silicon layer, a microcrystalline silicon layer or an amorphous silicon layer.
  • the peak doping concentration of the first dopant in the first doped layer 3 is 1 ⁇ 10 19 -5 ⁇ 10 21 atoms/cm 3 .
  • Step 3 Patterning the first doped layer 3, thereby retaining part of the first doped layer 3;
  • a first auxiliary layer is formed on the surface of the first doped layer 3 facing away from the semiconductor substrate 1, and then the first auxiliary layer and the first doped layer 3 above the second region are etched away. , so as to complete the patterning, leaving only the first doped layer 3 in the first region.
  • the first auxiliary layer may be a dielectric film such as silicon oxide or silicon nitride.
  • the aforementioned silicon oxide film formed upon doping with phosphorus may be used as the first auxiliary layer.
  • the first auxiliary layer is patterned, for example, using etching paste to print patterns to remove the first auxiliary layer, the first doped layer 3 and the first interface layer 2 outside the first region, or using a short pulse laser to remove The first auxiliary layer, the first doped layer 3 and the first interface layer 2 outside the first region.
  • an alkaline solution is used to remove the first doped layer 3 and the first interface layer 2 outside the first region, and the same alkaline solution is used to form a textured surface on the surface of the semiconductor substrate 1 in the second region structure.
  • the lye is used to complete the patterning of the first doped layer 3 in the first region, and at the same time complete the texture preparation of the second region.
  • the IBC preparation process is greatly simplified, and the currently commonly used single-side texturing process can be dispensed with.
  • Method 1 First, double-sided polishing of the silicon wafer, and then prepare the first auxiliary layer on one side, and then remove the first auxiliary layer after the texturing is completed.
  • Method 2 firstly polish both sides of the silicon wafer, then prepare the first auxiliary layer on one side, then polish on one side, and then remove the first auxiliary layer.
  • the existing two single-side texturing methods are relatively complicated, and the single-side texturing process must be completed at the very beginning of the battery manufacturing process. It takes at least four steps to complete.
  • the suede surface may be damaged in the subsequent normal battery preparation process, which reduces the antireflection effect of the suede surface of the battery.
  • Step 4 Form a third doped layer 5 on the surface of the first doped layer 3 facing away from the semiconductor substrate 1 through heat treatment, and form a third doped layer 5 on the surface of the semiconductor substrate 1 that does not cover the first doped layer 3 On one surface, a second doped layer 6 is formed;
  • the second interface layer 4 can also be formed first, and the second interface layer 4 not only covers a part of the first doped layer away from the semiconductor substrate.
  • in-situ doping LPCVD is used to form the second doped layer 6 on the surface of the second interface layer 4 away from the semiconductor substrate 1 and the first doped layer 3, and the in-situ doped Miscellaneous refers to the simultaneous completion of deposition of amorphous silicon doping.
  • the heat treatment is laser treatment or heat treatment.
  • the region directly irradiated by the laser is the first conductivity type region (the The region of the first conductivity type runs through the third doped layer 5) along the thickness direction, its conductivity type is the same as that of the first doped layer 3, and the doping concentration of the first dopant is greater than that of the second dopant Doping concentration of dopant.
  • the power of laser treatment is greater than 5W, preferably 5W-30W, and the heating effect is better.
  • green laser wavelength 532nm; yellow laser: wavelength 589nm; red laser: wavelength 635nm, wavelength 660nm, wavelength 660nm, wavelength 670nm, wavelength 671nm; infrared laser: wavelength 808nm, wavelength 914nm, wavelength 946nm , Wavelength 980nm, Wavelength 1047nm, Wavelength 1053nm, Wavelength 1064nm, Wavelength 1320nm, Wavelength 1342nm.
  • a second semiconductor layer is formed on the surface of the second interface layer 4 facing away from the semiconductor substrate 1 and the first doped layer 3, and the second dopant diffused into the second semiconductor layer, due to the high temperature, the first dopant in the first doped layer 3 will also diffuse into the second semiconductor layer above it, so that the The second semiconductor layer above the first doped layer 3 is the third doped layer 5 , and the second semiconductor layer on the first surface of the semiconductor substrate 1 is the second doped layer 6 .
  • the conductivity of at least a part of the region is the same as that of the first doped layer 3 .
  • the peak doping concentration of the first dopant in the first doped layer 3 is 1 ⁇ 10 19 to 3 ⁇ 10 21 atoms/cm 3
  • the peak doping concentration of the second dopant is 1 ⁇ 10 19 ⁇ 3 ⁇ 10 19 atoms/cm 3 .
  • the peak doping concentration of the first dopant in a partial region of the third doped layer 5 is 1 ⁇ 10 20 -5 ⁇ 10 20 atoms/cm 3
  • the peak doping concentration of the second dopant is 1 ⁇ 10 20 atoms/cm 3 . 10 19 to 3 ⁇ 10 19 atoms/cm 3 .
  • the peak doping concentration of the second dopant in the second doped layer 6 is 1 ⁇ 10 19 -3 ⁇ 10 19 atoms/cm 3 .
  • the heating peak temperature under the heat treatment or heating conditions is above 850°C, preferably above 900°C, more preferably 1000°C, for example, it can be 850°C, 900°C, 1000°C, 1100°C, 1200°C °C, etc.; at the peak temperature, the heating time is 10 min or more, preferably 30 min or more, for example, 10 min, 20 min, 30 min, 40 min, 50 min, 60 min, etc.
  • the second semiconductor layer may be a polycrystalline silicon layer, a microcrystalline silicon layer or an amorphous silicon layer. Due to the high peak temperature of the heat treatment, the amorphous silicon or microcrystalline silicon in the second semiconductor layer will be converted into polysilicon, thereby improving the electrical conductivity of the second semiconductor layer.
  • the solution used to remove the oxide film layer contains fluorine element, specifically, a solution containing HF or NH 4 F, etc. may be used. removing the oxide film layer.
  • Step 5 Form a second auxiliary layer on the surface of the third doped layer 5 and the second doped layer 6 facing away from the second interface layer 4 respectively, close to the third doped layer 5 and the second The junction of the doped layer 6 is not covered by the second auxiliary layer.
  • the second auxiliary layer may be a dielectric film such as silicon oxide or silicon nitride.
  • Step 6 Etching away the third doped layer 5 and the second doped layer 6 that do not cover the second auxiliary layer, thereby exposing the semiconductor substrate 1 (the exposed semiconductor substrate 1 is called an isolation region 10), the The third doped layer 5, the second interface layer 4, the first doped layer 3 and the first interface layer 2 are close to the side of the isolation region 10, the surface of the semiconductor substrate 1 of the isolation region 10, the second interface layer 4, the second interface layer 2 An isolation region 10 is formed on the side of the second doped layer 6 close to the isolation region 10 .
  • the first doped layer 3 has a first dopant and a second dopant
  • the third doped layer 5 has a first dopant and a second dopant
  • the conductivity type of the first doped layer 3 is opposite to that of the second doped layer 6;
  • the conductivity type of at least a part of the third doped layer 5 is the same as that of the first doped layer.
  • etching slurry or laser is used to remove the third doped layer 5 , the second doped layer 6 and the second interface layer 4 below it.
  • the isolation region 10 when removing the third doped layer 5, the second doped layer 6 and the second interface layer 4 below it, part of the semiconductor substrate 1 below the second interface layer 4 can be further removed, thereby deepening the isolation region 10 The deeper the isolation zone 10 is, the better the isolation effect will be. Because in general, a certain amount of dopants in the first semiconductor layer or the second semiconductor layer will pass through the interface layer and come into the semiconductor substrate, so the doping in the semiconductor substrate 1 is also as described above, there will be The risk of electric leakage or breakdown heating, so the isolation region 10 extends into the semiconductor substrate 1 can reduce the risk of leakage or breakdown heating.
  • the second auxiliary layer is removed.
  • Step 7 Form a back passivation layer 7 on the surface of the third doped layer 5 and the second doped layer 6 away from the second interface layer 4, and at the same time, form a back passivation layer 7 on the semiconductor substrate 1 away from the first One side surface of the interface layer 2 forms a front passivation layer.
  • Step 8 Form a first electrode 8 penetrating through the back passivation layer 7 above the third doped layer 5, and at the same time, form a penetrating through the back passivation layer above the second doped layer 6 7 of the second electrode 9 .
  • the electrodes there are various methods for forming the electrodes, which can be directly coated on the back passivation layer 7 with a fire-through paste, and then undergo heat treatment so that the electrode paste passes through the back passivation layer 7 and the third doped layer 5 And the second doped layer 6 forms a contact. It is also possible to open holes on the back passivation layer 7 first, and then use methods such as electrode paste, laser transfer printing, electroplating, electroless plating, light-induced electroplating, or physical vapor deposition such as evaporation and sputtering to form electrodes. Obviously, one or a combination of the above methods can also be used to form electrodes.
  • a second method for preparing a solar cell comprising the steps of:
  • Step 1 providing a semiconductor substrate 1;
  • Step 2 forming a first doped layer 3 on one side surface of the semiconductor substrate 1;
  • LPCVD is used to form the first interface layer 2 on one side of the semiconductor substrate 1 at a temperature of 400-700°C.
  • the first doped layer 3 is formed on the surface of the first interface layer 2 away from the semiconductor substrate 1 by in-situ doping LPCVD.
  • a first semiconductor layer is formed on the surface of the first interface layer 2 facing away from the semiconductor substrate 1, and the first dopant is doped into the first semiconductor layer by diffusion. layer, thereby forming the first doped layer 3.
  • the first semiconductor layer may be a polycrystalline silicon layer, a microcrystalline silicon layer or an amorphous silicon layer.
  • the peak doping concentration of the first dopant in the first doped layer 3 is 1 ⁇ 10 19 -5 ⁇ 10 21 atoms/cm 3 .
  • Step 3 Patterning the first doped layer 3, thereby retaining part of the first doped layer 3;
  • a first auxiliary layer is formed on the surface of the first doped layer 3 facing away from the semiconductor substrate 1, and then the first auxiliary layer and the first doped layer 3 above the second region are etched away. , so as to complete the patterning, leaving only the first doped layer 3 in the first region.
  • the first auxiliary layer may be a dielectric film such as silicon oxide or silicon nitride.
  • the aforementioned silicon oxide film formed upon doping with phosphorus can be used as the first auxiliary layer.
  • the first auxiliary layer is patterned, for example, using etching paste to print patterns to remove the first auxiliary layer, the first doped layer 3 and the first interface layer 2 outside the first region, or using a short pulse laser to remove The first auxiliary layer, the first doped layer 3 and the first interface layer 2 outside the first region.
  • an alkaline solution is used to remove the first doped layer 3 and the first interface layer 2 outside the first region, and the same alkaline solution is used to form a textured surface on the surface of the semiconductor substrate 1 in the second region structure.
  • the lye is used to complete the patterning of the first doped layer 3 in the first region, and at the same time complete the texture preparation of the second region.
  • the IBC preparation process is greatly simplified, and the currently commonly used single-side texturing process can be dispensed with.
  • Method 1 First, double-sided polishing of the silicon wafer, and then prepare the first auxiliary layer on one side, and then remove the first auxiliary layer after the texturing is completed.
  • Method 2 firstly polish both sides of the silicon wafer, then prepare the first auxiliary layer on one side, then polish on one side, and then remove the first auxiliary layer.
  • the existing two single-side texturing methods are relatively complicated, and the single-side texturing process must be completed at the very beginning of the battery manufacturing process. It takes at least four steps to complete.
  • the suede surface may be damaged in the subsequent normal battery preparation process, which reduces the antireflection effect of the suede surface of the battery.
  • Step 4 firstly form the second interface layer 4, the second interface layer 4 not only covers the surface and side of the first doped layer away from the semiconductor substrate, but also covers the The first surface of the semiconductor substrate covered by the impurity layer.
  • In-situ doping LPCVD is used to form the second doped layer 6 on the surface of the second interface layer 4 away from the semiconductor substrate 1 and the first doped layer 3.
  • In-situ doping refers to depositing amorphous Silicon doping is done simultaneously.
  • a second auxiliary layer is respectively formed on the surface of the second doped layer 6 facing away from the second interface layer 4, and the second doped layer 6 on the first surface of the semiconductor substrate 1 is combined with the first doped layer.
  • the interface of the layers is not covered by the second auxiliary layer.
  • the second auxiliary layer may be a dielectric film such as silicon oxide or silicon nitride.
  • this part of the semiconductor substrate can also be further removed 1, thereby deepening the depth of the isolation region 10, the deeper the isolation region 10, the better the isolation effect.
  • the doping in the semiconductor substrate 1 is also as described above, there will be The risk of electric leakage or breakdown heating, so the isolation region 10 extends into the semiconductor substrate 1 can reduce the risk of leakage or breakdown heating.
  • the second auxiliary layer is removed.
  • Step 5 heat-treating the second doped layer 6 above the first doped layer 3, so that the first dopant in the first doped layer 3 diffuses to the second doped layer thereon 6, the second dopant in the second doped layer 6 above the first doped layer will also diffuse into the first doped layer 3, so that the above first doped layer 3
  • the second doped layer 6 is transformed into the third doped layer 5 ; the second doped layer 6 not covering the first surface of the first doped layer 3 is still the second doped layer 6 .
  • the conductivity of at least a part of the region is the same as that of the first doped layer 3 .
  • the peak doping concentration of the first dopant in the first doped layer 3 is 1 ⁇ 10 19 to 3 ⁇ 10 21 atoms/cm 3
  • the peak doping concentration of the second dopant is 1 ⁇ 10 19 ⁇ 3 ⁇ 10 19 atoms/cm 3 .
  • the peak doping concentration of the first dopant in a partial region of the third doped layer 5 is 1 ⁇ 10 20 -5 ⁇ 10 20 atoms/cm 3
  • the peak doping concentration of the second dopant is 1 ⁇ 10 20 atoms/cm 3 . 10 19 to 3 ⁇ 10 19 atoms/cm 3 .
  • the peak doping concentration of the second dopant in the second doped layer 6 is 1 ⁇ 10 19 -3 ⁇ 10 19 atoms/cm 3 .
  • the heating peak temperature under the heat treatment or heating conditions is above 850°C, preferably above 900°C, more preferably 1000°C, for example, it can be 850°C, 900°C, 1000°C, 1100°C, 1200°C °C, etc.; at the peak temperature, the heating time is 10 min or more, preferably 30 min or more, for example, 10 min, 20 min, 30 min, 40 min, 50 min, 60 min, etc.
  • the second semiconductor layer may be a polycrystalline silicon layer, a microcrystalline silicon layer or an amorphous silicon layer. Due to the high peak temperature of the heat treatment, the amorphous silicon or microcrystalline silicon in the second semiconductor layer will be converted into polysilicon, so that the electrical conductivity of the second semiconductor layer can be improved.
  • the solution used to remove the oxide film layer contains fluorine element, specifically, a solution containing HF or NH 4 F, etc. may be used. removing the oxide film layer.
  • the first doped layer 3 has a first dopant and a second dopant
  • the third doped layer 5 has a first dopant and a second dopant
  • the conductivity type of the first doped layer 3 is opposite to that of the second doped layer 6;
  • the conductivity type of at least a part of the third doped layer 5 is the same as that of the first doped layer.
  • Step 6 Form a back passivation layer 7 on the surface of the third doped layer 5 and the second doped layer 6 facing away from the second interface layer 4, and at the same time, form a back passivation layer 7 on the semiconductor substrate 1 facing away from the first interface layer 4.
  • One side surface of the interface layer 2 forms a front passivation layer.
  • Step 7 Form a first electrode 8 penetrating through the back passivation layer 7 above the third doped layer 5, and at the same time, form a penetrating through the back passivation layer above the second doped layer 6 7 of the second electrode 9 .
  • the electrodes there are various methods for forming the electrodes, which can be directly coated on the back passivation layer 7 with a fire-through paste, and then undergo heat treatment so that the electrode paste passes through the back passivation layer 7 and the third doped layer 5 And the second doped layer 6 forms a contact. It is also possible to open holes on the back passivation layer 7 first, and then use methods such as electrode paste, laser transfer printing, electroplating, electroless plating, light-induced electroplating, or physical vapor deposition such as evaporation and sputtering to form electrodes. Obviously, one or a combination of the above methods can also be used to form electrodes.
  • the solar cell in this embodiment is the first solar cell, comprising the following steps:
  • Step 1 providing a semiconductor substrate 1;
  • a p-type silicon wafer is provided as a semiconductor substrate 1 with a thickness of 200 ⁇ m.
  • Step 2 forming a first doped layer 3 on one side surface of the semiconductor substrate 1;
  • LPCVD LPCVD to form a first interface layer 2 on one side of the semiconductor substrate 1 at a temperature of 700° C.
  • Crystalline silicon layer 3 The phosphorus-doped amorphous silicon 3 is formed by in-situ doping LPCVD, the deposition source is SiH 4 , and the phosphorus-containing doping source is PH 3 .
  • the first interface layer 2 is a silicon oxide layer with a thickness of 1 nm, and the thickness of the intrinsic amorphous silicon layer is 100 nm.
  • the peak doping concentration of the first dopant in the first doped layer 3 is 3 ⁇ 10 21 atoms/cm 3 .
  • Step 3 Patterning the first doped layer 3, thereby retaining part of the first doped layer 3;
  • a silicon oxide layer i.e. the first auxiliary layer
  • a thickness of 20 nm is formed on the surface of the first doped layer 3 facing away from the semiconductor substrate 1, and then a short pulse laser is used to oxidize the silicon oxide layer above the second region.
  • the silicon, the first doped layer 3 and the first interface layer 2 are etched away to complete the patterning, leaving only the first doped layer 3 in the first region.
  • Step 4 Forming oxidation covering the first doped layer 3 and the surface of the semiconductor substrate 1 not covered by the first doped layer 3 on the surface of the first doped layer 3 facing away from the semiconductor substrate 1
  • a silicon layer i.e. the second auxiliary layer, the thickness of which is 20nm;
  • Step 5 Form the second doped layer 6 on the surface of the second interface layer 4 away from the semiconductor substrate 1 and the first doped layer 3 by using in-situ doping LPCVD.
  • In-situ doping refers to Deposition of amorphous silicon doping is completed at the same time, the second doped layer 6 is 25nm in size, and the in-situ doped boron-containing dopant is B 2 H 6 , thereby forming the second doped layer 6 .
  • the second doped layer 6 located above the first doped layer 3 is subjected to heat treatment (peak temperature is 900° C., and the heating time is 30 min), so that the phosphorus in the first doped layer 3 diffuses thereon
  • the boron in the second doped layer 6 on the first region will also diffuse into the first doped layer 3, so that the corresponding second doped layer 6 on the first region is transformed into is the third doped layer 5; the corresponding second doped layer 6 on the second region is still the second doped layer 6, and at the same time, due to the high temperature of the heat treatment, the amorphous silicon layer is transformed into a polysilicon layer.
  • the conductivity of all regions in the third doped layer 5 is the same as that of the first doped layer 3 .
  • the peak doping concentration of phosphorus in the first doped layer 3 is 2 ⁇ 10 21 atoms/cm 3
  • the peak doping concentration of boron is 2 ⁇ 10 19 atoms/cm 3 .
  • the peak doping concentration of phosphorus in the third doped layer 5 is 2 ⁇ 10 21 atoms/cm 3
  • the peak doping concentration of boron is 2 ⁇ 10 19 atoms/cm 3 .
  • the thickness of the second doped layer 6 is 25 nm, and the doping concentration of boron in it is 2 ⁇ 10 19 atoms/cm 3 .
  • Step 6 Form a back passivation layer 7 (an aluminum oxide layer with a thickness of 15 nm) on the surface of the third doped layer 5 and the second doped layer 6 away from the second interface layer 4, and at the same time A front passivation layer (an aluminum oxide layer with a thickness of 15 nm) is formed on the surface of the semiconductor substrate 1 facing away from the first interface layer 2 .
  • a back passivation layer 7 an aluminum oxide layer with a thickness of 15 nm
  • Step 7 Form a first electrode 8 penetrating through the back passivation layer 7 above the third doped layer 5, and at the same time, form a penetrating through the back passivation layer above the second doped layer 6 7 of the second electrode 9 .
  • Both the first electrode 8 and the second electrode 9 are silver electrodes.
  • the solar cell in this embodiment is the second type of solar cell, comprising the following steps:
  • Step 1 providing a semiconductor substrate 1;
  • a p-type silicon wafer is provided as a semiconductor substrate 1 with a thickness of 200 ⁇ m.
  • Step 2 Forming a first doped layer 3 on one side of the semiconductor substrate 1; specifically, using LPCVD to form a first interface layer 2 on one side of the semiconductor substrate 1 at a temperature of 700° C.
  • a phosphorus-doped amorphous silicon layer 3 is formed on the surface of the first interface layer 2 away from the semiconductor substrate 1 .
  • the phosphorus-doped amorphous silicon is formed by in-situ doping LPCVD, the deposition source is SiH 4 , and the phosphorus-containing doping source is PH 3 .
  • the first interface layer 2 is a silicon oxide layer with a thickness of 1 nm, and the thickness of the intrinsic amorphous silicon layer is 100 nm.
  • the peak doping concentration of the first dopant in the first doped layer 3 is 3 ⁇ 10 21 atoms/cm 3 .
  • Step 3 Patterning the first doped layer 3, thereby retaining part of the first doped layer 3;
  • a silicon oxide layer i.e. the first auxiliary layer
  • a thickness of 20 nm is formed on the surface of the first doped layer 3 facing away from the semiconductor substrate 1, and then a short pulse laser is used to oxidize the silicon oxide layer above the second region.
  • the silicon, the first doped layer 3 and the first interface layer 2 are etched away to complete the patterning, leaving only the first doped layer 3 in the first region.
  • Step 4 Forming oxidation covering the first doped layer 3 and the surface of the semiconductor substrate 1 not covered by the first doped layer 3 on the surface of the first doped layer 3 facing away from the semiconductor substrate 1
  • a silicon layer i.e. the second auxiliary layer, the thickness of which is 20nm;
  • Step 5 Form the second doped layer 6 on the surface of the second interface layer 4 away from the semiconductor substrate 1 and the first doped layer 3 by using in-situ doping LPCVD.
  • In-situ doping refers to Deposition of amorphous silicon doping is completed at the same time, the second doped layer 6 is 25nm in size, and the in-situ doped boron-containing dopant is B 2 H 6 , thereby forming the second doped layer 6 .
  • the second doped layer 6 located above the first doped layer 3 is subjected to heat treatment (peak temperature is 900° C., and the heating time is 30 min), so that the phosphorus in the first doped layer 3 diffuses thereon
  • the boron in the second doped layer 6 on the first region will also diffuse into the first doped layer 3, so that the corresponding second doped layer 6 on the first region is transformed into is the third doped layer 5; the corresponding second doped layer 6 on the second region is still the second doped layer 6, and at the same time, due to the high temperature of the heat treatment, the amorphous silicon layer is transformed into a polysilicon layer.
  • the conductivity of all regions in the third doped layer 5 is the same as that of the first doped layer 3 .
  • the peak doping concentration of phosphorus in the first doped layer 3 is 2 ⁇ 10 21 atoms/cm 3
  • the peak doping concentration of boron is 2 ⁇ 10 19 atoms/cm 3 .
  • the peak doping concentration of phosphorus in the third doped layer 5 is 2 ⁇ 10 21 atoms/cm 3
  • the peak doping concentration of boron is 2 ⁇ 10 19 atoms/cm 3 .
  • the thickness of the second doped layer 6 is 25 nm, and the doping concentration of boron in it is 2 ⁇ 10 19 atoms/cm 3 .
  • Step 6 Form a second auxiliary layer on the surface of the third doped layer 5 and the second doped layer 6 facing away from the second interface layer 4 respectively, close to the third doped layer 5 and the second doped layer 6 The junction of the doped layer 6 is not covered by the second auxiliary layer.
  • the second auxiliary layer may be silicon oxide with a thickness of 20nm.
  • Step 7 using a short pulse laser to etch away the third doped layer 5, the second doped layer 6 and the second interface layer 4 below it that do not cover the second auxiliary layer, thereby exposing the semiconductor substrate 1 (exposed
  • the semiconductor substrate 1 is called the isolation region 10
  • the third doped layer 5, the second interface layer 4, the first doped layer 3 and the first interface layer 2 are close to the side of the isolation region 10, the isolation region 10
  • An isolation region 10 is formed on the surface of the semiconductor substrate 1, the second interface layer 4, and the second doped layer 6 near the isolation region 10, and the width w of the isolation region 10 is 100 ⁇ m.
  • the second auxiliary layer is removed, and the second auxiliary layer is removed by dilute hydrofluoric acid solution.
  • Step 8 Form a back passivation layer 7 (an aluminum oxide layer with a thickness of 15 nm) on the surface of the third doped layer 5 and the second doped layer 6 away from the second interface layer 4, and at the same time A front passivation layer (an aluminum oxide layer with a thickness of 15 nm) is formed on the surface of the semiconductor substrate 1 facing away from the first interface layer 2 .
  • a back passivation layer 7 an aluminum oxide layer with a thickness of 15 nm
  • Step 9 Form a first electrode 8 penetrating through the back passivation layer 7 above the third doped layer 5, and at the same time, form a penetrating through the back passivation layer above the second doped layer 6 7 of the second electrode 9 .
  • Both the first electrode 8 and the second electrode 9 are silver electrodes.
  • the difference between embodiment 3 and embodiment 2 is that the thickness of the second doped layer 6 is different. In this embodiment, the thickness of the second doped layer 6 is 50nm. In the third doped layer 5, some regions The electrical conductivity of the first doped layer 3 is the same as that of the first doped layer 3 .
  • the performance of the solar cell is shown in Table 1.
  • the difference between embodiment 4 and embodiment 2 is that the thickness of the second doped layer 6 is different.
  • the thickness of the second doped layer 6 is 100 nm
  • the part of the third doped layer 5 is The conductivity is the same as that of the first doped layer 3 .
  • the performance of the solar cell is shown in Table 1.
  • Step 5 of embodiment 5 is: forming a thickness It is a 25nm amorphous silicon layer.
  • the boron is doped into the amorphous silicon layer by boron diffusion.
  • the boron-containing dopant is BBr 3 .
  • the peak doping concentration of phosphorus in the first doped layer 3 is 2 ⁇ 10 21 atoms/cm 3
  • the peak doping concentration of boron is 2 ⁇ 10 19 atoms/cm 3 .
  • the peak doping concentration of phosphorus in the third doped layer 5 is 2 ⁇ 10 21 atoms/cm 3
  • the peak doping concentration of boron is 2 ⁇ 10 19 atoms/cm 3 .
  • the thickness of the second doped layer 6 is 25 nm, and the doping concentration of boron in it is 2 ⁇ 10 19 atoms/cm 3 .
  • Step 5 Form the second doped layer 6 on the surface of the second interface layer 4 away from the semiconductor substrate 1 and the first doped layer 3 by using in-situ doping LPCVD.
  • In-situ doping refers to Deposition of amorphous silicon doping is completed at the same time, the second doped layer 6 is 25nm in size, and the in-situ doped boron-containing dopant is B 2 H 6 , thereby forming the second doped layer 6 .
  • Step 6 Form a second auxiliary layer on the surface of the third doped layer 5 and the second doped layer 6 facing away from the second interface layer 4 respectively, close to the third doped layer 5 and the second doped layer 6 The junction of the doped layer 6 is not covered by the second auxiliary layer.
  • the second auxiliary layer may be silicon oxide with a thickness of 20nm.
  • Step 7 using a short pulse laser to etch away the third doped layer 5, the second doped layer 6 and the second interface layer 4 below it that do not cover the second auxiliary layer, thereby exposing the semiconductor substrate 1 (exposed
  • the semiconductor substrate 1 is called the isolation region 10
  • the third doped layer 5, the second interface layer 4, the first doped layer 3 and the first interface layer 2 are close to the side of the isolation region 10, the isolation region 10
  • An isolation region 10 is formed on the surface of the semiconductor substrate 1, the second interface layer 4, and the second doped layer 6 near the isolation region 10, and the width w of the isolation region 10 is 100 ⁇ m.
  • the second auxiliary layer is removed, and the second auxiliary layer is removed by dilute hydrofluoric acid solution.
  • Step 8 heat the second doped layer 6 located above the first doped layer 3 (the peak temperature is 900° C., and the heating time is 30 min), so that the phosphorus in the first doped layer 3 diffuses into In the second doped layer 6 on it, the boron in the second doped layer 6 on the first region will also diffuse into the first doped layer 3, so that the corresponding second doped layer on the first region 6 into the third doped layer 5; the corresponding second doped layer 6 on the second region is still the second doped layer 6, and at the same time due to the high temperature of the heat treatment, the amorphous silicon layer is transformed into a polysilicon layer .
  • the conductivity of all regions in the third doped layer 5 is the same as that of the first doped layer 3 .
  • the peak doping concentration of phosphorus in the first doped layer 3 is 2 ⁇ 10 21 atoms/cm 3
  • the peak doping concentration of boron is 2 ⁇ 10 19 atoms/cm 3 .
  • the peak doping concentration of phosphorus in the third doped layer 5 is 2 ⁇ 10 21 atoms/cm 3
  • the peak doping concentration of boron is 2 ⁇ 10 19 atoms/cm 3 .
  • the thickness of the second doped layer 6 is 25 nm, and the doping concentration of boron in it is 2 ⁇ 10 19 atoms/cm 3 .
  • Step 9 Form a rear passivation layer 7 (an aluminum oxide layer with a thickness of 15 nm) on the surface of the third doped layer 5 and the second doped layer 6 away from the second interface layer 4, and at the same time A front passivation layer (an aluminum oxide layer with a thickness of 15 nm) is formed on the surface of the semiconductor substrate 1 facing away from the first interface layer 2 .
  • a rear passivation layer 7 an aluminum oxide layer with a thickness of 15 nm
  • Step 10 Form a first electrode 8 penetrating through the back passivation layer 7 above the third doped layer 5, and at the same time, form a penetrating through the back passivation layer above the second doped layer 6 7 of the second electrode 9 .
  • Both the first electrode 8 and the second electrode 9 are silver electrodes.
  • embodiment 7 The difference between embodiment 7 and embodiment 2 is that the thickness of the second doped layer 6 is different.
  • the thickness of the second doped layer 6 is 200nm
  • part of the third doped layer 5 is The conductivity is the same as that of the first doped layer 3 .
  • Step 5 in Embodiment 8 is: on the surface of the second interface layer 4 away from the semiconductor substrate 1 and the first doped layer 3, use The in-situ doping method forms a boron-containing polysilicon layer.
  • B 2 H 6 is used as a doping source in the in-situ doping process, and the thickness of the formed polysilicon is 100 nm, thereby forming the second doped layer 6 .
  • the laser power of laser processing is 25W, and laser adopts green light laser: wavelength 532nm
  • the laser power of laser processing is 25W, and laser adopts green light laser: wavelength 532nm
  • the corresponding second doped layer 6 on the first region is converted into a third doped layer 5, and the doping concentration of the first dopant in the region irradiated by the laser in the third doped layer 5 is greater than that of the first dopant
  • the doping concentration of the second dopant, its conductivity type is the same as the conductivity type of the first doped layer 3; the corresponding second doped layer 6 on the second region not irradiated by the laser is still the second doped layer 6, the second doped layer 6
  • One region is the first electrode region, and the conductivity of
  • the peak doping concentration of phosphorus in the first doped layer 3 is 2 ⁇ 10 21 atoms/cm 3
  • the peak doping concentration of boron is 2 ⁇ 10 19 atoms/cm 3 .
  • the peak doping concentration of phosphorus in the third doped layer 5 is 2 ⁇ 10 21 atoms/cm 3
  • the peak doping concentration of boron is 2 ⁇ 10 19 atoms/cm 3 .
  • the thickness of the second doped layer 6 is 100 nm, and the doping concentration of boron in it is 2 ⁇ 10 19 atoms/cm 3 .
  • Example 1 As can be seen from Table 1, and from the comparison of Example 1 and Example 2, it can be seen that the interval region between the p-type region and the n-type region is formed on the battery to isolate the p-type and n-type semiconductor regions, reducing the p-n junction. Recombination reduces the lateral leakage, and the open circuit voltage and fill factor have been improved to a certain extent.
  • Example 5 From the comparison of Example 2 and Example 5, it can be seen that in Example 5, the boron diffusion replaces the in-situ doped boron diffusion, and the surface concentration of the boron diffusion is slightly greater than the concentration of the in-situ doped boron element, so the contact resistance can be reduced.
  • the FF has been improved to a certain extent, the opening pressure has been slightly reduced, and the efficiency is close.
  • Example 3 has the highest efficiency.
  • the second doped layer is 25nm, although the third doped layer is all inversion type and becomes n-type, but the second doped layer is thinner (also 25nm), the The metal recombination of the second electrode cannot be completely shielded, so the opening voltage is slightly lower than that of Example 3, while in Example 4, the second doped layer is 100nm, and the third doped layer only has the bottom layer reversed to n-type, and the top layer still has Part of it is p-type, the first electrode passes through the third doped layer on the surface and contacts the third n-type doped layer at the bottom, and its FF is slightly lower than that of Example 3.
  • the second doped layer is 200 nm. Since the third doped layer is relatively thick, the contact between the first electrode and the n-type bottom layer of the third doped layer is poor, which affects its fill factor.
  • Example 2 From the comparison of Example 2 and Example 6, it can be seen that there is little difference between forming the spacer region first and then heating, and heating first and then forming the spacer region, and the electrical performance is also relatively close.
  • Example 8 Compared with Example 4, because in Example 8, the laser continues to heat in the electrode region, so that the top p-type polysilicon layer under the electrode continues to be transformed into n-type, so that the first electrode and n-type doped semiconductor form a For better contact, the fill factor has been improved.
  • the solar cell described in the present disclosure only needs one patterning and one high-temperature heat treatment.
  • the doped region prepared by this method has a passivation contact structure at both poles, the passivation effect is good, and the recombination rate of the metal region is greatly reduced, thereby improving the performance of the battery. s efficiency. At the same time, it can also reduce the thermal damage caused by high temperature heat treatment.

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Abstract

本公开公开了一种太阳能电池，包括半导体基底，在半导体基底的一侧表面具有第一掺杂层和第二掺杂层，在第一掺杂层背离半导体基底的一侧表面具有第三掺杂层，第一掺杂层中具有第一掺杂剂和第二掺杂剂；第二掺杂层中具有第二掺杂剂；第三掺杂层中具有第一掺杂剂和第二掺杂剂；第三掺杂层中至少部分区域的导电类型与第一掺杂层的导电类型相同；第一掺杂层与第二掺杂层的导电类型相反。本公开还提供一种太阳能电池的制备方法。本公开的太阳能电池，仅需要一次图形化，即可以完成两个区域的掺杂半导体的制备。

Description

一种太阳能电池及其制备方法
本申请要求在2021年12月29日提交中国专利局、申请号为202111644240.1、名称为“一种太阳能电池及其制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及太阳能电池技术领域，具体涉及一种太阳能电池及其制备方法。
背景技术
目前现有的太阳电池结构中，背接触太阳电池由于正面没有电极遮挡，因此光电转换效率会更高。背接触电池的背面不同的区域上设置有p型区域和n型区域，然后在其上分别设置正极和负极。并且这种正面无遮挡的电池不仅转换效率高，而且看上去更美观，同时，全背电极的组件更易于装配。IBC电池是目前实现高效晶体硅电池的技术方向之一。
但由于IBC电池结构较为复杂，制备方法也较为复杂。通常需要至少两次图形化，才能完成p型区域和n型区域的图形化，因此成本较高。
概述
针对上述问题，本公开提出了一种太阳能电池及其制备方法，仅需要一次图形化，即可以完成两个区域的掺杂半导体的制备。并且该方法制备的掺杂区，两极均为钝化接触结构，钝化效果好，金属区复合速率大幅降低，从而提升了电池的效率。
本公开提供一种太阳能电池的制备方法，包括如下步骤：
提供半导体基底；
在所述半导体基底的第一表面形成第一掺杂层；
将所述第一掺杂层进行图形化，从而保留部分第一掺杂层；
在所述第一掺杂层背离所述半导体基底的一侧表面通过加热处理形成 第三掺杂层，在未覆盖所述第一掺杂层的半导体基底的第一表面形成第二掺杂层；
所述第一掺杂层中具有第一掺杂剂和第二掺杂剂；
所述第二掺杂层中具有第二掺杂剂；
所述第三掺杂层中具有第一掺杂剂和第二掺杂剂；
所述第一掺杂层与所述第二掺杂层的导电类型相反；
所述第三掺杂层中至少部分区域的导电类型与第一掺杂层的导电类型相同。
进一步地，在所述半导体基底的第一表面形成第一半导体层，然后将第一掺杂剂扩散到所述第一半导体层内，从而形成第一掺杂层，或在所述半导体基底的第一表面上，采用原位掺杂形成第一掺杂层；
在所述第一掺杂层背离所述半导体基底的一侧表面上形成第一辅助层，然后将部分第一辅助层以及第一掺杂层刻蚀掉，从而完成图形化，留下部分第一掺杂层。
进一步地，在所述第一掺杂层背离所述半导体基底的一侧表面以及未覆盖所述第一掺杂层的半导体基底的第一表面，采用原位掺杂形成第二掺杂层；
对位于所述第一掺杂层上方的第二掺杂层进行加热处理，从而使得第一掺杂层中的第一掺杂剂扩散到其上的第二掺杂层中，所述第二掺杂层中的第二掺杂剂也会扩散到第一掺杂层中，从而使得所述第一掺杂层上方的第二掺杂层转变为第三掺杂层。
进一步地，所述加热处理为激光处理或热处理，
当采用所述激光处理，在所述第三掺杂层中，被所述激光直接照射到的区域，其导电类型与第一掺杂层的导电类型相同。
进一步地，在所述第三掺杂层中，与所述第一掺杂层导电类型相同的区域沿厚度方向贯穿所述第三掺杂层。
进一步地，在所述第一掺杂层背离所述半导体基底的一侧表面以及未覆盖所述第一掺杂层的半导体基底的第一表面形成第二半导体层，
在加热处理条件下，将第二掺杂剂扩散到所述第二半导体层中，由于温度较高，所述第一掺杂层中的第一掺杂剂也会扩散到位于其上方的所述第二 半导体层中，从而使得位于所述第一掺杂层上方的第二半导体层为第三掺杂层，位于所述半导体基底第一表面上的第二半导体层为第二掺杂层。
进一步地，在所述第三掺杂层中，靠近所述第一掺杂层的区域，至少部分区域的导电性与所述第一掺杂层的导电类型相同。
进一步地，在形成第三掺杂层之前，所述第一掺杂层内的第一掺杂剂的峰值掺杂浓度为1×10 19～5×10 21atoms/cm 3。
进一步地，在形成第三掺杂层之后，在所述第一掺杂层中，所述第一掺杂剂的掺杂浓度大于所述第二掺杂剂的掺杂浓度；
在所述第三掺杂层中，至少部分区域的第一掺杂剂的掺杂浓度大于第二掺杂剂的掺杂浓度。
进一步地，所述第一掺杂层内的第一掺杂剂的峰值掺杂浓度为1×10 19～3×10 21atoms/cm 3；
在所述第二掺杂层中，所述第二掺杂剂的峰值掺杂浓度为1×10 19～3×10 19atoms/cm 3；
所述第三掺杂层内至少部分区域中的第一掺杂剂的峰值掺杂浓度为1×10 20～5×10 20atoms/cm 3。
进一步地，所述加热处理的加热峰值温度为850℃以上，优选为900℃以上，更优选为1000℃；在峰值温度下，加热时间为10min以上。
进一步地，在形成第三掺杂层时，由于温度较高，位于所述第一掺杂层以及第三掺杂层中的第一掺杂剂以及第二掺杂剂扩散进入所述半导体基底内，从而形成第三掺杂区；
和/或，位于所述第二掺杂层中的第二掺杂剂扩散进入所述半导体基底内，从而形成第四掺杂区；
优选地，在所述第三掺杂区内，所述第一掺杂剂的峰值掺杂浓度为1×10 18～3×10 21atoms/cm 3，所述第二掺杂剂的峰值掺杂浓度为1×10 17～3×10 19atoms/cm 3；
优选地，所述第四掺杂区内，所述第二掺杂剂的峰值掺杂浓度为1×10 18～3×10 19atoms/cm 3。
进一步地，所述第一掺杂剂为第VA族元素或第IIIA族元素，所述第二掺杂剂为第VA族元素或第IIIA族元素，优选地，所述第一掺杂剂为第VA 族元素，所述第二掺杂剂为第IIIA族元素。
进一步地，在形成第三掺杂层之前还包括如下步骤：
将位于所述半导体基底第一表面上的所述第二掺杂层与所述第一掺杂层交界处的第一掺杂层以及第二掺杂层刻蚀掉，露出所述半导体基底的第一表面，从而使得所述第一掺杂层与所述第二掺杂层之间具有隔离区。
进一步地，在形成第三掺杂层之后还包括如下步骤：
将位于所述半导体基底第一表面上的所述第二掺杂层与所述第一掺杂层的交界处的第一掺杂层、第二掺杂层以及第三掺杂层刻蚀掉，露出所述半导体基底的第一表面，从而使得所述第一掺杂层与所述第二掺杂层之间具有隔离区。
进一步地，所述第一掺杂层、第二掺杂层以及第三掺杂层均为掺杂的多晶硅层、微晶硅层或非晶硅层中的一种。
本公开提供一种太阳能电池，包括半导体基底，在所述半导体基底的第一表面具有第一掺杂层和第二掺杂层，在所述第一掺杂层背离所述半导体基底的一侧表面具有第三掺杂层，
所述第一掺杂层中具有第一掺杂剂和第二掺杂剂；
所述第二掺杂层中具有第二掺杂剂；
所述第三掺杂层中具有第一掺杂剂和第二掺杂剂；
所述第三掺杂层中至少部分区域导电类型与第一掺杂层的导电类型相同；
所述第一掺杂层与所述第二掺杂层的导电类型相反。
进一步地，所述第一掺杂层的厚度为50～300nm；
所述第三掺杂层和所述第二掺杂层厚度相同，均为小于等于150nm。
进一步地，当所述第三掺杂层的厚度d为小于等于30nm时，所述第三掺杂层中所有区域导电类型与第一掺杂层的导电类型相同。
进一步地，当所述第三掺杂层的厚度30nm<d≤150nm时，在所述第三掺杂层中，靠近所述第一掺杂层的区域，至少部分区域的导电性与所述第一掺杂层的导电类型相同。
进一步地，当所述第三掺杂层的厚度30nm<d≤150nm时，在所述第三 掺杂层中，与所述第一掺杂层导电类型相同的区域沿厚度方向贯穿所述第三掺杂层。
进一步地，在所述第一掺杂层内，所述第一掺杂剂的掺杂浓度从远离所述半导体基底的一侧表面到靠近所述半导体基底的一侧表面的掺杂浓度先增大后减小；第二掺杂剂的掺杂浓度逐渐减小。
进一步地，在所述第二掺杂层内，第二掺杂剂的掺杂浓度从远离所述半导体基底的一侧表面到靠近所述半导体基底的一侧表面的掺杂浓度相同。
进一步地，在所述第三掺杂层内，所述第一掺杂剂的掺杂浓度从远离所述半导体基底的一侧表面到靠近所述半导体基底的一侧表面的掺杂浓度逐渐增大；
所述第二掺杂剂的掺杂浓度从远离所述半导体基底的一侧表面到靠近所述半导体基底的一侧表面的掺杂浓度相同。
进一步地，所述第三掺杂层不仅覆盖所述第一掺杂层背离所述半导体基底的一侧表面，还覆盖靠近所述第二掺杂层的第一掺杂层的侧面，且覆盖所述第一掺杂层侧面的所述第三掺杂层与所述第二掺杂层接触。
进一步地，所述太阳能电池还包括第一界面层，所述第一界面层位于所述半导体基底与所述第一掺杂层之间；
和/或，还包括第二界面层，所述第二界面层从所述第一掺杂层背离所述第一界面层的表面延伸至其侧面，并继续延且伸覆盖所述半导体基底未覆盖第一掺杂层的部分，且所述第二掺杂层以及第三掺杂层分别设置于所述第二界面层的一侧表面上；
和/或，还包括背面钝化层，所述背面钝化层覆盖第三掺杂层以及第二掺杂层。
进一步地，所述第一掺杂层与所述第三掺杂层的宽度相同，所述第一掺杂层以及第三掺杂层与所述第二掺杂层之间具有隔离区。
进一步地，还包括第一界面层、所述第一界面层位于所述半导体基底与所述第一掺杂层之间；
和/或，还包括第二界面层，所述第二界面层位于第一掺杂层和第三掺杂层之间以及第二掺杂层与所述半导体基底之间；
和/或，还包括背面钝化层，所述背面钝化层覆盖第三掺杂层、隔离区以及第二掺杂层。
进一步地，还包括第一电极和第二电极，所述第一电极穿过背面钝化层与所述第三掺杂层中的与第一掺杂层导电类型相同的区域接触；所述第二电极穿过所述背面钝化层与所述第二掺杂层接触。
进一步地，所述太阳能电池为前述方法制备得到。
本公开提供的太阳能电池，仅需要一次图形化，即可以完成两个区域的掺杂半导体的制备。并且该方法制备的掺杂区，两极均为钝化接触结构，钝化效果好，金属区复合速率大幅降低，从而提升了电池的效率。并且这种背接触制备方法仅需要一次高温热处理，减少了高温热处理带来的热损伤。
附图简述
附图用于更好地理解本公开，不构成对本公开的不当限定。其中：
图1为本公开提供的太阳能电池的结构示意图。
图2为本公开提供的太阳能电池的结构示意图。
附图标记说明
1-半导体基底，2-第一界面层，3-第一掺杂层，4-第二界面层，5-第三掺杂层，6-第二掺杂层，7-背面钝化层，8-第一电极，9-第二电极，10-隔离区，11-第三掺杂区，12-第四掺杂区。
详细描述
以下对本公开的示范性实施例做出说明，其中包括本公开实施例的各种细节以助于理解，应当将它们认为仅仅是示范性的。因此，本领域普通技术人员应当认识到，可以对这里描述的实施例做出各种改变和修改，而不会背离本公开的范围和精神。同样，为了清楚和简明，以下的描述中省略了对公知功能和结构的描述。在本公开中上下位置依据光线入射方向而定，光线入射处为上。
本公开提供两种太阳能电池，具体如下：
如图1所示，第一种太阳能电池，包括半导体基底1，在所述半导体基底1的一侧表面划分为第一区域和第二区域，在所述第一区域内的半导体基底1的一侧表面依次设置有第一界面层2、第一掺杂层3、第二界面层4以及第三掺杂层5，在所述第二区域内的半导体基底1的同一侧表面依次设置有第二界面层4、第二掺杂层6，所述第二界面层4从所述第一掺杂层3的一侧表面延伸至其侧面，并覆盖所述第二区域的半导体基底1，所述第三掺杂层5不仅覆盖位于所述第一掺杂层3背离所述半导体基底1的一侧的第二界面层4，还覆盖其靠近所述第二掺杂层6的侧面，延伸至该侧面的第三掺杂层5与所述第二掺杂层6接触。在所述第三掺杂层5背离所述第二界面层4的一侧表面还设置有覆盖第三掺杂层5以及第二掺杂层6的背面钝化层7，位于所述第三掺杂层5上方的背面钝化层7上还设置有穿过所述背面钝化层7与所述第三掺杂层5接触的第一电极8。所述第一掺杂层3与所述第二掺杂层6的导电类型相反。所述第三掺杂层5中至少部分区域中的导电性与所述第一掺杂层3相同，在所述第三掺杂层5中，与所述第一掺杂层3导电类型相同的区域为第一导电类型区，与所述第二掺杂层导电类型相同的区域为第二导电类型区。所述第一电极8与所述第三掺杂层5中第一导电类型区接触，且所述第一电极通过所述第一导电类型区与所述第一掺杂层3导通，位于所述第二掺杂层6上方的背面钝化层7上还设置有穿过所述背面钝化层7与所述第二掺杂层6接触的第二电极9。
所述第一电极8以及第二电极9可以为金、银或铝。
所述半导体基底1为硅基底或锗基底。
所述半导体基底1可以为p型或者n型。
在本公开中，导电类型可以使用ECV等的测试，也可以使用pn笔测试得到。
掺杂浓度可以使用ECV方法测试。
所述第一掺杂层、第二掺杂层、第三掺杂区以及第四掺杂区内的掺杂元素可以通过STEM表征出来，也可以通过SIMS表征出来。
在本公开中，所述第一界面层2可以为氧化物层、氮化物层、碳化物层、氢化非晶硅层中的一种或多种，所述氧化物层包括：氧化硅、氮氧化硅、氧化铝、氧化钛、HfO 2、Ga 2O 3、Ta 2O 5、Nb 2O 5中的一种或多种的混合物，所 述氮化物层包括：氮化硅、氮化铝、TiN、TiCN中的一种或多种，所述碳化物包括：SiC、SiCN等。具体地，所述第一界面层2可以为隧穿氧化层，其厚度为0.5～5nm，例如可以为0.5nm、1nm、1.5nm、2nm、2.5nm、3nm、3.5nm、4nm、4.5nm或5nm。
在本公开中，所述第二界面层4可以为氧化物层、氮化物层、碳化物层、氢化非晶硅层中的一种或多种，所述氧化物层包括：氧化硅、氮氧化硅、氧化铝、氧化钛、HfO 2、Ga 2O 3、Ta 2O 5、Nb 2O 5中的一种或多种的混合物，所述氮化物层包括：氮化硅、氮化铝、TiN、TiCN中的一种或多种，所述碳化物包括：SiC、SiCN等。优选为氧化硅，其厚度为0.5-5nm，例如可以为0.5nm、1nm、1.5nm、2nm、2.5nm、3nm、3.5nm、4nm、4.5nm或5nm。
在本公开中，在所述半导体基底1背离所述第一界面层2的一侧表面还依次设置有正面钝化层和减反射层，所述正面钝化层可以为氮化硅、氧化硅、氮氧化硅、氧化铝、碳化硅、非晶硅中的一种或多种组成。
在本公开中，所述第一掺杂层3可以为掺杂的非晶硅层、微晶硅层、多晶硅层、纳米硅或者以上的一种或多种混合物，优选为掺杂的非晶硅层，因为非晶硅的制备温度更低，非晶硅不需要单独退火，在后续的各种掺杂或者加热的过程中均可以退火，相对来说工艺时间也会更节省。所述第一掺杂层3的厚度为50-300nm，例如可以为50nm、60nm、70nm、80nm、90nm、100nm、110nm、120nm、130nm、140nm、150nm、160nm、170nm、180nm、190nm、200nm、210nm、220nm、230nm、240nm、250nm、260nm、270nm、280nm、290nm或300nm。
具体地，第二掺杂层6可以为掺杂的非晶硅层、掺杂的微晶硅层、多晶硅层、纳米硅或者以上的一种或多种混合物，优选为掺杂的非晶硅层，因为非晶硅的制备温度更低，相对来说工艺时间也会更节省，第二掺杂层6的厚度小于等于150nm，例如可以为15nm、20nm、30nm、40nm、50nm、60nm、70nm、80nm、90nm、100nm、110nm、120nm、130nm、140nm或150nm。
具体地，所述第三掺杂层5可以为掺杂的非晶硅层、微晶硅层、多晶硅层、纳米硅或者以上的一种或多种混合物，优选地，所述第三掺杂层5与第二掺杂层6为同一种物质，所述第三掺杂层5的厚度小于等于150nm。例如可以为15nm、20nm、30nm、40nm、50nm、60nm、70nm、80nm、90nm、 100nm、110nm、120nm、130nm、140nm或150nm。
具体地，所述第三掺杂层5和所述第二掺杂层6厚度相同。
在本公开中，所述第一掺杂层3中具有第一掺杂剂和第二掺杂剂，所述第一掺杂剂的峰值掺杂浓度大于所述第二掺杂剂的峰值掺杂浓度；
所述第二掺杂层6中具有第二掺杂剂；
所述第三掺杂层5中具有第一掺杂剂和第二掺杂剂；
所述第三掺杂层5中至少部分区域中的第一掺杂剂的峰值掺杂浓度大于所述第二掺杂剂的峰值掺杂浓度，因此所述第三掺杂层5中至少部分区域中的导电性与所述第一掺杂层3相同。
当所述第一掺杂层3为p型时，则第二掺杂层6为n型。反之，当第一掺杂层3为n型时，则第二掺杂层6为p型，以硅为例，p型的导电掺杂剂一般为IIIA族元素，譬如镓Ga，或者硼B。n型的掺杂剂一般为VA元素，譬如磷P元素。
具体地，在所述第一掺杂层3中，所述第一掺杂剂的峰值掺杂浓度为1×10 19～3×10 21atoms/cm 3，例如可以为1×10 19atoms/cm 3、2×10 19atoms/cm 3、3×10 19atoms/cm 3、4×10 19atoms/cm 3、5×10 19atoms/cm 3、6×10 19atoms/cm 3、7×10 19atoms/cm 3、8×10 19atoms/cm 3、9×10 19atoms/cm 3、1×10 20atoms/cm 3、2×10 20atoms/cm 3、3×10 20atoms/cm 3、4×10 20atoms/cm 3、5×10 20atoms/cm 3、6×10 20atoms/cm 3、7×10 20atoms/cm 3、8×10 20atoms/cm 3、9×10 20atoms/cm 3、1×10 21atoms/cm 3、2×10 21atoms/cm 3或3×10 21atoms/cm 3。
在所述第二掺杂层6中，所述第二掺杂剂的峰值掺杂浓度为1×10 19～3×10 19atoms/cm 3，例如可以为1×10 19atoms/cm 3、2×10 19atoms/cm 3或3×10 19atoms/cm 3。
在所述第三掺杂层5中，至少部分区域所述第一掺杂剂的峰值掺杂浓度为1×10 20～5×10 20atoms/cm 3，例如可以为1×10 20atoms/cm 3、2×10 20atoms/cm 3、3×10 20atoms/cm 3、4×10 20atoms/cm 3或5×10 20atoms/cm 3。
在本公开中，所述第一掺杂剂为第VA族元素或第IIIA族元素，优选为第VA族元素，所述第二掺杂剂为第VA族元素或第IIIA族元素，优选为第IIIA族元素。
具体地，所述第一掺杂剂为磷、镓或硼，优选为磷，所述第二掺杂剂为 磷、镓或硼，优选为硼。
掺杂剂是通过掺杂物掺杂进去的物质，例如掺杂物为POCl 3时，掺杂剂为磷。
含磷掺杂物一般包括：POCl 3(一般在热扩散时使用)、PH 3(磷烷，会在离子注入，或者原位掺杂等的时候使用)、含磷氧化硅(APCVD法掺杂)等。含硼的掺杂物一般包括：BBr 3、BCl 3(BBr 3和BCl 3均为热扩散时使用)，B 2H 6(乙硼烷一般在原位掺杂，或者离子注入时使用)。
在本公开中，在所述第一掺杂层3内，所述第一掺杂剂的掺杂浓度从远离所述半导体基底1的一侧表面到靠近所述半导体基底1的一侧表面的掺杂浓度先增大后减小；第二掺杂剂的掺杂浓度逐渐减小。
在所述第二掺杂层6内，第二掺杂剂的掺杂浓度从远离所述半导体基底1的一侧表面到靠近所述半导体基底1的一侧表面的掺杂浓度相等；
在所述第三掺杂层5内，所述第一掺杂剂的掺杂浓度从远离所述第一掺杂层3的一侧表面到靠近所述第一掺杂层3的一侧表面的掺杂浓度逐渐增大；第二掺杂剂的掺杂浓度从远离所述半导体基底1的一侧表面到靠近所述半导体基底1的一侧表面的掺杂浓度相同。
进一步地，当所述第三掺杂层5的厚度小于30nm时，在所述第三掺杂层5中，第一掺杂剂的浓度大于第二掺杂剂的浓度，整个所述第三掺杂层5的导电类型与第一掺杂层3的导电类型相同。当所述第三掺杂层5的厚度d在30nm-150nm之间时，部分第一掺杂剂的浓度大于第二掺杂剂的浓度，该部分的所述第三掺杂层5中部分导电类型与所述第一掺杂层3相同，部分第一掺杂剂的浓度小于第二掺杂剂的浓度，该部分导电类型与所述第一掺杂层3相反。
具体地，当所述第三掺杂层5的厚度d在30nm-150nm之间时，在所述第三掺杂层5中，靠近所述第一掺杂层3的区域，至少部分区域的导电性与所述第一掺杂层3的导电类型相同，所述第一电极穿过背面钝化层7进入所述第三掺杂层中与第一导电类型区接触。
具体地，当所述第三掺杂层5的厚度30nm<d≤150nm时，在所述第三掺杂层5中，与所述第一掺杂层3导电类型相同的区域沿厚度方向贯穿所述第三掺杂层5，所述第一电极穿过背面钝化层直接与所述第一导电类型区域 接触。
在本公开中，在所述半导体基底1靠近所述第一掺杂层3的一侧内，所述第一掺杂剂或第一掺杂剂与第二掺杂剂穿过所述第一界面层2进入所述半导体基底1内形成第三掺杂区11，即所述第三掺杂区11内含有第一掺杂剂或第一掺杂剂和第二掺杂剂。
在所述半导体基底1靠近所述第二掺杂层6的一侧内，所述第二掺杂剂穿过所述第二界面层4进入所述半导体基底1内形成第四掺杂区12，即所述第四掺杂区12内含有第二掺杂剂。
在一个具体实施方式中，所述半导体基底1内只具有第三掺杂区11。
在一个具体实施方式中，所述半导体基底1内中具有第四掺杂区12。
在一个具体实施方式中，所述半导体基底1内既含有第三掺杂区11，又含有第四掺杂区12。
所述第一种太阳能电池的制备方法，包括如下步骤：
步骤一：提供半导体基底1；
步骤二：在所述半导体基底1的第一表面形成第一掺杂层3；
步骤三：将所述第一掺杂层3进行图形化，从而保留部分第一掺杂层3；
步骤四：在所述第一掺杂层3背离所述半导体基底1的一侧表面通过加热处理形成第三掺杂层5，在未覆盖所述第一掺杂层3的半导体基底1的第一表面，形成第二掺杂层6，
所述第一掺杂层3中具有第一掺杂剂和第二掺杂剂；
所述第二掺杂层6中具有第二掺杂剂；
所述第三掺杂层5中具有第一掺杂剂和第二掺杂剂；
所述第一掺杂层3与所述第二掺杂层6的导电类型相反；
所述第三掺杂层5中至少部分区域的导电类型与所述第一掺杂层3的导电类型相同。
在步骤二中，使用LPCVD在所述半导体基底1的一侧表面形成第一界面层2，使用温度为400-700℃，在所述第一界面层2背离所述半导体基底1的一侧表面采用原位掺杂LPCVD形成第一掺杂层3。
或在步骤二中，使用LPCVD在所述半导体基底1的一侧表面形成第一 界面层2，使用温度为400-700℃，在所述第一界面层2背离所述半导体基底1的一侧表面形成第一半导体层，采用扩散将所述第一掺杂剂掺杂到所述第一半导体层内，从而形成第一掺杂层3。
所述第一半导体层可以为多晶硅层、微晶硅层或非晶硅层。
所述第一掺杂层3内的第一掺杂剂的峰值掺杂浓度为1×10 19～5×10 21atoms/cm 3。
在步骤三中，在所述第一掺杂层3背离所述半导体基底1的一侧表面上形成第一辅助层，然后将第二区域上方的第一辅助层以及第一掺杂层3刻蚀掉，从而完成图形化，只留下第一区域的第一掺杂层3。
具体地，所述第一辅助层可以为氧化硅、氮化硅等介质膜。优选地，可以使用前述磷掺杂时形成的氧化硅膜作为第一辅助层。然后将第一辅助层进行图形化，例如，使用刻蚀浆料印刷图形去除第一区域之外的第一辅助层、第一掺杂层3以及第一界面层2，或者使用短脉冲激光去除第一区域以外的第一辅助层、第一掺杂层3以及第一界面层2。
优选方案中使用碱溶液去除位于第一区域之外的第一掺杂层3和第一界面层2，并使用同一所述碱溶液使得所述第二区域中的半导体基底1表面上形成绒面结构。使用碱液在第一区域完成图形化第一掺杂层3，也同时完成了第二区域的绒面制备。使得IBC制备流程过程大大简化，可以免去目前常用的单面制绒的工艺。
现有技术中的单面制绒有两种方法：方法1、先将硅片双面抛光，然后单面制备第一辅助层，然后去制绒，制绒完成后去除第一辅助层。
方法2、先将硅片双面抛光，然后单面制备第一辅助层，然后单面抛光，然后去除第一辅助层。
现有的两种单面制绒方法都比较复杂，并且在电池制备工艺的最开始就要完成单面制绒工序。需要起码四个工序才能完成。并且，绒面在后续的正常制备电池过程中可能还会被损坏，降低电池的绒面减反射效果。
在步骤四中，在形成第二掺杂层以及第三掺杂层之前还可以先形成第二界面层4，所述第二界面层4不仅覆盖所述第一掺杂层背离所述半导体基底的一侧表面以及侧面，而且还覆盖未被所述第一掺杂层覆盖的半导体基底的第一表面。
在一个具体实施方式中，在所述第二界面层4背离所述半导体基底1以及第一掺杂层3的一侧表面形成采用原位掺杂LPCVD形成第二掺杂层6，原位掺杂指的是沉积非晶硅掺杂同时完成。然后对位于所述第一掺杂层3上方的第二掺杂层6进行加热处理，从而使得第一掺杂层3中的第一掺杂剂扩散到其上的第二掺杂层6中，位于第一掺杂层上方的第二掺杂层6中的第二掺杂剂也会扩散到第一掺杂层3中，从而使得从而使得所述第一掺杂层3上方的第二掺杂层6转变为第三掺杂层5；未覆盖所述第一掺杂层3的第一表面上方的的第二掺杂层6依然为第二掺杂层6。
具体地，所述加热处理为激光处理或热处理，当采用所述激光处理时，在所述第三掺杂层5中，被所述激光直接照射到的区域为第一导电类型区(所述第一导电类型区沿厚度方向贯穿所述第三掺杂层5)，其导电类型与第一掺杂层3的导电类型相同，且所述第一掺杂剂的掺杂浓度大于第二掺杂剂的掺杂浓度。
激光处理的功率大于5W，优选为5W-30W，加热效果更好些。波长长于500nm，可以采用绿光激光器：波长532nm；黄光激光器：波长589nm；红光激光器：波长635nm、波长660nm、波长660nm、波长670n、波长671nm；红外激光：波长808nm、波长914nm、波长946nm、波长980nm、波长1047nm、波长1053nm、波长1064nm、波长1320nm、波长1342nm。
在另一个具体实施方式中，在所述第二界面层4背离所述半导体基底1以及第一掺杂层3的一侧表面形成第二半导体层，在加热处理条件下，将第二掺杂剂扩散到所述第二半导体层中，由于温度较高，所述第一掺杂层3中的第一掺杂剂也会扩散到位于其上方的所述第二半导体层中，从而使得位于所述第一掺杂层3上方的第二半导体层为第三掺杂层5，位于所述半导体基底1第一表面上的第二半导体层为第二掺杂层6。
具体地，在所述第三掺杂层5中，靠近所述第一掺杂层3的区域，至少部分区域的导电性与所述第一掺杂层3的导电类型相同。
所述第一掺杂层3内的第一掺杂剂的峰值掺杂浓度为为1×10 19～3×10 21atoms/cm 3，第二掺杂剂的峰值掺杂浓度为1×10 19～3×10 19atoms/cm 3。
所述第三掺杂层5内部分区域的第一掺杂剂的峰值掺杂浓度为1×10 20～5×10 20atoms/cm 3，第二掺杂剂的峰值掺杂浓度为1×10 19～3× 10 19atoms/cm 3。
所述第二掺杂层6内的第二掺杂剂的峰值掺杂浓度为1×10 19～3×10 19atoms/cm 3。
具体地，所述加热处理的加热的峰值温度为850℃以上，优选为900℃以上，更优选为1000℃，例如可以为850℃、900℃、1000℃、1100℃、1200℃等；在峰值温度下，加热时间为10min以上，优选为30min以上，例如可以为10min、20min、30min、40min、50min、60min等。
所述第二半导体层可以为为多晶硅层、微晶硅层或非晶硅层。由于加热处理峰值温度较高，所述第二半导体层中的非晶硅或微晶硅会转化为多晶硅，从而可以提高第二半导体层的电导率。
可选地，在加热处理后，可以设置有去除在加热过程中可能形成的氧化膜，去除所述氧化膜层使用的溶液中包含氟元素，具体可以使用含HF或者NH 4F等的溶液等去除所述的氧化膜层。
所述方法还包括如下步骤：
步骤五：在所述第三掺杂层5以及第二掺杂层6背离所述第二界面层4的一侧表面形成背面钝化层7，同时在所述半导体基底1背离所述第一界面层2的一侧表面形成正面钝化层。
步骤六：在所述第三掺杂层5的上方形成贯穿所述背面钝化层7的第一电极8，同时，在所述第二掺杂层6的上方形成贯穿所述背面钝化层7的第二电极9。
具体地，形成电极的方法包括多种，可以直接使用烧穿型浆料涂覆在背面钝化层7上，然后经过热处理使得电极浆料穿过背面钝化层7与第三掺杂层5以及第二掺杂层6形成接触。也可以先在背面钝化层7上开孔，然后使用电极浆料、激光转印法、电镀、化学镀、光诱导电镀等方法，或者蒸发、溅射等物理气相沉积等方法形成电极。显然地，也可以使用以上方法中的一种或者多种方法的结合来形成电极。
所述第一种太阳能电池的制备方法，包括如下步骤：
步骤一：提供半导体基底1；
步骤二：在所述半导体基底1的第一表面形成第一掺杂层3；
具体地，使用LPCVD在所述半导体基底1的一侧表面形成第一界面层2，使用温度为400-700℃，在所述第一界面层2背离所述半导体基底1的一侧表面采用原位掺杂LPCVD形成第一掺杂层3。
或在步骤二中，使用LPCVD在所述半导体基底1的一侧表面形成第一界面层2，使用温度为400-700℃，在所述第一界面层2背离所述半导体基底1的一侧表面形成第一半导体层，采用扩散将所述第一掺杂剂掺杂到所述第一半导体层内，从而形成第一掺杂层3。
所述第一半导体层可以为多晶硅层、微晶硅层或非晶硅层。
所述第一掺杂层3内的第一掺杂剂的峰值掺杂浓度为1×10 19～5×10 21atoms/cm 3。
步骤三：将所述第一掺杂层3进行图形化，从而保留部分第一掺杂层3；
具体地，在所述第一掺杂层3背离所述半导体基底1的一侧表面上形成第一辅助层，然后将第二区域上方的第一辅助层以及第一掺杂层3刻蚀掉，从而完成图形化，只留下第一区域的第一掺杂层3。
具体地，所述第一辅助层可以为氧化硅、氮化硅等介质膜。优选地，可以使用前述磷掺杂时形成的氧化硅膜作为第一辅助层。然后将第一辅助层进行图形化，例如，使用刻蚀浆料印刷图形去除第一区域之外的第一辅助层、第一掺杂层3以及第一界面层2，或者使用短脉冲激光去除第一区域以外的第一辅助层、第一掺杂层3以及第一界面层2。
优选方案中使用碱溶液去除位于第一区域之外的第一掺杂层3和第一界面层2，并使用同一所述碱溶液使得所述第二区域中的半导体基底1表面上形成绒面结构。使用碱液在第一区域完成图形化第一掺杂层3，也同时完成了第二区域的绒面制备。使得IBC制备流程过程大大简化，可以免去目前常用的单面制绒的工艺。
现有技术中的单面制绒有两种方法：方法1、先将硅片双面抛光，然后单面制备第一辅助层，然后去制绒，制绒完成后去除第一辅助层。
方法2、先将硅片双面抛光，然后单面制备第一辅助层，然后单面抛光，然后去除第一辅助层。
现有的两种单面制绒方法都比较复杂，并且在电池制备工艺的最开始就要完成单面制绒工序。需要起码四个工序才能完成。并且，绒面在后续的正 常制备电池过程中可能还会被损坏，降低电池的绒面减反射效果。
步骤四：在所述第一掺杂层3背离所述半导体基底1的一侧表面通过加热处理形成第三掺杂层5，在未覆盖所述第一掺杂层3的半导体基底1的第一表面，形成第二掺杂层6。
所述第一掺杂层3中具有第一掺杂剂和第二掺杂剂；
所述第二掺杂层6中具有第二掺杂剂；
所述第三掺杂层5中具有第一掺杂剂和第二掺杂剂；
所述第一掺杂层3与所述第二掺杂层6的导电类型相反；
所述第三掺杂层5中至少部分区域的导电类型与所述第一掺杂层3的导电类型相同。
具体地，在形成第二掺杂层以及第三掺杂层之前还可以先形成第二界面层4，所述第二界面层4不仅覆盖所述第一掺杂层背离所述半导体基底的一侧表面以及侧面，而且还覆盖未被所述第一掺杂层覆盖的半导体基底的第一表面。
在一个具体实施方式中，在所述第二界面层4背离所述半导体基底1以及第一掺杂层3的一侧表面采用原位掺杂LPCVD形成第二掺杂层6。然后对位于所述第一掺杂层3上方的第二掺杂层6进行加热处理，从而使得第一掺杂层3中的第一掺杂剂扩散到其上的第二掺杂层6中，位于第一掺杂层上方的第二掺杂层6中的第二掺杂剂也会扩散到第一掺杂层3中，从而使得从而使得所述第一掺杂层3上方的第二掺杂层6转变为第三掺杂层5；未覆盖所述第一掺杂层3的第一表面上方的的第二掺杂层6依然为第二掺杂层6。
具体地，所述加热处理为激光处理或热处理，当采用所述激光处理时，在所述第三掺杂层5中，被所述激光直接照射到的区域为第一导电类型区(所述第一导电类型区沿厚度方向贯穿所述第三掺杂层5)，其导电类型与第一掺杂层3的导电类型相同，且所述第一掺杂剂的掺杂浓度大于第二掺杂剂的掺杂浓度。激光处理的功率大于5W，优选为5W-30W，加热效果更好些。波长长于500nm，可以采用绿光激光器：波长532nm；黄光激光器：波长589nm；红光激光器：波长635nm、波长660nm、波长660nm、波长670n、波长671nm；红外激光：波长808nm、波长914nm、波长946nm、波长980nm、波长1047nm、波长1053nm、波长1064nm、波长1320nm、波长1342nm。
在另一个具体实施方式中，在所述第二界面层4背离所述半导体基底1以及第一掺杂层3的一侧表面形成第二半导体层，在加热处理的条件下，将第二掺杂剂扩散到所述第二半导体层中，由于温度较高，所述第一掺杂层3中的第一掺杂剂也会扩散到位于其上方的所述第二半导体层中，从而使得位于所述第一掺杂层3上方的第二半导体层为第三掺杂层5，位于所述半导体基底1第一表面上的第二半导体层为第二掺杂层6。
具体地，在所述第三掺杂层5中，靠近所述第一掺杂层3的区域，至少部分区域的导电性与所述第一掺杂层3的导电类型相同。
所述第一掺杂层3内的第一掺杂剂的峰值掺杂浓度为1×10 19～3×10 21atoms/cm 3，第二掺杂剂的峰值掺杂浓度为1×10 19～3×10 19atoms/cm 3。
所述第三掺杂层5内部分区域的第一掺杂剂的峰值掺杂浓度为1×10 20～5×10 20atoms/cm 3，第二掺杂剂的峰值掺杂浓度为1×10 19～3×10 19atoms/cm 3。
所述第二掺杂层6内的第二掺杂剂的峰值掺杂浓度为1×10 19～3×10 19atoms/cm 3。
具体地，所述加热处理或加热条件的下的加热的峰值温度为850℃以上，优选为900℃以上，更优选为1000℃，例如可以为850℃、900℃、1000℃、1100℃、1200℃等；在峰值温度下，加热时间为10min以上，优选为30min以上，例如可以为10min、20min、30min、40min、50min、60min等。
所述第二半导体层可以为为多晶硅层、微晶硅层或非晶硅层。由于加热处理峰值温度较高，所述第二半导体层中的非晶硅或微晶硅会转化为多晶硅，从而可以提高第二半导体层的电导率。
可选地，在加热处理后，可以设置有去除在加热过程中可能形成的氧化膜，去除所述氧化膜层使用的溶液中包含氟元素，具体可以使用含HF或者NH 4F等的溶液等去除所述的氧化膜层。
步骤五：在所述第三掺杂层5以及第二掺杂层6背离所述第二界面层4的一侧表面形成背面钝化层7，同时在所述半导体基底1背离所述第一界面层2的一侧表面形成正面钝化层。
步骤六：在所述第三掺杂层5的上方形成贯穿所述背面钝化层7的第一电极8，同时，在所述第二掺杂层6的上方形成贯穿所述背面钝化层7的第 二电极9。
具体地，形成电极的方法包括多种，可以直接使用烧穿型浆料涂覆在背面钝化层7上，然后经过热处理使得电极浆料穿过背面钝化层7与第三掺杂层5以及第二掺杂层6形成接触。也可以先在背面钝化层7上开孔，然后使用电极浆料、激光转印法、电镀、化学镀、光诱导电镀等方法，或者蒸发、溅射等物理气相沉积等方法形成电极。显然地，也可以使用以上方法中的一种或者多种方法的结合来形成电极。
如图2所示，第二种太阳能电池，包括半导体基底1，在所述半导体基底1的一侧表面划分为具有间隔的第一区域和第二区域，在所述第一区域内的半导体基底1的一侧表面依次设置有第一界面层2、第一掺杂层3、第二界面层4以及第三掺杂层5，在所述第二区域内的半导体基底1的同一侧表面依次设置有第二界面层4以及第二掺杂层6。所述第三掺杂层5、第二界面层4、第一掺杂层3以及第一界面层2靠近所述第二掺杂层6的侧面、未覆盖第一掺杂层3以及第二掺杂层6的半导体基底1表面以及第二界面层4、第二掺杂层6靠近所述第一掺杂层3的侧面形成一个凹槽，所述凹槽为隔离区10，在所述第三掺杂层5背离所述第二界面层4的一侧表面还设置有覆盖第三掺杂层5、隔离区10以及第二掺杂层6的背面钝化层7。位于所述第三掺杂层5上方的背面钝化层7上还设置有穿过所述背面钝化层7与所述第三掺杂层5接触的第一电极8，位于所述第二掺杂层6上方的背面钝化层7上还设置有穿过所述背面钝化层7与所述第二掺杂层6接触的第二电极9。
所述第二种太阳能电池和第一种太阳能电池的区别仅在于第二种太阳能电池中的第一区域和第二区域之间具有隔离区10，且在隔离区10内仅具有背面钝化层7(第三掺杂层5没有与第二掺杂层6接触)，因此第二种太阳能电池中的半导体基底1、第一界面层2、第二界面层4、第一掺杂层3、第二掺杂层6、第三掺杂层5、背面钝化层7以及第一电极8和第二电极9均可以参考第一种太阳能电池，
所述隔离区10的深度为h为300nm-1μm，例如可以为300nm、400nm、500nm、600nm、700nm、800nm、900nm或1μm。所述隔离区10的宽度为w为10-200μm，优选30-100μm。例如可以为10μm、20μm、30μm、40μm、 50μm、60μm、70μm、80μm、90μm、100μm、110μm、120μm、130μm、140μm、150μm、160μm、170μm、180μm、190μm或200μm。
位于所述隔离区10处的所述背面钝化层7与所述隔离区10共形。
所述隔离区10用于隔离p型和n型半导体区域，以防止漏电，也防止击穿侧向pn结导致发热等现象的出现。在本公开的方案中，由于所述第一掺杂区中既有p型掺杂，又有n型掺杂，因此，隔离区10的存在更为重要。
所述背面钝化层7在所述第一掺杂层3、隔离区10以及第二掺杂层6上的厚度相等。
第二种太阳能电池的制备方法，包括如下步骤：
步骤一：提供半导体基底1；
步骤二：在所述半导体基底1的一侧表面形成第一掺杂层3；
步骤三：将所述第一掺杂层3进行图形化，从而保留部分第一掺杂层3；
步骤四：在所述第一掺杂层3背离所述半导体基底1的一侧表面通过加热处理形成第三掺杂层5，在未覆盖所述第一掺杂层3的半导体基底1的第一表面，形成第二掺杂层6；
步骤五：在所述第三掺杂层5以及第二掺杂层6背离所述第二界面层4的一侧表面分别形成第二辅助层，靠近第三掺杂层5与所述第二掺杂层6的交界处未覆盖第二辅助层。
步骤六：将未覆盖所述第二辅助层的第三掺杂层5以及第二掺杂层6刻蚀掉，从而露出半导体基底1(露出的半导体基底1称为隔离区10)，所述第三掺杂层5、第二界面层4、第一掺杂层3以及第一界面层2靠近所述隔离区10的侧面、隔离区10的半导体基底1表面以及第二界面层4、第二掺杂层6靠近所述隔离区10的侧面形成一个隔离区10。
所述第一掺杂层3中具有第一掺杂剂和第二掺杂剂；
所述第二掺杂层6中具有第二掺杂剂；
所述第三掺杂层5中具有第一掺杂剂和第二掺杂剂；
所述第一掺杂层3与所述第二掺杂层6的导电类型相反；
所述第三掺杂层5中至少部分区域中的导电类型与所述第一掺杂层的导电类型相同。
在步骤二中使用LPCVD在所述半导体基底1的一侧表面形成第一界面层2，使用温度为400-700℃。
一个具体实施方式中，在所述第一界面层2背离所述半导体基底1的一侧表面采用原位掺杂LPCVD形成第一掺杂层3。
在另一个具体实施方式中，在所述第一界面层2背离所述半导体基底1的一侧表面形成第一半导体层，将所述第一掺杂剂掺杂到所述第一半导体层内，从而形成第一掺杂层3。
所述第一半导体层可以为多晶硅层、微晶硅层或非晶硅层。
所述第一掺杂层3内的第一掺杂剂的峰值掺杂浓度为1×10 19～5×10 21atoms/cm 3。
在步骤三中，在所述第一掺杂层3背离所述半导体基底1的一侧表面上形成第一辅助层，然后将第二区域上方的第一辅助层以及第一掺杂层3刻蚀掉，从而完成图形化，只留下第一区域的第一掺杂层3。
具体地，所述第一辅助层可以为氧化硅、氮化硅等介质膜。优选地，可以使用前述磷掺杂时形成的氧化硅膜作为第一辅助层。然后将第一辅助层进行图形化，例如，使用刻蚀浆料印刷图形去除第一区域之外的第一辅助层、第一掺杂层3以及第一界面层2，或者使用短脉冲激光去除第一区域以外的第一辅助层、第一掺杂层3以及第一界面层2。
优选方案中使用碱溶液去除位于第一区域之外的第一掺杂层3和第一界面层2，并使用同一所述碱溶液使得所述第二区域中的半导体基底1表面上形成绒面结构。使用碱液在第一区域完成图形化第一掺杂层3，也同时完成了第二区域的绒面制备。使得IBC制备流程过程大大简化，可以免去目前常用的单面制绒的工艺。
现有技术中的单面制绒有两种方法：方法1、先将硅片双面抛光，然后单面制备第一辅助层，然后去制绒，制绒完成后去除第一辅助层。
方法2、先将硅片双面抛光，然后单面制备第一辅助层，然后单面抛光，然后去除第一辅助层。
现有的两种单面制绒方法都比较复杂，并且在电池制备工艺的最开始就要完成单面制绒工序。需要起码四个工序才能完成。并且，绒面在后续的正常制备电池过程中可能还会被损坏，降低电池的绒面减反射效果。
在步骤四中，在形成第二掺杂层以及第三掺杂层之前还可以先形成第二界面层4，所述第二界面层4不仅覆盖所述第一掺杂层背离所述半导体基底的一侧表面以及侧面，而且还覆盖未被所述第一掺杂层覆盖的半导体基底的第一表面。
在一个具体实施方式中，在所述第二界面层4背离所述半导体基底1以及第一掺杂层3的一侧表面形成采用原位掺杂LPCVD形成第二掺杂层6，原位掺杂指的是沉积非晶硅掺杂同时完成。然后对位于所述第一掺杂层3上方的第二掺杂层6进行加热处理，从而使得第一掺杂层3中的第一掺杂剂扩散到其上的第二掺杂层6中，位于第一掺杂层上方的第二掺杂层6中的第二掺杂剂也会扩散到第一掺杂层3中，从而使得从而使得所述第一掺杂层3上方的第二掺杂层6转变为第三掺杂层5；未覆盖所述第一掺杂层3的第一表面上方的的第二掺杂层6依然为第二掺杂层6。
具体地，所述加热处理为激光处理或热处理，当采用所述激光处理时，在所述第三掺杂层5中，被所述激光直接照射到的区域为第一导电类型区(所述第一导电类型区沿厚度方向贯穿所述第三掺杂层5)，其导电类型与第一掺杂层3的导电类型相同，且所述第一掺杂剂的掺杂浓度大于第二掺杂剂的掺杂浓度。激光处理的功率大于5W，优选为5W-30W，加热效果更好些。波长长于500nm，可以采用绿光激光器：波长532nm；黄光激光器：波长589nm；红光激光器：波长635nm、波长660nm、波长660nm、波长670n、波长671nm；红外激光：波长808nm、波长914nm、波长946nm、波长980nm、波长1047nm、波长1053nm、波长1064nm、波长1320nm、波长1342nm。
在另一个具体实施方式中，在所述第二界面层4背离所述半导体基底1以及第一掺杂层3的一侧表面形成第二半导体层，在加热处理条件下，将第二掺杂剂扩散到所述第二半导体层中，由于温度较高，所述第一掺杂层3中的第一掺杂剂也会扩散到位于其上方的所述第二半导体层中，从而使得位于所述第一掺杂层3上方的第二半导体层为第三掺杂层5，位于所述半导体基底1第一表面上的第二半导体层为第二掺杂层6。
具体地，在所述第三掺杂层5中，靠近所述第一掺杂层3的区域，至少部分区域的导电性与所述第一掺杂层3的导电类型相同。
所述第一掺杂层3内的第一掺杂剂的峰值掺杂浓度为1×10 19～3× 10 21atoms/cm 3，第二掺杂剂的峰值掺杂浓度为1×10 19～3×10 19atoms/cm 3。
所述第三掺杂层5内部分区域的第一掺杂剂的峰值掺杂浓度为1×10 20～5×10 20atoms/cm 3，第二掺杂剂的峰值掺杂浓度为1×10 19～3×10 19atoms/cm 3。
所述第二掺杂层6内的第二掺杂剂的峰值掺杂浓度为1×10 19～3×10 19atoms/cm 3。
具体地，所述加热处理或加热条件的下的加热的峰值温度为850℃以上，优选为900℃以上，更优选为1000℃，例如可以为850℃、900℃、1000℃、1100℃、1200℃等；在峰值温度下，加热时间为10min以上，优选为30min以上，例如可以为10min、20min、30min、40min、50min、60min等。
所述第二半导体层可以为多晶硅层、微晶硅层或非晶硅层。由于加热处理峰值温度较高，所述第二半导体层中的非晶硅或微晶硅会转化为多晶硅，从而可以提高第二半导体层的电导率。
可选地，在加热处理后，可以设置有去除在加热过程中可能形成的氧化膜，去除所述氧化膜层使用的溶液中包含氟元素，具体可以使用含HF或者NH 4F等的溶液等去除所述的氧化膜层。
在步骤五中，所述第二辅助层可以为氧化硅、氮化硅等介质膜。
在步骤六中，采用刻蚀浆料或激光去除第三掺杂层5、第二掺杂层6以及其下方的第二界面层4。
优选地，在去除第三掺杂层5第二掺杂层6以及其下方的第二界面层4时，还可以进一步去掉该第二界面层4下方的部分半导体基底1，从而加深隔离区10的深度，隔离区10越深，隔离效果越好。因为一般情况下，第一半导体层或第二半导体层中的掺杂剂都会有一定的量穿过界面层而来到半导体基底中，因此半导体基底1中的掺杂也如前面描述，会有漏电或者击穿发热的危险，因此隔离区10伸入半导体基底1内，可以减小漏电或者击穿发热的危险。
进一步地，刻蚀步骤完成后，去除第二辅助层。
所述方法还包括如下步骤：
步骤七：在所述第三掺杂层5以及第二掺杂层6背离所述第二界面层4的一侧表面形成背面钝化层7，同时在所述半导体基底1背离所述第一界面 层2的一侧表面形成正面钝化层。
步骤八：在所述第三掺杂层5的上方形成贯穿所述背面钝化层7的第一电极8，同时，在所述第二掺杂层6的上方形成贯穿所述背面钝化层7的第二电极9。
具体地，形成电极的方法包括多种，可以直接使用烧穿型浆料涂覆在背面钝化层7上，然后经过热处理使得电极浆料穿过背面钝化层7与第三掺杂层5以及第二掺杂层6形成接触。也可以先在背面钝化层7上开孔，然后使用电极浆料、激光转印法、电镀、化学镀、光诱导电镀等方法，或者蒸发、溅射等物理气相沉积等方法形成电极。显然地，也可以使用以上方法中的一种或者多种方法的结合来形成电极。
第二种太阳能电池的制备方法，包括如下步骤：
步骤一：提供半导体基底1；
步骤二：在所述半导体基底1的一侧表面形成第一掺杂层3；
具体地，使用LPCVD在所述半导体基底1的一侧表面形成第一界面层2，使用温度为400-700℃。
在一个具体实施方式中，在所述第一界面层2背离所述半导体基底1的一侧表面采用原位掺杂LPCVD形成第一掺杂层3。
在另一个具体实施方式中，在所述第一界面层2背离所述半导体基底1的一侧表面形成第一半导体层，将所述第一掺杂剂掺杂到所述第一半导体层内，从而形成第一掺杂层3。
所述第一半导体层可以为多晶硅层、微晶硅层或非晶硅层。
所述第一掺杂层3内的第一掺杂剂的峰值掺杂浓度为1×10 19～5×10 21atoms/cm 3。
步骤三：将所述第一掺杂层3进行图形化，从而保留部分第一掺杂层3；
具体地，在所述第一掺杂层3背离所述半导体基底1的一侧表面上形成第一辅助层，然后将第二区域上方的第一辅助层以及第一掺杂层3刻蚀掉，从而完成图形化，只留下第一区域的第一掺杂层3。
具体地，所述第一辅助层可以为氧化硅、氮化硅等介质膜。优选地，可以使用前述磷掺杂时形成的氧化硅膜作为第一辅助层。然后将第一辅助层进 行图形化，例如，使用刻蚀浆料印刷图形去除第一区域之外的第一辅助层、第一掺杂层3以及第一界面层2，或者使用短脉冲激光去除第一区域以外的第一辅助层、第一掺杂层3以及第一界面层2。
优选方案中使用碱溶液去除位于第一区域之外的第一掺杂层3和第一界面层2，并使用同一所述碱溶液使得所述第二区域中的半导体基底1表面上形成绒面结构。使用碱液在第一区域完成图形化第一掺杂层3，也同时完成了第二区域的绒面制备。使得IBC制备流程过程大大简化，可以免去目前常用的单面制绒的工艺。
现有技术中的单面制绒有两种方法：方法1、先将硅片双面抛光，然后单面制备第一辅助层，然后去制绒，制绒完成后去除第一辅助层。
方法2、先将硅片双面抛光，然后单面制备第一辅助层，然后单面抛光，然后去除第一辅助层。
现有的两种单面制绒方法都比较复杂，并且在电池制备工艺的最开始就要完成单面制绒工序。需要起码四个工序才能完成。并且，绒面在后续的正常制备电池过程中可能还会被损坏，降低电池的绒面减反射效果。
步骤四：在所述第一掺杂层3背离所述半导体基底1的一侧表面通过加热处理形成第三掺杂层5，在未覆盖所述第一掺杂层3的半导体基底1的第一表面，形成第二掺杂层6；
具体地，在形成第二掺杂层以及第三掺杂层之前还可以先形成第二界面层4，所述第二界面层4不仅覆盖所述第一掺杂层背离所述半导体基底的一侧表面以及侧面，而且还覆盖未被所述第一掺杂层覆盖的半导体基底的第一表面。
在一个具体实施方式中，在所述第二界面层4背离所述半导体基底1以及第一掺杂层3的一侧表面形成采用原位掺杂LPCVD形成第二掺杂层6，原位掺杂指的是沉积非晶硅掺杂同时完成。然后对位于所述第一掺杂层3上方的第二掺杂层6进行加热处理，从而使得第一掺杂层3中的第一掺杂剂扩散到其上的第二掺杂层6中，位于第一掺杂层上方的第二掺杂层6中的第二掺杂剂也会扩散到第一掺杂层3中，从而使得从而使得所述第一掺杂层3上方的第二掺杂层6转变为第三掺杂层5；未覆盖所述第一掺杂层3的第一表面上方的的第二掺杂层6依然为第二掺杂层6。
具体地，所述加热处理为激光处理或热处理，当采用所述激光处理时，在所述第三掺杂层5中，被所述激光直接照射到的区域为第一导电类型区(所述第一导电类型区沿厚度方向贯穿所述第三掺杂层5)，其导电类型与第一掺杂层3的导电类型相同，且所述第一掺杂剂的掺杂浓度大于第二掺杂剂的掺杂浓度。激光处理的功率大于5W，优选为5W-30W，加热效果更好些。波长长于500nm，可以采用绿光激光器：波长532nm；黄光激光器：波长589nm；红光激光器：波长635nm、波长660nm、波长660nm、波长670n、波长671nm；红外激光：波长808nm、波长914nm、波长946nm、波长980nm、波长1047nm、波长1053nm、波长1064nm、波长1320nm、波长1342nm。
在另一个具体实施方式中，在所述第二界面层4背离所述半导体基底1以及第一掺杂层3的一侧表面形成第二半导体层，在加热条件下，将第二掺杂剂扩散到所述第二半导体层中，由于温度较高，所述第一掺杂层3中的第一掺杂剂也会扩散到位于其上方的所述第二半导体层中，从而使得位于所述第一掺杂层3上方的第二半导体层为第三掺杂层5，位于所述半导体基底1第一表面上的第二半导体层为第二掺杂层6。
具体地，在所述第三掺杂层5中，靠近所述第一掺杂层3的区域，至少部分区域的导电性与所述第一掺杂层3的导电类型相同。
所述第一掺杂层3内的第一掺杂剂的峰值掺杂浓度为1×10 19～3×10 21atoms/cm 3，第二掺杂剂的峰值掺杂浓度为1×10 19～3×10 19atoms/cm 3。
所述第三掺杂层5内部分区域的第一掺杂剂的峰值掺杂浓度为1×10 20～5×10 20atoms/cm 3，第二掺杂剂的峰值掺杂浓度为1×10 19～3×10 19atoms/cm 3。
所述第二掺杂层6内的第二掺杂剂的峰值掺杂浓度为1×10 19～3×10 19atoms/cm 3。
具体地，所述加热处理或加热条件的下的加热的峰值温度为850℃以上，优选为900℃以上，更优选为1000℃，例如可以为850℃、900℃、1000℃、1100℃、1200℃等；在峰值温度下，加热时间为10min以上，优选为30min以上，例如可以为10min、20min、30min、40min、50min、60min等。
所述第二半导体层可以为为多晶硅层、微晶硅层或非晶硅层。由于加热处理峰值温度较高，所述第二半导体层中的非晶硅或微晶硅会转化为多晶 硅，从而可以提高第二半导体层的电导率。
可选地，在加热处理后，可以设置有去除在加热过程中可能形成的氧化膜，去除所述氧化膜层使用的溶液中包含氟元素，具体可以使用含HF或者NH 4F等的溶液等去除所述的氧化膜层。
步骤五：在所述第三掺杂层5以及第二掺杂层6背离所述第二界面层4的一侧表面分别形成第二辅助层，靠近第三掺杂层5与所述第二掺杂层6的交界处未覆盖第二辅助层。
所述第二辅助层可以为氧化硅、氮化硅等介质膜。
步骤六：将未覆盖所述第二辅助层的第三掺杂层5以及第二掺杂层6刻蚀掉，从而露出半导体基底1(露出的半导体基底1称为隔离区10)，所述第三掺杂层5、第二界面层4、第一掺杂层3以及第一界面层2靠近所述隔离区10的侧面、隔离区10的半导体基底1表面以及第二界面层4、第二掺杂层6靠近所述隔离区10的侧面形成一个隔离区10。
所述第一掺杂层3中具有第一掺杂剂和第二掺杂剂；
所述第二掺杂层6中具有第二掺杂剂；
所述第三掺杂层5中具有第一掺杂剂和第二掺杂剂；
所述第一掺杂层3与所述第二掺杂层6的导电类型相反；
所述第三掺杂层5中至少部分区域中的导电类型与所述第一掺杂层的导电类型相同。
具体地，采用刻蚀浆料或激光去除第三掺杂层5第二掺杂层6以及其下方的第二界面层4。
优选地，在去除第三掺杂层5第二掺杂层6以及其下方的第二界面层4时，还可以进一步去掉该第二界面层4下方的部分半导体基底1，从而加深隔离区10的深度，隔离区10越深，隔离效果越好。因为一般情况下，第一半导体层或第二半导体层中的掺杂剂都会有一定的量穿过界面层而来到半导体基底中，因此半导体基底1中的掺杂也如前面描述，会有漏电或者击穿发热的危险，因此隔离区10伸入半导体基底1内，可以减小漏电或者击穿发热的危险。
进一步地，刻蚀步骤完成后，去除第二辅助层。
步骤七：在所述第三掺杂层5以及第二掺杂层6背离所述第二界面层4 的一侧表面形成背面钝化层7，同时在所述半导体基底1背离所述第一界面层2的一侧表面形成正面钝化层。
步骤八：在所述第三掺杂层5的上方形成贯穿所述背面钝化层7的第一电极8，同时，在所述第二掺杂层6的上方形成贯穿所述背面钝化层7的第二电极9。
具体地，形成电极的方法包括多种，可以直接使用烧穿型浆料涂覆在背面钝化层7上，然后经过热处理使得电极浆料穿过背面钝化层7与第三掺杂层5以及第二掺杂层6形成接触。也可以先在背面钝化层7上开孔，然后使用电极浆料、激光转印法、电镀、化学镀、光诱导电镀等方法，或者蒸发、溅射等物理气相沉积等方法形成电极。显然地，也可以使用以上方法中的一种或者多种方法的结合来形成电极。
第二种太阳能电池的制备方法，包括如下步骤：
步骤一：提供半导体基底1；
步骤二：在所述半导体基底1的一侧表面形成第一掺杂层3；
具体地，使用LPCVD在所述半导体基底1的一侧表面形成第一界面层2，使用温度为400-700℃。
在一个具体实施方式中，在所述第一界面层2背离所述半导体基底1的一侧表面采用原位掺杂LPCVD形成第一掺杂层3。
在另一个具体实施方式中，在所述第一界面层2背离所述半导体基底1的一侧表面形成第一半导体层，采用扩散将所述第一掺杂剂掺杂到所述第一半导体层内，从而形成第一掺杂层3。
所述第一半导体层可以为多晶硅层、微晶硅层或非晶硅层。
所述第一掺杂层3内的第一掺杂剂的峰值掺杂浓度为1×10 19～5×10 21atoms/cm 3。
步骤三：将所述第一掺杂层3进行图形化，从而保留部分第一掺杂层3；
具体地，在所述第一掺杂层3背离所述半导体基底1的一侧表面上形成第一辅助层，然后将第二区域上方的第一辅助层以及第一掺杂层3刻蚀掉，从而完成图形化，只留下第一区域的第一掺杂层3。
具体地，所述第一辅助层可以为氧化硅、氮化硅等介质膜。优选地，可 以使用前述磷掺杂时形成的氧化硅膜作为第一辅助层。然后将第一辅助层进行图形化，例如，使用刻蚀浆料印刷图形去除第一区域之外的第一辅助层、第一掺杂层3以及第一界面层2，或者使用短脉冲激光去除第一区域以外的第一辅助层、第一掺杂层3以及第一界面层2。
优选方案中使用碱溶液去除位于第一区域之外的第一掺杂层3和第一界面层2，并使用同一所述碱溶液使得所述第二区域中的半导体基底1表面上形成绒面结构。使用碱液在第一区域完成图形化第一掺杂层3，也同时完成了第二区域的绒面制备。使得IBC制备流程过程大大简化，可以免去目前常用的单面制绒的工艺。
现有技术中的单面制绒有两种方法：方法1、先将硅片双面抛光，然后单面制备第一辅助层，然后去制绒，制绒完成后去除第一辅助层。
方法2、先将硅片双面抛光，然后单面制备第一辅助层，然后单面抛光，然后去除第一辅助层。
现有的两种单面制绒方法都比较复杂，并且在电池制备工艺的最开始就要完成单面制绒工序。需要起码四个工序才能完成。并且，绒面在后续的正常制备电池过程中可能还会被损坏，降低电池的绒面减反射效果。
步骤四：首先先形成第二界面层4，所述第二界面层4不仅覆盖所述第一掺杂层背离所述半导体基底的一侧表面以及侧面，而且还覆盖未被所述第一掺杂层覆盖的半导体基底的第一表面。
在所述第二界面层4背离所述半导体基底1以及第一掺杂层3的一侧表面形成采用原位掺杂LPCVD形成第二掺杂层6，原位掺杂指的是沉积非晶硅掺杂同时完成。
在所述第二掺杂层6背离所述第二界面层4的一侧表面分别形成第二辅助层，在半导体基底1第一表面上的所述第二掺杂层6与第一掺杂层的交界处未覆盖第二辅助层。
将未覆盖第二辅助层的第一掺杂层3、第二掺杂层6、第一界面层以及第二界面层均刻蚀掉，露出所述半导体基底的第一表面，从而使得所述第一掺杂层3与所述第二掺杂层6之间具有隔离区10。然后去掉所述第二辅助层。
所述第二辅助层可以为氧化硅、氮化硅等介质膜。
优选地，在去除第一掺杂层3、第二掺杂层6以及其下方的第一界面层、 第二界面层4露出半导体基底1的第一表面时，还可以进一步去掉该部分半导体基底1，从而加深隔离区10的深度，隔离区10越深，隔离效果越好。因为一般情况下，第一半导体层或第二半导体层中的掺杂剂都会有一定的量穿过界面层而来到半导体基底中，因此半导体基底1中的掺杂也如前面描述，会有漏电或者击穿发热的危险，因此隔离区10伸入半导体基底1内，可以减小漏电或者击穿发热的危险。
进一步地，刻蚀步骤完成后，去除第二辅助层。
步骤五：对位于所述第一掺杂层3上方的第二掺杂层6进行加热处理，从而使得第一掺杂层3中的第一掺杂剂扩散到其上的第二掺杂层6中，位于第一掺杂层上方的第二掺杂层6中的第二掺杂剂也会扩散到第一掺杂层3中，从而使得从而使得所述第一掺杂层3上方的第二掺杂层6转变为第三掺杂层5；未覆盖所述第一掺杂层3的第一表面上方的的第二掺杂层6依然为第二掺杂层6。
具体地，在所述第三掺杂层5中，靠近所述第一掺杂层3的区域，至少部分区域的导电性与所述第一掺杂层3的导电类型相同。
所述第一掺杂层3内的第一掺杂剂的峰值掺杂浓度为1×10 19～3×10 21atoms/cm 3，第二掺杂剂的峰值掺杂浓度为1×10 19～3×10 19atoms/cm 3。
所述第三掺杂层5内部分区域的第一掺杂剂的峰值掺杂浓度为1×10 20～5×10 20atoms/cm 3，第二掺杂剂的峰值掺杂浓度为1×10 19～3×10 19atoms/cm 3。
所述第二掺杂层6内的第二掺杂剂的峰值掺杂浓度为1×10 19～3×10 19atoms/cm 3。
具体地，所述加热处理或加热条件的下的加热的峰值温度为850℃以上，优选为900℃以上，更优选为1000℃，例如可以为850℃、900℃、1000℃、1100℃、1200℃等；在峰值温度下，加热时间为10min以上，优选为30min以上，例如可以为10min、20min、30min、40min、50min、60min等。
所述第二半导体层可以为为多晶硅层、微晶硅层或非晶硅层。由于加热处理峰值温度较高，所述第二半导体层中的非晶硅或微晶硅会转化为多晶硅，从而可以提高第二半导体层的电导率。
可选地，在加热处理后，可以设置有去除在加热过程中可能形成的氧化 膜，去除所述氧化膜层使用的溶液中包含氟元素，具体可以使用含HF或者NH 4F等的溶液等去除所述的氧化膜层。
所述第一掺杂层3中具有第一掺杂剂和第二掺杂剂；
所述第二掺杂层6中具有第二掺杂剂；
所述第三掺杂层5中具有第一掺杂剂和第二掺杂剂；
所述第一掺杂层3与所述第二掺杂层6的导电类型相反；
所述第三掺杂层5中至少部分区域中的导电类型与所述第一掺杂层的导电类型相同。
步骤六：在所述第三掺杂层5以及第二掺杂层6背离所述第二界面层4的一侧表面形成背面钝化层7，同时在所述半导体基底1背离所述第一界面层2的一侧表面形成正面钝化层。
步骤七：在所述第三掺杂层5的上方形成贯穿所述背面钝化层7的第一电极8，同时，在所述第二掺杂层6的上方形成贯穿所述背面钝化层7的第二电极9。
具体地，形成电极的方法包括多种，可以直接使用烧穿型浆料涂覆在背面钝化层7上，然后经过热处理使得电极浆料穿过背面钝化层7与第三掺杂层5以及第二掺杂层6形成接触。也可以先在背面钝化层7上开孔，然后使用电极浆料、激光转印法、电镀、化学镀、光诱导电镀等方法，或者蒸发、溅射等物理气相沉积等方法形成电极。显然地，也可以使用以上方法中的一种或者多种方法的结合来形成电极。
实施例
下述实施例中所使用的实验方法如无特殊要求，均为常规方法。
下述实施例中所使用的材料、试剂等，如无特殊说明，均可从商业途径得到。
实施例1
本实施例中的太阳能电池为第一种太阳能电池，包括如下步骤：
步骤一：提供半导体基底1；
提供p型硅片为半导体基底1，其厚度为200μm。
步骤二：在所述半导体基底1的一侧表面形成第一掺杂层3；
具体地，使用LPCVD在所述半导体基底1的一侧表面形成第一界面层2，使用温度为700℃，在所述第一界面层2背离所述半导体基底1的一侧表面形成掺磷非晶硅层3。此掺磷非晶硅3采用原位掺杂LPCVD形成，沉积源为SiH 4，含磷掺杂源为PH 3。
第一界面层2为氧化硅层，其厚度为1nm，所述本征非晶硅层的厚度为100nm。
所述第一掺杂层3内的第一掺杂剂的峰值掺杂浓度为3×10 21atoms/cm 3。
步骤三：将所述第一掺杂层3进行图形化，从而保留部分第一掺杂层3；
具体地，在所述第一掺杂层3背离所述半导体基底1的一侧表面上形成厚度为20nm氧化硅层(即第一辅助层)，然后使用短脉冲激光将第二区域上方的氧化硅、第一掺杂层3以及第一界面层2刻蚀掉，从而完成图形化，只留下第一区域的第一掺杂层3。
步骤四：在所述第一掺杂层3背离所述半导体基底1的一侧表面形成覆盖所述第一掺杂层3以及所述半导体基底1未覆盖第一掺杂层3的表面的氧化硅层(即第二辅助层)，其厚度为20nm；
步骤五：在所述第二界面层4背离所述半导体基底1以及第一掺杂层3的一侧表面形成采用原位掺杂LPCVD形成第二掺杂层6，原位掺杂指的是沉积非晶硅掺杂同时完成，第二掺杂层6为25nm，采用原位掺杂的含硼掺杂物为B 2H 6，从而形成第二掺杂层6。然后对位于所述第一掺杂层3上方的第二掺杂层6进行加热处理(峰值温度为900℃，加热时长为30min)，从而使得第一掺杂层3中的磷扩散到其上的第二掺杂层6中，第一区域上的第二掺杂层6中的硼也会扩散到第一掺杂层3中，从而使得第一区域上对应的第二掺杂层6转变为第三掺杂层5；第二区域上对应的第二掺杂层6依然为第二掺杂层6，同时由于加热处理的温度较高，所述非晶硅层转化为多晶硅层。所述第三掺杂层5中所有区域的导电性均与第一掺杂层3的导电性相同。
所述第一掺杂层3内的磷的峰值掺杂浓度为2×10 21atoms/cm 3，硼的峰值掺杂浓度为2×10 19atoms/cm 3。
所述第三掺杂层5内的磷的峰值掺杂浓度为2×10 21atoms/cm 3，硼的峰值掺杂浓度为2×10 19atoms/cm 3。
所述第二掺杂层6的厚度为25nm，其内硼的掺杂浓度为2×10 19atoms/cm 3。
步骤六：在所述第三掺杂层5以及第二掺杂层6背离所述第二界面层4的一侧表面形成背面钝化层7(厚度为15nm的氧化铝层)，同时在所述半导体基底1背离所述第一界面层2的一侧表面形成正面钝化层(厚度为15nm的氧化铝层)。
步骤七：在所述第三掺杂层5的上方形成贯穿所述背面钝化层7的第一电极8，同时，在所述第二掺杂层6的上方形成贯穿所述背面钝化层7的第二电极9。所述第一电极8和第二电极9均为银电极。
所述太阳能电池的性能如表1。
实施例2
本实施例中的太阳能电池为第二种太阳能电池，包括如下步骤：
步骤一：提供半导体基底1；
提供p型硅片为半导体基底1，其厚度为200μm。
步骤二：在所述半导体基底1的一侧表面形成第一掺杂层3；具体地，使用LPCVD在所述半导体基底1的一侧表面形成第一界面层2，使用温度为700℃，在所述第一界面层2背离所述半导体基底1的一侧表面形成掺磷非晶硅层3。此掺磷非晶硅采用原位掺杂LPCVD形成，沉积源为SiH 4，含磷掺杂源为PH 3。
第一界面层2为氧化硅层，其厚度为1nm，所述本征非晶硅层的厚度为100nm。
所述第一掺杂层3内的第一掺杂剂的峰值掺杂浓度为3×10 21atoms/cm 3。
步骤三：将所述第一掺杂层3进行图形化，从而保留部分第一掺杂层3；
具体地，在所述第一掺杂层3背离所述半导体基底1的一侧表面上形成厚度为20nm氧化硅层(即第一辅助层)，然后使用短脉冲激光将第二区域上方的氧化硅、第一掺杂层3以及第一界面层2刻蚀掉，从而完成图形化，只留下第一区域的第一掺杂层3。
步骤四：在所述第一掺杂层3背离所述半导体基底1的一侧表面形成覆盖所述第一掺杂层3以及所述半导体基底1未覆盖第一掺杂层3的表面的氧 化硅层(即第二辅助层)，其厚度为20nm；
步骤五：在所述第二界面层4背离所述半导体基底1以及第一掺杂层3的一侧表面形成采用原位掺杂LPCVD形成第二掺杂层6，原位掺杂指的是沉积非晶硅掺杂同时完成，第二掺杂层6为25nm，采用原位掺杂的含硼掺杂物为B 2H 6，从而形成第二掺杂层6。然后对位于所述第一掺杂层3上方的第二掺杂层6进行加热处理(峰值温度为900℃，加热时长为30min)，从而使得第一掺杂层3中的磷扩散到其上的第二掺杂层6中，第一区域上的第二掺杂层6中的硼也会扩散到第一掺杂层3中，从而使得第一区域上对应的第二掺杂层6转变为第三掺杂层5；第二区域上对应的第二掺杂层6依然为第二掺杂层6，同时由于加热处理的温度较高，所述非晶硅层转化为多晶硅层。所述第三掺杂层5中所有区域的导电性均与第一掺杂层3的导电性相同。
所述第一掺杂层3内的磷的峰值掺杂浓度为2×10 21atoms/cm 3，硼的峰值掺杂浓度为2×10 19atoms/cm 3。
所述第三掺杂层5内的磷的峰值掺杂浓度为2×10 21atoms/cm 3，硼的峰值掺杂浓度为2×10 19atoms/cm 3。
所述第二掺杂层6的厚度为25nm，其内硼的掺杂浓度为2×10 19atoms/cm 3。
步骤六：在所述第三掺杂层5以及第二掺杂层6背离所述第二界面层4的一侧表面分别形成第二辅助层，靠近第三掺杂层5与所述第二掺杂层6的交界处未覆盖第二辅助层。
所述第二辅助层可以为氧化硅，其厚度为20nm。
步骤七：使用短脉冲激光将未覆盖所述第二辅助层的第三掺杂层5、第二掺杂层6以及其下方的第二界面层4刻蚀掉，从而露出半导体基底1(露出的半导体基底1称为隔离区10)，所述第三掺杂层5、第二界面层4、第一掺杂层3以及第一界面层2靠近所述隔离区10的侧面、隔离区10的半导体基底1表面以及第二界面层4、第二掺杂层6靠近所述隔离区10的侧面形成一个隔离区10，所述隔离区10的宽度w为100μm。
刻蚀步骤完成后，去除第二辅助层，采用稀氢氟酸酸液去除第二辅助层。
步骤八：在所述第三掺杂层5以及第二掺杂层6背离所述第二界面层4的一侧表面形成背面钝化层7(厚度为15nm的氧化铝层)，同时在所述半 导体基底1背离所述第一界面层2的一侧表面形成正面钝化层(厚度为15nm的氧化铝层)。
步骤九：在所述第三掺杂层5的上方形成贯穿所述背面钝化层7的第一电极8，同时，在所述第二掺杂层6的上方形成贯穿所述背面钝化层7的第二电极9。所述第一电极8和第二电极9均为银电极。
所述太阳能电池的性能如表1。
实施例3
实施例3与实施例2的不同之处在于，第二掺杂层6的厚度不同，本实施例中第二掺杂层6的厚度为50nm，所述第三掺杂层5中，部分区域的导电性与第一掺杂层3的导电性相同。所述太阳能电池的性能如表1。
实施例4
实施例4与实施例2的不同之处在于，第二掺杂层6的厚度不同，本实施例中第二掺杂层6的厚度为100nm，所述第三掺杂层5中部分区域的导电性与第一掺杂层3的导电性相同。所述太阳能电池的性能如表1。
实施例5
实施例5与实施例2的不同之处在于步骤五，实施例5的步骤五为：在所述第二界面层4背离所述半导体基底1以及第一掺杂层3的一侧表面形成厚度为25nm非晶硅层，采用硼扩散将所述硼掺杂到所述非晶硅层内，含硼掺杂物为BBr 3，硼扩散温度峰值温度为900℃，加热时长为30min从而形成第二掺杂层6，同时使得第一掺杂层3中的磷扩散到其上的第二掺杂层6中，第一区域上的第二掺杂层6中的硼也会扩散到第一掺杂层3中，从而使得第一区域上对应的第二掺杂层6转变为第三掺杂层5；第二区域上对应的第二掺杂层6依然为第二掺杂层6，同时由于硼扩散处理的温度较高，所述非晶硅层转化为多晶硅层。所述第三掺杂层5中所有区域的导电性均与第一掺杂层3的导电性相同。
所述第一掺杂层3内的磷的峰值掺杂浓度为2×10 21atoms/cm 3，硼的峰值掺杂浓度为2×10 19atoms/cm 3。
所述第三掺杂层5内的磷的峰值掺杂浓度为2×10 21atoms/cm 3，硼的峰值掺杂浓度为2×10 19atoms/cm 3。
所述第二掺杂层6的厚度为25nm，其内硼的掺杂浓度为2×10 19atoms/cm 3。
所述太阳能电池的性能如表1。
实施例6
实施例6与实施例2的不同之处在于，
步骤五：在所述第二界面层4背离所述半导体基底1以及第一掺杂层3的一侧表面形成采用原位掺杂LPCVD形成第二掺杂层6，原位掺杂指的是沉积非晶硅掺杂同时完成，第二掺杂层6为25nm，采用原位掺杂的含硼掺杂物为B 2H 6，从而形成第二掺杂层6。
步骤六：在所述第三掺杂层5以及第二掺杂层6背离所述第二界面层4的一侧表面分别形成第二辅助层，靠近第三掺杂层5与所述第二掺杂层6的交界处未覆盖第二辅助层。
所述第二辅助层可以为氧化硅，其厚度为20nm。
步骤七：使用短脉冲激光将未覆盖所述第二辅助层的第三掺杂层5、第二掺杂层6以及其下方的第二界面层4刻蚀掉，从而露出半导体基底1(露出的半导体基底1称为隔离区10)，所述第三掺杂层5、第二界面层4、第一掺杂层3以及第一界面层2靠近所述隔离区10的侧面、隔离区10的半导体基底1表面以及第二界面层4、第二掺杂层6靠近所述隔离区10的侧面形成一个隔离区10，所述隔离区10的宽度w为100μm。
刻蚀步骤完成后，去除第二辅助层，采用稀氢氟酸酸液去除第二辅助层。
步骤八：对位于所述第一掺杂层3上方的第二掺杂层6进行加热处理(峰值温度为900℃，加热时长为30min)，从而使得第一掺杂层3中的磷扩散到其上的第二掺杂层6中，第一区域上的第二掺杂层6中的硼也会扩散到第一掺杂层3中，从而使得第一区域上对应的第二掺杂层6转变为第三掺杂层5；第二区域上对应的第二掺杂层6依然为第二掺杂层6，同时由于加热处理的温度较高，所述非晶硅层转化为多晶硅层。所述第三掺杂层5中所有区域的导电性均与第一掺杂层3的导电性相同。
所述第一掺杂层3内的磷的峰值掺杂浓度为2×10 21atoms/cm 3，硼的峰值掺杂浓度为2×10 19atoms/cm 3。
所述第三掺杂层5内的磷的峰值掺杂浓度为2×10 21atoms/cm 3，硼的峰值掺杂浓度为2×10 19atoms/cm 3。
所述第二掺杂层6的厚度为25nm，其内硼的掺杂浓度为2×10 19atoms/cm 3。
步骤九：在所述第三掺杂层5以及第二掺杂层6背离所述第二界面层4的一侧表面形成背面钝化层7(厚度为15nm的氧化铝层)，同时在所述半导体基底1背离所述第一界面层2的一侧表面形成正面钝化层(厚度为15nm的氧化铝层)。
步骤十：在所述第三掺杂层5的上方形成贯穿所述背面钝化层7的第一电极8，同时，在所述第二掺杂层6的上方形成贯穿所述背面钝化层7的第二电极9。所述第一电极8和第二电极9均为银电极。
所述太阳能电池的性能如表1。
实施例7
实施例7与实施例2的不同之处在于，第二掺杂层6的厚度不同，本实施例中第二掺杂层6的厚度为200nm，所述第三掺杂层5中部分区域的导电性与第一掺杂层3的导电性相同。
所述太阳能电池的性能如表1。
实施例8
实施例8与实施例2的不同之处在于步骤五，实施例8中的步骤五为：在所述第二界面层4背离所述半导体基底1以及第一掺杂层3的一侧表面采用原位掺杂方法形成含硼多晶硅层，原位掺杂过程中使用B 2H 6作为掺杂源，形成的多晶硅厚度为100nm，从而形成第二掺杂层6。然后采用激光局部照射位于所述第一掺杂层3上方的第二掺杂层6的第一区域，(激光处理的激光功率为25W，激光采用绿光激光器：波长532nm)，从而使得第一掺杂层3中的磷扩散到其上的第二掺杂层6的第一区域中，第一区域上的第二掺杂层6中的硼也会扩散到第一掺杂层3中，从而使得第一区域上对应的第二掺 杂层6转变为第三掺杂层5，在所述第三掺杂层5中激光照射过的区域的第一掺杂剂的掺杂浓度大于第二掺杂剂的掺杂浓度，其导电类型与第一掺杂层3的导电类型相同；激光未照射的第二区域上对应的第二掺杂层6依然为第二掺杂层6，第一区域为第一电极区域，所述第三掺杂层5中与所述第一电极接触的区域的导电性与第一掺杂层3的导电性相同。
所述第一掺杂层3内的磷的峰值掺杂浓度为2×10 21atoms/cm 3，硼的峰值掺杂浓度为2×10 19atoms/cm 3。
所述第三掺杂层5内的磷的峰值掺杂浓度为2×10 21atoms/cm 3，硼的峰值掺杂浓度为2×10 19atoms/cm 3。
所述第二掺杂层6的厚度为100nm，其内硼的掺杂浓度为2×10 19atoms/cm 3。
所述太阳能电池的性能如表1。
表1
Figure PCTCN2022092291-appb-000001
小结：由表1可知，由实施例1和实施例2对比可知，在电池上形成p型区和n型区的间隔区域，用于隔离p型和n型半导体区域，减少了pn交接处的复合，减少了横向漏电，开路电压、填充因子都得到了一定提升。
由实施例2和实施例5对比可知，实施例5为硼扩散替代了原位掺杂硼扩散，硼扩散的表面浓度略大于原位掺杂的硼元素的浓度，因此可以减少接触电阻，其FF有一定的提高，开压略有降低，效率接近。
由实施例2、实施例3、实施例4、实施例7对比可以看到，实施例3效率最高。主要原因，实施例2中，第二掺杂层为25nm，第三掺杂层虽全部反型成为n型，但第二掺杂层由于较薄(也为25nm)，在第二掺杂层不能完全屏蔽第二电极的金属复合，因此开压略低于实施例3，而实施例4，第二掺杂层为100nm，第三掺杂层仅有底层反型成为n型，顶层仍有部分为 p型，第一电极穿过表层第三掺杂层和底层的n型第三掺杂层接触，其FF则略低于低于实施例3。实施例7中，第二掺杂层为200nm，由于第三掺杂膜层较厚，第一电极和第三掺杂膜层的n型底层部分接触不佳，影响了其填充因子。
由实施例2和实施例6对比可知，先形成间隔区域再加热，和先加热再形成间隔区域差异不大，电性能表现也较为接近。
相较于实施例4，由于实施例8中，由激光在电极区域中继续进行加热，使得电极下方的顶层p型多晶硅层继续转变为了n型，使得第一电极和n型掺杂半导体形成了更好的接触，填充因子得到了提升。
因此本公开所述的太阳能电池仅需要一次图形化，一次高温热处理，该方法制备的掺杂区，两极均为钝化接触结构，钝化效果好，金属区复合速率大幅降低，从而提升了电池的效率。同时还可以减少高温热处理带来的热损伤。
尽管以上结合对本公开的实施方案进行了描述，但本公开并不局限于上述的具体实施方案和应用领域，上述的具体实施方案仅仅是示意性的、指导性的，而不是限制性的。本领域的普通技术人员在本说明书的启示下和在不脱离本公开权利要求所保护的范围的情况下，还可以做出很多种的形式，这些均属于本公开保护之列。

Claims (30)

  1. 一种太阳能电池的制备方法，其特征在于，包括如下步骤：
    提供半导体基底；
    在所述半导体基底的第一表面形成第一掺杂层；
    将所述第一掺杂层进行图形化，从而保留部分第一掺杂层；
    在所述第一掺杂层背离所述半导体基底的一侧表面通过加热处理形成第三掺杂层，在未覆盖所述第一掺杂层的半导体基底的第一表面形成第二掺杂层；
    所述第一掺杂层中具有第一掺杂剂和第二掺杂剂；
    所述第二掺杂层中具有第二掺杂剂；
    所述第三掺杂层中具有第一掺杂剂和第二掺杂剂；
    所述第一掺杂层与所述第二掺杂层的导电类型相反；
    所述第三掺杂层中至少部分区域的导电类型与第一掺杂层的导电类型相同。
  2. 根据权利要求1所述的制备方法，其特征在于，在所述半导体基底的第一表面形成第一半导体层，然后将第一掺杂剂扩散到所述第一半导体层内，从而形成第一掺杂层，或在所述半导体基底的第一表面上，采用原位掺杂形成第一掺杂层；
    在所述第一掺杂层背离所述半导体基底的一侧表面上形成第一辅助层，然后将部分第一辅助层以及第一掺杂层刻蚀掉，从而完成图形化，留下部分第一掺杂层。
  3. 根据权利要求2所述的制备方法，其特征在于，在所述第一掺杂层背离所述半导体基底的一侧表面以及未覆盖所述第一掺杂层的半导体基底的第一表面，采用原位掺杂形成第二掺杂层；
    对位于所述第一掺杂层上方的第二掺杂层进行加热处理，从而使得第一掺杂层中的第一掺杂剂扩散到其上的第二掺杂层中，所述第二掺杂层中的第二掺杂剂也会扩散到第一掺杂层中，从而使得所述第一掺杂层上方的第二掺 杂层转变为第三掺杂层。
  4. 根据权利要求3所述的制备方法，其特征在于，所述加热处理为激光处理或热处理，
    当采用所述激光处理，在所述第三掺杂层中，被所述激光直接照射到的区域，其导电类型与第一掺杂层的导电类型相同。
  5. 根据权利要求4所述的制备方法，其特征在于，在所述第三掺杂层中，与所述第一掺杂层导电类型相同的区域沿厚度方向贯穿所述第三掺杂层。
  6. 根据权利要求2所述的制备方法，其特征在于，在所述第一掺杂层背离所述半导体基底的一侧表面以及未覆盖所述第一掺杂层的半导体基底的第一表面形成第二半导体层，
    在加热处理条件下，将第二掺杂剂扩散到所述第二半导体层中，由于温度较高，所述第一掺杂层中的第一掺杂剂也会扩散到位于其上方的所述第二半导体层中，从而使得位于所述第一掺杂层上方的第二半导体层为第三掺杂层，位于所述半导体基底第一表面上的第二半导体层为第二掺杂层。
  7. 根据权利要求6所述的制备方法，其特征在于，在所述第三掺杂层中，靠近所述第一掺杂层的区域，至少部分区域的导电性与所述第一掺杂层的导电类型相同。
  8. 根据权利要求1-7任一项所述的制备方法，其特征在于，在形成第三掺杂层之前，所述第一掺杂层内的第一掺杂剂的峰值掺杂浓度为1×10 19～5×10 21atoms/cm 3。
  9. 根据权利要求1-7任一项所述的制备方法，其特征在于，在形成第三掺杂层之后，在所述第一掺杂层中，所述第一掺杂剂的掺杂浓度大于所述第二掺杂剂的掺杂浓度；
    在所述第三掺杂层中，至少部分区域的第一掺杂剂的掺杂浓度大于第二掺杂剂的掺杂浓度。
  10. 根据权利要求9所述的制备方法，其特征在于，所述第一掺杂层内的第一掺杂剂的峰值掺杂浓度为1×10 19～3×10 21atoms/cm 3；
    在所述第二掺杂层中，所述第二掺杂剂的峰值掺杂浓度为1×10 19～3×10 19atoms/cm 3；
    所述第三掺杂层内至少部分区域中的第一掺杂剂的峰值掺杂浓度为1×10 20～5×10 20atoms/cm 3。
  11. 根据权利要求3或6所述的制备方法，其特征在于，所述加热处理的加热峰值温度为850℃以上，优选为900℃以上，更优选为1000℃；在峰值温度下，加热时间为10min以上。
  12. 根据权利要求3或6所述的制备方法，其特征在于，在形成第三掺杂层时，由于温度较高，位于所述第一掺杂层以及第三掺杂层中的第一掺杂剂以及第二掺杂剂扩散进入所述半导体基底内，从而形成第三掺杂区；
    和/或，位于所述第二掺杂层中的第二掺杂剂扩散进入所述半导体基底内，从而形成第四掺杂区；
    优选地，在所述第三掺杂区内，所述第一掺杂剂的峰值掺杂浓度为1×10 18～3×10 21atoms/cm 3，所述第二掺杂剂的峰值掺杂浓度为1×10 17～3×10 19atoms/cm 3；
    优选地，所述第四掺杂区内，所述第二掺杂剂的峰值掺杂浓度为1×10 18～3×10 19atoms/cm 3。
  13. 根据权利要求1-12任一项所述的制备方法，其特征在于，所述第一掺杂剂为第VA族元素或第IIIA族元素，所述第二掺杂剂为第VA族元素或第IIIA族元素，优选地，所述第一掺杂剂为第VA族元素，所述第二掺杂剂为第IIIA族元素。
  14. 根据权利要求3所述的制备方法，其特征在于，在形成第三掺杂层之前还包括如下步骤：
    将位于所述半导体基底第一表面上的所述第二掺杂层与所述第一掺杂层交界处的第一掺杂层以及第二掺杂层刻蚀掉，露出所述半导体基底的第一表面，从而使得所述第一掺杂层与所述第二掺杂层之间具有隔离区。
  15. 根据权利要求1所述的制备方法，其特征在于，在形成第三掺杂层之后还包括如下步骤：
    将位于所述半导体基底第一表面上的所述第二掺杂层与所述第一掺杂层的交界处的第一掺杂层、第二掺杂层以及第三掺杂层刻蚀掉，露出所述半导体基底的第一表面，从而使得所述第一掺杂层与所述第二掺杂层之间具有隔离区。
  16. 根据权利要求1-15任一项所述的制备方法，其特征在于，所述第一掺杂层、第二掺杂层以及第三掺杂层均为掺杂的多晶硅层、微晶硅层或非晶硅层中的一种。
  17. 一种太阳能电池，其特征在于，包括半导体基底，在所述半导体基底的第一表面具有第一掺杂层和第二掺杂层，在所述第一掺杂层背离所述半导体基底的一侧表面具有第三掺杂层，
    所述第一掺杂层中具有第一掺杂剂和第二掺杂剂；
    所述第二掺杂层中具有第二掺杂剂；
    所述第三掺杂层中具有第一掺杂剂和第二掺杂剂；
    所述第三掺杂层中至少部分区域导电类型与第一掺杂层的导电类型相同；
    所述第一掺杂层与所述第二掺杂层的导电类型相反。
  18. 根据权利要求17所述的太阳能电池，其特征在于，所述第一掺杂层的厚度为50～300nm；
    所述第三掺杂层和所述第二掺杂层厚度相同，均为小于等于150nm。
  19. 根据权利要求18所述的太阳能电池，其特征在于，当所述第三掺杂层的厚度d为小于等于30nm时，所述第三掺杂层中所有区域导电类型与第一掺杂层的导电类型相同。
  20. 根据权利要求18所述的太阳能电池，其特征在于，当所述第三掺杂层的厚度30nm<d≤150nm时，在所述第三掺杂层中，靠近所述第一掺杂层的区域，至少部分区域的导电性与所述第一掺杂层的导电类型相同。
  21. 根据权利要求18所述的太阳能电池，其特征在于，当所述第三掺杂层的厚度30nm<d≤150nm时，在所述第三掺杂层中，与所述第一掺杂层导电类型相同的区域沿厚度方向贯穿所述第三掺杂层。
  22. 根据权利要求17所述的太阳能电池，其特征在于，在所述第一掺杂层内，所述第一掺杂剂的掺杂浓度从远离所述半导体基底的一侧表面到靠近所述半导体基底的一侧表面的掺杂浓度先增大后减小；第二掺杂剂的掺杂浓度逐渐减小。
  23. 根据权利要求17所述的太阳能电池，其特征在于，在所述第二掺杂层内，第二掺杂剂的掺杂浓度从远离所述半导体基底的一侧表面到靠近所述半导体基底的一侧表面的掺杂浓度相同。
  24. 根据权利要求17所述的太阳能电池，其特征在于，在所述第三掺杂层内，所述第一掺杂剂的掺杂浓度从远离所述半导体基底的一侧表面到靠近所述半导体基底的一侧表面的掺杂浓度逐渐增大；
    所述第二掺杂剂的掺杂浓度从远离所述半导体基底的一侧表面到靠近所述半导体基底的一侧表面的掺杂浓度相同。
  25. 根据权利要求17所述的太阳能电池，其特征在于，所述第三掺杂层不仅覆盖所述第一掺杂层背离所述半导体基底的一侧表面，还覆盖靠近所 述第二掺杂层的第一掺杂层的侧面，且覆盖所述第一掺杂层侧面的所述第三掺杂层与所述第二掺杂层接触。
  26. 根据权利要求25所述的太阳能电池，其特征在于，所述太阳能电池还包括第一界面层，所述第一界面层位于所述半导体基底与所述第一掺杂层之间；
    和/或，还包括第二界面层，所述第二界面层从所述第一掺杂层背离所述第一界面层的表面延伸至其侧面，并继续延且伸覆盖所述半导体基底未覆盖第一掺杂层的部分，且所述第二掺杂层以及第三掺杂层分别设置于所述第二界面层的一侧表面上；
    和/或，还包括背面钝化层，所述背面钝化层覆盖第三掺杂层以及第二掺杂层。
  27. 根据权利要求17所述的太阳能电池，其特征在于，所述第一掺杂层与所述第三掺杂层的宽度相同，所述第一掺杂层以及第三掺杂层与所述第二掺杂层之间具有隔离区。
  28. 根据权利要求27所述的太阳能电池，其特征在于，还包括第一界面层、所述第一界面层位于所述半导体基底与所述第一掺杂层之间；
    和/或，还包括第二界面层，所述第二界面层位于第一掺杂层和第三掺杂层之间以及第二掺杂层与所述半导体基底之间；
    和/或，还包括背面钝化层，所述背面钝化层覆盖第三掺杂层、隔离区以及第二掺杂层。
  29. 根据权利要求26或28任一项所述的太阳能电池，其特征在于，还包括第一电极和第二电极，所述第一电极穿过背面钝化层与所述第三掺杂层中的与第一掺杂层导电类型相同的区域接触；所述第二电极穿过所述背面钝化层与所述第二掺杂层接触。
  30. 根据权利要求17-29任一项所述的太阳能电池，其特征在于，所述 太阳能电池为权利要求1-16任一项所述的方法制备得到。
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