WO2023072165A1 - 一种钝化接触的太阳能电池 - Google Patents

一种钝化接触的太阳能电池 Download PDF

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WO2023072165A1
WO2023072165A1 PCT/CN2022/127775 CN2022127775W WO2023072165A1 WO 2023072165 A1 WO2023072165 A1 WO 2023072165A1 CN 2022127775 W CN2022127775 W CN 2022127775W WO 2023072165 A1 WO2023072165 A1 WO 2023072165A1
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conductivity type
layer
semiconductor substrate
solar cell
doped polysilicon
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PCT/CN2022/127775
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English (en)
French (fr)
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胡匀匀
徐冠超
张倬涵
张学玲
陈达明
陈奕峰
冯志强
阿特玛特·皮亚同·皮特
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天合光能股份有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/022441—Electrode arrangements specially adapted for back-contact solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0216—Coatings
    • H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
    • H01L31/0682—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells back-junction, i.e. rearside emitter, solar cells, e.g. interdigitated base-emitter regions back-junction cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
    • H01L31/1868—Passivation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the application belongs to the technical field of crystalline silicon solar cell design, and relates to a passivated contact solar cell.
  • Tunnel oxide passivation contact (Topcon) technology is a technology that has significantly improved the photoelectric conversion efficiency of photovoltaic cells in recent years.
  • This passivation contact structure is formed by superimposing an ultra-thin tunnel oxide layer and a doped polysilicon layer on crystalline silicon.
  • the oxide layer is used to passivate the surface
  • the doped polysilicon layer is used as a carrier selective contact material, which can significantly reduce the carrier recombination in the metal-semiconductor contact area, and has good contact performance, thereby greatly improving the solar cell. efficiency.
  • CN109585578A discloses a back-junction solar cell and its preparation method.
  • the back-junction solar cell includes a P-type silicon substrate.
  • a local front surface field doped with group III elements is formed on the front side of the silicon substrate.
  • the front side is provided with a front side from inside to outside.
  • Passivation layer, passivation anti-reflection layer, front electrode is provided on the front
  • tunnel oxide layer is provided on the back from inside to outside
  • doped silicon layer doped with group V elements passivation layer on the back
  • rear electrode is provided on the back .
  • the preparation method includes: forming a tunnel oxide layer on the back of the P-type silicon substrate, forming a doped silicon layer doped with group V elements on the tunnel oxide layer, forming a front passivation layer, a passivation anti-reflection layer and a back passivation layer. layer, silver grid lines are printed on the back, metal grid lines are printed on the passivation anti-reflection layer and sintered.
  • the method can obtain a back-junction solar cell, reduce the minority carrier recombination in the metal-semiconductor contact region, avoid boron doping or slotting, avoid high temperature damage to the silicon substrate, and superimpose silver wires on the metal grid lines to reduce grid line resistance.
  • CN108666393A discloses a method for preparing a solar cell and a solar cell.
  • the method includes: preparing a first tunneling oxide layer on the front side of the substrate after the substrate is textured and polished on the back; Prepare a second tunnel oxide layer on the back; grow a first polysilicon layer on the surface of the first tunnel oxide layer corresponding to the front gate line, and grow a second polysilicon layer on the surface of the second tunnel oxide layer.
  • CN111162145A discloses a passivation contact solar cell with a selective emitter structure and a preparation method thereof.
  • the method comprises: preparing textured surfaces on both surfaces of the N-type crystalline silicon substrate; performing boron diffusion treatment on the textured surface of the front surface of the substrate to form a lightly doped region layer; using a mask on the lightly doped region layer Perform partial boron ion implantation and annealing to form a local heavily doped region; prepare a tunnel oxide layer on the textured surface of the back surface of the substrate, and prepare a phosphorus-doped polysilicon layer on the tunnel oxide layer; A silicon nitride anti-reflection layer is prepared on the layer; an aluminum oxide passivation layer is prepared on the lightly doped region layer on the front of the substrate, and a silicon nitride anti-reflection layer is prepared on the aluminum oxide passivation layer;
  • the metallization paste is screen printed and fired. The application can significantly reduce the recombination current on the
  • the Topcon technology of the battery is becoming more and more mature, and has achieved large-scale mass production. It is one of the seed players of the next-generation mainstream technology. Due to the high light absorption coefficient of the polysilicon layer, it will lead to serious parasitic absorption and current loss. Therefore, the conventional Topcon technology only has a passivation contact structure on the back (non-main light-receiving surface) of the battery, and the front (main light-receiving surface) is still traditional. Heavily or selectively doped emitters. That is to say, the conventional Topcon cell structure only passivates the metal contact area on the back, which improves the open circuit voltage and conversion efficiency to a certain extent. Therefore, it is urgent to develop and design a new solar cell structure to meet the needs of actual production and life. , while improving the performance of solar cells.
  • the purpose of this application is to provide a solar cell with passivation contacts.
  • the metal-semiconductor substrate contact regions on the front and back sides of the semiconductor substrate can be passivated at the same time, reducing the Carrier recombination in the contact area and placing the emitter on the back can reduce the recombination of carriers in the non-contact area on the front, thereby obtaining higher open circuit voltage and conversion efficiency than conventional Topcon.
  • the present application provides a passivated contact solar cell, the solar cell includes a semiconductor substrate of the first conductivity type, the semiconductor substrate of the first conductivity type has a metal contact area and a non-metal contact area on the front side, the The surface of the semiconductor substrate of the first conductivity type in the metal contact area is sequentially provided with a tunneling layer and a doped polysilicon layer of the first conductivity type, and the doped polysilicon layer of the first conductivity type is in contact with the metal electrode.
  • the surface of the semiconductor substrate of the first conductivity type in the non-metal contact region is provided with a lightly doped layer of the first conductivity type, or a stacked tunneling layer and a doped polysilicon layer of the first conductivity type, or no tunneling layer
  • the polysilicon layer and the polysilicon layer also have no doped layer, and the outermost layer of the semiconductor substrate surface of the first conductivity type in the non-metal contact region is provided with a dielectric layer.
  • a tunneling layer, a doped polysilicon layer of a second conductivity type and a dielectric layer are sequentially stacked on the back of the semiconductor substrate of the first conductivity type, and the metal electrode is in contact with the doped polysilicon layer of the second conductivity type.
  • the front side of the semiconductor substrate of the first conductivity type is the main light receiving surface, and the back side of the semiconductor substrate of the first conductivity type is the non-main light receiving surface.
  • the metal-semiconductor substrate contact area on the front and back sides of the semiconductor substrate can be passivated at the same time, the carrier recombination in the contact area on both sides can be reduced, and the emitter can be placed on the back side, which can reduce the contact area of the non-contact area on the front side. Carrier recombination, resulting in higher open circuit voltage and conversion efficiency than conventional Topcon.
  • the tunneling layer preparation methods in this application include but not limited to thermal oxygen method, wet chemical method, PECVD method, ALD method or excimer source dry oxygen method, etc.;
  • the doped polysilicon layer in this application can be It is prepared by chemical vapor deposition (CVD), including but not limited to LPCVD, PECVD, etc., and then heat-treated to form polysilicon.
  • the doping method can be in-situ doping or ex-situ doping. Ex-situ doping includes but not Limited to thermal diffusion, ion implantation, and source-containing paste printing;
  • the metal electrode in this application can be screen-printed metal paste, electroplated metal, or inkjet printing, laser transfer, or vapor-deposited metal. The specific selection is based on It depends on the actual situation, and the dielectric film may or may not exist in the metal contact area, and holes may or may not be opened by means of laser or etching.
  • the thickness of the tunneling layer in the metal contact region is ⁇ 3nm, for example, it can be 1nm, 1.5nm, 2nm, 2.5nm, 3nm, but it is not limited to the listed values. Other unrecited values within the range of values also apply.
  • the doped polysilicon layer of the first conductivity type in the metal contact region has a thickness of 10-1000nm, for example, 10nm, 100nm, 200nm, 300nm, 400nm, 500nm, 600nm, 700nm, 800nm, 900nm, 1000nm, but not only Limited to the listed numerical values, other unlisted numerical values within this numerical range are also applicable.
  • the square resistance of the lightly doped layer of the first conductivity type in the non-metal contact region is 50-1000 ohm/sq, for example, it can be 50 ohm/sq, 100 ohm/sq, 200 ohm/sq . Numerical values also apply.
  • the superimposed tunneling layer thickness of the non-metal contact region is ⁇ 3nm, for example, it can be 1nm, 1.5nm, 2nm, 2.5nm, 3nm, but it is not limited to the listed values, and other unlisted values within this range Numerical values also apply.
  • the thickness of the doped polysilicon layer of the first conductivity type superimposed on the non-metal contact region is 1-100nm, for example, it can be 1nm, 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm , but not limited to the listed values, other unlisted values within this range are also applicable.
  • the square resistance of the doped polysilicon layer of the first conductivity type superimposed on the non-metal contact region is 1 to 1000 ohm/sq, for example, it can be 1 ohm/sq, 100 ohm/sq, 200 ohm/sq, 300 ohm/sq, 400 ohm/sq sq. 500ohm/sq. 600ohm/sq. 700ohm/sq. 800ohm/sq. 900ohm/sq.
  • the doped polysilicon layer of the first conductivity type superimposed on the non-metal contact region and the tunneling layer and the doped polysilicon layer of the first conductivity type superimposed on the metal contact region may be integrated or not.
  • the front side of the semiconductor substrate of the first conductivity type is textured.
  • the front side of the semiconductor substrate of the first conductivity type in this application may be a conventional textured surface or a combination of other types of complete and incomplete textured surfaces, and the specific selection depends on the actual situation.
  • the thickness of the tunneling layer on the back side of the semiconductor substrate of the first conductivity type is ⁇ 3nm, such as 1nm, 1.5nm, 2nm, 2.5nm, 3nm, but not limited to the Numerical values listed, other unlisted numerical values within the numerical range are also applicable.
  • the doped polysilicon layer of the second conductivity type on the backside of the semiconductor substrate of the first conductivity type has a thickness of 10 to 1000 nm, for example, 10 nm, 100 nm, 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1000nm, but not limited to the listed values, other unlisted values within this range are also applicable.
  • the back surface of the semiconductor substrate of the first conductivity type is a textured surface, a polished surface or a partially textured and partially polished surface.
  • the back surface can be a complete or incomplete suede surface (or a combination of the two), a polished surface (acid polishing, alkali polishing or a combination of the two), a partial suede surface and a local polishing surface, etc., and the specific selection is based on It depends on the actual situation.
  • the tunneling layer is a dielectric film with carrier tunneling and interface passivation, including a silicon oxide dielectric film or an aluminum oxide dielectric film.
  • the outer surface of the semiconductor substrate of the first conductivity type is provided with a dielectric layer.
  • the material of the dielectric layer includes any one or a combination of two or more of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, aluminum oxide, gallium oxide, zinc oxide, titanium oxide or magnesium fluoride.
  • the semiconductor substrate of the first conductivity type includes crystalline silicon.
  • the semiconductor substrate of the first conductivity type includes but is not limited to crystalline silicon.
  • the semiconductor substrate of the first conductivity type is an N-type semiconductor or a P-type semiconductor.
  • the metal-semiconductor substrate contact area on the front and back sides of the semiconductor substrate can be passivated at the same time, the carrier recombination in the contact area on both sides can be reduced, and the emitter can be placed on the back side, which can reduce the contact area of the non-contact area on the front side.
  • Carrier recombination so as to obtain higher open circuit voltage and conversion efficiency than conventional Topcon.
  • FIG. 1 is a schematic front view of a solar cell structure provided in a specific embodiment of the present application
  • Fig. 2 is a front schematic diagram II of a solar cell structure provided by a specific embodiment of the present application.
  • Fig. 3 is a schematic front view III of a solar cell structure provided in a specific embodiment of the present application.
  • FIG. 4 is a schematic view of the back of a solar cell structure provided in a specific embodiment of the present application.
  • the present application provides a solar cell with a passivation contact, as shown in Figures 1-4, the solar cell includes a semiconductor substrate 1 having a first conductivity type, a semiconductor The front surface of the substrate 1 has a metal contact area and a non-metal contact area.
  • the semiconductor substrate surface of the first conductivity type in the metal contact area is sequentially stacked with a tunneling layer 6 and a doped polysilicon layer 7 of the first conductivity type.
  • the first conductivity type Type of doped polysilicon layer 7 is in contact with the front metal electrode 12 of the semiconductor substrate.
  • the surface of the semiconductor substrate 1 of the first conductivity type in the non-metal contact region is provided with a lightly doped layer 8 of the first conductivity type, or the stacked tunneling layer 9 and the doped polysilicon layer 10 of the first conductivity type are denoted as passivation
  • the contact structure, or no passivation contact structure and no doped layer, the outermost layer of the semiconductor substrate surface of the first conductivity type in the non-metal contact region is provided with a semiconductor substrate front dielectric layer 11 .
  • the back side of the semiconductor substrate 1 of the first conductivity type is sequentially stacked with a tunneling layer 2, a doped polysilicon layer 3 of the second conductivity type and a dielectric layer 4 on the back side of the semiconductor substrate, and a metal electrode 5 on the back side of the semiconductor substrate and the second conductivity type
  • the doped polysilicon layer 3 contacts.
  • the front side of the semiconductor substrate 1 of the first conductivity type is the main light-receiving surface
  • the back side of the semiconductor substrate 1 of the first conductivity type is the non-main light-receiving surface.
  • the metal-semiconductor substrate 1 contact area on the front and back sides of the semiconductor substrate 1 can be passivated at the same time, the carrier recombination in the contact area on both sides can be reduced, and the emitter can be placed on the back side, which can reduce the front non-contact
  • the carriers in the region recombine to obtain higher open circuit voltage and conversion efficiency than conventional Topcon.
  • the tunneling layer 2 preparation method in this application includes but not limited to thermal oxygen method, wet chemical method, PECVD method, ALD method or excimer source dry oxygen method, etc.;
  • the doped polysilicon layer in this application can be It is prepared by chemical vapor deposition (CVD), including but not limited to LPCVD, PECVD, etc., and then heat-treated to form polysilicon.
  • the doping method can be in-situ doping or ex-situ doping.
  • Ex-situ doping includes but Not limited to methods such as thermal diffusion, ion implantation, and source-containing paste printing; the metal electrode in this application can be screen-printed metal paste, electroplated metal, or inkjet printing, laser transfer, or vapor-deposited metal, depending on the specific choice It depends on the actual situation, and the dielectric film may or may not have holes in the metal contact area by means of laser or etching.
  • the thickness of the tunneling layer 6 in the metal contact area is ⁇ 3nm
  • the thickness of the doped polysilicon layer 7 of the first conductivity type in the metal contact area is 10-1000nm
  • the lightly doped layer 8 of the first conductivity type in the non-metal contact area is resistive 50-1000 ohm/sq
  • the thickness of the superimposed tunneling layer 9 in the non-metal contact region is 10-1000 nm
  • the thickness of the doped polysilicon layer 10 of the first conductivity type superimposed on the non-metal contact region is 1-100 nm
  • the square resistance 1 ⁇ 1000ohm/sq.
  • the front side of the semiconductor substrate 1 of the first conductivity type is textured. It should be noted that the front side of the semiconductor substrate 1 of the first conductivity type in this application may be a conventional textured surface or a combination of other types of complete and incomplete textured surfaces, and the specific selection depends on the actual situation.
  • the thickness of the tunneling layer 2 on the back of the semiconductor substrate 1 of the first conductivity type is ⁇ 3nm
  • the thickness of the doped polysilicon layer 3 of the second conductivity type on the back of the semiconductor substrate 1 of the first conductivity type is 10-1000nm
  • the back side of type semiconductor substrate 1 is a suede surface, a polished surface or a partial suede surface and a local polished surface. Polishing, alkali polishing or a combination of the two), partial suede and partial polishing, etc., the specific choice depends on the actual situation.
  • the tunneling layer 2 is a dielectric film with carrier tunneling and interface passivation, including a silicon oxide dielectric film or an aluminum oxide dielectric film, and the outer surface of the semiconductor substrate 1 of the first conductivity type is provided with a dielectric layer, including The dielectric layer 11 on the front side of the semiconductor substrate and the dielectric layer 4 on the back side of the semiconductor substrate, the materials of the dielectric layer include silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, aluminum oxide, gallium oxide, zinc oxide, titanium oxide or magnesium fluoride Any one and a combination of two or more.
  • the semiconductor substrate 1 of the first conductivity type includes crystalline silicon. It should be noted that the semiconductor substrate of the first conductivity type includes but not limited to crystalline silicon. Further, the semiconductor substrate 1 of the first conductivity type is an N-type semiconductor or P-type semiconductor.

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Abstract

本申请提供了一种钝化接触的太阳能电池，所述太阳能电池包括第一导电类型的半导体衬底(1)，所述第一导电类型的半导体衬底(1)正面具有金属接触区和非金属接触区，所述第一导电类型的半导体衬底(1)背面依次层叠设置有隧穿层(2)、第二导电类型的掺杂多晶硅层(3)和介质层(4)。在本申请中，可以同时钝化半导体衬底的正面和背面的金属-半导体衬底接触区，降低两面接触区的载流子复合，并将发射极放到背面，可以降低正面非接触区的载流子复合，从而获得比常规Topcon更高的开路电压和转换效率。

Description

一种钝化接触的太阳能电池
本申请要求于2021年10月27日提交中国专利局、申请号为202111254049.6、申请名称为“一种钝化接触的太阳能电池”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请属于晶体硅太阳能电池设计技术领域，涉及一种钝化接触太阳能电池。
背景技术
在晶体硅太阳能电池中，表面复合及金属-半导体接触区的复合，是制约太阳能电池效率提升的关键因素。隧穿氧化层钝化接触(Topcon)技术是近年来显著提升光伏电池光电转换效率的技术。这种钝化接触结构是由在晶体硅上叠加一层超薄的隧穿氧化层和掺杂多晶硅层形成。其中氧化层用来钝化表面，掺杂多晶硅层作为载流子选择性接触材料，可以显著降低金属-半导体接触区的载流子复合，同时具有良好的接触性能，从而极大地提升太阳能电池的效率。
CN109585578A公开了一种背结太阳能电池及其制备方法，背结太阳能电池包括P型硅基体，硅基体的正面形成有第III族元素掺杂的局部前表面场，正面由内至外设有正面钝化层、钝化减反层，正面设有正面电极，背面由内至外设有隧穿氧化层、第V族元素掺杂的掺杂硅层、背面钝化层，背面设有背面电极。制备方法包括：在P型硅基体背面形成隧穿氧化层，在隧穿氧化层上形成用V族元素掺杂的掺杂硅层，形成正面钝化层、钝化减反层与背面钝化层，在背面印银栅线，钝化减反层印金属栅线并烧结。该方法能得到背结太阳能电池，降低金属半导体接触区的少子复合，避免硼掺杂或开槽，避免高温损伤硅基体，金属栅线上叠加银线降低栅线电阻。
CN108666393A公开了一种太阳能电池的制备方法及太阳能电池，该方法包括：衬底经制绒和背面抛光处理后，在所述衬底的正面制备第一隧穿氧化层，在所述衬底的背面制备第二隧穿氧化层；在所述第一隧穿氧化层中与正面栅线对应区域的表面生长第一多晶硅层，在所述第二隧穿氧化层的表面生 长第二多晶硅层，并在所述衬底的正面制备前场，在所述衬底的背面制备发射极；在制备前场和发射极后的衬底的正面生长第一减反膜，衬底的背面生长第二减反膜；在制备第一减反膜和第二减反膜后的衬底的正面印刷正面栅线，衬底的背面印刷背面栅线，并进行烧结处理，该申请能够提高太阳能电池的效率。
CN111162145A公开了一种具有选择性发射极结构的钝化接触太阳能电池及其制备方法。该方法包括：在N型晶体硅基体的两个表面均制备制绒面；在基体正表面的制绒面上进行硼扩散处理，形成轻掺杂区层；在轻掺杂区层利用掩膜进行局部硼离子注入，并退火，形成局部重掺杂区；在基体背表面的制绒面上制备隧穿氧化层，并在隧穿氧化层上制备磷掺杂多晶硅层；在磷掺杂多晶硅层上制备氮化硅减反射层；在基体正面的轻掺杂区层上制备氧化铝钝化层，并在氧化铝钝化层上制备氮化硅减反射层；对基体两个面均丝网印刷金属化浆料，并烧结。该申请可以显著降低发射极表面的复合电流，从而能将N型钝化接触电池效率提升0.2％以上。
目前电池的Topcon技术日益趋于成熟，已经实现了规模化量产，是下一代主流技术的种子选手之一。由于多晶硅层的吸光系数较大，会导致严重的寄生吸收和电流损失，因此常规的Topcon技术针对电池只有背面(非主受光面)有钝化接触结构，正面(主受光面)仍是传统的重掺或选择性掺杂的发射极。也就是说，常规Topcon电池结构只对背面的金属接触区进行钝化，一定程度上提高了开路电压和转换效率，因此，亟需开发设计一种新的太阳能电池结构以满足实际生产生活的需求，同时提高太阳能电池的性能。
发明内容
针对现有技术存在的不足，本申请的目的在于提供一种钝化接触的太阳能电池，在本申请中，可以同时钝化半导体衬底的正面和背面的金属-半导体衬底接触区，降低两面接触区的载流子复合，并将发射极放到背面，可以降低正面非接触区的载流子复合，从而获得比常规Topcon更高的开路电压和转换效率。
为达此目的，本申请采用以下技术方案：
本申请提供了一种钝化接触的太阳能电池，所述太阳能电池包括第一导电类型的半导体衬底，所述第一导电类型的半导体衬底正面具有金属接触区 和非金属接触区，所述金属接触区的第一导电类型的半导体衬底表面依次层叠设置有隧穿层和第一导电类型的掺杂多晶硅层，所述第一导电类型的掺杂多晶硅层和金属电极接触。
所述非金属接触区的第一导电类型的半导体衬底表面设置有第一导电类型的轻掺杂层，或叠加的隧穿层和第一导电类型的掺杂多晶硅层，或无隧穿层和多晶硅层也无掺杂层，所述非金属接触区的第一导电类型的半导体衬底表面最外层设置有介质层。
所述第一导电类型的半导体衬底背面依次层叠设置有隧穿层、第二导电类型的掺杂多晶硅层和介质层，所述金属电极和第二导电类型的掺杂多晶硅层接触。
所述第一导电类型的半导体衬底正面为主受光面，所述第一导电类型的半导体衬底背面为非主受光面。
在本申请中，可以同时钝化半导体衬底的正面和背面的金属-半导体衬底接触区，降低两面接触区的载流子复合，并将发射极放到背面，可以降低正面非接触区的载流子复合，从而获得比常规Topcon更高的开路电压和转换效率。
需要说明的是，本申请中的隧穿层制备方法包括但不限于热氧法、湿化学法、PECVD法、ALD法或准分子源干氧法等；本申请中的掺杂多晶硅层可以是由化学气相沉积(CVD)法制备，包括但不限于LPCVD、PECVD等，再经过热处理形成多晶硅，其掺杂方式可以是原位掺杂或非原位掺杂，非原位掺杂包括但不限于热扩散、离子注入、含源浆料印刷等方式；本申请中的金属电极可以为丝网印刷的金属浆料、电镀金属或喷墨打印、激光转印、蒸镀的金属，具体选择依照实际情况而定，且介质膜在金属接触区可以存在或者不存在，可以通过激光、刻蚀等手段开孔也可以不开孔。
作为本申请一种优选的技术方案，所述的金属接触区的隧穿层厚度为≤3nm，例如可以是1nm、1.5nm、2nm、2.5nm、3nm，但并不仅限于所列举的数值，该数值范围内其他未列举的数值同样适用。
所述的金属接触区的第一导电类型的掺杂多晶硅层厚度为10～1000nm，例如可以是10nm、100nm、200nm、300nm、400nm、500nm、600nm、700nm、800nm、900nm、1000nm，但并不仅限于所列举的数值，该数值范围内其他未列举的数值同样适用。
作为本申请一种优选的技术方案，所述的非金属接触区的第一导电类型的轻掺杂层方阻为50～1000ohm/sq，例如可以是50ohm/sq、100ohm/sq、200ohm/sq、300ohm/sq、400ohm/sq、500ohm/sq、600ohm/sq、700ohm/sq、800ohm/sq、900ohm/sq、1000ohm/sq，但并不仅限于所列举的数值，该数值范围内其他未列举的数值同样适用。
所述的非金属接触区的叠加的隧穿层厚度为≤3nm，例如可以是1nm、1.5nm、2nm、2.5nm、3nm，但并不仅限于所列举的数值，该数值范围内其他未列举的数值同样适用。
所述的非金属接触区的叠加的第一导电类型的掺杂多晶硅层的厚度为1～100nm，例如可以是1nm、10nm、20nm、30nm、40nm、50nm、60nm、70nm、80nm、90nm、100nm，但并不仅限于所列举的数值，该数值范围内其他未列举的数值同样适用。
所述的非金属接触区的叠加的第一导电类型的掺杂多晶硅层的方阻为1～1000ohm/sq，例如可以是1ohm/sq、100ohm/sq、200ohm/sq、300ohm/sq、400ohm/sq、500ohm/sq、600ohm/sq、700ohm/sq、800ohm/sq、900ohm/sq、1000ohm/sq，但并不仅限于所列举的数值，该数值范围内其他未列举的数值同样适用。
所述的非金属接触区叠加的第一导电类型的掺杂多晶硅层与所述的金属接触区叠加的遂穿层和第一导电类型的掺杂多晶硅层可以是一体的或不一体的。
作为本申请一种优选的技术方案，所述第一导电类型的半导体衬底正面为绒面。
需要说明的是，本申请中的第一导电类型的半导体衬底正面可以是常规的绒面或其他类型完整和不完整绒面相结合，具体选择依照实际情况而定。
作为本申请一种优选的技术方案，所述第一导电类型的半导体衬底背面的隧穿层厚度为≤3nm，例如可以是1nm、1.5nm、2nm、2.5nm、3nm，但并不仅限于所列举的数值，该数值范围内其他未列举的数值同样适用。
所述第一导电类型的半导体衬底背面的第二导电类型的掺杂多晶硅层厚度为10～1000nm，例如可以是10nm、100nm、200nm、300nm、400nm、500nm、600nm、700nm、800nm、900nm、1000nm，但并不仅限于所列举的数值，该数值范围内其他未列举的数值同样适用。
作为本申请一种优选的技术方案，所述第一导电类型的半导体衬底背面为绒面、抛光面或局部绒面局部抛光面。
需要说明的是，本申请中背面可以是完整或不完整的绒面(或二者结合)、抛光面(酸抛、碱抛或二者结合)、局部绒面局部抛光面等，具体选择依照实际情况而定。
作为本申请一种优选的技术方案，所述隧穿层为具有载流子隧穿作用和界面钝化作用的介质膜，包括氧化硅介质膜或氧化铝介质膜。
作为本申请一种优选的技术方案，所述第一导电类型的半导体衬底外表面均设置有介质层。
所述介质层的材质包括氮化硅、氧化硅、氮氧化硅、碳化硅、氧化铝、氧化镓、氧化锌、氧化钛或氟化镁的任意一种和两种及以上的组合。
作为本申请一种优选的技术方案，所述第一导电类型的半导体衬底包括晶体硅。
需要说明的是，第一导电类型的半导体衬底包括但不限于晶体硅。
作为本申请一种优选的技术方案，所述第一导电类型的半导体衬底为N型半导体或P型半导体。
与现有技术相比，本申请的有益效果为：
在本申请中，可以同时钝化半导体衬底的正面和背面的金属-半导体衬底接触区，降低两面接触区的载流子复合，并将发射极放到背面，可以降低正面非接触区的载流子复合，从而获得比常规Topcon更高的开路电压和转换效率。
附图说明
图1为本申请一个具体实施方式提供的太阳能电池结构的正面示意图一；
图2为本申请一个具体实施方式提供的太阳能电池结构的正面示意图二；
图3为本申请一个具体实施方式提供的太阳能电池结构的正面示意图三；
图4为本申请一个具体实施方式提供的太阳能电池结构的背面示意图；
其中，1-第一导电类型的半导体衬底；2-隧穿层；3-第二导电类型的掺杂多晶硅层；4-半导体衬底背面介质层；5-半导体衬底背面金属电极；6-接触区的隧穿层；7-接触区第一导电类型的掺杂多晶硅层；8-非接触区的第一导电类型的轻掺杂层；9-非接触区第一导电类型的掺杂多晶硅层；10-非接触区的隧 穿层；11-半导体衬底正面介质层；12-半导体衬底正面金属电极。
具体实施方式
需要理解的是，在本申请的描述中，术语“中心”、“纵向”、“横向”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”等仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”等的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。
需要说明的是，在本申请的描述中，除非另有明确的规定和限定，术语“设置”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以通过具体情况理解上述术语在本申请中的具体含义。
下面结合附图并通过具体实施方式来进一步说明本申请的技术方案。
在一个具体实施方式中，本申请提供了一种钝化接触的太阳能电池，如图1-4所示，所述太阳能电池包括具有第一导电类型的半导体衬底1，第一导电类型的半导体衬底1正面具有金属接触区和非金属接触区，金属接触区的第一导电类型的半导体衬底表面依次层叠设置有隧穿层6和第一导电类型的掺杂多晶硅层7，第一导电类型的掺杂多晶硅层7和半导体衬底正面金属电极12接触。
非金属接触区的第一导电类型的半导体衬底1表面设置有第一导电类型的轻掺杂层8，或叠加的隧穿层9和第一导电类型的掺杂多晶硅层10记为钝化接触结构，或无钝化接触结构也无掺杂层，非金属接触区的第一导电类型的半导体衬底表面最外层设置有半导体衬底正面介质层11。
第一导电类型的半导体衬底1背面依次层叠设置有隧穿层2、第二导电类型的掺杂多晶硅层3和半导体衬底背面介质层4，半导体衬底背面金属电极5和第二导电类型的掺杂多晶硅层3接触。第一导电类型的半导体衬底1正面为主受光面，第一导电类型的半导体衬底1背面为非主受光面。
在本申请中，可以同时钝化半导体衬底1的正面和背面的金属-半导体衬底1接触区，降低两面接触区的载流子复合，并将发射极放到背面，可以降低正面非接触区的载流子复合，从而获得比常规Topcon更高的开路电压和转换效率。
需要说明的是，本申请中的隧穿层2制备方法包括但不限于热氧法、湿化学法、PECVD法、ALD法或准分子源干氧法等；本申请中的掺杂多晶硅层可以是由化学气相沉积(CVD)法制备，包括但不限于LPCVD、PECVD等，再经过热处理形成多晶硅，其掺杂方式可以是原位掺杂或非原位掺杂，非原位掺杂包括但不限于热扩散、离子注入、含源浆料印刷等方式；本申请中的金属电极可以为丝网印刷的金属浆料、电镀金属或喷墨打印、激光转印、蒸镀的金属，具体选择依照实际情况而定，且介质膜在金属接触区可以通过激光、刻蚀等手段开孔也可以不开孔。
金属接触区的隧穿层6厚度为≤3nm，金属接触区的第一导电类型的掺杂多晶硅层7厚度为10～1000nm，非金属接触区的第一导电类型的轻掺杂层8方阻为50～1000ohm/sq，非金属接触区的叠加的隧穿层9厚度为10～1000nm，非金属接触区的叠加的第一导电类型的掺杂多晶硅层10的厚度为1～100nm，方阻为1～1000ohm/sq。
第一导电类型的半导体衬底1正面为绒面。需要说明的是，本申请中的第一导电类型的半导体衬底1正面可以是常规的绒面或其他类型完整和不完整绒面相结合，具体选择依照实际情况而定。
第一导电类型的半导体衬底1背面的隧穿层2厚度为≤3nm，第一导电类型的半导体衬底1背面的第二导电类型的掺杂多晶硅层3厚度为10～1000nm，第一导电类型的半导体衬底1背面为绒面、抛光面或局部绒面局部抛光面，需要说明的是，本申请中背面可以是完整或不完整的绒面(或二者结合)、抛光面(酸抛、碱抛或二者结合)、局部绒面局部抛光面等，具体选择依照实际情况而定。
隧穿层2为具有载流子隧穿作用和界面钝化作用的介质膜，包括氧化硅介质膜或氧化铝介质膜，第一导电类型的半导体衬底1外表面均设置有介质层，包括半导体衬底正面介质层11和半导体衬底背面介质层4，介质层的材质包括氮化硅、氧化硅、氮氧化硅、碳化硅、氧化铝、氧化镓、氧化锌、氧化钛或氟化镁的任意一种和两种及以上的组合。
第一导电类型的半导体衬底1包括晶体硅，需要说明的是，第一导电类型的半导体衬底包括但不限于晶体硅，进一步地，第一导电类型的半导体衬底1为N型半导体或P型半导体。
申请人声明，以上所述仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，所属技术领域的技术人员应该明了，任何属于本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到的变化或替换，均落在本申请的保护范围和公开范围之内。

Claims (10)

  1. 一种钝化接触的太阳能电池，所述太阳能电池包括第一导电类型的半导体衬底(1)，所述第一导电类型的半导体衬底(1)正面具有金属接触区和非金属接触区，所述金属接触区的第一导电类型的半导体衬底(1)表面依次层叠设置有隧穿层(6)和第一导电类型的掺杂多晶硅层(7)，所述第一导电类型的掺杂多晶硅层(7)和金属电极(12)接触；所述非金属接触区的第一导电类型的半导体衬底(1)表面设置有第一导电类型的轻掺杂层(8)，或叠加的隧穿层(10)和第一导电类型的掺杂多晶硅层(9)，或无隧穿层和多晶硅层也无掺杂层，所述非金属接触区的第一导电类型的半导体衬底(1)表面最外层设置有介质层(11)；所述第一导电类型的半导体衬底(1)背面依次层叠设置有隧穿层(2)、第二导电类型的掺杂多晶硅层(3)和介质层(4)，金属电极(5)和第二导电类型的掺杂多晶硅层(3)接触；所述第一导电类型的半导体衬底(1)正面为主受光面，所述第一导电类型的半导体衬底(1)背面为非主受光面。
  2. 根据权利要求1所述的钝化接触的太阳能电池，所述的金属接触区的隧穿层(6)厚度为≤3nm；所述的金属接触区的第一导电类型的掺杂多晶硅层(7)厚度为10～1000nm。
  3. 根据权利要求1所述的钝化接触的太阳能电池，所述的非金属接触区的第一导电类型的轻掺杂层(8)方阻为50～1000ohm/sq；所述的非金属接触区的叠加的隧穿层(10)厚度为≤3nm；所述的非金属接触区的叠加的第一导电类型的掺杂多晶硅层(9)的厚度为1～100nm，方阻为1～1000ohm/sq。
  4. 根据权利要求1所述的钝化接触的太阳能电池，所述第一导电类型的半导体衬底(1)正面为绒面。
  5. 根据权利要求1所述的钝化接触的太阳能电池，所述第一导电类型的半导体衬底(1)背面的隧穿层(2)厚度为≤3nm；所述第一导电类型的半导体衬底(1)背面的第二导电类型的掺杂多晶硅层(3)的厚度为10～1000nm。
  6. 根据权利要求1所述的钝化接触的太阳能电池，所述第一导电类型的半导体衬底(1)背面为绒面、抛光面或局部绒面局部抛光面。
  7. 根据权利要求1所述的钝化接触的太阳能电池，所述隧穿层(2)和隧穿层(6)均为具有载流子隧穿作用和界面钝化作用的介质膜，包括氧化硅介质膜或氧化铝介质膜。
  8. 根据权利要求1所述的钝化接触的太阳能电池，所述介质层(4)和所述介质层(11)的材质包括氮化硅、氧化硅、氮氧化硅、碳化硅、氧化铝、氧化镓、氧化锌、氧化钛或氟化镁的任意一种或两种及以上的组合。
  9. 根据权利要求1所述的钝化接触的太阳能电池，所述第一导电类型的半导体衬底(1)包括晶体硅。
  10. 根据权利要求1所述的钝化接触的太阳能电池，所述第一导电类型的半导体衬底(1)为N型半导体或P型半导体。
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CN114497241A (zh) * 2021-10-27 2022-05-13 天合光能股份有限公司 一种钝化接触的太阳能电池
CN116525708B (zh) * 2023-07-05 2023-09-12 福建金石能源有限公司 正面宽带隙掺杂的联合钝化背接触太阳电池及其制备方法
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017004624A1 (en) * 2015-07-02 2017-01-05 Solexel, Inc. Discrete carrier selective passivated contacts for solar cells
CN107195699A (zh) * 2017-07-12 2017-09-22 泰州中来光电科技有限公司 一种钝化接触太阳能电池及制备方法
CN111628050A (zh) * 2020-06-11 2020-09-04 常州时创能源股份有限公司 实现电子局部钝化接触的方法、晶体硅太阳能电池及其制备方法
CN112201701A (zh) * 2020-09-30 2021-01-08 浙江晶科能源有限公司 太阳能电池和光伏组件
CN113644142A (zh) * 2021-06-18 2021-11-12 天合光能股份有限公司 一种具有钝化接触的太阳能电池及其制备方法
CN114497241A (zh) * 2021-10-27 2022-05-13 天合光能股份有限公司 一种钝化接触的太阳能电池

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111180551A (zh) * 2020-01-02 2020-05-19 浙江晶科能源有限公司 一种选择性发射极太阳能电池及其制备方法
CN216597604U (zh) * 2021-10-27 2022-05-24 天合光能股份有限公司 一种钝化接触的太阳能电池

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017004624A1 (en) * 2015-07-02 2017-01-05 Solexel, Inc. Discrete carrier selective passivated contacts for solar cells
CN107195699A (zh) * 2017-07-12 2017-09-22 泰州中来光电科技有限公司 一种钝化接触太阳能电池及制备方法
CN111628050A (zh) * 2020-06-11 2020-09-04 常州时创能源股份有限公司 实现电子局部钝化接触的方法、晶体硅太阳能电池及其制备方法
CN112201701A (zh) * 2020-09-30 2021-01-08 浙江晶科能源有限公司 太阳能电池和光伏组件
CN113644142A (zh) * 2021-06-18 2021-11-12 天合光能股份有限公司 一种具有钝化接触的太阳能电池及其制备方法
CN114497241A (zh) * 2021-10-27 2022-05-13 天合光能股份有限公司 一种钝化接触的太阳能电池

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