WO2023119450A1 - Module semi-conducteur et module empilé - Google Patents

Module semi-conducteur et module empilé Download PDF

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Publication number
WO2023119450A1
WO2023119450A1 PCT/JP2021/047418 JP2021047418W WO2023119450A1 WO 2023119450 A1 WO2023119450 A1 WO 2023119450A1 JP 2021047418 W JP2021047418 W JP 2021047418W WO 2023119450 A1 WO2023119450 A1 WO 2023119450A1
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Prior art keywords
chip
semiconductor module
memory
stacking direction
input
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PCT/JP2021/047418
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English (en)
Japanese (ja)
Inventor
一彦 梶谷
文武 奥津
和雄 加藤
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ウルトラメモリ株式会社
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Priority to PCT/JP2021/047418 priority Critical patent/WO2023119450A1/fr
Priority to JP2023568850A priority patent/JPWO2023119450A1/ja
Publication of WO2023119450A1 publication Critical patent/WO2023119450A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration

Definitions

  • the present invention relates to semiconductor modules and laminated modules.
  • RAM volatile memories
  • DRAM Dynamic Random Access Memory
  • logic chips arithmetic units
  • an increase in the amount of data Therefore, attempts have been made to increase the capacity by miniaturizing the memory (memory cell array, memory chip) and increasing the number of cells in a plane.
  • this type of increase in capacity has reached its limit due to the vulnerability to noise due to miniaturization, the increase in chip area, and the like.
  • Patent Document 1 In the storage device of Patent Document 1, a command die and a memory die are stacked. In Patent Document 1, a command die and a memory die are connected by a TSV (Through Silicon Via). In Patent Document 1, as the number of stacked memory dies increases, the number of stages of TSVs increases, so it is conceivable that the yield will decrease. Further, in Patent Document 1, when a plurality of TSVs bypassing between dies are provided, an increase in die size and an increase in manufacturing cost can be considered. Furthermore, in Japanese Patent Laid-Open No. 2002-100001, even when the variation of the storage device is increased, it is necessary to change the positions of the TSVs, etc., so that the die size and the manufacturing cost may increase.
  • the present invention has been made in view of the above problems, and aims to provide a semiconductor module and a laminated module that can be manufactured easily.
  • the present invention includes a plurality of memory sections stacked in a stacking direction, each having input/output terminals for inputting and outputting signals and connection terminals for connecting to other memory sections. are arranged between the memory units adjacent in the stacking direction and on one surface of the memory unit on one end side in the stacking direction, and protrude beyond the end face of the memory unit in a direction crossing the stacking direction.
  • a rewiring layer having an edge; and an external electrode disposed between the rewiring layers adjacent in the stacking direction and electrically connecting the edge of the rewiring layer, wherein the rewiring layer and the The external electrode relates to a semiconductor module forming a connection circuit connecting the connection terminal of one memory section and the input/output terminal of another memory section.
  • the memory section preferably has a plurality of stacked memory chips.
  • the memory section preferably has a primary chip having the input/output terminals and the connection terminals, and a secondary chip connected to the primary chip.
  • the primary chip preferably has a timing control section that adjusts operation timings of the primary chip and the secondary chip.
  • the primary chip and the secondary chip are the same chip with partially changed functions.
  • the primary chip is preferably connected to the secondary chip by a bumpless TSV.
  • the primary chip is preferably connected to the adjacent secondary chip by hybrid bonding.
  • the primary chip is preferably connected to the secondary chip by contactless communication.
  • connection circuit connects the connection terminal for the clock signal and the command signal of one of the memory sections and the input/output terminal for the clock signal and the command signal of the other memory section.
  • the semiconductor module preferably further comprises a logic chip arranged at the end of the rewiring layer.
  • the present invention also relates to a laminated module in which a plurality of the above semiconductor modules are laminated.
  • FIG. 1 is a cross-sectional view showing a semiconductor module according to a first embodiment of the invention
  • FIG. 1 is a block diagram showing a semiconductor module of a first embodiment
  • FIG. 1 is a circuit diagram showing a semiconductor module of a first embodiment
  • FIG. It is a block diagram showing a semiconductor module according to a second embodiment of the present invention. It is a circuit diagram showing a semiconductor module of a second embodiment. It is a block diagram showing a semiconductor module according to a third embodiment of the present invention. It is a circuit diagram which shows the semiconductor module of 3rd Embodiment.
  • It is a block diagram showing a semiconductor module according to a fourth embodiment of the present invention. It is a circuit diagram which shows the semiconductor module of 4th Embodiment.
  • FIG. 11 is a cross-sectional view taken along line AA of FIG. 10;
  • FIG. 11 is a cross-sectional view showing a laminate module according to a sixth embodiment of the present invention.
  • a semiconductor module 1 and a laminated module 100 according to each embodiment of the present invention will be described below with reference to FIGS. 1 to 12.
  • FIG. First, outlines of the semiconductor module 1 and the laminated module 100 according to each embodiment will be described.
  • the semiconductor module 1 and the stacked module 100 are, for example, stacking a plurality of stacked memories.
  • the semiconductor module 1 and the stacked module 100 are configured by stacking a plurality of memory chips.
  • external wirings for electrically connecting the stacked memories are arranged in a direction crossing the stacking direction D of the stacked memories.
  • the semiconductor module 1 and the laminated module 100 bypass the communication of the laminated memory using external wiring (for example, the external electrodes 14). Accordingly, in the following embodiments, the semiconductor module 1 and the laminated module 100 are intended to be manufactured easily.
  • the laminated module 100 is obtained by laminating a plurality of semiconductor modules 1 .
  • FIG. A semiconductor module 1 includes a plurality of stacked memories, as shown in FIG.
  • the semiconductor module 1 includes a memory section 11 , a rewiring layer 12 , a mold section 13 , external electrodes 14 and solder balls 15 .
  • the memory units 11 are, as shown in FIGS. 2 and 3, a plurality of memory units 11 stacked in the stacking direction D, each having input/output terminals 31 and connection terminals 32 .
  • the memory unit 11 has a plurality of stacked memory chips. Specifically, the memory unit 11 has four stacked memory chips. Also, the memory unit 11 has a primary chip 110 and a secondary chip 120 . Note that the primary chip 110 and the secondary chip 120 are the same chip with partially changed functions. In this embodiment, the memory unit 11 has one primary chip 110 and three secondary chips 120 . Note that, in the present embodiment, the memory unit 11 arranged at one end in the stacking direction D is also described as a primary stack 21 .
  • the input/output terminal 31 is, for example, a terminal for inputting/outputting signals to/from the outside.
  • the input/output terminal 31 has, for example, a clock terminal 311 , a command terminal 312 and a data terminal 313 .
  • the clock terminal 311 receives, for example, a signal from the outside.
  • the clock terminal 311 receives an input of a clock signal provided from the outside, for example.
  • the command terminal 312 receives, for example, signals from the outside.
  • the command terminal 312 receives an input of a command signal provided from the outside, for example.
  • the data terminal 313 receives input/output of data with the outside, for example.
  • the data terminal 313 receives input/output of data signals with the outside, for example.
  • the connection terminal 32 is a terminal for connecting to another memory unit 11, for example.
  • the connection terminal 32 has a clock terminal 321 , a command terminal 322 , and a data terminal 323 like the input/output terminal 31 .
  • the connection terminal 32 is connected to the input/output terminal 31 via the buffer 41 as shown in FIG.
  • the primary chip 110 has input/output terminals 31 and connection terminals 32, as shown in FIGS.
  • one primary chip 110 is arranged at one end in the stacking direction D in the memory section 11 .
  • the primary chip 110 is connected to a secondary chip 120, which will be described later, by a bumpless TSV 200, for example.
  • the primary chip 110 has transfer terminals 121 for transferring clock signals, command signals, and data signals to other stacked memory chips.
  • the primary chip 110 has a timing control section 111 that adjusts operation timings of the primary chip 110 and a secondary chip 120, which will be described later.
  • the primary chip 110 has a timing controller 111 including memory cells (not shown) and memory control circuits (not shown).
  • the secondary chip 120 is stacked on the primary chip 110, for example. Secondary chip 120 is connected to primary chip 110 .
  • the secondary chip 120 has transfer terminals 121 for transferring clock signals, command signals, and data signals between the primary chip 110 or other secondary chips 120 adjacent in the stacking direction D.
  • FIG. In this embodiment, three secondary chips 120 are stacked within one memory unit 11 .
  • Each of the secondary chips 120 are connected to the primary chip 110 using bumpless TSVs 200 .
  • the secondary chip 120 has a memory controller 122 including memory cells (not shown) and memory control circuits (not shown).
  • the rewiring layer 12 is arranged between the memory sections 11 adjacent in the stacking direction D and on one surface of the memory section 11 on one end side in the stacking direction D.
  • the rewiring layer 12 is arranged adjacent to the primary chip 110 in the stacking direction D, for example.
  • the rewiring layer 12 is electrically connected to the input/output terminals 31 and the connection terminals 32 of the primary chip 110 .
  • the rewiring layer 12 has an end portion 42 that protrudes from the end face of the memory portion 11 in the direction intersecting the stacking direction D. As shown in FIG.
  • the rewiring layer 12 has, for example, end portions 42 arranged to protrude from both end faces of the memory portion 11 in a direction intersecting the stacking direction D, for example.
  • the molded part 13 is made of epoxy resin or the like, for example.
  • the mold part 13 is arranged between the end parts 42 of the adjacent rewiring layers 12 .
  • the mold part 13 is formed to have the same height as the memory part 11 in the stacking direction D, for example.
  • the external electrodes 14 are arranged between the rewiring layers 12 adjacent in the stacking direction D, and electrically connect the ends 42 of the rewiring layers 12 .
  • the external electrodes 14 are formed, for example, as mold through electrodes penetrating the mold portion 13, as shown in FIG.
  • the external electrodes 14 electrically connect adjacent rewiring layers 12 .
  • the external electrodes 14 are arranged across the memory section 11 in the direction intersecting the stacking direction D.
  • the number of external electrodes 14 corresponding to the number of circuits connecting the plurality of connection circuits 50 is provided.
  • one external electrode 14 is provided as one set of three in accordance with the clock signal, the command signal, and the input/output signal.
  • a connection circuit 50 for connecting the connection terminal 32 and the input/output terminal 31 of the other memory section 11 is formed.
  • the connection terminal 32 connects one memory unit 11 (primary stack 21 ) and the other three memory units 11 . That is, the connection circuit 50 connects the clock terminal 311, the command terminal 312, and the data terminal 313 of the connection terminal 32 of the primary stack 21, and the clock signals, command signals, and data signals of the input/output terminals 31 of all the other memory units 11. It is connected to the signal input/output terminal 31 .
  • connection circuit 50 bypass-connects the three memory units 11 to the primary stack 21 .
  • the connection circuit 50 aggregates the data signals input/output from the other three memory units 11 to the primary stack 21 according to the clock signal and command signal input to the primary stack 21 .
  • a plurality of solder balls 15 are arranged in contact with the rewiring layer 12 at one end in the stacking direction D, for example.
  • the solder balls 15 are arranged to electrically connect the semiconductor module 1 to another substrate (not shown) or the like.
  • the primary stack 21 (for example, the memory section 11 arranged at one end in the stacking direction D) is connected via the solder ball 15 and the rewiring layer 12 at one end in the stacking direction D connected to the solder ball 15 . ) are input with a clock signal, a command signal, and a data signal for writing.
  • the connection terminal 32 of the primary stack 21 outputs the clock signal, command signal, and data signal input to the input/output terminal 31 to the connection circuit 50 .
  • the output clock signal, command signal, and data signal are input to the input/output terminals 31 of the other memory section 11 via the external electrodes 14 and the rewiring layer 12 that constitute the connection circuit 50 .
  • the primary chip 110 of each memory unit 11 uses transfer terminals 121 to transfer clock signals, command signals, and data signals to the secondary chip 120 .
  • the primary chip 110 and secondary chip 120 access the memory areas of their respective chips in response to clock signals, command signals, and data signals.
  • the primary chip 110 and the secondary chip 120 write data to their respective memory areas based on clock signals, command signals, and data signals.
  • the primary stack 21 (for example, the memory section arranged at one end in the stacking direction D) is connected to the solder ball 15 and the rewiring layer 12 connected to the solder ball 15 at one end in the stacking direction D.
  • a clock signal and a command signal are input to the input/output terminal 31 of 11).
  • the connection terminal 32 of the primary stack 21 outputs the clock signal and command signal input to the input/output terminal 31 to the connection circuit 50 .
  • the output clock signal and command signal are input to the input/output terminal 31 of the other memory section 11 via the external electrode 14 and the rewiring layer 12 that constitute the connection circuit 50 .
  • the primary chip 110 of each memory unit 11 uses the transfer terminal 121 to transfer the clock signal and command signal to the secondary chip 120 .
  • the primary chip 110 and the secondary chip 120 access the memory area of each chip according to clock signals and command signals.
  • the primary chip 110 and secondary chip 120 read data from their respective memory areas based on the clock signal and command signal.
  • the secondary chip 120 transfers the data read using the transfer terminal 121 to the primary chip 110 as a data signal.
  • the primary chip 110 buffers its own read data and transferred data.
  • the primary chip 110 of the other memory unit 11 uses the input/output terminal 31 and the connection circuit 50 to transmit the buffered data signal to the connection terminal 32 of the primary stack 21 .
  • the primary chip 110 of the primary stack 21 receives its own buffered data and the data transmitted from the other memory unit 11 as data signals to the outside via the input/output terminal 31, the rewiring layer 12, and the solder balls 15. output to
  • a semiconductor module 1 including a plurality of stacked memories a plurality of memory sections 11 stacked in the stacking direction, each having an input/output terminal 31 for inputting/outputting a signal and a terminal for connecting to another memory section.
  • the memory section 11 having the connection terminal 32 and the memory sections 11 adjacent in the stacking direction are arranged between the memory sections 11 adjacent to each other in the stacking direction and on one surface of the memory section on one end side in the stacking direction, and the memory section is arranged in the direction crossing the stacking direction.
  • connection circuit 50 that connects the connection terminal 32 of one memory section 11 and the input/output terminal 31 of another memory section.
  • the memory unit 11 has a plurality of memory chips stacked using bumpless TSV200. As a result, the memory capacity can be easily increased while suppressing the height of the memory section 11 in the stacking direction and facilitating manufacturing.
  • the memory unit 11 has a primary chip 110 having input/output terminals 31 and connection terminals 32 and a secondary chip 120 connected to the primary chip 110 . Thereby, it is possible to easily control the plurality of stacked memory units 11 . Also, the circuit configuration can be simplified for a plurality of memory chips.
  • the primary chip 110 has a timing control section 111 that adjusts the operation timings of the primary chip 110 and secondary chip 120 . Thereby, it is possible to appropriately control the operation of a plurality of memory chips.
  • FIG. 1 a semiconductor module 1 according to a second embodiment of the invention will be described with reference to FIGS. 4 and 5.
  • FIG. In 2nd Embodiment the same code
  • the semiconductor module 1 according to the second embodiment differs from the first embodiment in that the data terminal 313 of the connection terminals 32 is not connected to the connection circuit 50, as shown in FIGS.
  • the data terminal 313 among the input/output terminals 31 of the plurality of memory units 11 includes the rewiring layer 12 adjacent to the primary chip 110, the external electrode 14, the rewiring layer 12 at one end in the stacking direction D, and the solder.
  • the data terminal 313 among the input/output terminals 31 of the plurality of memory units 11 is directly connected to the outside. Accordingly, the data terminal 313 of the connection terminals 32 of the primary stack 21 is not connected to the connection circuit 50 .
  • the semiconductor module 1 according to the first embodiment as described above has the following effects.
  • (4) The data terminals 313 among the input/output terminals 31 of the plurality of memory units 11 are connected to the outside via the adjacent rewiring layer 12, the external electrode 14, the rewiring layer 12 at one end in the stacking direction D, and the solder balls 15. connected to As a result, the data signal is directly communicated with the outside, so that the data transmission path can be shortened and the data quality can be improved. Also, by operating a plurality of memory units 11 simultaneously, the number of data signals can be increased and the bandwidth can be improved.
  • FIG. 1 differs from the first and second embodiments in that a plurality of primary stacks 21 and connection circuits 50 are provided as shown in FIGS.
  • the third embodiment differs from the first and second embodiments in that two sets of one primary stack 21, one other memory section 11, and a connection circuit 50 connecting the two are provided. That is, the semiconductor module 1 according to the third embodiment differs from the first and second embodiments in that two input/output terminals 31 of the primary stack 21 connected to the outside are provided.
  • the semiconductor module 1 according to the third embodiment as described above has the following effects. (5) A plurality of sets of one memory section 11, another memory section 11, and a connection circuit 50 connecting the two are provided. As a result, the input/output terminals 31 can be multi-channeled, so that the utilization efficiency of the semiconductor module 1 can be improved.
  • FIG. 8 and 9 a semiconductor module 1 according to a fourth embodiment of the invention will be described with reference to FIGS. 8 and 9.
  • FIG. 8 and 9 the same code
  • the semiconductor module 1 according to the fourth embodiment is different from the first in that one memory section 11 is connected in series with another memory section 11 using a connection circuit 50 . It differs from the third embodiment.
  • the semiconductor module 1 includes a connection circuit 50 that connects the connection terminal 32 of the primary stack 21 and the input/output terminal 31 of the other memory section 11, and It differs from the first to third embodiments in that it has a connection circuit 50 that connects the connection terminal 32 and the input/output terminal 31 of the other memory section 11 .
  • the semiconductor module 1 according to the fourth embodiment as described above has the following effects. (6) One memory section 11 is connected in series with another memory section 11 using the connection circuit 50 . As a result, the path of the connection circuit 50 can be shortened, so that the yield can be improved. In addition, since the parasitic resistance and parasitic capacitance of the connection circuit 50 can be kept substantially constant regardless of the number of stacked memory units 11, the number of stacked memory units 11 can be easily changed.
  • the semiconductor module 1 according to the fifth embodiment is different from the first to fourth embodiments in that it further includes a logic chip 130 arranged at the end portion 42 of the rewiring layer 12 . different.
  • a plurality of dummy silicon layers 132 are arranged over the logic chip 130 .
  • the plurality of memory units 11 are arranged in pairs with the logic chip 130 interposed therebetween.
  • the logic chip 130 also has a controller 131 that is connected to the memory section 11 and controls input/output of signals to/from the memory section 11 .
  • the semiconductor module 1 according to the fifth embodiment as described above has the following effects.
  • the semiconductor module 1 further includes a logic chip 130 arranged at the end portion 42 of the rewiring layer 12 . Thereby, the wiring distance between the memory unit 11 and the logic chip 130 can be shortened. Therefore, the semiconductor module 1 with high memory frequency (signal quality) and low data transfer power can be realized.
  • a stacked module 100 according to the sixth embodiment differs from the first to fifth embodiments in that a plurality of semiconductor modules 1 according to the first to fifth embodiments are stacked.
  • the stacked module 100 connects a plurality of semiconductor modules 1 using microbumps 16, for example, as shown in FIG.
  • the rewiring layer 12 is arranged on the surface of the other end side of the semiconductor module 1 on which the other semiconductor module 1 is stacked on the one end side in the stacking direction D.
  • Other semiconductor modules 1 are electrically connected using the arranged rewiring layers 12 and microbumps 16 .
  • the laminated module 100 is formed by laminating a plurality of the semiconductor modules 1 described above. As a result, the number of memory units 11 included in the semiconductor module 1 can be reduced, so that the yield of the semiconductor module 1 can be improved. Thereby, the yield of the laminated module 100 can also be improved. In addition, since the number of stages of the memory section 11 of the semiconductor module 1 can be reduced, assembly can be facilitated.
  • the present invention is not limited to the above-described embodiments and can be modified as appropriate.
  • the memory unit 11 includes a plurality of memory chips in the above embodiment, it may include one memory chip.
  • the primary chip 110 may be connected to the adjacent secondary chip 120 by hybrid bonding. Also, the primary chip 110 may be connected to the secondary chip 120 by contactless communication. As a result, the height of the memory section 11 in the stacking direction can be suppressed, so that the manufacturing of the semiconductor module 1 can be facilitated.
  • the number of primary stacks 21 and other memory units 11 is not limited to four. Also, the number of secondary chips 120 is not limited.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)

Abstract

La présente invention concerne un module semi-conducteur et un module empilé qui peuvent être fabriqués plus facilement. Un module semi-conducteur 1 doté d'une pluralité de mémoires empilées comprend : une pluralité d'unités de mémoire 11 qui sont empilées dans une direction d'empilement D, et qui ont chacune une borne d'entrée/sortie 31 pour l'entrée/sortie d'un signal et une borne de connexion 32 pour la connexion à une autre unité de mémoire 11 ; des couches de redistribution 12 disposées entre les unités de mémoire 11 adjacentes dans la direction d'empilement D et sur une surface de l'unité de mémoire 11 sur un côté de la direction d'empilement D, et ayant chacune une partie marginale 42 dépassant la surface marginale de l'unité de mémoire 11 dans une direction croisant la direction d'empilement D ; et des électrodes externes 14 disposées entre les couches de redistribution 12 adjacentes dans la direction d'empilement D et connectant électriquement les parties marginales 42 des couches de redistribution 12. La couche de redistribution 12 et l'électrode externe 14 forment un circuit de connexion 50 qui permet de connecter la borne de connexion 32 d'une unité de mémoire 11 à la borne d'entrée/sortie 31 d'une autre unité de mémoire 11.
PCT/JP2021/047418 2021-12-21 2021-12-21 Module semi-conducteur et module empilé WO2023119450A1 (fr)

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JP2009016786A (ja) * 2007-07-02 2009-01-22 Nepes Corp 超薄型半導体パッケージ及びその製造方法
JP2009295699A (ja) * 2008-06-03 2009-12-17 Keio Gijuku 電子回路
JP2013201218A (ja) * 2012-03-23 2013-10-03 Toshiba Corp 半導体装置とそれを用いた半導体モジュール
WO2018220846A1 (fr) * 2017-06-02 2018-12-06 ウルトラメモリ株式会社 Module semi-conducteur
US20200227386A1 (en) * 2019-01-14 2020-07-16 Intel Corporation Dual rdl stacked die package using vertical wire
US20210118851A1 (en) * 2019-10-17 2021-04-22 Micron Technology, Inc. Microelectronic device assemblies and packages including surface mount components

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002368185A (ja) * 2001-06-01 2002-12-20 Toshiba Corp 半導体装置
JP2009016786A (ja) * 2007-07-02 2009-01-22 Nepes Corp 超薄型半導体パッケージ及びその製造方法
JP2009295699A (ja) * 2008-06-03 2009-12-17 Keio Gijuku 電子回路
JP2013201218A (ja) * 2012-03-23 2013-10-03 Toshiba Corp 半導体装置とそれを用いた半導体モジュール
WO2018220846A1 (fr) * 2017-06-02 2018-12-06 ウルトラメモリ株式会社 Module semi-conducteur
US20200227386A1 (en) * 2019-01-14 2020-07-16 Intel Corporation Dual rdl stacked die package using vertical wire
US20210118851A1 (en) * 2019-10-17 2021-04-22 Micron Technology, Inc. Microelectronic device assemblies and packages including surface mount components

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