WO2023119450A1 - Semiconductor module and stacked module - Google Patents

Semiconductor module and stacked module Download PDF

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Publication number
WO2023119450A1
WO2023119450A1 PCT/JP2021/047418 JP2021047418W WO2023119450A1 WO 2023119450 A1 WO2023119450 A1 WO 2023119450A1 JP 2021047418 W JP2021047418 W JP 2021047418W WO 2023119450 A1 WO2023119450 A1 WO 2023119450A1
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Prior art keywords
chip
semiconductor module
memory
stacking direction
input
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PCT/JP2021/047418
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French (fr)
Japanese (ja)
Inventor
一彦 梶谷
文武 奥津
和雄 加藤
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ウルトラメモリ株式会社
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Priority to PCT/JP2021/047418 priority Critical patent/WO2023119450A1/en
Publication of WO2023119450A1 publication Critical patent/WO2023119450A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration

Definitions

  • the present invention relates to semiconductor modules and laminated modules.
  • RAM volatile memories
  • DRAM Dynamic Random Access Memory
  • logic chips arithmetic units
  • an increase in the amount of data Therefore, attempts have been made to increase the capacity by miniaturizing the memory (memory cell array, memory chip) and increasing the number of cells in a plane.
  • this type of increase in capacity has reached its limit due to the vulnerability to noise due to miniaturization, the increase in chip area, and the like.
  • Patent Document 1 In the storage device of Patent Document 1, a command die and a memory die are stacked. In Patent Document 1, a command die and a memory die are connected by a TSV (Through Silicon Via). In Patent Document 1, as the number of stacked memory dies increases, the number of stages of TSVs increases, so it is conceivable that the yield will decrease. Further, in Patent Document 1, when a plurality of TSVs bypassing between dies are provided, an increase in die size and an increase in manufacturing cost can be considered. Furthermore, in Japanese Patent Laid-Open No. 2002-100001, even when the variation of the storage device is increased, it is necessary to change the positions of the TSVs, etc., so that the die size and the manufacturing cost may increase.
  • the present invention has been made in view of the above problems, and aims to provide a semiconductor module and a laminated module that can be manufactured easily.
  • the present invention includes a plurality of memory sections stacked in a stacking direction, each having input/output terminals for inputting and outputting signals and connection terminals for connecting to other memory sections. are arranged between the memory units adjacent in the stacking direction and on one surface of the memory unit on one end side in the stacking direction, and protrude beyond the end face of the memory unit in a direction crossing the stacking direction.
  • a rewiring layer having an edge; and an external electrode disposed between the rewiring layers adjacent in the stacking direction and electrically connecting the edge of the rewiring layer, wherein the rewiring layer and the The external electrode relates to a semiconductor module forming a connection circuit connecting the connection terminal of one memory section and the input/output terminal of another memory section.
  • the memory section preferably has a plurality of stacked memory chips.
  • the memory section preferably has a primary chip having the input/output terminals and the connection terminals, and a secondary chip connected to the primary chip.
  • the primary chip preferably has a timing control section that adjusts operation timings of the primary chip and the secondary chip.
  • the primary chip and the secondary chip are the same chip with partially changed functions.
  • the primary chip is preferably connected to the secondary chip by a bumpless TSV.
  • the primary chip is preferably connected to the adjacent secondary chip by hybrid bonding.
  • the primary chip is preferably connected to the secondary chip by contactless communication.
  • connection circuit connects the connection terminal for the clock signal and the command signal of one of the memory sections and the input/output terminal for the clock signal and the command signal of the other memory section.
  • the semiconductor module preferably further comprises a logic chip arranged at the end of the rewiring layer.
  • the present invention also relates to a laminated module in which a plurality of the above semiconductor modules are laminated.
  • FIG. 1 is a cross-sectional view showing a semiconductor module according to a first embodiment of the invention
  • FIG. 1 is a block diagram showing a semiconductor module of a first embodiment
  • FIG. 1 is a circuit diagram showing a semiconductor module of a first embodiment
  • FIG. It is a block diagram showing a semiconductor module according to a second embodiment of the present invention. It is a circuit diagram showing a semiconductor module of a second embodiment. It is a block diagram showing a semiconductor module according to a third embodiment of the present invention. It is a circuit diagram which shows the semiconductor module of 3rd Embodiment.
  • It is a block diagram showing a semiconductor module according to a fourth embodiment of the present invention. It is a circuit diagram which shows the semiconductor module of 4th Embodiment.
  • FIG. 11 is a cross-sectional view taken along line AA of FIG. 10;
  • FIG. 11 is a cross-sectional view showing a laminate module according to a sixth embodiment of the present invention.
  • a semiconductor module 1 and a laminated module 100 according to each embodiment of the present invention will be described below with reference to FIGS. 1 to 12.
  • FIG. First, outlines of the semiconductor module 1 and the laminated module 100 according to each embodiment will be described.
  • the semiconductor module 1 and the stacked module 100 are, for example, stacking a plurality of stacked memories.
  • the semiconductor module 1 and the stacked module 100 are configured by stacking a plurality of memory chips.
  • external wirings for electrically connecting the stacked memories are arranged in a direction crossing the stacking direction D of the stacked memories.
  • the semiconductor module 1 and the laminated module 100 bypass the communication of the laminated memory using external wiring (for example, the external electrodes 14). Accordingly, in the following embodiments, the semiconductor module 1 and the laminated module 100 are intended to be manufactured easily.
  • the laminated module 100 is obtained by laminating a plurality of semiconductor modules 1 .
  • FIG. A semiconductor module 1 includes a plurality of stacked memories, as shown in FIG.
  • the semiconductor module 1 includes a memory section 11 , a rewiring layer 12 , a mold section 13 , external electrodes 14 and solder balls 15 .
  • the memory units 11 are, as shown in FIGS. 2 and 3, a plurality of memory units 11 stacked in the stacking direction D, each having input/output terminals 31 and connection terminals 32 .
  • the memory unit 11 has a plurality of stacked memory chips. Specifically, the memory unit 11 has four stacked memory chips. Also, the memory unit 11 has a primary chip 110 and a secondary chip 120 . Note that the primary chip 110 and the secondary chip 120 are the same chip with partially changed functions. In this embodiment, the memory unit 11 has one primary chip 110 and three secondary chips 120 . Note that, in the present embodiment, the memory unit 11 arranged at one end in the stacking direction D is also described as a primary stack 21 .
  • the input/output terminal 31 is, for example, a terminal for inputting/outputting signals to/from the outside.
  • the input/output terminal 31 has, for example, a clock terminal 311 , a command terminal 312 and a data terminal 313 .
  • the clock terminal 311 receives, for example, a signal from the outside.
  • the clock terminal 311 receives an input of a clock signal provided from the outside, for example.
  • the command terminal 312 receives, for example, signals from the outside.
  • the command terminal 312 receives an input of a command signal provided from the outside, for example.
  • the data terminal 313 receives input/output of data with the outside, for example.
  • the data terminal 313 receives input/output of data signals with the outside, for example.
  • the connection terminal 32 is a terminal for connecting to another memory unit 11, for example.
  • the connection terminal 32 has a clock terminal 321 , a command terminal 322 , and a data terminal 323 like the input/output terminal 31 .
  • the connection terminal 32 is connected to the input/output terminal 31 via the buffer 41 as shown in FIG.
  • the primary chip 110 has input/output terminals 31 and connection terminals 32, as shown in FIGS.
  • one primary chip 110 is arranged at one end in the stacking direction D in the memory section 11 .
  • the primary chip 110 is connected to a secondary chip 120, which will be described later, by a bumpless TSV 200, for example.
  • the primary chip 110 has transfer terminals 121 for transferring clock signals, command signals, and data signals to other stacked memory chips.
  • the primary chip 110 has a timing control section 111 that adjusts operation timings of the primary chip 110 and a secondary chip 120, which will be described later.
  • the primary chip 110 has a timing controller 111 including memory cells (not shown) and memory control circuits (not shown).
  • the secondary chip 120 is stacked on the primary chip 110, for example. Secondary chip 120 is connected to primary chip 110 .
  • the secondary chip 120 has transfer terminals 121 for transferring clock signals, command signals, and data signals between the primary chip 110 or other secondary chips 120 adjacent in the stacking direction D.
  • FIG. In this embodiment, three secondary chips 120 are stacked within one memory unit 11 .
  • Each of the secondary chips 120 are connected to the primary chip 110 using bumpless TSVs 200 .
  • the secondary chip 120 has a memory controller 122 including memory cells (not shown) and memory control circuits (not shown).
  • the rewiring layer 12 is arranged between the memory sections 11 adjacent in the stacking direction D and on one surface of the memory section 11 on one end side in the stacking direction D.
  • the rewiring layer 12 is arranged adjacent to the primary chip 110 in the stacking direction D, for example.
  • the rewiring layer 12 is electrically connected to the input/output terminals 31 and the connection terminals 32 of the primary chip 110 .
  • the rewiring layer 12 has an end portion 42 that protrudes from the end face of the memory portion 11 in the direction intersecting the stacking direction D. As shown in FIG.
  • the rewiring layer 12 has, for example, end portions 42 arranged to protrude from both end faces of the memory portion 11 in a direction intersecting the stacking direction D, for example.
  • the molded part 13 is made of epoxy resin or the like, for example.
  • the mold part 13 is arranged between the end parts 42 of the adjacent rewiring layers 12 .
  • the mold part 13 is formed to have the same height as the memory part 11 in the stacking direction D, for example.
  • the external electrodes 14 are arranged between the rewiring layers 12 adjacent in the stacking direction D, and electrically connect the ends 42 of the rewiring layers 12 .
  • the external electrodes 14 are formed, for example, as mold through electrodes penetrating the mold portion 13, as shown in FIG.
  • the external electrodes 14 electrically connect adjacent rewiring layers 12 .
  • the external electrodes 14 are arranged across the memory section 11 in the direction intersecting the stacking direction D.
  • the number of external electrodes 14 corresponding to the number of circuits connecting the plurality of connection circuits 50 is provided.
  • one external electrode 14 is provided as one set of three in accordance with the clock signal, the command signal, and the input/output signal.
  • a connection circuit 50 for connecting the connection terminal 32 and the input/output terminal 31 of the other memory section 11 is formed.
  • the connection terminal 32 connects one memory unit 11 (primary stack 21 ) and the other three memory units 11 . That is, the connection circuit 50 connects the clock terminal 311, the command terminal 312, and the data terminal 313 of the connection terminal 32 of the primary stack 21, and the clock signals, command signals, and data signals of the input/output terminals 31 of all the other memory units 11. It is connected to the signal input/output terminal 31 .
  • connection circuit 50 bypass-connects the three memory units 11 to the primary stack 21 .
  • the connection circuit 50 aggregates the data signals input/output from the other three memory units 11 to the primary stack 21 according to the clock signal and command signal input to the primary stack 21 .
  • a plurality of solder balls 15 are arranged in contact with the rewiring layer 12 at one end in the stacking direction D, for example.
  • the solder balls 15 are arranged to electrically connect the semiconductor module 1 to another substrate (not shown) or the like.
  • the primary stack 21 (for example, the memory section 11 arranged at one end in the stacking direction D) is connected via the solder ball 15 and the rewiring layer 12 at one end in the stacking direction D connected to the solder ball 15 . ) are input with a clock signal, a command signal, and a data signal for writing.
  • the connection terminal 32 of the primary stack 21 outputs the clock signal, command signal, and data signal input to the input/output terminal 31 to the connection circuit 50 .
  • the output clock signal, command signal, and data signal are input to the input/output terminals 31 of the other memory section 11 via the external electrodes 14 and the rewiring layer 12 that constitute the connection circuit 50 .
  • the primary chip 110 of each memory unit 11 uses transfer terminals 121 to transfer clock signals, command signals, and data signals to the secondary chip 120 .
  • the primary chip 110 and secondary chip 120 access the memory areas of their respective chips in response to clock signals, command signals, and data signals.
  • the primary chip 110 and the secondary chip 120 write data to their respective memory areas based on clock signals, command signals, and data signals.
  • the primary stack 21 (for example, the memory section arranged at one end in the stacking direction D) is connected to the solder ball 15 and the rewiring layer 12 connected to the solder ball 15 at one end in the stacking direction D.
  • a clock signal and a command signal are input to the input/output terminal 31 of 11).
  • the connection terminal 32 of the primary stack 21 outputs the clock signal and command signal input to the input/output terminal 31 to the connection circuit 50 .
  • the output clock signal and command signal are input to the input/output terminal 31 of the other memory section 11 via the external electrode 14 and the rewiring layer 12 that constitute the connection circuit 50 .
  • the primary chip 110 of each memory unit 11 uses the transfer terminal 121 to transfer the clock signal and command signal to the secondary chip 120 .
  • the primary chip 110 and the secondary chip 120 access the memory area of each chip according to clock signals and command signals.
  • the primary chip 110 and secondary chip 120 read data from their respective memory areas based on the clock signal and command signal.
  • the secondary chip 120 transfers the data read using the transfer terminal 121 to the primary chip 110 as a data signal.
  • the primary chip 110 buffers its own read data and transferred data.
  • the primary chip 110 of the other memory unit 11 uses the input/output terminal 31 and the connection circuit 50 to transmit the buffered data signal to the connection terminal 32 of the primary stack 21 .
  • the primary chip 110 of the primary stack 21 receives its own buffered data and the data transmitted from the other memory unit 11 as data signals to the outside via the input/output terminal 31, the rewiring layer 12, and the solder balls 15. output to
  • a semiconductor module 1 including a plurality of stacked memories a plurality of memory sections 11 stacked in the stacking direction, each having an input/output terminal 31 for inputting/outputting a signal and a terminal for connecting to another memory section.
  • the memory section 11 having the connection terminal 32 and the memory sections 11 adjacent in the stacking direction are arranged between the memory sections 11 adjacent to each other in the stacking direction and on one surface of the memory section on one end side in the stacking direction, and the memory section is arranged in the direction crossing the stacking direction.
  • connection circuit 50 that connects the connection terminal 32 of one memory section 11 and the input/output terminal 31 of another memory section.
  • the memory unit 11 has a plurality of memory chips stacked using bumpless TSV200. As a result, the memory capacity can be easily increased while suppressing the height of the memory section 11 in the stacking direction and facilitating manufacturing.
  • the memory unit 11 has a primary chip 110 having input/output terminals 31 and connection terminals 32 and a secondary chip 120 connected to the primary chip 110 . Thereby, it is possible to easily control the plurality of stacked memory units 11 . Also, the circuit configuration can be simplified for a plurality of memory chips.
  • the primary chip 110 has a timing control section 111 that adjusts the operation timings of the primary chip 110 and secondary chip 120 . Thereby, it is possible to appropriately control the operation of a plurality of memory chips.
  • FIG. 1 a semiconductor module 1 according to a second embodiment of the invention will be described with reference to FIGS. 4 and 5.
  • FIG. In 2nd Embodiment the same code
  • the semiconductor module 1 according to the second embodiment differs from the first embodiment in that the data terminal 313 of the connection terminals 32 is not connected to the connection circuit 50, as shown in FIGS.
  • the data terminal 313 among the input/output terminals 31 of the plurality of memory units 11 includes the rewiring layer 12 adjacent to the primary chip 110, the external electrode 14, the rewiring layer 12 at one end in the stacking direction D, and the solder.
  • the data terminal 313 among the input/output terminals 31 of the plurality of memory units 11 is directly connected to the outside. Accordingly, the data terminal 313 of the connection terminals 32 of the primary stack 21 is not connected to the connection circuit 50 .
  • the semiconductor module 1 according to the first embodiment as described above has the following effects.
  • (4) The data terminals 313 among the input/output terminals 31 of the plurality of memory units 11 are connected to the outside via the adjacent rewiring layer 12, the external electrode 14, the rewiring layer 12 at one end in the stacking direction D, and the solder balls 15. connected to As a result, the data signal is directly communicated with the outside, so that the data transmission path can be shortened and the data quality can be improved. Also, by operating a plurality of memory units 11 simultaneously, the number of data signals can be increased and the bandwidth can be improved.
  • FIG. 1 differs from the first and second embodiments in that a plurality of primary stacks 21 and connection circuits 50 are provided as shown in FIGS.
  • the third embodiment differs from the first and second embodiments in that two sets of one primary stack 21, one other memory section 11, and a connection circuit 50 connecting the two are provided. That is, the semiconductor module 1 according to the third embodiment differs from the first and second embodiments in that two input/output terminals 31 of the primary stack 21 connected to the outside are provided.
  • the semiconductor module 1 according to the third embodiment as described above has the following effects. (5) A plurality of sets of one memory section 11, another memory section 11, and a connection circuit 50 connecting the two are provided. As a result, the input/output terminals 31 can be multi-channeled, so that the utilization efficiency of the semiconductor module 1 can be improved.
  • FIG. 8 and 9 a semiconductor module 1 according to a fourth embodiment of the invention will be described with reference to FIGS. 8 and 9.
  • FIG. 8 and 9 the same code
  • the semiconductor module 1 according to the fourth embodiment is different from the first in that one memory section 11 is connected in series with another memory section 11 using a connection circuit 50 . It differs from the third embodiment.
  • the semiconductor module 1 includes a connection circuit 50 that connects the connection terminal 32 of the primary stack 21 and the input/output terminal 31 of the other memory section 11, and It differs from the first to third embodiments in that it has a connection circuit 50 that connects the connection terminal 32 and the input/output terminal 31 of the other memory section 11 .
  • the semiconductor module 1 according to the fourth embodiment as described above has the following effects. (6) One memory section 11 is connected in series with another memory section 11 using the connection circuit 50 . As a result, the path of the connection circuit 50 can be shortened, so that the yield can be improved. In addition, since the parasitic resistance and parasitic capacitance of the connection circuit 50 can be kept substantially constant regardless of the number of stacked memory units 11, the number of stacked memory units 11 can be easily changed.
  • the semiconductor module 1 according to the fifth embodiment is different from the first to fourth embodiments in that it further includes a logic chip 130 arranged at the end portion 42 of the rewiring layer 12 . different.
  • a plurality of dummy silicon layers 132 are arranged over the logic chip 130 .
  • the plurality of memory units 11 are arranged in pairs with the logic chip 130 interposed therebetween.
  • the logic chip 130 also has a controller 131 that is connected to the memory section 11 and controls input/output of signals to/from the memory section 11 .
  • the semiconductor module 1 according to the fifth embodiment as described above has the following effects.
  • the semiconductor module 1 further includes a logic chip 130 arranged at the end portion 42 of the rewiring layer 12 . Thereby, the wiring distance between the memory unit 11 and the logic chip 130 can be shortened. Therefore, the semiconductor module 1 with high memory frequency (signal quality) and low data transfer power can be realized.
  • a stacked module 100 according to the sixth embodiment differs from the first to fifth embodiments in that a plurality of semiconductor modules 1 according to the first to fifth embodiments are stacked.
  • the stacked module 100 connects a plurality of semiconductor modules 1 using microbumps 16, for example, as shown in FIG.
  • the rewiring layer 12 is arranged on the surface of the other end side of the semiconductor module 1 on which the other semiconductor module 1 is stacked on the one end side in the stacking direction D.
  • Other semiconductor modules 1 are electrically connected using the arranged rewiring layers 12 and microbumps 16 .
  • the laminated module 100 is formed by laminating a plurality of the semiconductor modules 1 described above. As a result, the number of memory units 11 included in the semiconductor module 1 can be reduced, so that the yield of the semiconductor module 1 can be improved. Thereby, the yield of the laminated module 100 can also be improved. In addition, since the number of stages of the memory section 11 of the semiconductor module 1 can be reduced, assembly can be facilitated.
  • the present invention is not limited to the above-described embodiments and can be modified as appropriate.
  • the memory unit 11 includes a plurality of memory chips in the above embodiment, it may include one memory chip.
  • the primary chip 110 may be connected to the adjacent secondary chip 120 by hybrid bonding. Also, the primary chip 110 may be connected to the secondary chip 120 by contactless communication. As a result, the height of the memory section 11 in the stacking direction can be suppressed, so that the manufacturing of the semiconductor module 1 can be facilitated.
  • the number of primary stacks 21 and other memory units 11 is not limited to four. Also, the number of secondary chips 120 is not limited.

Abstract

The present invention provides a semiconductor module and stacked module that can be manufactured more easily. A semiconductor module 1 having a plurality of stacked memories comprises: a plurality of memory units 11 that are stacked in a stacking direction D, and each have an input/output terminal 31 for inputting/outputting a signal and a connection terminal 32 for connecting to another memory unit 11; redistribution layers 12 that are each placed between memory units 11 adjacent to each other in the stacking direction D and on one surface of the memory unit 11 on one stacking direction D side, and each have an edge portion 42 protruding more than the edge surface of the memory unit 11 in a direction intersecting with the stacking direction D; and external electrodes 14 that are each placed between redistribution layers 12 adjacent to each other in the stacking direction D and electrically connect the edge portions 42 of the redistribution layers 12. The redistribution layer 12 and the external electrode 14 form a connection circuit 50 for connecting the connection terminal 32 of one memory unit 11 to the input/output terminal 31 of another memory unit 11.

Description

半導体モジュール及び積層モジュールSemiconductor modules and laminated modules
　本発明は、半導体モジュール及び積層モジュールに関する。 The present invention relates to semiconductor modules and laminated modules.
　従来より、記憶装置としてＤＲＡＭ（Dynamic Random Access Memory）等の揮発性メモリ（ＲＡＭ）が知られている。ＤＲＡＭには、演算装置（以下、論理チップあるいはロジックチップという）の高性能化やデータ量の増大に耐えうる大容量化が求められている。そこで、メモリ（メモリセルアレイ、メモリチップ）の微細化及びセルの平面的な増設による大容量化が図られてきた。一方で、微細化によるノイズへの惰弱性や、チップ面積の増加等により、この種の大容量化は限界に達してきている。 Conventionally, volatile memories (RAM) such as DRAM (Dynamic Random Access Memory) have been known as storage devices. DRAMs are required to have a large capacity capable of withstanding higher performance of arithmetic units (hereinafter referred to as logic chips or logic chips) and an increase in the amount of data. Therefore, attempts have been made to increase the capacity by miniaturizing the memory (memory cell array, memory chip) and increasing the number of cells in a plane. On the other hand, this type of increase in capacity has reached its limit due to the vulnerability to noise due to miniaturization, the increase in chip area, and the like.
　そこで、昨今では、平面的なメモリを複数積層して３次元化（３Ｄ化）して大容量化を実現する技術が開発されている。また、データ量の増大に伴い、チップ（ロジックチップ及びメモリチップ）間のデータ通信の高速化が図られている（例えば、特許文献１及び２参照）。 Therefore, in recent years, technology has been developed to realize large capacity by stacking multiple planar memories to make them three-dimensional (3D). In addition, as the amount of data increases, efforts are being made to speed up data communication between chips (logic chips and memory chips) (see Patent Documents 1 and 2, for example).
特表２０１３－５３６９８５号公報Japanese Patent Application Publication No. 2013-536985 特開２００５－１９１１７２号公報JP 2005-191172 A
　特許文献１の記憶装置では、コマンドダイと、メモリダイとが積層される。特許文献１では、コマンドダイとメモリダイとがＴＳＶ（Ｔｈｒｏｕｇｈ　Ｓｉｌｉｃｏｎ　Ｖｉａ）により接続される。特許文献１では、メモリダイの積層数が増加すると、ＴＳＶの段数が増加するので、歩留まりが低下することが考えられる。また、特許文献１では、ダイの間をバイパスするＴＳＶを複数設ける場合、ダイサイズの増加及び製造コストの増加が考えられる。さらには、特許文献１において、記憶装置のバリエーションを増やす場合にも、ＴＳＶの位置変更等が必要であるので、ダイサイズの増加及び製造コストの増加が考えられる。 In the storage device of Patent Document 1, a command die and a memory die are stacked. In Patent Document 1, a command die and a memory die are connected by a TSV (Through Silicon Via). In Patent Document 1, as the number of stacked memory dies increases, the number of stages of TSVs increases, so it is conceivable that the yield will decrease. Further, in Patent Document 1, when a plurality of TSVs bypassing between dies are provided, an increase in die size and an increase in manufacturing cost can be considered. Furthermore, in Japanese Patent Laid-Open No. 2002-100001, even when the variation of the storage device is increased, it is necessary to change the positions of the TSVs, etc., so that the die size and the manufacturing cost may increase.
　特許文献２のメモリシステムでは、複数のＤＲＡＭ積層体をマザーボード上に搭載している。特許文献２では、ＤＲＡＭ積層体がマザーボードの面内方向に配置されるので、配置面積が大きくなることが考えられる。 In the memory system of Patent Document 2, multiple DRAM stacks are mounted on the motherboard. In Japanese Patent Laid-Open No. 2002-200021, the DRAM stack is arranged in the in-plane direction of the mother board, so it is conceivable that the layout area becomes large.
　本発明は、上記のような課題に鑑みてなされたものであり、製造を容易にすることが可能な半導体モジュール及び積層モジュールを提供することを目的とする。 The present invention has been made in view of the above problems, and aims to provide a semiconductor module and a laminated module that can be manufactured easily.
　本発明は、複数の積層メモリを含む半導体モジュールにおいて、積層方向に積層される複数のメモリ部であって、それぞれが信号を入出力する入出力端子と他のメモリ部と接続するための接続端子とを有するメモリ部と、積層方向において隣接する前記メモリ部の間と積層方向一端側の前記メモリ部の一面上とに配置され、積層方向に交差する方向において前記メモリ部の端面よりも突出する端部を有する再配線層と、積層方向において隣接する前記再配線層の間に配置され、前記再配線層の端部を電気的に接続する外部電極と、を備え、前記再配線層及び前記外部電極は、１つの前記メモリ部の前記接続端子と他の前記メモリ部の前記入出力端子とを接続する接続回路を形成する半導体モジュールに関する。 In a semiconductor module including a plurality of stacked memories, the present invention includes a plurality of memory sections stacked in a stacking direction, each having input/output terminals for inputting and outputting signals and connection terminals for connecting to other memory sections. are arranged between the memory units adjacent in the stacking direction and on one surface of the memory unit on one end side in the stacking direction, and protrude beyond the end face of the memory unit in a direction crossing the stacking direction. a rewiring layer having an edge; and an external electrode disposed between the rewiring layers adjacent in the stacking direction and electrically connecting the edge of the rewiring layer, wherein the rewiring layer and the The external electrode relates to a semiconductor module forming a connection circuit connecting the connection terminal of one memory section and the input/output terminal of another memory section.
　また、前記メモリ部は、積層された複数のメモリチップを有するのが好ましい。 Also, the memory section preferably has a plurality of stacked memory chips.
　また、前記メモリ部は、前記入出力端子及び前記接続端子を有するプライマリチップと、前記プライマリチップに接続されるセカンダリチップと、を有するのが好ましい。 The memory section preferably has a primary chip having the input/output terminals and the connection terminals, and a secondary chip connected to the primary chip.
　また、前記プライマリチップは、前記プライマリチップ及び前記セカンダリチップの動作タイミングを調整するタイミング制御部を有するのが好ましい。 Also, the primary chip preferably has a timing control section that adjusts operation timings of the primary chip and the secondary chip.
　また、前記プライマリチップと前記セカンダリチップとは同一チップの一部機能を変更したものであることが好ましい。 Further, it is preferable that the primary chip and the secondary chip are the same chip with partially changed functions.
　また、前記プライマリチップは、前記セカンダリチップとバンプレスＴＳＶにより接続されるのが好ましい。 Also, the primary chip is preferably connected to the secondary chip by a bumpless TSV.
　前記プライマリチップは、隣接する前記セカンダリチップとハイブリッドボンディングにより接続されるのが好ましい。 The primary chip is preferably connected to the adjacent secondary chip by hybrid bonding.
　また、前記プライマリチップは、前記セカンダリチップと非接触通信により接続されるのが好ましい。 Also, the primary chip is preferably connected to the secondary chip by contactless communication.
　また、前記接続回路は、１つの前記メモリ部のクロック信号及びコマンド信号の前記接続端子と、他の前記メモリ部の前記クロック信号及び前記コマンド信号の前記入出力端子とを接続するのが好ましい。 Also, it is preferable that the connection circuit connects the connection terminal for the clock signal and the command signal of one of the memory sections and the input/output terminal for the clock signal and the command signal of the other memory section.
　また、半導体モジュールは、前記再配線層の端部に配置されるロジックチップをさらに備えるのが好ましい。 Also, the semiconductor module preferably further comprises a logic chip arranged at the end of the rewiring layer.
　また、本発明は、上記の半導体モジュールを複数積層した積層モジュールに関する。 The present invention also relates to a laminated module in which a plurality of the above semiconductor modules are laminated.
　本発明によれば、製造を容易にすることが可能な半導体モジュール及び積層モジュールを提供することができる。 According to the present invention, it is possible to provide a semiconductor module and a laminated module that can be manufactured easily.
本発明の第１実施形態に係る半導体モジュールを示す断面図である。1 is a cross-sectional view showing a semiconductor module according to a first embodiment of the invention; FIG. 第１実施形態の半導体モジュールを示すブロック図である。1 is a block diagram showing a semiconductor module of a first embodiment; FIG. 第１実施形態の半導体モジュールを示す回路図である。1 is a circuit diagram showing a semiconductor module of a first embodiment; FIG. 本発明の第２実施形態に係る半導体モジュールを示すブロック図である。It is a block diagram showing a semiconductor module according to a second embodiment of the present invention. 第２実施形態の半導体モジュールを示す回路図である。It is a circuit diagram showing a semiconductor module of a second embodiment. 本発明の第３実施形態に係る半導体モジュールを示すブロック図である。It is a block diagram showing a semiconductor module according to a third embodiment of the present invention. 第３実施形態の半導体モジュールを示す回路図である。It is a circuit diagram which shows the semiconductor module of 3rd Embodiment. 本発明の第４実施形態に係る半導体モジュールを示すブロック図である。It is a block diagram showing a semiconductor module according to a fourth embodiment of the present invention. 第４実施形態の半導体モジュールを示す回路図である。It is a circuit diagram which shows the semiconductor module of 4th Embodiment. 本発明の第５実施形態に係る半導体モジュールを示す平面図である。It is a top view which shows the semiconductor module based on 5th Embodiment of this invention. 図１０のＡ－Ａ線断面図である。FIG. 11 is a cross-sectional view taken along line AA of FIG. 10; 本発明の第６実施形態に係る積層モジュールを示す断面図である。FIG. 11 is a cross-sectional view showing a laminate module according to a sixth embodiment of the present invention;
　以下、本発明の各実施形態に係る半導体モジュール１及び積層モジュール１００について、図１から図１２を参照して説明する。
　まず、各実施形態に係る半導体モジュール１及び積層モジュール１００の概要について説明する。 A semiconductor module 1 and a laminated module 100 according to each embodiment of the present invention will be described below with reference to FIGS. 1 to 12. FIG.
First, outlines of the semiconductor module 1 and the laminated module 100 according to each embodiment will be described.
　各実施形態に係る半導体モジュール１及び積層モジュール１００は、例えば、複数の積層メモリを積層したものである。具体的には、半導体モジュール１及び積層モジュール１００は、複数のメモリチップを積層して構成される。また、半導体モジュール１及び積層モジュール１００は、積層メモリの積層方向Ｄに交差する方向において、積層メモリを電気的に接続する外部配線が配置される。半導体モジュール１及び積層モジュール１００は、外部配線（例えば、外部電極１４）を用いて積層メモリの通信をバイパスする。これにより、以下の実施形態では、半導体モジュール１及び積層モジュール１００の製造を容易にすることを図ったものである。なお、積層モジュール１００は、半導体モジュール１を複数積層したものである。 The semiconductor module 1 and the stacked module 100 according to each embodiment are, for example, stacking a plurality of stacked memories. Specifically, the semiconductor module 1 and the stacked module 100 are configured by stacking a plurality of memory chips. Also, in the semiconductor module 1 and the stacked module 100, external wirings for electrically connecting the stacked memories are arranged in a direction crossing the stacking direction D of the stacked memories. The semiconductor module 1 and the laminated module 100 bypass the communication of the laminated memory using external wiring (for example, the external electrodes 14). Accordingly, in the following embodiments, the semiconductor module 1 and the laminated module 100 are intended to be manufactured easily. Note that the laminated module 100 is obtained by laminating a plurality of semiconductor modules 1 .
［第１実施形態］
　次に、本発明の第１実施形態に係る半導体モジュール１及び積層モジュール１００について、図１から図３を参照して説明する。
　半導体モジュール１は、図１に示すように、複数の積層メモリを含む。半導体モジュール１は、メモリ部１１と、再配線層１２と、モールド部１３と、外部電極１４と、半田ボール１５と、を備える。 [First embodiment]
Next, a semiconductor module 1 and a laminated module 100 according to a first embodiment of the invention will be described with reference to FIGS. 1 to 3. FIG.
A semiconductor module 1 includes a plurality of stacked memories, as shown in FIG. The semiconductor module 1 includes a memory section 11 , a rewiring layer 12 , a mold section 13 , external electrodes 14 and solder balls 15 .
　メモリ部１１は、図２及び図３に示すように、積層方向Ｄに積層される複数のメモリ部１１であって、それぞれが入出力端子３１と接続端子３２とを有する。本実施形態において、メモリ部１１は、積層された複数のメモリチップを有する。具体的には、メモリ部１１は、積層された４つのメモリチップを有する。また、メモリ部１１は、プライマリチップ１１０と、セカンダリチップ１２０と、を有する。なお、プライマリチップ１１０及びセカンダリチップ１２０は、同一チップの一部機能を変更したものである。本実施形態において、メモリ部１１は、１つのプライマリチップ１１０と、３つのセカンダリチップ１２０とを備える。なお、本実施形態において、積層方向Ｄ一端に配置されるメモリ部１１は、プライマリスタック２１とも記載される。 The memory units 11 are, as shown in FIGS. 2 and 3, a plurality of memory units 11 stacked in the stacking direction D, each having input/output terminals 31 and connection terminals 32 . In this embodiment, the memory unit 11 has a plurality of stacked memory chips. Specifically, the memory unit 11 has four stacked memory chips. Also, the memory unit 11 has a primary chip 110 and a secondary chip 120 . Note that the primary chip 110 and the secondary chip 120 are the same chip with partially changed functions. In this embodiment, the memory unit 11 has one primary chip 110 and three secondary chips 120 . Note that, in the present embodiment, the memory unit 11 arranged at one end in the stacking direction D is also described as a primary stack 21 .
　入出力端子３１は、例えば、外部に信号を入出力する端子である。入出力端子３１は、例えば、クロック端子３１１と、コマンド端子３１２と、データ端子３１３と、を有する。 The input/output terminal 31 is, for example, a terminal for inputting/outputting signals to/from the outside. The input/output terminal 31 has, for example, a clock terminal 311 , a command terminal 312 and a data terminal 313 .
　クロック端子３１１は、例えば、外部からの信号を受け付ける。クロック端子３１１は、例えば、外部から提供されるクロック信号の入力を受け付ける。 The clock terminal 311 receives, for example, a signal from the outside. The clock terminal 311 receives an input of a clock signal provided from the outside, for example.
　コマンド端子３１２は、例えば、外部からの信号を受け付ける。コマンド端子３１２は、例えば、外部から提供されるコマンド信号の入力を受け付ける。 The command terminal 312 receives, for example, signals from the outside. The command terminal 312 receives an input of a command signal provided from the outside, for example.
　データ端子３１３は、例えば、外部との間でデータの入出力を受け付ける。データ端子３１３は、例えば外部との間でのデータ信号の入出力を受け付ける。 The data terminal 313 receives input/output of data with the outside, for example. The data terminal 313 receives input/output of data signals with the outside, for example.
　接続端子３２は、例えば、他のメモリ部１１と接続するための端子である。接続端子３２は、入出力端子３１と同様に、クロック端子３２１と、コマンド端子３２２と、データ端子３２３と、を有する。接続端子３２は、図３に示すように、バッファ４１を介して入出力端子３１と接続される。 The connection terminal 32 is a terminal for connecting to another memory unit 11, for example. The connection terminal 32 has a clock terminal 321 , a command terminal 322 , and a data terminal 323 like the input/output terminal 31 . The connection terminal 32 is connected to the input/output terminal 31 via the buffer 41 as shown in FIG.
　プライマリチップ１１０は、図２及び図３に示すように、入出力端子３１及び接続端子３２を有する。プライマリチップ１１０は、例えば、メモリ部１１内において、積層方向Ｄ一端に１つ配置される。また、プライマリチップ１１０は、例えば、後述するセカンダリチップ１２０とバンプレスＴＳＶ２００により接続される。プライマリチップ１１０は、積層される他のメモリチップにクロック信号、コマンド信号、及びデータ信号を転送するための転送端子１２１を有する。さらには、プライマリチップ１１０は、プライマリチップ１１０及び後述するセカンダリチップ１２０の動作タイミングを調整するタイミング制御部１１１を有する。本実施形態において、プライマリチップ１１０は、メモリセル（図示せず）及びメモリ制御回路（図示せず）を含むタイミング制御部１１１を有する。 The primary chip 110 has input/output terminals 31 and connection terminals 32, as shown in FIGS. For example, one primary chip 110 is arranged at one end in the stacking direction D in the memory section 11 . Also, the primary chip 110 is connected to a secondary chip 120, which will be described later, by a bumpless TSV 200, for example. The primary chip 110 has transfer terminals 121 for transferring clock signals, command signals, and data signals to other stacked memory chips. Further, the primary chip 110 has a timing control section 111 that adjusts operation timings of the primary chip 110 and a secondary chip 120, which will be described later. In this embodiment, the primary chip 110 has a timing controller 111 including memory cells (not shown) and memory control circuits (not shown).
　セカンダリチップ１２０は、例えば、プライマリチップ１１０に積層される。セカンダリチップ１２０は、プライマリチップ１１０に接続される。セカンダリチップ１２０は、積層方向Ｄで隣接するプライマリチップ１１０又は他のセカンダリチップ１２０との間でクロック信号、コマンド信号、及びデータ信号を転送する転送端子１２１を有する。本実施形態において、セカンダリチップ１２０は、１つのメモリ部１１内に３つ積層される。セカンダリチップ１２０のそれぞれは、バンプレスＴＳＶ２００を用いてプライマリチップ１１０に接続される。本実施形態において、セカンダリチップ１２０は、メモリセル（図示せず）及びメモリ制御回路（図示せず）を含むメモリ制御部１２２を有する。 The secondary chip 120 is stacked on the primary chip 110, for example. Secondary chip 120 is connected to primary chip 110 . The secondary chip 120 has transfer terminals 121 for transferring clock signals, command signals, and data signals between the primary chip 110 or other secondary chips 120 adjacent in the stacking direction D. FIG. In this embodiment, three secondary chips 120 are stacked within one memory unit 11 . Each of the secondary chips 120 are connected to the primary chip 110 using bumpless TSVs 200 . In this embodiment, the secondary chip 120 has a memory controller 122 including memory cells (not shown) and memory control circuits (not shown).
　再配線層１２は、積層方向Ｄにおいて隣接するメモリ部１１の間と積層方向Ｄ一端側のメモリ部１１の一面上とに配置される。再配線層１２は、例えば、積層方向Ｄにおいて、プライマリチップ１１０に隣接して配置される。また、再配線層１２は、プライマリチップ１１０の入出力端子３１及び接続端子３２と電気的に接続される。再配線層１２は、積層方向Ｄに交差する方向においてメモリ部１１の端面よりも突出する端部４２を有する。再配線層１２は、例えば、積層方向Ｄに交差する方向において、メモリ部１１の両端面のそれぞれよりも突出して配置される端部４２を有する。 The rewiring layer 12 is arranged between the memory sections 11 adjacent in the stacking direction D and on one surface of the memory section 11 on one end side in the stacking direction D. The rewiring layer 12 is arranged adjacent to the primary chip 110 in the stacking direction D, for example. Also, the rewiring layer 12 is electrically connected to the input/output terminals 31 and the connection terminals 32 of the primary chip 110 . The rewiring layer 12 has an end portion 42 that protrudes from the end face of the memory portion 11 in the direction intersecting the stacking direction D. As shown in FIG. The rewiring layer 12 has, for example, end portions 42 arranged to protrude from both end faces of the memory portion 11 in a direction intersecting the stacking direction D, for example.
　モールド部１３は、例えば、エポキシ樹脂等により形成される。モールド部１３は、隣接する再配線層１２の端部４２間に配置される。モールド部１３は、例えば、積層方向Ｄにおけるメモリ部１１の高さと同じ高さで形成される。 The molded part 13 is made of epoxy resin or the like, for example. The mold part 13 is arranged between the end parts 42 of the adjacent rewiring layers 12 . The mold part 13 is formed to have the same height as the memory part 11 in the stacking direction D, for example.
　外部電極１４は、積層方向Ｄにおいて隣接する再配線層１２の間に配置され、再配線層１２の端部４２を電気的に接続する。外部電極１４は、例えば、図１に示すように、モールド部１３を貫通するモールド貫通電極として形成される。外部電極１４は、隣接する再配線層１２を電気的に接続する。本実施形態において、外部電極１４は、積層方向Ｄに交差する方向において、メモリ部１１を挟んで配置される。また、外部電極１４は、複数の接続回路５０を接続する回路数に応じた数だけ設けられる。また、本実施形態において、１つの外部電極１４は、クロック信号、コマンド信号、及び入出力信号に合わせて３つを１セットとして設けられる。 The external electrodes 14 are arranged between the rewiring layers 12 adjacent in the stacking direction D, and electrically connect the ends 42 of the rewiring layers 12 . The external electrodes 14 are formed, for example, as mold through electrodes penetrating the mold portion 13, as shown in FIG. The external electrodes 14 electrically connect adjacent rewiring layers 12 . In this embodiment, the external electrodes 14 are arranged across the memory section 11 in the direction intersecting the stacking direction D. As shown in FIG. Also, the number of external electrodes 14 corresponding to the number of circuits connecting the plurality of connection circuits 50 is provided. Also, in this embodiment, one external electrode 14 is provided as one set of three in accordance with the clock signal, the command signal, and the input/output signal.
　以上の接続端子３２、入出力端子３１、再配線層１２、及び外部電極１４によれば、図２及び図３に示すように、再配線層１２及び外部電極１４は、１つのメモリ部１１の接続端子３２と他のメモリ部１１の入出力端子３１とを接続する接続回路５０を形成する。本実施形態において、接続端子３２は、１つのメモリ部１１（プライマリスタック２１）と、他の３つのメモリ部１１とを接続する。すなわち、接続回路５０は、プライマリスタック２１の接続端子３２のクロック端子３１１、コマンド端子３１２、及びデータ端子３１３と、他の全てのメモリ部１１の入出力端子３１のクロック信号、コマンド信号、及びデータ信号の入出力端子３１とを接続する。これにより、接続回路５０は、プライマリスタック２１に対して３つのメモリ部１１をバイパス接続する。接続回路５０は、プライマリスタック２１に入力されたクロック信号及びコマンド信号に応じて、他の３つのメモリ部１１から入出力されたデータ信号をプライマリスタック２１に集約する。 According to the connection terminals 32, the input/output terminals 31, the rewiring layer 12, and the external electrodes 14 described above, the rewiring layer 12 and the external electrodes 14 form one memory section 11 as shown in FIGS. A connection circuit 50 for connecting the connection terminal 32 and the input/output terminal 31 of the other memory section 11 is formed. In this embodiment, the connection terminal 32 connects one memory unit 11 (primary stack 21 ) and the other three memory units 11 . That is, the connection circuit 50 connects the clock terminal 311, the command terminal 312, and the data terminal 313 of the connection terminal 32 of the primary stack 21, and the clock signals, command signals, and data signals of the input/output terminals 31 of all the other memory units 11. It is connected to the signal input/output terminal 31 . As a result, the connection circuit 50 bypass-connects the three memory units 11 to the primary stack 21 . The connection circuit 50 aggregates the data signals input/output from the other three memory units 11 to the primary stack 21 according to the clock signal and command signal input to the primary stack 21 .
　半田ボール１５は、例えば、積層方向Ｄ一端の再配線層１２に接触して複数配置される。半田ボール１５は、他の基板（図示しない）等に半導体モジュール１を電気的に接続するために配置される A plurality of solder balls 15 are arranged in contact with the rewiring layer 12 at one end in the stacking direction D, for example. The solder balls 15 are arranged to electrically connect the semiconductor module 1 to another substrate (not shown) or the like.
　次に、半導体モジュール１の動作について説明する。
　まず、メモリ領域にデータ書き込む場合、半田ボール１５と、半田ボール１５に接続する積層方向Ｄ一端の再配線層１２を介して、プライマリスタック２１（例えば、積層方向Ｄ一端に配置されるメモリ部１１）の入出力端子３１にクロック信号、コマンド信号、及び書き込み用のデータ信号が入力される。プライマリスタック２１の接続端子３２は、入出力端子３１に入力されたクロック信号、コマンド信号、及びデータ信号を接続回路５０に出力する。出力されたクロック信号、コマンド信号、及びデータ信号は、接続回路５０を構成する外部電極１４及び再配線層１２を介して、他のメモリ部１１の入出力端子３１に入力される。 Next, operation of the semiconductor module 1 will be described.
First, when writing data to the memory area, the primary stack 21 (for example, the memory section 11 arranged at one end in the stacking direction D) is connected via the solder ball 15 and the rewiring layer 12 at one end in the stacking direction D connected to the solder ball 15 . ) are input with a clock signal, a command signal, and a data signal for writing. The connection terminal 32 of the primary stack 21 outputs the clock signal, command signal, and data signal input to the input/output terminal 31 to the connection circuit 50 . The output clock signal, command signal, and data signal are input to the input/output terminals 31 of the other memory section 11 via the external electrodes 14 and the rewiring layer 12 that constitute the connection circuit 50 .
　各メモリ部１１のプライマリチップ１１０は、転送端子１２１を用いて、クロック信号、コマンド信号、及びデータ信号をセカンダリチップ１２０に転送する。プライマリチップ１１０及びセカンダリチップ１２０は、クロック信号、コマンド信号、及びデータ信号に応じて、それぞれのチップのメモリ領域にアクセスする。プライマリチップ１１０及びセカンダリチップ１２０は、クロック信号、コマンド信号、及びデータ信号に基づいて、それぞれのメモリ領域にデータを書き込む。 The primary chip 110 of each memory unit 11 uses transfer terminals 121 to transfer clock signals, command signals, and data signals to the secondary chip 120 . The primary chip 110 and secondary chip 120 access the memory areas of their respective chips in response to clock signals, command signals, and data signals. The primary chip 110 and the secondary chip 120 write data to their respective memory areas based on clock signals, command signals, and data signals.
　また、メモリ領域からデータを読み出す場合、半田ボール１５と、半田ボール１５に接続する積層方向Ｄ一端の再配線層１２を介して、プライマリスタック２１（例えば、積層方向Ｄ一端に配置されるメモリ部１１）の入出力端子３１にクロック信号及びコマンド信号が入力される。プライマリスタック２１の接続端子３２は、入出力端子３１に入力されたクロック信号及びコマンド信号を接続回路５０に出力する。出力されたクロック信号及びコマンド信号は、接続回路５０を構成する外部電極１４及び再配線層１２を介して、他のメモリ部１１の入出力端子３１に入力される。 When data is read from the memory area, the primary stack 21 (for example, the memory section arranged at one end in the stacking direction D) is connected to the solder ball 15 and the rewiring layer 12 connected to the solder ball 15 at one end in the stacking direction D. A clock signal and a command signal are input to the input/output terminal 31 of 11). The connection terminal 32 of the primary stack 21 outputs the clock signal and command signal input to the input/output terminal 31 to the connection circuit 50 . The output clock signal and command signal are input to the input/output terminal 31 of the other memory section 11 via the external electrode 14 and the rewiring layer 12 that constitute the connection circuit 50 .
　各メモリ部１１のプライマリチップ１１０は、転送端子１２１を用いて、クロック信号及びコマンド信号をセカンダリチップ１２０に転送する。プライマリチップ１１０及びセカンダリチップ１２０は、クロック信号及びコマンド信号に応じて、それぞれのチップのメモリ領域にアクセスする。プライマリチップ１１０及びセカンダリチップ１２０は、クロック信号及びコマンド信号に基づいて、それぞれのメモリ領域からデータを読み出す。セカンダリチップ１２０は、転送端子１２１を用いて読み出したデータをデータ信号としてプライマリチップ１１０に転送する。プライマリチップ１１０は、自身の読み出したデータと、転送されたデータとをバッファリングする。 The primary chip 110 of each memory unit 11 uses the transfer terminal 121 to transfer the clock signal and command signal to the secondary chip 120 . The primary chip 110 and the secondary chip 120 access the memory area of each chip according to clock signals and command signals. The primary chip 110 and secondary chip 120 read data from their respective memory areas based on the clock signal and command signal. The secondary chip 120 transfers the data read using the transfer terminal 121 to the primary chip 110 as a data signal. The primary chip 110 buffers its own read data and transferred data.
　他のメモリ部１１のプライマリチップ１１０は、入出力端子３１と接続回路５０とを用いて、バッファリングしたデータ信号をプライマリスタック２１の接続端子３２に送信する。プライマリスタック２１のプライマリチップ１１０は、自身のバッファリングしたデータと、他のメモリ部１１から送信されたデータとをデータ信号として入出力端子３１、再配線層１２、及び半田ボール１５を介して外部に出力する。 The primary chip 110 of the other memory unit 11 uses the input/output terminal 31 and the connection circuit 50 to transmit the buffered data signal to the connection terminal 32 of the primary stack 21 . The primary chip 110 of the primary stack 21 receives its own buffered data and the data transmitted from the other memory unit 11 as data signals to the outside via the input/output terminal 31, the rewiring layer 12, and the solder balls 15. output to
　以上のような第１実施形態に係る半導体モジュール１及び積層モジュール１００によれば、以下の効果を奏する。
（１）複数の積層メモリを含む半導体モジュール１において、積層方向に積層される複数のメモリ部１１であって、それぞれが信号を入出力する入出力端子３１と他のメモリ部と接続するための接続端子３２とを有するメモリ部１１と、積層方向において隣接する前記メモリ部１１の間と積層方向一端側の前記メモリ部の一面上とに配置され、前記積層方向に交差する方向において前記メモリ部１１の端面よりも突出する端部を有する再配線層１２と、積層方向において隣接する前記再配線層１２の間に配置され、前記再配線層１２の端部を電気的に接続する外部電極１４と、を備え、前記再配線層１２及び前記外部電極１４は、１つの前記メモリ部１１の前記接続端子３２と他の前記メモリ部の前記入出力端子３１とを接続する接続回路５０を形成する。これにより、製造を容易にすることが可能な半導体モジュール１及び積層モジュール１００を提供することができる。また、メモリ部１１とは別に外部配線を設けることにより、メモリ部１１内に配線を形成する必要が無いので、歩留まりを向上することができる。また、外部配線の形成を変更することにより、半導体モジュール１のバリエーションを容易に増やすことができる。また、プライマリチップ１１０及びセカンダリチップ１２０は、同一チップの一部機能を変更したものであるので、例えばヒューズ素子等を用いて変更することで製造を容易にすることができる。 According to the semiconductor module 1 and the laminated module 100 according to the first embodiment as described above, the following effects are obtained.
(1) In a semiconductor module 1 including a plurality of stacked memories, a plurality of memory sections 11 stacked in the stacking direction, each having an input/output terminal 31 for inputting/outputting a signal and a terminal for connecting to another memory section. The memory section 11 having the connection terminal 32 and the memory sections 11 adjacent in the stacking direction are arranged between the memory sections 11 adjacent to each other in the stacking direction and on one surface of the memory section on one end side in the stacking direction, and the memory section is arranged in the direction crossing the stacking direction. 11 and an external electrode 14 disposed between the rewiring layers 12 adjacent in the stacking direction and electrically connecting the ends of the rewiring layers 12. and the rewiring layer 12 and the external electrode 14 form a connection circuit 50 that connects the connection terminal 32 of one memory section 11 and the input/output terminal 31 of another memory section. . Accordingly, it is possible to provide the semiconductor module 1 and the laminated module 100 that can be manufactured easily. Further, by providing the external wiring separately from the memory section 11, it is not necessary to form the wiring in the memory section 11, so that the yield can be improved. Also, by changing the formation of the external wiring, the variations of the semiconductor module 1 can be easily increased. In addition, since the primary chip 110 and the secondary chip 120 are the same chip with partially changed functions, manufacturing can be facilitated by changing the functions using, for example, fuse elements.
（２）メモリ部１１は、バンプレスＴＳＶ２００を用いて積層された複数のメモリチップを有する。これにより、メモリ部１１の積層方向の高さを抑えて製造を容易にしつつ、メモリ容量を容易に増やすことができる。 (2) The memory unit 11 has a plurality of memory chips stacked using bumpless TSV200. As a result, the memory capacity can be easily increased while suppressing the height of the memory section 11 in the stacking direction and facilitating manufacturing.
（３）メモリ部１１は、入出力端子３１及び接続端子３２を有するプライマリチップ１１０と、プライマリチップ１１０に接続されるセカンダリチップ１２０と、を有する。これにより、複数の積層されたメモリ部１１の制御を容易にすることができる。また、複数のメモリチップに対して、回路構成を単純化することができる。 (3) The memory unit 11 has a primary chip 110 having input/output terminals 31 and connection terminals 32 and a secondary chip 120 connected to the primary chip 110 . Thereby, it is possible to easily control the plurality of stacked memory units 11 . Also, the circuit configuration can be simplified for a plurality of memory chips.
（４）プライマリチップ１１０は、プライマリチップ１１０及びセカンダリチップ１２０の動作タイミングを調整するタイミング制御部１１１を有する。これにより、複数のメモリチップに対して適切に動作を制御することができる。 (4) The primary chip 110 has a timing control section 111 that adjusts the operation timings of the primary chip 110 and secondary chip 120 . Thereby, it is possible to appropriately control the operation of a plurality of memory chips.
［第２実施形態］
　次に、本発明の第２実施形態に係る半導体モジュール１について、図４及び図５を参照して説明する。第２実施形態において、同一構成について同一の符号を付し、説明を簡略化又は省略する。
　第２実施形態に係る半導体モジュール１は、図４及び図６に示すように、接続端子３２のうち、データ端子３１３が接続回路５０に接続されていない点で、第１実施形態と異なる。具体的には、複数のメモリ部１１の入出力端子３１のうちのデータ端子３１３は、プライマリチップ１１０に隣接する再配線層１２、外部電極１４、積層方向Ｄ一端の再配線層１２、及び半田ボール１５を介して外部に接続される。すなわち、複数のメモリ部１１の入出力端子３１のうちのデータ端子３１３は、直接外部に接続される。これに伴い、プライマリスタック２１の接続端子３２のうち、データ端子３１３は、接続回路５０に接続されない。 [Second embodiment]
Next, a semiconductor module 1 according to a second embodiment of the invention will be described with reference to FIGS. 4 and 5. FIG. In 2nd Embodiment, the same code|symbol is attached|subjected about the same structure, and description is simplified or abbreviate|omitted.
The semiconductor module 1 according to the second embodiment differs from the first embodiment in that the data terminal 313 of the connection terminals 32 is not connected to the connection circuit 50, as shown in FIGS. Specifically, the data terminal 313 among the input/output terminals 31 of the plurality of memory units 11 includes the rewiring layer 12 adjacent to the primary chip 110, the external electrode 14, the rewiring layer 12 at one end in the stacking direction D, and the solder. It is connected to the outside through the ball 15 . That is, the data terminal 313 among the input/output terminals 31 of the plurality of memory units 11 is directly connected to the outside. Accordingly, the data terminal 313 of the connection terminals 32 of the primary stack 21 is not connected to the connection circuit 50 .
　以上のような第１実施形態に係る半導体モジュール１によれば、以下の効果を奏する。
（４）複数のメモリ部１１の入出力端子３１のうちのデータ端子３１３は、隣接する再配線層１２、外部電極１４、積層方向Ｄ一端の再配線層１２、及び半田ボール１５を介して外部に接続される。これにより、データ信号が直接外部と通信されるので、データの伝送経路を短くしてデータ品質を向上することができる。また、複数のメモリ部１１を同時に動作させるようにしてデータ信号の本数を増やし、バンド幅を向上することができる。 The semiconductor module 1 according to the first embodiment as described above has the following effects.
(4) The data terminals 313 among the input/output terminals 31 of the plurality of memory units 11 are connected to the outside via the adjacent rewiring layer 12, the external electrode 14, the rewiring layer 12 at one end in the stacking direction D, and the solder balls 15. connected to As a result, the data signal is directly communicated with the outside, so that the data transmission path can be shortened and the data quality can be improved. Also, by operating a plurality of memory units 11 simultaneously, the number of data signals can be increased and the bandwidth can be improved.
［第３実施形態］
　次に、本発明の第３実施形態に係る半導体モジュール１について、図６及び図７を参照して説明する。第３実施形態において、同一構成について同一の符号を付し、説明を簡略化又は省略する。
　第３実施形態に係る半導体モジュール１は、図６及び図７に示すように、プライマリスタック２１と、接続回路５０を複数設ける点で、第１及び第２実施形態と異なる。具体的には、第３実施形態は、１つのプライマリスタック２１と１つの他のメモリ部１１と両者を接続する接続回路５０とを２セット設ける点で、第１及び第２実施形態と異なる。すなわち、第３実施形態に係る半導体モジュール１は、外部に接続されるプライマリスタック２１の入出力端子３１が２つ設けられる点で、第１及び第２実施形態と異なる。 [Third embodiment]
Next, a semiconductor module 1 according to a third embodiment of the invention will be described with reference to FIGS. 6 and 7. FIG. In 3rd Embodiment, the same code|symbol is attached|subjected about the same structure, and description is simplified or abbreviate|omitted.
The semiconductor module 1 according to the third embodiment differs from the first and second embodiments in that a plurality of primary stacks 21 and connection circuits 50 are provided as shown in FIGS. Specifically, the third embodiment differs from the first and second embodiments in that two sets of one primary stack 21, one other memory section 11, and a connection circuit 50 connecting the two are provided. That is, the semiconductor module 1 according to the third embodiment differs from the first and second embodiments in that two input/output terminals 31 of the primary stack 21 connected to the outside are provided.
　以上のような第３実施形態に係る半導体モジュール１によれば、以下の効果を奏する。
（５）１つのメモリ部１１と、他のメモリ部１１と、両者を接続する接続回路５０とを複数セット設けた。これにより、入出力端子３１を多チャンネル化することができるので、半導体モジュール１の利用効率を向上することができる。 The semiconductor module 1 according to the third embodiment as described above has the following effects.
(5) A plurality of sets of one memory section 11, another memory section 11, and a connection circuit 50 connecting the two are provided. As a result, the input/output terminals 31 can be multi-channeled, so that the utilization efficiency of the semiconductor module 1 can be improved.
［第４実施形態］
　次に、本発明の第４実施形態に係る半導体モジュール１について、図８及び図９を参照して説明する。第４実施形態において、同一構成について同一の符号を付し、説明を簡略化又は省略する。
　第４実施形態に係る半導体モジュール１は、図８及び図９に示すように、１つのメモリ部１１が、他のメモリ部１１と接続回路５０を用いて直列に接続される点で第１から第３実施形態と異なる。具体的には、第４実施形態に係る半導体モジュール１は、プライマリスタック２１の接続端子３２と、他のメモリ部１１の入出力端子３１とを接続する接続回路５０と、他のメモリ部１１の接続端子３２とさらに他のメモリ部１１の入出力端子３１とを接続する接続回路５０とを有している点で第１から第３実施形態と異なる。 [Fourth embodiment]
Next, a semiconductor module 1 according to a fourth embodiment of the invention will be described with reference to FIGS. 8 and 9. FIG. In 4th Embodiment, the same code|symbol is attached|subjected about the same structure, and description is simplified or abbreviate|omitted.
As shown in FIGS. 8 and 9, the semiconductor module 1 according to the fourth embodiment is different from the first in that one memory section 11 is connected in series with another memory section 11 using a connection circuit 50 . It differs from the third embodiment. Specifically, the semiconductor module 1 according to the fourth embodiment includes a connection circuit 50 that connects the connection terminal 32 of the primary stack 21 and the input/output terminal 31 of the other memory section 11, and It differs from the first to third embodiments in that it has a connection circuit 50 that connects the connection terminal 32 and the input/output terminal 31 of the other memory section 11 .
　以上のような第４実施形態に係る半導体モジュール１によれば、以下の効果を奏する。
（６）１つのメモリ部１１が、他のメモリ部１１と接続回路５０を用いて直列に接続されるようにした。これにより、接続回路５０の経路を短くすることができるので、歩留まりを向上することができる。また、積層するメモリ部１１の個数によらず接続回路５０の寄生抵抗と寄生容量を概ね一定に揃えることができるので、積層するメモリ部１１の個数を容易に変更することができる。 The semiconductor module 1 according to the fourth embodiment as described above has the following effects.
(6) One memory section 11 is connected in series with another memory section 11 using the connection circuit 50 . As a result, the path of the connection circuit 50 can be shortened, so that the yield can be improved. In addition, since the parasitic resistance and parasitic capacitance of the connection circuit 50 can be kept substantially constant regardless of the number of stacked memory units 11, the number of stacked memory units 11 can be easily changed.
［第５実施形態］
　次に、本発明の第５実施形態に係る半導体モジュール１について、図１０及び図１１を参照して説明する。第５実施形態において、同一構成について同一の符号を付し、説明を簡略化又は省略する。
　第５実施形態に係る半導体モジュール１は、図１０及び図１１に示すように、再配線層１２の端部４２に配置されるロジックチップ１３０をさらに備える点で、第１から第４実施形態と異なる。なお、第５実施形態に係る半導体モジュール１は、ロジックチップ１３０に重ねて複数のダミーシリコン１３２を配置する。本実施形態において、複数のメモリ部１１は、ロジックチップ１３０を挟んで一対に配置される。また、ロジックチップ１３０は、メモリ部１１と接続され、メモリ部１１との間の信号の入出力を制御するコントローラ１３１を有する。 [Fifth embodiment]
Next, a semiconductor module 1 according to a fifth embodiment of the invention will be described with reference to FIGS. 10 and 11. FIG. In the fifth embodiment, the same reference numerals are given to the same configurations, and the description is simplified or omitted.
As shown in FIGS. 10 and 11, the semiconductor module 1 according to the fifth embodiment is different from the first to fourth embodiments in that it further includes a logic chip 130 arranged at the end portion 42 of the rewiring layer 12 . different. In addition, in the semiconductor module 1 according to the fifth embodiment, a plurality of dummy silicon layers 132 are arranged over the logic chip 130 . In this embodiment, the plurality of memory units 11 are arranged in pairs with the logic chip 130 interposed therebetween. The logic chip 130 also has a controller 131 that is connected to the memory section 11 and controls input/output of signals to/from the memory section 11 .
　以上のような第５実施形態に係る半導体モジュール１によれば、以下の効果を奏する。
（７）半導体モジュール１は、再配線層１２の端部４２に配置されるロジックチップ１３０をさらに備える。これにより、メモリ部１１とロジックチップ１３０との間の配線距離を短くすることができる。したがって、メモリ周波数（信号品質）が高く、データ移動電力の少ない半導体モジュール１を実現することができる。 The semiconductor module 1 according to the fifth embodiment as described above has the following effects.
(7) The semiconductor module 1 further includes a logic chip 130 arranged at the end portion 42 of the rewiring layer 12 . Thereby, the wiring distance between the memory unit 11 and the logic chip 130 can be shortened. Therefore, the semiconductor module 1 with high memory frequency (signal quality) and low data transfer power can be realized.
［第６実施形態］
　次に、本発明の第６実施形態に係る積層モジュール１００について、図１２を参照して説明する。第６実施形態において、同一構成について同一の符号を付し、説明を簡略化又は省略する。
　第６実施形態に係る積層モジュール１００は、上記第１実施形態から第５実施形態の半導体モジュール１を複数積層している点で、第１から第５実施形態と異なる。積層モジュール１００は、例えば、図１２に示すように、マイクロバンプ１６を用いて、複数の半導体モジュール１を接続する。このとき、積層方向Ｄ一端側で他の半導体モジュール１を積層する半導体モジュール１の他端側の表面には、再配線層１２が配置される。他の半導体モジュール１は、配置された再配線層１２とマイクロバンプ１６を用いて電気的に接続される。 [Sixth Embodiment]
Next, a laminate module 100 according to a sixth embodiment of the invention will be described with reference to FIG. In 6th Embodiment, the same code|symbol is attached|subjected about the same structure, and description is simplified or abbreviate|omitted.
A stacked module 100 according to the sixth embodiment differs from the first to fifth embodiments in that a plurality of semiconductor modules 1 according to the first to fifth embodiments are stacked. The stacked module 100 connects a plurality of semiconductor modules 1 using microbumps 16, for example, as shown in FIG. At this time, the rewiring layer 12 is arranged on the surface of the other end side of the semiconductor module 1 on which the other semiconductor module 1 is stacked on the one end side in the stacking direction D. As shown in FIG. Other semiconductor modules 1 are electrically connected using the arranged rewiring layers 12 and microbumps 16 .
　以上のような第６実施形態に係る積層モジュール１００によれば、以下の効果を奏する。
（８）積層モジュール１００は、上記の半導体モジュール１を複数積層して形成される。これにより、半導体モジュール１に含めるメモリ部１１の数を減らすことができるので、半導体モジュール１の歩留まりを向上することができる。これにより、積層モジュール１００の歩留まりも向上することができる。また、半導体モジュール１のメモリ部１１の段数を減らすことができるので、組立を容易にすることができる。 According to the laminate module 100 according to the sixth embodiment as described above, the following effects can be obtained.
(8) The laminated module 100 is formed by laminating a plurality of the semiconductor modules 1 described above. As a result, the number of memory units 11 included in the semiconductor module 1 can be reduced, so that the yield of the semiconductor module 1 can be improved. Thereby, the yield of the laminated module 100 can also be improved. In addition, since the number of stages of the memory section 11 of the semiconductor module 1 can be reduced, assembly can be facilitated.
　以上、本発明の半導体モジュール及び積層モジュールの好ましい各実施形態につき説明したが、本発明は、上述の実施形態に制限されるものではなく、適宜変更が可能である。
　例えば、上記実施形態において、メモリ部１１が複数のメモリチップを含むとしたが、１つのメモリチップを含んでもよい。 Although preferred embodiments of the semiconductor module and the laminated module of the present invention have been described above, the present invention is not limited to the above-described embodiments and can be modified as appropriate.
For example, although the memory unit 11 includes a plurality of memory chips in the above embodiment, it may include one memory chip.
　また、上記実施形態において、プライマリチップ１１０は、隣接するセカンダリチップ１２０とハイブリッドボンディングにより接続されてもよい。また、プライマリチップ１１０は、セカンダリチップ１２０と非接触通信により接続されてもよい。これによりメモリ部１１の積層方向の高さを抑えられるので、半導体モジュール１の製造を容易にできる。 Also, in the above embodiments, the primary chip 110 may be connected to the adjacent secondary chip 120 by hybrid bonding. Also, the primary chip 110 may be connected to the secondary chip 120 by contactless communication. As a result, the height of the memory section 11 in the stacking direction can be suppressed, so that the manufacturing of the semiconductor module 1 can be facilitated.
　また、上記実施形態において、プライマリスタック２１及び他のメモリ部１１の数は４つに制限されない。また、セカンダリチップ１２０の数も制限されない。 Also, in the above embodiment, the number of primary stacks 21 and other memory units 11 is not limited to four. Also, the number of secondary chips 120 is not limited.
１　半導体モジュール
１１　メモリ部
１２　再配線層
１３　モールド部
１４　外部電極
１５　半田ボール
１６　マイクロバンプ
２１　プライマリスタック
３１　入出力端子
３２　接続端子
４１　バッファ
４２　端部
５０　接続回路
１００　積層モジュール
１１０　プライマリチップ
１１１　タイミング制御部
１２０　セカンダリチップ
１２１　転送端子
１３０　ロジックチップ
１３１　コントローラ
１３２　ダミーシリコン
２００　バンプレスＴＳＶ
３１１、３２１　クロック端子
３１２、３２２　コマンド端子
３１３、３２３　データ端子
Ｄ　積層方向 1 Semiconductor module 11 Memory unit 12 Rewiring layer 13 Mold unit 14 External electrode 15 Solder ball 16 Micro bump 21 Primary stack 31 Input/output terminal 32 Connection terminal 41 Buffer 42 End 50 Connection circuit 100 Laminated module 110 Primary chip 111 Timing control unit 120 secondary chip 121 transfer terminal 130 logic chip 131 controller 132 dummy silicon 200 bumpless TSV
311, 321 Clock terminals 312, 322 Command terminals 313, 323 Data terminals D Lamination direction

Claims (11)

  1. 　複数の積層メモリを含む半導体モジュールにおいて、
    　積層方向に積層される複数のメモリ部であって、それぞれが信号を入出力する入出力端子と他のメモリ部と接続するための接続端子とを有するメモリ部と、
    　積層方向において隣接する前記メモリ部の間と積層方向一端側の前記メモリ部の一面上とに配置され、積層方向に交差する方向において前記メモリ部の端面よりも突出する端部を有する再配線層と、
    　積層方向において隣接する前記再配線層の間に配置され、前記再配線層の端部を電気的に接続する外部電極と、
    を備え、
    　前記再配線層及び前記外部電極は、１つの前記メモリ部の前記接続端子と他の前記メモリ部の前記入出力端子とを接続する接続回路を形成する半導体モジュール。     In a semiconductor module containing multiple stacked memories,
    a plurality of memory units stacked in a stacking direction, each memory unit having an input/output terminal for inputting/outputting a signal and a connection terminal for connecting to another memory unit;
    A rewiring layer disposed between the memory sections adjacent in the stacking direction and on one surface of the memory section on one end side in the stacking direction, and having an end projecting beyond the end surface of the memory section in a direction crossing the stacking direction and,
    an external electrode disposed between the rewiring layers adjacent in the stacking direction and electrically connecting ends of the rewiring layers;
    with
    A semiconductor module in which the rewiring layer and the external electrodes form a connection circuit that connects the connection terminal of one memory section and the input/output terminal of another memory section.
  2. 　前記メモリ部は、積層された複数のメモリチップを有する請求項１に記載の半導体モジュール。 3. The semiconductor module according to claim 1, wherein the memory section has a plurality of stacked memory chips.
  3. 　前記メモリ部は、
    　前記入出力端子及び前記接続端子を有するプライマリチップと、
    　前記プライマリチップに接続されるセカンダリチップと、
    を有する請求項２に記載の半導体モジュール。     The memory unit
    a primary chip having the input/output terminals and the connection terminals;
    a secondary chip connected to the primary chip;
    3. The semiconductor module according to claim 2, comprising:
  4. 　前記プライマリチップは、前記プライマリチップ及び前記セカンダリチップの動作タイミングを調整するタイミング制御部を有する請求項３に記載の半導体モジュール。 4. The semiconductor module according to claim 3, wherein the primary chip has a timing control section that adjusts operation timings of the primary chip and the secondary chip.
  5. 　前記プライマリチップと前記セカンダリチップとは同一チップの一部機能を変更した請求項３又は４に記載の半導体モジュール。 5. The semiconductor module according to claim 3 or 4, wherein the primary chip and the secondary chip are the same chip with partially different functions.
  6. 　前記プライマリチップは、前記セカンダリチップとバンプレスＴＳＶにより接続される請求項３から５のいずれかに記載の半導体モジュール。 The semiconductor module according to any one of claims 3 to 5, wherein said primary chip is connected to said secondary chip by a bumpless TSV.
  7. 　前記プライマリチップは、隣接する前記セカンダリチップとハイブリッドボンディングにより接続される請求項３から６のいずれかに記載の半導体モジュール。 The semiconductor module according to any one of claims 3 to 6, wherein said primary chip is connected to said adjacent secondary chip by hybrid bonding.
  8. 　前記プライマリチップは、前記セカンダリチップと非接触通信により接続される請求項３から５のいずれかに記載の半導体モジュール。 The semiconductor module according to any one of claims 3 to 5, wherein the primary chip is connected to the secondary chip by contactless communication.
  9. 　前記接続回路は、１つの前記メモリ部のクロック信号及びコマンド信号の前記接続端子と、他の前記メモリ部の前記クロック信号及び前記コマンド信号の前記入出力端子とを接続する請求項１から８のいずれかに記載の半導体モジュール。 9. The connection circuit according to any one of claims 1 to 8, wherein the connection circuit connects the connection terminal for the clock signal and the command signal of one of the memory sections and the input/output terminal for the clock signal and the command signal of another memory section. A semiconductor module according to any one of the above.
  10. 　前記再配線層の端部に配置されるロジックチップをさらに備える請求項１から８のいずれかに記載の半導体モジュール。 The semiconductor module according to any one of claims 1 to 8, further comprising a logic chip arranged at an end of said rewiring layer.
  11. 　請求項１から１０のいずれかに記載の半導体モジュールを複数積層した積層モジュール。 A laminated module obtained by laminating a plurality of semiconductor modules according to any one of claims 1 to 10.
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