WO2023116190A1 - 同步触发系统和方法、量子控制系统和量子计算机 - Google Patents

同步触发系统和方法、量子控制系统和量子计算机 Download PDF

Info

Publication number
WO2023116190A1
WO2023116190A1 PCT/CN2022/127936 CN2022127936W WO2023116190A1 WO 2023116190 A1 WO2023116190 A1 WO 2023116190A1 CN 2022127936 W CN2022127936 W CN 2022127936W WO 2023116190 A1 WO2023116190 A1 WO 2023116190A1
Authority
WO
WIPO (PCT)
Prior art keywords
routing
time
trigger signal
control device
devices
Prior art date
Application number
PCT/CN2022/127936
Other languages
English (en)
French (fr)
Inventor
孔伟成
赵勇杰
李雪白
范良晨
Original Assignee
合肥本源量子计算科技有限责任公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CN202111587715.8A external-priority patent/CN116401200A/zh
Priority claimed from CN202111587945.4A external-priority patent/CN116400615A/zh
Priority claimed from CN202111588000.4A external-priority patent/CN116400776A/zh
Application filed by 合肥本源量子计算科技有限责任公司 filed Critical 合肥本源量子计算科技有限责任公司
Publication of WO2023116190A1 publication Critical patent/WO2023116190A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena
    • G06N10/20—Models of quantum computing, e.g. quantum circuits or universal quantum computers

Definitions

  • the present application relates to the technical field of quantum measurement and control, in particular to a synchronous trigger system and method, a quantum control system and a quantum computer.
  • the quantum chip is the core component of quantum computing.
  • Multiple signal modules are set in the quantum control system for each quantum.
  • Bits provide various control signals, such as frequency control signals, quantum state control signals.
  • the results of quantum calculations performed by qubits also need to be collected through the collection module.
  • the number of qubits on the quantum chip increases to hundreds, or even tens of thousands, and the number of functional modules in the corresponding quantum control system will also increase, and the signal wiring will also increase. It's getting more and more complicated.
  • the existing functional boards for qubit control are generally a data processing device to control several functional devices, for example, a data processing device is connected to several ADC (Analog Digital Converter) or DAC (Digital Analog Converter) ).
  • ADC Analog Digital Converter
  • DAC Digital Analog Converter
  • the qubit control function board needs to generate more and more various signals required for manipulating, measuring and reading qubits, and its data throughput will become Exponential growth requires a large number of channels, so the existing structure of one data processing device to control several functional devices cannot meet the needs of large-scale quantum chips.
  • the purpose of this application is to provide a synchronous triggering system and method, and a quantum control system, which are used to realize synchronous triggering during the manipulation, measurement and reading operations of each qubit.
  • a synchronous trigger system of a quantum control system including:
  • the central control device is connected to several routing boards to provide several groups of trigger signals to the corresponding routing boards, and adjust the initial moment of each group of trigger signal output so that each chassis receives the same time when the trigger signal is received ;
  • each of the routing boards is connected to several functional boards, and the communication lines between each routing board and the connected several functional boards are equal in length, and the routing boards are used for forwarding all
  • the trigger signal is sent to the function board;
  • the synchronous triggering system also includes:
  • a reference clock is used to provide a reference clock signal to the central control device and the routing board.
  • the reference clock is also used to provide a reference clock signal to the functional board.
  • the number of the central control devices is at least two, and at least two of the central control devices work based on the same reference clock signal of the reference clock.
  • the routing board is configured to output a feedback signal to the central control device based on the trigger signal
  • the central control device is further configured to obtain a first time set, wherein the first time set is from the time when the central control device outputs the trigger signal to the time when the central control device receives a signal from each of the routing boards. A set of time consumed by the feedback signals respectively;
  • the central control device is further configured to calibrate the initial trigger signal sent by the central control device to each of the routing boards based on the first time set when each element in the first time set is not completely equal. time.
  • each of the routing boards and several functional boards connected to the routing boards are set in the same chassis, the routing boards are set in the middle of the chassis, and several The two functional boards are respectively arranged on both sides of the routing board.
  • the function board further includes a board main body, wherein the AND gate chip and the plurality of data processing devices are all arranged on the board main body.
  • the AND chip has several input terminals, the input terminals of the AND chip are used to receive trigger signals, and the output terminals of the AND chip are communicatively connected to the input terminals of several data processing devices, so The AND gate chip is used to make the trigger signal reach the several data processing devices at the same time.
  • each of the data processing devices is communicatively connected to several functional devices, and the functional devices are configured to perform corresponding actions according to instructions of the data processing device.
  • the function board further includes a communication interface, the communication interface is arranged on the board body, and the communication interface is connected to the data processing device.
  • the board main body includes a PCB, and the data processing device, the AND chip, and the functional devices are all arranged on the PCB.
  • the AND gate chip is connected to the functional device through wires on the top signal layer of the PCB board.
  • the AND gate chip is connected to the data processing device through wires on the top signal layer of the PCB board.
  • the number of the data processing devices is equal to the number of input terminals of the AND chip.
  • each of the data processing devices is connected to several of the functional devices.
  • the AND chip is disposed between two adjacent data processing devices on the board main body.
  • the functional device includes ADC or DAC.
  • the data processing device includes FPGA or MCU or MPU or DSP.
  • this application also proposes a method for synchronous triggering of a quantum control system, including:
  • the central control device provides several groups of trigger signals to the corresponding routing boards, and adjusts the initial moment of output of each group of trigger signals so that each of the chassis receives the same time when the trigger signal is received, wherein the central control device Connect several said routing boards;
  • the routing board forwards the trigger signal to the AND chip of the functional board, wherein each routing board is connected to several functional boards, and each routing board is connected to the several functional boards.
  • the communication line of the board is equal in length;
  • the trigger signal reaches several data processing devices at the same time after being processed by the AND operation of the AND gate chip to trigger the data processing devices synchronously, wherein the functional board has the AND gate chip and several data processing devices. processing device.
  • the central control device provides several sets of trigger signals to corresponding routing boards, and adjusts the initial moment of output of each set of trigger signals so that each chassis receives the same moment when the trigger signals are received, including:
  • the control device outputs trigger signals to multiple routing devices at a set initial time based on the reference clock signal, wherein the reference clock signal is provided by the reference clock;
  • the multiple routing devices respectively output feedback signals based on the reference clock signal and the trigger signal
  • the first time set is a set of time consumed respectively from when the control device outputs the trigger signal to when the control device receives the feedback signals from each of the routing devices;
  • the initial time of the trigger signal sent by the control device to each of the routing devices is calibrated based on the first time set.
  • the plurality of routing devices respectively output feedback signals based on the reference clock signal and the trigger signal, including:
  • the multiple routing devices receive the trigger signal, and after waiting for a second time, the multiple routing devices respectively output feedback signals based on the reference clock signal.
  • the second time is several clock periods of the reference clock.
  • the control device outputs trigger signals to multiple routing devices at a set initial time based on the reference clock signal until all elements in the first time set are equal.
  • the adjusting the initial moment of the trigger signal sent by the control device to each of the routing devices based on the first time set includes:
  • a third time set is obtained, wherein the third time set is the time consumed by each of the routing devices from when the control device outputs the trigger signal to when each of the routing devices receives the trigger signal gather;
  • the routing device corresponding to the fourth time is the first routing device; adjusting the initial moment of the trigger signal sent by the control device to each of the routing devices based on the fourth time, include:
  • the adjusting the initial moment of the trigger signal sent by the control device to each of the routing devices based on the first time set includes:
  • a third time set is obtained, wherein the third time set is the time consumed by each of the routing devices from when the control device outputs the trigger signal to when each of the routing devices receives the trigger signal gather;
  • the initial moment of the trigger signal sent by the control device to each of the routing devices is adjusted based on the fifth time.
  • the routing device corresponding to the fifth time is the second routing device; adjusting the initial moment of the trigger signal sent by the control device to each of the routing devices based on the fifth time, include:
  • the adjusting the initial timing of the trigger signal sent by the control device to each of the routing devices based on the first time set includes:
  • a third time set is obtained, wherein the third time set is the time consumed by each of the routing devices from when the control device outputs the trigger signal to when each of the routing devices receives the trigger signal gather;
  • the initial moment of the trigger signal sent by the control device to each of the routing devices is adjusted based on the sixth time.
  • the adjusting the initial moment of the trigger signal sent by the control device to each of the routing devices based on the sixth time includes:
  • each element in the third time set is obtained by the following formula:
  • t is the time taken from when the control device outputs the trigger signal to when one of the routing devices receives the trigger signal, and T is determined according to elements in the first time set.
  • the present application also proposes a quantum control system, which utilizes the above-mentioned synchronous triggering system of the quantum control system, or includes the above-mentioned synchronous triggering method of the quantum control system.
  • the present application also proposes a quantum computer, which includes the above-mentioned quantum control system.
  • the synchronous triggering system proposed by this application includes central control equipment, several routing boards and several functional boards.
  • the synchronous triggering of trigger signals is ensured through a three-level trigger synchronization system, wherein the first level provides several groups of The trigger signal is sent to the corresponding routing board, and the initial moment of each group of trigger signal output is adjusted so that the moment when each chassis receives the trigger signal is the same; the second stage is for each routing board to connect to all The communication lines of the above-mentioned several function boards are equal in length; the third stage is that the trigger signal reaches the several data processing devices at the same time after being processed by the AND operation of the AND gate chip, so as to trigger the data processing devices synchronously.
  • the trigger synchronization of the quantum control system can be effectively realized.
  • the reference clock signal is provided to the control device and the routing device through the same reference clock, so that each device in the quantum control system can perform related actions in the same sequence. , which further ensures the accuracy of the calibration method, and at the same time reduces the difficulty of triggering the simultaneous calibration of the quantum control system.
  • the trigger synchronization system, quantum control system, and readable storage medium of the quantum control system proposed in this application belong to the same inventive concept as the trigger synchronization calibration method of the quantum control system, so they have the same beneficial effects, and will not be repeated here.
  • FIG. 1 is a schematic structural diagram of a synchronous trigger system proposed in an embodiment of the present application
  • Fig. 2 is a schematic structural diagram of the central control device in Fig. 1;
  • FIG. 3 is a schematic flowchart of a synchronization triggering method proposed in another embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a functional board for qubit control proposed in the embodiment of the present application.
  • FIG. 5 is a schematic flowchart of a method for triggering synchronous calibration of a quantum control system proposed in an embodiment of the present application
  • FIG. 6 is a schematic structural diagram of a trigger synchronization system of a quantum control system proposed by another embodiment of the present application.
  • 100-central control equipment 200-routing board, 300-function board, 301-AND chip, 302-data processing device, 303-function device, 400-reference clock, 1100-board main body, 2100- AND gate chip, 3100-data processing device, 4100-function device.
  • first and second are used for descriptive purposes only, and cannot be interpreted as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Thus, a feature defined as “first” and “second” may explicitly or implicitly include one or more of these features.
  • “plurality” means at least two, such as two, three, etc., unless otherwise specifically defined.
  • quantum computers currently on the market, most of them use the combination of host computer, quantum control system and quantum chip to realize some quantum computing tasks.
  • the host computer receives the user’s quantum computing tasks and processes the quantum computing tasks. And form a quantum circuit, and then map the quantum circuit to the topology of the corresponding quantum chip.
  • the quantum circuit contains the quantum logic gates required for this quantum computing task, the measurement operation of the final quantum computing result, and the timing of each operation.
  • the quantum control system When the quantum control system receives the information contained in the quantum circuit, it will convert the information into Synthesize corresponding instructions to make corresponding hardware devices operate and complete quantum computing tasks.
  • a quantum chip is provided with a plurality of qubits (also referred to as qubits) and data transmission lines, and each qubit includes a detector and a qubit device coupled to each other, wherein the qubit device can be used
  • An artificial superconducting qubit composed of a superconducting Josephson junction and a capacitance to ground, and the detector can be a resonant cavity.
  • the qubit device is provided with a first control signal line and a second control signal line, and a detector coupled to the qubit device is provided with a third control signal line, wherein the first control signal line is used to transmit a signal to the qubit device.
  • the quantum state regulation signal for regulating the quantum state information is used to transmit the frequency regulation signal for regulating the frequency parameters of the qubit device, and the third control signal line is used to transmit the signal for measuring and reading the detector
  • the measurement signal is used to output the readback signal returned by the detector, so as to realize the indirect readout measurement of the state of the qubit device. Therefore, the quantum control system used for the regulation and measurement of qubits in the quantum chip needs to generate and output three kinds of control signals for the first to third control signal lines respectively, so as to realize the regulation and measurement of the qubits in the quantum chip.
  • the embodiment of the present application provides a synchronous trigger system, please refer to Figure 1, including: a central control device 100, connected to several routing boards 200, used Several sets of trigger signals are provided to the corresponding routing boards 200, and the initial moment of outputting each set of trigger signals is adjusted so that each chassis receives the same moment when the trigger signals are received.
  • a central control device 100 connected to several routing boards 200, used Several sets of trigger signals are provided to the corresponding routing boards 200, and the initial moment of outputting each set of trigger signals is adjusted so that each chassis receives the same moment when the trigger signals are received.
  • Several routing boards 200 each of the routing boards 200 is connected to several functional boards 300, the communication lines from each routing board 200 to the connected several functional boards 300 are equal in length, the routing boards
  • the card 200 is used to forward the trigger signal to the function board 300 .
  • the synchronous trigger system proposed in this embodiment includes a central control device 100, several routing boards 200 and several functional boards 300, and a three-level trigger synchronization system ensures the synchronous triggering of trigger signals , wherein the first stage is: the central control device 100 provides several sets of trigger signals to the corresponding routing board 200, and adjusts the initial moment of each set of trigger signal output so that each of the chassis receives the trigger signal The time is the same; the second level is: the communication lines from each routing board 200 to the connected function boards 300 are equal in length; the third level is: the trigger signal is operated through the AND operation of the AND gate chip 301 After processing, the processing reaches the several data processing devices 302 at the same time to trigger the data processing devices 302 synchronously.
  • the synchronous trigger system further includes a reference clock 400, and the reference clock 400 uses The reference clock 400 is used to provide the reference clock 400 signal to the central control device 100 and the routing board 200 , and the reference clock 400 is also used to provide the reference clock 400 signal to the function board 300 .
  • the reference clock 400 proposed in this embodiment can be an atomic clock, which is a timekeeping device with extremely high precision.
  • atomic clocks such as cesium atomic clocks, hydrogen atomic clocks, rubidium atomic clocks, CPT atomic clocks, etc.
  • the reference clock 400 is preferably a rubidium atomic clock.
  • other types of atomic clocks can also be selected, which are not limited here and can be selected according to actual needs.
  • the data processing device 302 is a device with data forwarding and processing functions, generally FPGA (Field Programmable Gate Array), MCU (Microcontroller Unit), MPU (Microprocessor Unit) or DSP (Digital Signal Processor) can be used.
  • FPGA Field Programmable Gate Array
  • MCU Microcontroller Unit
  • MPU Microprocessor Unit
  • DSP Digital Signal Processor
  • the data processing device 302 is preferably an FPGA, and other devices with similar data processing functions may also be selected in other embodiments, which is not limited here.
  • the central control device 100 is an intelligent device with data processing capability, for example, FPGA, MCU, MPU or DSP, etc. In this embodiment, the central control device 100 is preferably an FPGA.
  • any hardware device can provide are always limited. It is foreseeable that after the successful development of large-scale or ultra-large-scale quantum chips in the future, the number of qubits that need to be controlled will also become larger. Exponential increase, at this time, the synchronous triggering system needs to ensure the synchronous triggering of a large number of qubits.
  • the synchronous triggering system proposed in this application can meet the needs of large-scale quantum chips to a certain extent. We only need to expand according to the structure proposed above. Specifically, it can increase the number of central control devices 100, and all The central control devices 100 all work based on the reference clock 400 signal of the same reference clock 400 .
  • the central control device can be an intelligent device with data processing capabilities.
  • the central control device can also be composed of an intelligent device with data processing capabilities connected to several routers. Please refer to Figure 2. Several routing boards are connected below the router. This structure can also meet the needs of a large number of qubits. Trigger requirements synchronously. It should be noted that the above is only an exemplary description. In addition to the above-mentioned solutions, there are many other similar solutions, which will not be repeated here. The specific solutions for large-scale quantum chips can be determined according to actual needs. choose.
  • the central control device 100 calibrates the initial sending time of the trigger signal sent to the routing board 200 .
  • the routing board 200 is configured to output a feedback signal to the central control device 100 based on the trigger signal.
  • the central control device 100 is further configured to obtain a first time set, wherein the first time set is from the time when the central control device 100 outputs the trigger signal to the time when the central control device 100 receives signals from each of the routes A set of times consumed by the feedback signals of the board 200 respectively.
  • the central control device 100 is further configured to calibrate the triggers sent by the central control device 100 to each of the routing boards 200 based on the first time set when each element in the first time set is not completely equal. The initial moment of the signal.
  • the central control device 100 outputs a trigger signal to multiple routing boards 200 based on the reference clock 400 signal provided by the reference clock 400; the multiple routing boards 200 are based on the reference clock 400 signal and The trigger signal respectively outputs the feedback signal to obtain a first time set; when each element in the first time set is not completely equal, based on the first time set, the central control device 100 is calibrated and sent to each set The initial moment of the trigger signal of the above-mentioned routing board 200. Based on the above calibration process, the trigger synchronization can be effectively realized.
  • the reference clock 400 signal is provided to the central control device 100 and the routing board 200 through the same reference clock 400, so that each device in the quantum control system can be executed under the same sequence. Relevant actions further ensure the accuracy of the calibration process, and at the same time reduce the difficulty of ensuring that the quantum control system triggers synchronous calibration.
  • All routing boards 200 take the reference clock 400 signal provided by the reference clock 400 as a reference to perform synchronous actions. If the routing board 200 immediately returns to output the feedback signal when receiving the trigger signal, it is very likely The timing of the clock will be confused. Since the routing board 200 works according to a certain timing, it takes a period of time to process the received information when the trigger signal is received. For example, we assume that the routing board 200 is set to trigger work at the rising edge of the clock timing.
  • routing board 200 If the routing board 200 currently receives the trigger signal at the falling edge of the clock timing, if the signal is returned directly at this time, then the The routing board 200 does not actually receive the trigger signal, therefore, the signal returned to the central control device 100 must be wrong, and the final result is that the trigger synchronization calibration of the quantum control system is inaccurate.
  • the multiple routing boards 200 respectively output feedback signals based on the reference clock 400 signal and the trigger signal, and the multiple routing boards 200 wait for the second time after receiving the trigger signal.
  • the multiple routing boards 200 respectively output feedback signals based on the reference clock 400 signal.
  • the second time may be several clock cycles of the reference clock 400 .
  • the applicant proposes the following scheme, based on the initial moment after calibration, return to execute the central control device 100 based on the reference clock Signal 400 outputs a trigger signal to multiple routing boards 200 according to the set initial time until each element in the first time set is equal.
  • the scheme of using the first time set to adjust the initial moment of the trigger signal sent by the central control device 100 to each of the routing boards 200 can be selected according to actual needs.
  • three preferred schemes are provided for selection.
  • the three schemes proposed in this embodiment are preferred implementation schemes, and other schemes can also be selected in actual application, and will not be described here one by one. These three preferred schemes are described in detail below:
  • the first option is:
  • a third time set is obtained, wherein the third time set is from when the central control device 100 outputs the trigger signal to when each of the routing boards 200 receives the trigger signal The collection of time consumed;
  • the initial time of the trigger signal sent by the central control device 100 to each of the routing boards 200 is adjusted based on the fourth time.
  • the routing board 200 corresponding to the fourth time is the first routing board 200; the adjustment based on the fourth time by the central control device 100 is sent to each of the routing boards 200
  • the initial moment of the trigger signal can include:
  • the central control device 100 outputs the trigger signal to the initial moment of all routing boards 200 in the plurality of routing boards 200 except the first routing board 200 to perform delayed sending processing, so that the central control
  • the timing at which the trigger signal output by the device 100 reaches each of the routing boards 200 is the same.
  • the second option is:
  • a third time set is obtained, wherein the third time set is from when the central control device 100 outputs the trigger signal to when each of the routing boards 200 receives the trigger signal The collection of time consumed;
  • the initial time of the trigger signal sent by the central control device 100 to each of the routing boards 200 is adjusted based on the fifth time.
  • the routing board 200 corresponding to the fifth time is the second routing board 200; the adjustment based on the fifth time is sent by the central control device 100 to each of the routing boards 200
  • the initial moment of the trigger signal can include:
  • the central control device 100 outputs the trigger signal to the initial moment of all routing boards 200 in the plurality of routing boards 200 except the second routing board 200 for sending in advance, so that the central control
  • the timing at which the trigger signal output by the device 100 reaches each of the routing boards 200 is the same.
  • the third option is:
  • a third time set is obtained, wherein the third time set is from when the central control device 100 outputs the trigger signal to when each of the routing boards 200 receives the trigger signal The collection of time consumed;
  • the initial time of the trigger signal sent by the central control device 100 to each of the routing boards 200 is adjusted based on the sixth time.
  • the adjusting the initial moment of the trigger signal sent by the central control device 100 to each of the routing boards 200 based on the sixth time may include:
  • the central control device 100 outputs the trigger signal to the initial moment of all routing boards 200 in the plurality of routing boards 200 except the third routing board 200 to perform delayed sending processing or early sending processing,
  • the time when the trigger signal output by the central control device 100 reaches each of the routing boards 200 is the same.
  • each element in the third time set is obtained by the following formula:
  • t is the time taken from when the central control device 100 outputs the trigger signal to when one of the routing boards 200 receives the trigger signal
  • the trigger signal mentioned in the above three schemes is the signal used in the calibration process, which can be used in the practical application of quantum computing, but in order to ensure that the trigger synchronization calibration accuracy of the quantum control system is high enough, the above The trigger signal mentioned in the three schemes may not be the signal used in the practical application of quantum computing.
  • the frequency of the trigger signal is higher than the frequency of the signal used in the practical application of quantum computing. For example, if If the frequency of the signal used in the practical application of quantum computing is 1 MHz, then the frequency of the trigger signal can be set to 10 MHz.
  • each of the routing boards 200 and several functional boards 300 connected to the routing boards 200 are arranged in the same chassis,
  • the routing board 200 is arranged in the middle of the chassis, and several functional boards 300 are respectively arranged on both sides of the routing board 200 .
  • the functional board 300 also includes a board main body, wherein the AND gate chip 301 and several data processing devices 302 are set on the on the board body.
  • the function of the functional device 303 is to generate various signals required for manipulating, measuring and reading qubits.
  • it can be an ADC or a DAC.
  • the ADC is used to obtain information in the resonant cavity
  • the DAC is used to generate a quantum state regulation signal for regulating quantum state information or a frequency regulation signal for regulating frequency parameters.
  • quantum state regulation signal for regulating quantum state information
  • frequency regulation signal for regulating frequency parameters.
  • each of the data processing devices 302 is communicatively connected to several functional devices 303 , and the functional devices 303 are configured to perform corresponding actions according to instructions of the data processing device 302 .
  • FIG. 1 is only an exemplary illustration of this embodiment, and should not be construed as any limitation to the present application.
  • each data processing device 302 is only connected to one functional device 303.
  • One data processing device 302 may be connected to multiple functional devices 303, which is not limited here.
  • each of the data processing devices 302 is preferably connected to four functional devices 303 , which can be understood as four ADCs or four DACs connected to each FPGA in a specific application.
  • each of the data processing devices 302 can also be connected to other numbers of functional devices 303 , which is not limited here and can be adjusted according to actual needs.
  • the AND gate chip 301 is placed between two adjacent FPGAs nearby, and the output of the high-speed AND gate chip 301 is distributed and connected to the two FPGAs by strict equal-length control of the shortest path.
  • each of the data processing devices 302 needs a trigger signal. Therefore, in order to ensure that the trigger signal of each of the data processing devices 302 has a trigger signal, the number of the data processing devices 302 It is equal to the number of input terminals of the AND chip 301 .
  • the data processing device 302 is a device with data forwarding and processing functions, and generally FPGA (Field Programmable Gate Array), MCU (Microcontroller Unit)), MPU (Microprocessor Unit) or DSP (Digital Signal Processor) can be selected. )wait.
  • FPGA Field Programmable Gate Array
  • MCU Microcontroller Unit
  • MPU Microprocessor Unit
  • DSP Digital Signal Processor
  • the data processing device 302 is preferably an FPGA, and other devices with similar data processing functions may also be selected in other embodiments, which is not limited here.
  • the functional board 300 needs to have a corresponding functional device 303 to realize the corresponding function, for example, a device with an analog-to-digital conversion function is required to realize analog-to-digital conversion, and a digital-to-analog conversion function is required.
  • devices for digital-to-analog conversion A device with an analog-to-digital conversion function can be implemented using a pure circuit structure and can also be implemented using an AD chip (that is, ADC).
  • a device with a digital-to-analog conversion function can also be implemented using a pure circuit structure. chip (that is, DAC) to achieve.
  • the functional device 303 is preferably an ADC or a DAC.
  • the type of the AND gate chip 301 can be selected according to actual needs, and the utilization can include but not limited to HMC746, 7408TTL, 7409TTL, 74X11, 74X21, CD4081, CD4082, and there is no limitation here.
  • the board main body may be a PCB (Printed Circuit Board), and the data processing device 302, the AND chip 301 and the functional device 303 are all arranged on the PCB.
  • PCB Print Circuit Board
  • the AND gate chip 301 and the functional device 303 are preferably connected by wires on the top signal layer of the PCB board, and the AND gate chip 301 and the data processing device 302 are connected by wiring on the top signal layer of the PCB board.
  • top signal layer to distribute fast signals, such as 2.5GHz or 3.125GHz, try not to punch holes when distributing high-speed signals, if you really need to punch holes, change layers from the top layer to the bottom layer, or from the There is no stub effect of via holes when the bottom layer is punched to change layers to the top layer signal layer. This feature is also not available in the inner layer wiring.
  • the functional board 300 also has some peripheral circuits or devices, for example, the functional board 300 also includes a communication interface, and the communication interface is set On the card body, the communication interface is connected to the data processing device 302, and there are some other devices, which are not listed here.
  • the central control device provides several sets of trigger signals to the corresponding routing boards, and adjusts the initial moment of output of each set of trigger signals so that each of the chassis receives the same moment when the trigger signal is received, wherein the central The control device is connected to several of the routing boards;
  • each of the routing boards is connected to several functional boards, and each routing board is connected to the several connected The communication lines of each functional board are equal in length;
  • the trigger signal reaches several data processing devices at the same time after being processed by the AND operation of the AND gate chip to trigger the data processing devices synchronously, wherein the functional board has the AND gate chip and several The data processing device described above.
  • an embodiment of the present application further proposes a quantum control system, including the synchronous trigger system described in any one of the above feature descriptions.
  • a quantum chip is provided with a plurality of qubits (also referred to as qubits) and data transmission lines, and each qubit includes a detector and a qubit device coupled to each other, wherein the qubit device can be used
  • An artificial superconducting qubit composed of a superconducting Josephson junction and a capacitance to ground, and the detector can be a resonant cavity.
  • the qubit device is provided with a first control signal line and a second control signal line, and a detector coupled to the qubit device is provided with a third control signal line, wherein the first control signal line is used to transmit a signal to the qubit device.
  • the quantum state regulation signal for regulating the quantum state information is used to transmit the frequency regulation signal for regulating the frequency parameters of the qubit device, and the third control signal line is used to transmit the signal for measuring and reading the detector
  • the measurement signal is used to output the readback signal returned by the detector, so as to realize the indirect readout measurement of the state of the qubit device. Therefore, the quantum control system used for the regulation and measurement of qubits in the quantum chip needs to generate and output three kinds of control signals for the first to third control signal lines respectively, so as to realize the regulation and measurement of the qubits in the quantum chip.
  • the embodiment of the present application proposes a functional board for qubit control, including a board main body 1100 , an AND gate chip 2100 , several data processing devices 3100 and several functional devices 4100 .
  • the AND chip 2100 is arranged on the board main body 1100, the AND chip 2100 has several input terminals, the input terminals of the AND chip 2100 are used to receive trigger signals, and the AND chip 2100
  • the output terminal is communicatively connected to the input terminals of several data processing devices 3100 , and the AND chip 2100 is used to make the trigger signal reach the several data processing devices 3100 at the same time.
  • the plurality of data processing devices 3100 are arranged at intervals on the board main body 1100, and the data processing devices 3100 are used to generate work instructions based on the trigger signal.
  • the several functional devices 4100 are arranged on the board main body 1100 and communicated with the output end of the data processing device 3100, and the functional devices 4100 are used to perform corresponding actions on the quantum ratio control based on the working instructions .
  • the function of the functional device is to generate various signals required for controlling qubits such as manipulation, measurement and reading. Generally, it can be an ADC or a DAC.
  • the ADC is used to obtain information in the resonant cavity, and the DAC is used to generate a quantum state regulation signal for regulating quantum state information or a frequency regulation signal for regulating frequency parameters.
  • the DAC is used to generate a quantum state regulation signal for regulating quantum state information or a frequency regulation signal for regulating frequency parameters.
  • the embodiment of this application proposes a functional board for qubit control, including a board main body 1100 , an AND chip 2100 , several data processing devices 3100 and several functional devices 4100 .
  • the AND chip 2100 is arranged on the board main body 1100, the AND chip 2100 has several input terminals, the input terminals of the AND chip 2100 are used to receive trigger signals, and the AND chip 2100
  • the output terminal is communicatively connected to the input terminals of several data processing devices 3100 , and the AND chip 2100 is used to make the trigger signal reach the several data processing devices 3100 at the same time.
  • the plurality of data processing devices 3100 are arranged at intervals on the board main body 1100, and the data processing devices 3100 are used to generate work instructions based on the trigger signal.
  • the several functional devices 4100 are arranged on the board main body 1100 and communicated with the output end of the data processing device 3100, and the functional devices 4100 are used to execute corresponding actions based on the work instructions. Based on the above structure, by connecting multiple data processing devices 3100 with the gate chip 2100, the needs of large-scale quantum chips can be met, and because multiple data processing devices 3100 in the function board for single qubit control need to ensure that its trigger is Fully synchronous, the structure of the AND chip 2100 can also ensure that multiple trigger signals reach the corresponding data processing device 3100 at the same time.
  • each of the data processing devices 3100 needs a trigger signal. Therefore, in order to ensure that the trigger signal of each of the data processing devices 3100 has a trigger signal, the number of the data processing devices 3100 It is equal to the number of input terminals of the AND chip 2100 .
  • the data processing device 3100 is a device with data forwarding and processing functions, generally FPGA (Field Programmable Gate Array), MCU (Microcontroller Unit)), MPU (Microprocessor Unit) or DSP (Digital Signal Processor )wait.
  • FPGA Field Programmable Gate Array
  • MCU Microcontroller Unit
  • MPU Microprocessor Unit
  • DSP Digital Signal Processor
  • the data processing device 3100 is preferably an FPGA, and other devices with similar data processing functions may also be selected in other embodiments, which is not limited here.
  • the function board for qubit control needs to have a corresponding functional device 4100 to realize the corresponding function.
  • a device with an analog-to-digital conversion function can be implemented using a pure circuit structure and can also be implemented using an AD chip (that is, ADC).
  • a device with a digital-to-analog conversion function can also be implemented using a pure circuit structure. chip (that is, DAC) to achieve.
  • the functional device 4100 is preferably an ADC or a DAC.
  • the AND gate chip 2100 can be selected according to actual needs, and the use can include but not limited to HMC746, 7408TTL, 7409TTL, 74X11, 74X21, CD4081, CD4082, and there is no limitation here.
  • each of the data processing devices 3100 is connected to several of the functional devices 4100 .
  • each of the data processing devices 3100 is connected to four functional devices 4100 , which can be understood as four AD chips or four DA chips connected to each FPGA in a specific application.
  • each of the data processing devices 3100 may also be connected to other numbers of functional devices 4100 , which is not limited here and may be adjusted according to actual needs.
  • the AND chip 2100 is placed between two adjacent FPGAs nearby, and the output of the high-speed AND chip 2100 is distributed and connected to the two FPGAs by strict equal-length control of the shortest path.
  • the board main body 1100 may be a PCB (Printed Circuit Board), and the data processing device 3100, the AND chip 2100 and the functional device 4100 are all arranged on the PCB.
  • PCB Print Circuit Board
  • the AND gate chip 2100 and the functional device 4100 are preferably connected by wires on the top signal layer of the PCB board, and the AND gate chip 2100 and the data processing device 3100 are connected by wiring on the top signal layer of the PCB board.
  • top signal layer to distribute fast signals, such as 2.5GHz or 3.125GHz, try not to punch holes when distributing high-speed signals, if you really need to punch holes, change layers from the top layer to the bottom layer, or from the There is no stub effect of via holes when the bottom layer is punched to change layers to the top layer signal layer. This feature is also not available in the inner layer wiring.
  • the functional board for qubit control also has some peripheral circuits or devices, for example, the functional board for qubit control also includes a communication interface , the communication interface is arranged on the board body, and the communication interface is connected to the data processing device 3100 .
  • an embodiment of the present application further proposes a backplane, including the functional board for qubit control described in any one of the above feature descriptions.
  • an embodiment of the present application further proposes a VPX chassis, including the backplane described in the above feature description.
  • an embodiment of the present application also proposes a quantum control system, including the function board for qubit control described in any one of the above feature descriptions.
  • the embodiment of the present application proposes a trigger synchronization calibration method for a quantum control system, including:
  • the control device outputs a trigger signal to multiple routing devices at a set initial time based on the reference clock signal, wherein the reference clock signal is provided by the reference clock;
  • the multiple routing devices respectively output feedback signals based on the reference clock signal and the trigger signal;
  • S1206 Obtain a first time set, wherein the first time set is a set of time consumed respectively from when the control device outputs the trigger signal to when the control device receives the feedback signals from each of the routing devices ;
  • the control device outputs the trigger signal to multiple routing devices based on the reference clock signal provided by the reference clock; the multiple routing devices are based on the The reference clock signal and the trigger signal respectively output the feedback signal to obtain a first time set; when each element in the first time set is not completely equal, calibrate the control device based on the first time set to send The initial moment of the trigger signal to each of the routing devices.
  • the trigger synchronization of the quantum control system can be effectively realized.
  • the reference clock signal is provided to the control device and the routing device through the same reference clock, so that each device in the quantum control system can perform related actions in the same sequence. , which further ensures the accuracy of the calibration method, and at the same time reduces the difficulty of triggering the simultaneous calibration of the quantum control system.
  • the trigger signal is a signal used in the calibration process, not a signal used in the actual application of quantum computing.
  • the The frequency of the trigger signal is higher than the frequency of the signal used in the practical application of quantum computing. For example, if the frequency of the signal used in the practical application of quantum computing is 1 MHz, then the frequency of the trigger signal can be set to 10 MHz.
  • All routing devices take the reference clock signal provided by the reference clock as a reference to perform synchronous actions. If the routing device immediately returns to output the feedback signal when receiving the trigger signal, it is likely to cause clock timing confusion. Since the routing device works according to a certain sequence, when the trigger signal is received, it needs to spend a period of time to process the received information. For example, we assume that the routing device is set to trigger work at the rising edge of the clock timing. If the current routing device receives the trigger signal at the falling edge of the clock timing, if the signal is returned directly at this time, the routing device actually The trigger signal is not received, therefore, the signal returned to the control device must be wrong, and the final result is that the trigger synchronization calibration of the quantum control system is inaccurate.
  • the plurality of routing devices respectively output feedback signals based on the reference clock signal and the trigger signal, that is, the step S1204 includes:
  • the multiple routing devices receive the trigger signal, and after waiting for a second time, the multiple routing devices respectively output feedback signals based on the reference clock signal.
  • the second time may be several clock periods of the reference clock.
  • the trigger synchronization calibration method may also include:
  • S1210 Based on the calibrated initial time, return to execute the control device outputting trigger signals to multiple routing devices at the set initial time based on the reference clock signal until all elements in the first time set are equal.
  • the scheme of using the first time set to adjust the initial moment of the trigger signal sent by the control device to each of the routing devices can be selected according to actual needs,
  • three preferred schemes are provided for selection, and the three schemes proposed in this embodiment are preferred implementation schemes, and other schemes can also be selected in actual application, and will not be repeated here. These three preferred schemes are described in detail below:
  • the adjusting the initial moment of the trigger signal sent by the control device to each of the routing devices based on the first time set may include:
  • a third time set is obtained, wherein the third time set is the time consumed by each of the routing devices from when the control device outputs the trigger signal to when each of the routing devices receives the trigger signal gather;
  • the routing device corresponding to the fourth time is the first routing device; adjusting the initial moment of the trigger signal sent by the control device to each of the routing devices based on the fourth time includes :
  • the adjusting the initial moment of the trigger signal sent by the control device to each of the routing devices based on the first time set may further include:
  • a third time set is obtained, wherein the third time set is the time consumed by each of the routing devices from when the control device outputs the trigger signal to when each of the routing devices receives the trigger signal gather;
  • the initial moment of the trigger signal sent by the control device to each of the routing devices is adjusted based on the fifth time.
  • the routing device corresponding to the fifth time is the second routing device; adjusting the initial moment of the trigger signal sent by the control device to each of the routing devices based on the fifth time includes :
  • the adjusting the initial moment of the trigger signal sent by the control device to each of the routing devices based on the first time set may further include:
  • a third time set is obtained, wherein the third time set is the time consumed by each of the routing devices from when the control device outputs the trigger signal to when each of the routing devices receives the trigger signal gather;
  • the initial moment of the trigger signal sent by the control device to each of the routing devices is adjusted based on the sixth time.
  • the adjusting the initial moment of the trigger signal sent by the control device to each of the routing devices based on the sixth time includes:
  • each element in the third time set is obtained by the following formula:
  • t is the time taken from when the control device outputs the trigger signal to when one of the routing devices receives the trigger signal
  • the control device When actually applied to a quantum control system, the control device is generally a central control, which is an intelligent device with data processing capabilities, such as FPGA (Field Programmable Gate Array), MCU (Microcontroller Unit), MPU (Microprocessor Unit) or DSP (Digital Signal Processor), etc.
  • the control device is preferably an FPGA.
  • the routing device can generally be a routing board.
  • the control device sends a trigger signal to each routing device. Assuming that the process takes t, at the same time, it starts timing with the high-precision rubidium clock as the reference clock. After the signal reaches the routing device, each routing device uses the high-precision rubidium clock as the clock source. Referring to the action, the routing device outputs a feedback signal to the control device after waiting for the same time t 2 . Let the process take time t 1 , and the control device stops timing after receiving the feedback signal. Let the total time consumption be T 1 .
  • the same group passes through a customized double-headed SMA connector, a pair of communication lines used to transmit the trigger signal and a pair of communication lines used to transmit the feedback signal.
  • the embodiment of the present application also proposes a trigger synchronization system for a quantum control system, including:
  • a reference clock configured to provide a reference clock signal
  • control device configured to output a trigger signal to a plurality of routing devices based on the reference clock signal
  • the plurality of routing devices are configured to respectively output the feedback signals based on the reference clock signal and the trigger signal;
  • the control device is further configured to obtain a first time set, wherein the first time set is from the time when the control device outputs the trigger signal to when the control device receives the feedback from each of the routing devices The collection of time consumed by the signals respectively;
  • the control device is further configured to calibrate the initial moment of the trigger signal sent by the control device to each of the routing devices based on the first time set when each element in the first time set is not completely equal.
  • the reference clock may be an atomic clock, which is a timekeeping device with extremely high precision.
  • atomic clocks such as cesium atomic clocks, hydrogen atomic clocks, rubidium atomic clocks, and CPT atomic clocks.
  • the reference clock is preferably a rubidium atomic clock.
  • other types of atomic clocks can also be selected, which are not limited here and can be selected according to actual needs.
  • the control device is generally a central control, and the central control is an intelligent device with data processing capabilities, such as FPGA (Field Programmable Gate Array), MCU (Microcontroller Unit), MPU (Microprocessor Unit) or DSP (Digital Signal Processor) wait.
  • the control device is preferably an FPGA
  • the routing device may generally be a routing board.
  • the embodiment of the present application also proposes a quantum control system, using the trigger synchronization calibration method of the quantum control system described in any one of the above feature descriptions, or the triggering of the quantum control system described in the above feature description sync system.
  • an embodiment of the present application also proposes a readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, it can realize the quantum control system described in any one of the above feature descriptions
  • the trigger synchronization calibration method is also proposes a readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, it can realize the quantum control system described in any one of the above feature descriptions.
  • the readable storage medium may be a tangible device capable of holding and storing instructions for use by an instruction execution device, such as but not limited to an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or the above-mentioned any suitable combination. More specific examples (a non-exhaustive list) of readable storage media include: portable computer disks, hard disks, random access memory (RAM), read only memory (ROM), erasable programmable read only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disk read only memory (CD-ROM), digital versatile disk (DVD), memory sticks, floppy disks, mechanically encoded devices such as punched The protruding structure in the card or groove, and any suitable combination of the above.
  • RAM random access memory
  • ROM read only memory
  • EPROM or flash memory erasable programmable read only memory
  • SRAM static random access memory
  • CD-ROM compact disk read only memory
  • DVD digital versatile disk
  • memory sticks floppy disk
  • the computer programs described herein may be downloaded from a readable storage medium to various computing/processing devices, or downloaded to an external computer or external storage device over a network, such as the Internet, local area network, wide area network, and/or wireless network.
  • the network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and/or edge servers.
  • a network adapter card or a network interface in each computing/processing device receives the computer program from the network, and forwards the computer program for storage in a readable storage medium in each computing/processing device.
  • a computer program for performing the operations of the present application may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or any Combining source or object code written in programming languages including object-oriented programming languages such as Smalltalk, C++, etc., and conventional procedural programming languages such as the "C" language or similar programming languages.
  • the computer program can execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer, or entirely on the remote computer or server .
  • the remote computer can be connected to the user computer through any kind of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computer (such as through the Internet using an Internet service provider). connect).
  • electronic circuits such as programmable logic circuits, field programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), can be customized by utilizing state information from a computer program that can execute computer-programmable Program instructions are read, thereby implementing various aspects of the present application.
  • These computer programs can also be stored in a readable storage medium, and these computer programs make computers, programmable data processing devices and/or other devices work in a specific way, so that the readable storage medium storing the computer programs includes a An article of manufacture comprising instructions for implementing various aspects of the functions/acts specified in one or more blocks in flowcharts and/or block diagrams.
  • description with reference to the terms “one embodiment”, “some embodiments”, “example” or “specific example” means that a specific feature, structure, material or characteristic described in connection with the embodiment or example Included in at least one embodiment or example of the present application.
  • the schematic representations of the above terms are not necessarily directed to the same embodiment or example.
  • the particular features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments.
  • those skilled in the art can combine and combine different embodiments or examples described in this specification.

Abstract

公开了一种同步触发系统和方法、量子控制系统和量子计算机。该同步触发系统包括中控设备（100）、若干个路由板卡（200）以及若干个功能板卡（300），通过三级触发同步系统确保触发信号的同步触发，其中，第一级为中控设备（100）提供若干组触发信号给对应的路由板卡（200），并通过调整每组触发信号输出的初始时刻以使每个机箱接收到触发信号的时刻相同；第二级为每个路由板卡（200）到连接的若干个功能板卡（300）的通信线路等长；第三级为触发信号经与门芯片（301）的与操作处理后同时到达若干个数据处理器件（302）以同步触发数据处理器件（302）。

Description

同步触发系统和方法、量子控制系统和量子计算机
本申请要求于2021年12月23日提交中国专利局的申请号为202111587945.4、申请名称为“同步触发系统和方法、量子控制系统”的中国专利申请的优先权。本申请还要求于2021年12月23日提交中国专利局的申请号为202111587715.8、申请名称为“量子比特控制用功能板卡、背板以及量子控制系统”的中国专利申请的优先权。本申请还要求于2021年12月23日提交中国专利局的申请号为202111588000.4、申请名称为“量子控制系统的触发同步校准方法以及触发同步系统”的中国专利申请的优先权。上述三件申请的全部内容通过引用结合在本申请中。
技术领域
本申请涉及量子测控技术领域，尤其是涉及一种同步触发系统和方法、量子控制系统和量子计算机。
背景技术
量子芯片为运行量子计算的核心部件，量子芯片上集成有多位量子比特，为了保证量子比特的正常工作，需要搭建专门的量子控制系统，在量子控制系统内设置多个信号模块为每个量子比特提供各种控制信号、例如频率控制信号、量子态控制信号。此外对于量子比特运行完量子计算的结果，也需要通过采集模块进行采集。随着技术的发展，量子芯片上的量子比特的位数提高至几百位、甚至几千上万位，对应的量子控制系统内的功能模块数量也会越来越多，信号走线也会越来越复杂。在量子芯片上运行量子计算任务时，对于执行同一个量子计算任务的若干个量子比特而言，通过多个功能模块对其操控、测量和读取的时候，很难保证触发是完全同步的，使得任务结果的精确性大大降低。
因此，如何实现对各个量子比特的操控、测量和读取操作时的同步触发是本领域亟待解决的技术问题。
在当前量子芯片结构基础上，现有的量子比特控制用功能板卡一般是一个数据处理器件管控若干个功能器件，例如一个数据处理器件连接若干个ADC(Analog Digital Converter)或DAC(Digital Analog Convert)。但是随着技术的发展，量子芯片上的量子比特的位数提高至几百位、甚至几千上万位，对应的量子控制系统内的量子比特控制用功能板卡数量也会越来越多，信号走线也会越来越复杂。对于单个量子比特控制用功能板卡而言，需要量子比特控制用功能板卡生成对量子比特进行操控、测量和读取时所需的各种信号也越来越多，其数据吞吐量会成指数级增长，因此需要的通道数量很多，故现有的一个数据处理器件管控若干个功能器件的结构无法满足大规模量子芯片的需要。
因此，如何使得量子比特控制用功能板卡满足大规模量子芯片的需要是本领域亟待解决的技术问题。
需要说明的是，公开于本申请背景技术部分的信息仅仅旨在加深对本申请一般背景技术的理解，而不应当被视为承认或以任何形式暗示该信息构成已为本领域技术人员所公知的现有技术。
发明内容
本申请的目的在于提供一种同步触发系统和方法、量子控制系统，用于实现对各个量子比特的操控、测量和读取操作时的同步触发。
为了实现上述目的，本申请提出一种量子控制系统的同步触发系统，包括：
中控设备，连接若干个路由板卡，用于提供若干组触发信号给对应的路由板卡，并通过调整每组触发 信号输出的初始时刻以使每个机箱接收到所述触发信号的时刻相同；
若干个路由板卡，每个所述路由板卡连接若干个功能板卡，每个路由板卡到连接的所述若干个功能板卡的通信线路等长，所述路由板卡用于转发所述触发信号到所述功能板卡；
若干个功能板卡，每个所述功能板卡具有与门芯片以及若干个数据处理器件，所述触发信号经所述与门芯片的与操作处理后同时到达所述若干个数据处理器件以同步触发所述数据处理器件。
可选地，所述同步触发系统还包括：
参考时钟，用于给所述中控设备以及所述路由板卡提供参考时钟信号。
可选地，所述参考时钟还用于给所述功能板卡提供参考时钟信号。
可选地，所述中控设备的数量为至少两个，至少两个所述中控设备均基于同一个所述参考时钟的参考时钟信号进行工作。
可选地，所述路由板卡用于基于所述触发信号输出反馈信号给所述中控设备；
所述中控设备还用于获取第一时间集合，其中，所述第一时间集合为从所述中控设备输出所述触发信号到所述中控设备接收到来自各个所述路由板卡的所述反馈信号分别消耗的时间集合；
所述中控设备还用于在当所述第一时间集合中各个元素不完全相等时，基于所述第一时间集合校准所述中控设备发送给各个所述路由板卡的触发信号的初始时刻。
可选地，每个所述路由板卡以及连接在所述路由板卡上的若干个所述功能板卡设置在同一个机箱中，所述路由板卡设置在所述机箱的中间位置，若干个所述功能板卡分别设置在所述路由板卡的两侧。
可选地，所述功能板卡还包括板卡主体，其中，所述与门芯片以及若干个所述数据处理器件均设置在所述板卡主体上。
可选地，所述与门芯片具有若干个输入端，所述与门芯片的输入端用于接收触发信号，所述与门芯片的输出端与若干个数据处理器件的输入端通信连接，所述与门芯片用于使得所述触发信号同时到达所述若干个数据处理器件。
可选地，若干个数据处理器件间隔设置在所述板卡主体上。
可选地，每个所述数据处理器件通信连接若干个功能器件，所述功能器件用于根据所述数据处理器件的指令执行相应的动作。
可选地，若干个功能器件设置在所述板卡主体上。
可选地，所述功能板卡还包括通信接口，所述通信接口设置在所述板卡体上，所述通信接口与所述数据处理器件连接。
可选地，所述板卡主体包括PCB板，所述数据处理器件、所述与门芯片以及所述功能器件均设置在所述PCB板上。
可选地，所述与门芯片与所述功能器件通过在所述PCB板的顶层信号层走线连接。
可选地，所述与门芯片与所述数据处理器件通过在所述PCB板的顶层信号层走线连接。
可选地，所述数据处理器件的数量与所述与门芯片的输入端数量相等。
可选地，每个所述数据处理器件均与若干个所述功能器件连接。
可选地，所述与门芯片设置在所述板卡主体上相邻两个所述数据处理器件之间。
可选地，所述功能器件包括ADC或DAC。
可选地，所述数据处理器件包括FPGA或MCU或MPU或DSP。
基于同一发明构思，本申请还提出一种量子控制系统的同步触发方法，包括：
中控设备提供若干组触发信号给对应的路由板卡，并通过调整每组触发信号输出的初始时刻以使每个所述机箱接收到所述触发信号的时刻相同，其中，所述中控设备连接若干个所述路由板卡；
所述路由板卡转发所述触发信号到所述功能板卡的与门芯片，其中，每个所述路由板卡连接若干个功能板卡，每个路由板卡到连接的所述若干个功能板卡的通信线路等长；
所述触发信号经所述与门芯片的与操作处理后同时到达若干个数据处理器件以同步触发所述数据处理器件，其中，所述功能板卡具有所述与门芯片以及若干个所述数据处理器件。
可选地，所述中控设备提供若干组触发信号给对应的路由板卡，并通过调整每组触发信号输出的初始时刻以使每个机箱接收到所述触发信号的时刻相同，包括：
控制器件基于参考时钟信号按照设定好的初始时刻输出触发信号给多个路由器件，其中，所述参考时钟信号通过参考时钟提供；
所述多个路由器件基于所述参考时钟信号以及所述触发信号分别输出反馈信号；
获取第一时间集合，其中，所述第一时间集合为从所述控制器件输出所述触发信号到所述控制器件接收到来自各个所述路由器件的所述反馈信号分别消耗的时间集合；
当所述第一时间集合中各个元素不完全相等时，基于所述第一时间集合校准所述控制器件发送给各个所述路由器件的触发信号的初始时刻。
可选地，所述多个路由器件基于所述参考时钟信号以及所述触发信号分别输出反馈信号，包括：
所述多个路由器件接收到所述触发信号，均等待第二时间后所述多个路由器件基于所述参考时钟信号分别输出反馈信号。
可选地，所述第二时间为若干个所述参考时钟的时钟周期。
可选地，基于校准后的初始时刻，返回执行所述控制器件基于参考时钟信号按照设定好的初始时刻输出触发信号给多个路由器件，直至所述第一时间集合中各个元素均相等。
可选地，所述基于所述第一时间集合调整所述控制器件发送给各个所述路由器件的触发信号的初始时刻，包括：
基于所述第一时间集合，获取第三时间集合，其中，所述第三时间集合为从所述控制器件输出所述触发信号到各个所述路由器件接收到所述触发信号各自所消耗的时间集合；
获取所述第三时间集合中时间最长的时间为第四时间；
基于所述第四时间调整所述控制器件发送给各个所述路由器件的触发信号的初始时刻。
可选地，所述第四时间对应的所述路由器件为所述第一路由器件；所述基于所述第四时间调整所述控制器件发送给各个所述路由器件的触发信号的初始时刻，包括：
将所述控制器件输出所述触发信号给所述多个路由器件中除第一路由器件外的所有路由器件的初始时刻做延迟发送处理，以使所述控制器件输出的所述触发信号到达各个所述路由器件的时刻相同。
可选地，所述基于所述第一时间集合调整所述控制器件发送给各个所述路由器件的触发信号的初始时刻，包括：
基于所述第一时间集合，获取第三时间集合，其中，所述第三时间集合为从所述控制器件输出所述触发信号到各个所述路由器件接收到所述触发信号各自所消耗的时间集合；
获取所述第三时间集合中时间最短的时间为第五时间；
基于所述第五时间调整所述控制器件发送给各个所述路由器件的触发信号的初始时刻。
可选地，所述第五时间对应的所述路由器件为所述第二路由器件；所述基于所述第五时间调整所述控制器件发送给各个所述路由器件的触发信号的初始时刻，包括：
将所述控制器件输出所述触发信号给所述多个路由器件中除第二路由器件外的所有路由器件的初始时刻做提前发送处理，以使所述控制器件输出的所述触发信号到达各个所述路由器件的时刻相同。
可选地，所述基于所述第一时间集合调整所述控制器件发送给各个所述路由器件的触发信号的初始时 刻，包括：
基于所述第一时间集合，获取第三时间集合，其中，所述第三时间集合为从所述控制器件输出所述触发信号到各个所述路由器件接收到所述触发信号各自所消耗的时间集合；
获取所述第三时间集合中选定的第三路由器件对应的是时间为第六时间；
基于所述第六时间调整所述控制器件发送给各个所述路由器件的触发信号的初始时刻。
可选地，所述基于所述第六时间调整所述控制器件发送给各个所述路由器件的触发信号的初始时刻，包括：
将所述控制器件输出所述触发信号给所述多个路由器件中除所述第三路由器件外的所有路由器件的初始时刻做延迟发送处理或提前发送处理，以使所述控制器件输出的所述触发信号到达各个所述路由器件的时刻相同。
可选地，所述第三时间集合中的各个元素通过以下公式获取：
t＝T/2；
其中，t为从所述控制器件输出所述触发信号到其中一个路由器件接收到所述触发信号所消耗的时间，T根据所述第一时间集合中的元素确定。
基于同一发明构思，本申请还提出一种量子控制系统，其利用如上所述的量子控制系统的同步触发系统，或包括如上所述的量子控制系统的同步触发方法。
基于同一发明构思，本申请还提出一种量子计算机，其包括如上所述的量子控制系统。
与现有技术相比，本申请具有以下有益效果：
本申请提出的同步触发系统，包括中控设备、若干个路由板卡以及若干个功能板卡，通过三级触发同步系统确保触发信号的同步触发，其中，第一级为中控设备提供若干组触发信号给对应的路由板卡，并通过调整每组触发信号输出的初始时刻以使每个所述机箱接收到所述触发信号的时刻相同；第二级为每个路由板卡到连接的所述若干个功能板卡的通信线路等长；第三级为所述触发信号经所述与门芯片的与操作处理后同时到达所述若干个数据处理器件以同步触发所述数据处理器件。
基于以上结构，通过与门芯片连接多个数据处理器件，可以满足大规模量子芯片的需求，并且由于对于单个量子比特控制用功能板卡内的多个数据处理器件需要保证其触发是完全同步的，与门芯片的结构还可保证多个触发信号同时到达对应的数据处理器件，进而实现量子比特控制相应操作的同步进行。本申请提出的背板、VPX机箱以及量子控制系统，与所述量子比特控制用功能板卡属于同一发明构思，因此具有相同的有益效果，在此不做赘述。
基于以上校准方法可以有效实现量子控制系统的触发同步，另外，通过同一个参考时钟给控制器件以及路由器件提供参考时钟信号，可以使得量子控制系统中的各个器件均在同一个时序下执行相关动作，进一步保证了校准方法的精度，同时降低了量子控制系统触发同步校准的难度。本申请提出的量子控制系统的触发同步系统、量子控制系统以及可读存储介质，与所述量子控制系统的触发同步校准方法属于同一发明构思，因此具有相同的有益效果，在此不做赘述。
附图说明
图1为本申请实施例提出的一种同步触发系统的结构示意图；
图2为图1中中控设备的结构示意图；
图3为本申请另一实施例提出的一种同步触发方法的流程示意图；
图4为本申请实施例提出的一种量子比特控制用功能板卡的结构示意图；
图5为本申请实施例提出的一种量子控制系统的触发同步校准方法的流程示意图；
图6为本申请另一实施例提出的一种量子控制系统的触发同步系统的结构示意图。
其中，100-中控设备，200-路由板卡，300-功能板卡，301-与门芯片，302-数据处理器件，303-功能器件，400-参考时钟，1100-板卡主体，2100-与门芯片，3100-数据处理器件，4100-功能器件。
具体实施方式
下面将结合示意图对本申请的具体实施方式进行更详细的描述。根据下列描述和权利要求书，本申请的优点和特征将更清楚。需说明的是，附图均采用非常简化的形式且均使用非精准的比例，仅用以方便、明晰地辅助说明本申请实施例的目的。
在本申请的描述中，需要理解的是，术语“中心”、“上”、“下”、“左”、“右”等指示的方位或者位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，“多个”的含义是至少两个，例如两个，三个等，除非另有明确具体的限定。
对现在市场上已有的一些量子计算机而言，大都采用上位机、量子控制系统以及量子芯片的组合来实现一些量子计算任务，一般通过上位机接收用户的量子计算任务，对量子计算任务进行处理并形成量子线路，然后将量子线路映射到对应量子芯片的拓扑结构中。量子线路中包含了本次量子计算任务所需要的量子逻辑门、最终量子计算结果的测量操作以及各个操作的时序，量子控制系统在接收到量子线路中包含的这些信息时，会将这些信息转化成相应指令以使得相应的硬件设备进行操作并完成量子计算任务。
一般地，一个量子芯片上设有多个量子比特(也可称之为量子位)以及数据传输线，每个量子比特包括相互耦合连接的探测器和量子比特装置，其中，量子比特装置可以为利用超导约瑟夫森结和对地电容构成的人造超导量子比特，探测器可以为谐振腔。量子比特装置上设置有第一控制信号线和第二控制信号线，与量子比特装置耦合连接的探测器上设有第三控制信号线，其中，第一控制信号线用于传输对量子比特装置进行量子态信息调控的量子态调控信号，第二控制信号线用于传输对量子比特装置进行频率参数调控的频率调控信号，而第三控制信号线既用于传输对探测器进行测量读取的测量信号又用于将探测器返回的读取回传信号输出，以实现对量子比特装置状态的间接读取测量。因此，用于量子芯片中量子比特调控和测量的量子控制系统需要生成并输出三种控制信号分别提供给第一至第三控制信号线，以实现对量子芯片中量子比特的调控和测量。
申请人在实际应用时发现，由于量子计算任务中包含的量子逻辑门需要在对应的量子比特退相干之前完成，因此，在进行量子芯片在处理量子计算任务时对控制信号的精度要求很高。在执行量子计算任务时，往往需要同时对多个量子比特进行调控或读取操作，此时就需要保证量子控制系统输出给多个量子比特的信号可以同步触发。
基于上述发现，为了确保发送给多个量子比特的信号可以同步触发，本申请实施例提供一种同步触发系统，请参考图1，包括：中控设备100，连接若干个路由板卡200，用于提供若干组触发信号给对应的路由板卡200，并通过调整每组触发信号输出的初始时刻以使每个所述机箱接收到所述触发信号的时刻相同。若干个路由板卡200，每个所述路由板卡200连接若干个功能板卡300，每个路由板卡200到连接的所述若干个功能板卡300的通信线路等长，所述路由板卡200用于转发所述触发信号到所述功能板卡300。若干个功能板卡300，每个所述功能板卡300具有与门芯片301以及若干个数据处理器件302，所述触发信号经所述与门芯片301的与操作处理后同时到达所述若干个数据处理器件302以同步触发所述数据处理器件302。
与现有技术不同之处在于，本实施例提出的同步触发系统，包括中控设备100、若干个路由板卡200以及若干个功能板卡300，通过三级触发同步系统确保触发信号的同步触发，其中，第一级为：中控设备100提供若干组触发信号给对应的路由板卡200，并通过调整每组触发信号输出的初始时刻以使每个所述机箱接收到所述触发信号的时刻相同；第二级为：每个路由板卡200到连接的所述若干个功能板卡300的通信线路等长；第三级为：所述触发信号经所述与门芯片301的与操作处理后同时到达所述若干个数据处理器件302以同步触发所述数据处理器件302。
进一步地，请继续参考图1，由于硬件设备需要按照一定时序进行工作，为了使得同步触发系统中的硬件设备按照同一时钟工作，所述同步触发系统还包括参考时钟400，所述参考时钟400用于给所述中控设备100以及所述路由板卡200提供参考时钟400信号，所述参考时钟400还用于给所述功能板卡300提供参考时钟400信号。
需要注意的是，在本实施例中提出的所述参考时钟400可为原子钟，原子钟一种精度极高的计时装置，原子钟有多种类型，例如铯原子钟、氢原子钟、铷原子钟、CPT原子钟等。在本实施例中，所述参考时钟400优选为铷原子钟，在其他实施例中，还可选择其它类型的原子钟，在此不做限制，可根据实际需要来选择。另外，所述数据处理器件302为具有数据转发与处理功能的器件，一般可选用FPGA(Field Programmable Gate Array)、MCU(Microcontroller Unit)、MPU(Microprocessor Unit)或DSP(Digital Signal Processor)等。在本实施例中，所述数据处理器件302优选为FPGA，在其他实施例中还可选用其它具有类似数据处理功能的器件，在此不做限制。所述中控设备100为具有数据处理能力的智能器件，例如，可以为FPGA、MCU、MPU或DSP等，在本实施例中，所述中控设备100优选为FPGA。
本领域技术人员可以理解的是，任何硬件设备能提供的接口总是有限的，可以预见的是，在未来大规模或超大规模量子芯片研发成功后，需要控制的量子比特数量也会随之成指数级增加，此时，同步触发系统需要保证大量的量子比特的同步触发。本申请提出的同步触发系统可以在一定程度上满足大规模量子芯片的需求，我们只需要按照上述提出的结构中进行扩展即可，具体可为增加所述中控设备100的数量，且所有的所述中控设备100均基于同一个参考时钟400的参考时钟400信号进行工作。当然，由于参考时钟400的通道数也是有限的，因此，在一个参考时钟400的通道数不够用时，可采用多个参考时钟400共同提供参考时钟400信号，其中一个参考时钟400作为主时钟，其余所有参考时钟400作为从时钟，主时钟用于给所有的从时钟提供参考时钟400，从时钟则用于给同步触发系统中的硬件提供参考时钟400信号，以上可以理解为本申请提出的同步触发系统的横向扩展。另外，本申请提出的同步触发系统还可进行纵向扩展，具体地，在本实施例中，所述中控设备可为具有数据处理能力的智能器件，在解决大量量子比特的同步触发情形时，所述中控设备还可以为是具有数据处理能力的智能器件连接若干个路由器件构成，请参考图2，所述路由器件下面连接若干个路由板卡，以此结构也可以满足大量量子比特的同步触发需求。需要注意的是，以上仅是一种示例性说明，除了上述方案外，还有很多其它类似的方案，在此不一一赘述，在面临大规模量子芯片时的具体解决方式可根据实际需要来选择。
进一步地，在所述同步触发系统的第一级同步中，所述中控设备100会对发送所述路由板卡200的触发信号进行发送初始时刻的校准。具体地，所述路由板卡200用于基于所述触发信号输出反馈信号给所述中控设备100。所述中控设备100还用于获取第一时间集合，其中，所述第一时间集合为从所述中控设备100输出所述触发信号到所述中控设备100接收到来自各个所述路由板卡200的所述反馈信号分别消耗的时间集合。所述中控设备100还用于在当所述第一时间集合中各个元素不完全相等时，基于所述第一时间集合校准所述中控设备100发送给各个所述路由板卡200的触发信号的初始时刻。
本实施例提出的同步触发系统，中控设备100基于参考时钟400提供的参考时钟400信号输出触发信号给多个路由板卡200；所述多个路由板卡200基于所述参考时钟400信号以及所述触发信号分别输出所 述反馈信号，获取第一时间集合；当所述第一时间集合中各个元素不完全相等时，基于所述第一时间集合校准所述中控设备100发送给各个所述路由板卡200的触发信号的初始时刻。基于以上校准过程可以有效实现触发同步，另外，通过同一个参考时钟400给中控设备100以及路由板卡200提供参考时钟400信号，可以使得量子控制系统中的各个器件均在同一个时序下执行相关动作，进一步保证了校准过程的精度，同时降低了保证量子控制系统触发同步校准的难度。
所有的路由板卡200均以所述参考时钟400提供的参考时钟400信号作为基准进行同步动作，如果所述路由板卡200在接收到所述触发信号时立即返回输出所述反馈信号很有可能会导致时钟时序混乱，由于所述路由板卡200是按照一定时序进行工作，在接收到所述触发信号时刻，需要先消耗一段时间来处理接收到的信息。例如，我们假设所述路由板卡200设定在时钟时序的上升沿触发工作，如果当前所述路由板卡200在时钟时序的下降沿接收到所述触发信号，此时如果直接返回信号那么由于路由板卡200实际上并未接收到所述触发信号，因此，返回到所述中控设备100的信号必然会有误，最终导致的结果就是对于量子控制系统的触发同步校准不精确。申请人考虑将所有的路由板卡200在接收到所述触发信号后，均等待一定时钟周期，然后在返回所述反馈信号，这样可以有效解决以上问题。
基于以上构思，所述多个路由板卡200基于所述参考时钟400信号以及所述触发信号分别输出反馈信号，所述多个路由板卡200接收到所述触发信号，均等待第二时间后所述多个路由板卡200基于所述参考时钟400信号分别输出反馈信号。
在本实施例中，所述第二时间可以为若干个所述参考时钟400的时钟周期。
由于仅依靠一次校准过程达到的触发同步精度可能无法满足量子计算的需要，为了提高触发同步的精度，申请人提出以下方案，基于校准后的初始时刻，返回执行所述中控设备100基于参考时钟400信号按照设定好的初始时刻输出触发信号给多个路由板卡200，直至所述第一时间集合中各个元素均相等。
利用所述第一时间集合调整所述中控设备100发送给各个所述路由板卡200的触发信号的初始时刻的方案可根据实际需要来选择，在本实施例中提供三种优选方案供选择，本实施例提出的三种方案为优选实施方案，在实际应用时还可选择其它方案，在此不一一赘述。以下具体说明这三种优选方案：
第一种方案为：
基于所述第一时间集合，获取第三时间集合，其中，所述第三时间集合为从所述中控设备100输出所述触发信号到各个所述路由板卡200接收到所述触发信号各自所消耗的时间集合；
获取所述第三时间集合中时间最长的时间为第四时间；
基于所述第四时间调整所述中控设备100发送给各个所述路由板卡200的触发信号的初始时刻。
具体地，所述第四时间对应的所述路由板卡200为所述第一路由板卡200；所述基于所述第四时间调整所述中控设备100发送给各个所述路由板卡200的触发信号的初始时刻，可包括：
将所述中控设备100输出所述触发信号给所述多个路由板卡200中除第一路由板卡200外的所有路由板卡200的初始时刻做延迟发送处理，以使所述中控设备100输出的所述触发信号到达各个所述路由板卡200的时刻相同。
第二种方案为：
基于所述第一时间集合，获取第三时间集合，其中，所述第三时间集合为从所述中控设备100输出所述触发信号到各个所述路由板卡200接收到所述触发信号各自所消耗的时间集合；
获取所述第三时间集合中时间最短的时间为第五时间；
基于所述第五时间调整所述中控设备100发送给各个所述路由板卡200的触发信号的初始时刻。
具体地，所述第五时间对应的所述路由板卡200为所述第二路由板卡200；所述基于所述第五时间调整所述中控设备100发送给各个所述路由板卡200的触发信号的初始时刻，可包括：
将所述中控设备100输出所述触发信号给所述多个路由板卡200中除第二路由板卡200外的所有路由板卡200的初始时刻做提前发送处理，以使所述中控设备100输出的所述触发信号到达各个所述路由板卡200的时刻相同。
第三种方案为：
基于所述第一时间集合，获取第三时间集合，其中，所述第三时间集合为从所述中控设备100输出所述触发信号到各个所述路由板卡200接收到所述触发信号各自所消耗的时间集合；
获取所述第三时间集合中选定的第三路由板卡200对应的是时间为第六时间；
基于所述第六时间调整所述中控设备100发送给各个所述路由板卡200的触发信号的初始时刻。
具体地，所述基于所述第六时间调整所述中控设备100发送给各个所述路由板卡200的触发信号的初始时刻，可包括：
将所述中控设备100输出所述触发信号给所述多个路由板卡200中除所述第三路由板卡200外的所有路由板卡200的初始时刻做延迟发送处理或提前发送处理，以使所述中控设备100输出的所述触发信号到达各个所述路由板卡200的时刻相同。
在本实施例中，所述第三时间集合中的各个元素通过以下公式获取：
t＝T/2；
其中，t为从所述中控设备100输出所述触发信号到其中一个路由板卡200接收到所述触发信号所消耗的时间，T根据所述第一时间集合中的元素确定。需要注意的是，若多个所述路由板卡200接收到所述触发信号，均等待第二时间时，T＝T1-t2，其中，T1为所述第一时间集合中的元素，t2为所述第二时间。若多个所述路由板卡200接收到所述触发信号，无需等待第二时间时，T＝T1。
本领域技术人员应当理解的是，除了上述描述的三种方案外，还可以有其它类似的方案，在具体实际应用时选择哪种方案可根据需要选择调整，在此不做限制。
另外，在上述三种方案中提到的触发信号为在校准过程中利用的信号，可以是在量子计算的实际应用中使用的信号，但是为了保证量子控制系统的触发同步校准精度足够高，上述三种方案中提到的触发信号也可以不是量子计算中实际应用中使用的信号，特别地，所述触发信号的频率比在量子计算的实际应用中使用的信号的频率要高，例如，若在量子计算的实际应用中使用的信号的频率的1MHz，那么所述触发信号的频率可设置为10MHz。
进一步地，在所述同步触发系统的第二级同步中，每个所述路由板卡200以及连接在所述路由板卡200上的若干个所述功能板卡300设置在同一个机箱中，所述路由板卡200设置在所述机箱的中间位置，若干个所述功能板卡300分别设置在所述路由板卡200的两侧。
进一步地，在所述同步触发系统的第三级同步中，所述功能板卡300还包括板卡主体，其中，所述与门芯片301以及若干个所述数据处理器件302均设置在所述板卡主体上。
本领域技术人员应当理解的是，在本实施例中，所述功能器件303的作用是生成对量子比特进行操控、测量和读取时所需的各种信号。一般可为ADC或DAC，ADC用于获取谐振腔中的信息，DAC则用于生成进行量子态信息调控的量子态调控信号或生成进行频率参数调控的频率调控信号。例如，在实际应用时，在利用量子芯片进行量子计算时，需要在对应的量子比特上执行相应的操作，假设需要对量子比特进行量子态信息调控，而量子比特的调控信号精度要求很高，而且有时会需要同时对多个量子比特进行调控，因此很多时候我们需要多组DAC同时执行相应动作以生成相应的调控信号，这也就需要相应的触发信号能同时触发对应的功能器件303以使其生成我们需要的调控信号并输出给量子芯片中对应的量子比特，利用本实施例的提出的功能板卡300可以有效保证发送给多组DAC的触发信号同步触发其对应的数据处理器件302以实现同步触发多组DAC，最终提高在量子芯片上运行的量子计算的精度。
进一步地，每个所述数据处理器件302通信连接若干个功能器件303，所述功能器件303用于根据所述数据处理器件302的指令执行相应的动作。需要注意的是，图1仅为本实施例的示例性说明，不能理解为对本申请的任何限制，图1中每个所述数据处理器件302仅连接一个功能器件303，在实际应用时，每个所述数据处理器件302可连接多个功能器件303，在此不做限制。本实施例中，每个所述数据处理器件302优选为均连接了四个功能器件303，在具体应用时可以理解为每个FPGA下连接了四个ADC或四个DAC。本领域技术人员应当理解的是，在其它实施例中，每个所述数据处理器件302还可连接其它数量的功能器件303，在此不做限制，可根据实际需要来进行调整。另外，与门芯片301就就近摆放在两个相邻FPGA之间，以最短路径严格等长控制将高速与门芯片301的输出分发连接到两个FPGA。
请继续参考图1，通过与门芯片301连接多个数据处理器件302，可以满足大规模量子芯片的需求，并且由于单个功能板卡300内的多个数据处理器件302需要保证其触发是完全同步的，与门芯片301的结构还可保证多个触发信号同时到达对应的数据处理器件302。
在本申请实施例中，每个所述数据处理器件302均需要一个触发信号，因此，为了保障每个所述数据处理器件302的触发信号均有触发信号，故所述数据处理器件302的数量与所述与门芯片301的输入端数量相等。
需要注意的是，所述数据处理器件302为具有数据转发与处理功能的器件，一般可选用FPGA(Field Programmable Gate Array)、MCU(Microcontroller Unit))、MPU(Microprocessor Unit)或DSP(Digital Signal Processor)等。在本实施例中，所述数据处理器件302优选为FPGA，在其他实施例中还可选用其它具有类似数据处理功能的器件，在此不做限制。
本领域技术人员可以理解的是，所述功能板卡300需要具有对应的功能器件303才能实现对应的功能，例如，需要具有模数转换功能的器件来实现模数转换，需要具有数模转换功能的器件来实现数模转换。而具有模数转换功能的器件可以利用纯电路结构来实现还可利用AD芯片(也即ADC)来实现，同理，具有数模转换功能的器件也可以利用纯电路结构来实现还可利用DA芯片(也即DAC)来实现。在本实施例中，所述功能器件303优选为ADC或DAC。
另外，在本实施例中，所述与门芯片301可根据实际需要进行选型，利用可包括但不限于HMC746、7408TTL、7409TTL、74X11、74X21、CD4081、CD4082，在此不做限制。
具体地，所述板卡主体可以为PCB(Printed Circuit Board)板，所述数据处理器件302、所述与门芯片301以及所述功能器件303均设置在所述PCB板上。
在本实施例中，所述与门芯片301与所述功能器件303优选通过在所述PCB板的顶层信号层走线连接，且所述与门芯片301与所述数据处理器件302通过在所述PCB板的顶层信号层走线连接。当采用顶层信号层走线时，传输线的一侧是介质，一侧是空气，等效介电常数小于中间层，传输线延时较小，这个特点决定了顶层信号层走线可以有更快的信号传输速度，因此可以利用顶层信号层布速度很快的信号，如2.5GHz或3.125GHz，布高速信号时尽量不要打孔，如果实在需要打孔，从顶层打孔换层到底层，或者从底层打孔换层到顶层信号层，也不存在过孔的短截线效应，这个特点也是内层布线所不具备的。
本领域技术人员应当理解的是，除了本实施例中列举的一些部件，所述功能板卡300还具有一些外围电路或器件，例如所述功能板卡300还包括通信接口，所述通信接口设置在所述板卡体上，所述通信接口与所述数据处理器件302连接，还有一些其它器件，在此不一一列举。
请参考图3，基于同一发明构思，本申请实施例还提出一种同步触发方法，包括：
S10：中控设备提供若干组触发信号给对应的路由板卡，并通过调整每组触发信号输出的初始时刻以使每个所述机箱接收到所述触发信号的时刻相同，其中，所述中控设备连接若干个所述路由板卡；
S20：所述路由板卡转发所述触发信号到所述功能板卡的与门芯片，其中，每个所述路由板卡连接若干个功能板卡，每个路由板卡到连接的所述若干个功能板卡的通信线路等长；
S30：所述触发信号经所述与门芯片的与操作处理后同时到达若干个数据处理器件以同步触发所述数据处理器件，其中，所述功能板卡具有所述与门芯片以及若干个所述数据处理器件。
基于同一发明构思，本申请实施例还提出一种量子控制系统，包括上述特征描述中任一项所述的同步触发系统。
一般地，一个量子芯片上设有多个量子比特(也可称之为量子位)以及数据传输线，每个量子比特包括相互耦合连接的探测器和量子比特装置，其中，量子比特装置可以为利用超导约瑟夫森结和对地电容构成的人造超导量子比特，探测器可以为谐振腔。量子比特装置上设置有第一控制信号线和第二控制信号线，与量子比特装置耦合连接的探测器上设有第三控制信号线，其中，第一控制信号线用于传输对量子比特装置进行量子态信息调控的量子态调控信号，第二控制信号线用于传输对量子比特装置进行频率参数调控的频率调控信号，而第三控制信号线既用于传输对探测器进行测量读取的测量信号又用于将探测器返回的读取回传信号输出，以实现对量子比特装置状态的间接读取测量。因此，用于量子芯片中量子比特调控和测量的量子控制系统需要生成并输出三种控制信号分别提供给第一至第三控制信号线，以实现对量子芯片中量子比特的调控和测量。
请参考图4，本申请实施例提出一种量子比特控制用功能板卡，包括板卡主体1100、与门芯片2100、若干个数据处理器件3100以及若干个功能器件4100。所述与门芯片2100设置在所述板卡主体1100上，所述与门芯片2100具有若干个输入端，所述与门芯片2100的输入端用于接收触发信号，所述与门芯片2100的输出端与若干个数据处理器件3100的输入端通信连接，所述与门芯片2100用于使得所述触发信号同时到达所述若干个数据处理器件3100。所述若干个数据处理器件3100间隔设置在所述板卡主体1100上，所述数据处理器件3100用于基于所述触发信号生成工作指令。所述若干个功能器件4100设置在所述板卡主体1100上，与所述数据处理器件3100的输出端通信连接，所述功能器件4100用于基于所述工作指令执行对量子比控制的相应动作。本领域技术人员应当理解的是，在本实施例中，所述功能器件的作用是生成对量子比特进行操控、测量和读取时等控制所需的各种信号。一般可为ADC或DAC，ADC用于获取谐振腔中的信息，DAC则用于生成进行量子态信息调控的量子态调控信号或生成进行频率参数调控的频率调控信号。例如，在实际应用中，在利用量子芯片进行量子计算时，需要在对应的量子比特上执行相应的操作，假设需要对量子比特进行量子态信息调控，而量子比特的调控信号精度要求很高，而且有时会需要同时对多个量子比特进行调控，因此很多时候我们需要多组DAC同时执行相应动作以生成相应的调控信号，这也就需要相应的触发信号能同时触发对应的功能器件以使其生成我们需要的调控信号并输出给量子芯片中对应的量子比特，利用本实施例提出的量子比特控制用功能板卡可以有效保证发送给多组DAC的触发信号同步触发其对应的数据处理器件以实现同步触发多组DAC，最终提高在量子芯片上运行的量子计算的精度。
与现有技术不同之处在于，本申请实施例提出一种量子比特控制用功能板卡，包括板卡主体1100、与门芯片2100、若干个数据处理器件3100以及若干个功能器件4100。所述与门芯片2100设置在所述板卡主体1100上，所述与门芯片2100具有若干个输入端，所述与门芯片2100的输入端用于接收触发信号，所述与门芯片2100的输出端与若干个数据处理器件3100的输入端通信连接，所述与门芯片2100用于使得所述触发信号同时到达所述若干个数据处理器件3100。所述若干个数据处理器件3100间隔设置在所述板卡主体1100上，所述数据处理器件3100用于基于所述触发信号生成工作指令。所述若干个功能器件4100 设置在所述板卡主体1100上，与所述数据处理器件3100的输出端通信连接，所述功能器件4100用于基于所述工作指令执行相应动作。基于以上结构，通过与门芯片2100连接多个数据处理器件3100，可以满足大规模量子芯片的需求，并且由于对于单个量子比特控制用功能板卡内的多个数据处理器件3100需要保证其触发是完全同步的，与门芯片2100的结构还可保证多个触发信号同时到达对应的数据处理器件3100。
在本申请实施例中，每个所述数据处理器件3100均需要一个触发信号，因此，为了保障每个所述数据处理器件3100的触发信号均有触发信号，故所述数据处理器件3100的数量与所述与门芯片2100的输入端数量相等。
需要注意的是，所述数据处理器件3100为具有数据转发与处理功能的器件，一般可选用FPGA(Field Programmable Gate Array)、MCU(Microcontroller Unit))、MPU(Microprocessor Unit)或DSP(Digital Signal Processor)等。在本实施例中，所述数据处理器件3100优选为FPGA，在其他实施例中还可选用其它具有类似数据处理功能的器件，在此不做限制。
本领域技术人员可以理解的是，所述量子比特控制用功能板卡需要具有对应的功能器件4100才能实现对应的功能，例如，需要具有模数转换功能的器件来实现模数转换，需要具有数模转换功能的器件来实现数模转换。而具有模数转换功能的器件可以利用纯电路结构来实现还可利用AD芯片(也即ADC)来实现，同理，具有数模转换功能的器件也可以利用纯电路结构来实现还可利用DA芯片(也即DAC)来实现。在本实施例中，所述功能器件4100优选为ADC或DAC。
另外，在本实施例中，所述与门芯片2100可根据实际需要进行选型，利用可包括但不限于HMC746、7408TTL、7409TTL、74X11、74X21、CD4081、CD4082，在此不做限制。
可选地，每个所述数据处理器件3100均与若干个所述功能器件4100连接。请参考图4，本实施例中，每个所述数据处理器件3100均连接了四个功能器件4100，在具体应用时可以理解为每个FPGA下连接了四个AD芯片或四个DA芯片。本领域技术人员应当理解的是，在其它实施例中，每个所述数据处理器件3100还可连接其它数量的功能器件4100，在此不做限制，可根据实际需要来进行调整。另外，与门芯片2100就就近摆放在两个相邻FPGA之间，以最短路径严格等长控制将高速与门芯片2100的输出分发连接到两个FPGA。
具体地，所述板卡主体1100可以为PCB(Printed Circuit Board)板，所述数据处理器件3100、所述与门芯片2100以及所述功能器件4100均设置在所述PCB板上。
在本实施例中，所述与门芯片2100与所述功能器件4100优选通过在所述PCB板的顶层信号层走线连接，且所述与门芯片2100与所述数据处理器件3100通过在所述PCB板的顶层信号层走线连接。当采用顶层信号层走线时，传输线的一侧是介质，一侧是空气，等效介电常数小于中间层，传输线延时较小，这个特点决定了顶层信号层走线可以有更快的信号传输速度，因此可以利用顶层信号层布速度很快的信号，如2.5GHz或3.125GHz，布高速信号时尽量不要打孔，如果实在需要打孔，从顶层打孔换层到底层，或者从底层打孔换层到顶层信号层，也不存在过孔的短截线效应，这个特点也是内层布线所不具备的。
本领域技术人员应当理解的是，除了本实施例中列举的一些部件，所述量子比特控制用功能板卡还具有一些外围电路或器件，例如所述量子比特控制用功能板卡还包括通信接口，所述通信接口设置在所述板卡体上，所述通信接口与所述数据处理器件3100连接。
基于同一发明构思，本申请实施例还提出一种背板，包括上述特征描述中任一项所述的量子比特控制用功能板卡。
基于同一发明构思，本申请实施例还提出一种VPX机箱，包括上述特征描述中所述的背板。
基于同一发明构思，本申请实施例还提出一种量子控制系统，包括上述特征描述中任一项所述的量子比特控制用功能板卡。
请参考图5，本申请实施例提出了一种量子控制系统的触发同步校准方法，包括：
S1202：控制器件基于参考时钟信号按照设定好的初始时刻输出触发信号给多个路由器件，其中，所述参考时钟信号通过参考时钟提供；
S1204：所述多个路由器件基于所述参考时钟信号以及所述触发信号分别输出反馈信号；
S1206：获取第一时间集合，其中，所述第一时间集合为从所述控制器件输出所述触发信号到所述控制器件接收到来自各个所述路由器件的所述反馈信号分别消耗的时间集合；
S1208：当所述第一时间集合中各个元素不完全相等时，基于所述第一时间集合校准所述控制器件发送给各个所述路由器件的触发信号的初始时刻。
与现有技术不同之处在于，本实施例提出的量子控制系统的触发同步校准方法，控制器件基于参考时钟提供的参考时钟信号输出触发信号给多个路由器件；所述多个路由器件基于所述参考时钟信号以及所述触发信号分别输出所述反馈信号，获取第一时间集合；当所述第一时间集合中各个元素不完全相等时，基于所述第一时间集合校准所述控制器件发送给各个所述路由器件的触发信号的初始时刻。基于以上校准方法可以有效实现量子控制系统的触发同步，另外，通过同一个参考时钟给控制器件以及路由器件提供参考时钟信号，可以使得量子控制系统中的各个器件均在同一个时序下执行相关动作，进一步保证了校准方法的精度，同时降低了量子控制系统触发同步校准的难度。
在本实施例中，所述触发信号为在校准过程中利用的信号，并非是在量子计算的实际应用中使用的信号，为了保证量子控制系统的触发同步校准精度足够高，特别地，所述触发信号的频率比在量子计算的实际应用中使用的信号的频率要高，例如，若在量子计算的实际应用中使用的信号的频率的1MHz，那么所述触发信号的频率可设置为10MHz。
所有的路由器件均以所述参考时钟提供的参考时钟信号作为基准进行同步动作，如果所述路由器件在接收到所述触发信号时立即返回输出所述反馈信号很有可能会导致时钟时序混乱，由于所述路由器件是按照一定时序进行工作，在接收到所述触发信号的时刻，需要先消耗一段时间来处理接收到的信息。例如，我们假设所述路由器件设定在时钟时序的上升沿触发工作，如果当前所述路由器件在时钟时序的下降沿接收到所述触发信号，此时如果直接返回信号那么由于路由器件实际上并未接收到所述触发信号，因此，返回到所述控制器件的信号必然会有误，最终导致的结果就是对于量子控制系统的触发同步校准不精确。申请人考虑将所有的路由器件在接收到所述触发信号后，均等待一定时钟周期，然后再返回所述反馈信号，这样可以有效解决以上问题。基于以上构思，所述多个路由器件基于所述参考时钟信号以及所述触发信号分别输出反馈信号，也即所述步骤S1204包括：
所述多个路由器件接收到所述触发信号，均等待第二时间后所述多个路由器件基于所述参考时钟信号分别输出反馈信号。
在本实施例中，所述第二时间可以为若干个所述参考时钟的时钟周期。
由于仅依靠一次校准过程达到的触发同步精度可能无法满足量子计算的需要，为了提高触发同步的精度，申请人提出以下方案，所述触发同步校准方法还可包括：
S1210：基于校准后的初始时刻，返回执行所述控制器件基于参考时钟信号按照设定好的初始时刻输出触发信号给多个路由器件，直至所述第一时间集合中各个元素均相等。
在所述量子控制系统的触发同步校准方法的步骤S1208中提高利用所述第一时间集合调整所述控制器 件发送给各个所述路由器件的触发信号的初始时刻的方案可根据实际需要来选择，在本实施例中提供三种优选方案供选择，本实施例提出的三种方案为优选实施方案，在实际应用时还可选择其它方案，在此不一一赘述。以下具体说明这三种优选方案：
可选地，所述基于所述第一时间集合调整所述控制器件发送给各个所述路由器件的触发信号的初始时刻，可包括：
基于所述第一时间集合，获取第三时间集合，其中，所述第三时间集合为从所述控制器件输出所述触发信号到各个所述路由器件接收到所述触发信号各自所消耗的时间集合；
获取所述第三时间集合中时间最长的时间为第四时间；
基于所述第四时间调整所述控制器件发送给各个所述路由器件的触发信号的初始时刻。
具体地，所述第四时间对应的所述路由器件为所述第一路由器件；所述基于所述第四时间调整所述控制器件发送给各个所述路由器件的触发信号的初始时刻，包括：
将所述控制器件输出所述触发信号给所述多个路由器件中除第一路由器件外的所有路由器件的初始时刻做延迟发送处理，以使所述控制器件输出的所述触发信号到达各个所述路由器件的时刻相同。
可选地，所述基于所述第一时间集合调整所述控制器件发送给各个所述路由器件的触发信号的初始时刻，还可包括：
基于所述第一时间集合，获取第三时间集合，其中，所述第三时间集合为从所述控制器件输出所述触发信号到各个所述路由器件接收到所述触发信号各自所消耗的时间集合；
获取所述第三时间集合中时间最短的时间为第五时间；
基于所述第五时间调整所述控制器件发送给各个所述路由器件的触发信号的初始时刻。
具体地，所述第五时间对应的所述路由器件为所述第二路由器件；所述基于所述第五时间调整所述控制器件发送给各个所述路由器件的触发信号的初始时刻，包括：
将所述控制器件输出所述触发信号给所述多个路由器件中除第二路由器件外的所有路由器件的初始时刻做提前发送处理，以使所述控制器件输出的所述触发信号到达各个所述路由器件的时刻相同。
可选地，所述基于所述第一时间集合调整所述控制器件发送给各个所述路由器件的触发信号的初始时刻，还可包括：
基于所述第一时间集合，获取第三时间集合，其中，所述第三时间集合为从所述控制器件输出所述触发信号到各个所述路由器件接收到所述触发信号各自所消耗的时间集合；
获取所述第三时间集合中选定的第三路由器件对应的是时间为第六时间；
基于所述第六时间调整所述控制器件发送给各个所述路由器件的触发信号的初始时刻。
具体地，所述基于所述第六时间调整所述控制器件发送给各个所述路由器件的触发信号的初始时刻，包括：
将所述控制器件输出所述触发信号给所述多个路由器件中除所述第三路由器件外的所有路由器件的初始时刻做延迟发送处理或提前发送处理，以使所述控制器件输出的所述触发信号到达各个所述路由器件的时刻相同。
在本实施例中，所述第三时间集合中的各个元素通过以下公式获取：
t＝T/2；
其中，t为从所述控制器件输出所述触发信号到其中一个路由器件接收到所述触发信号所消耗的时间，T根据所述第一时间集合中的元素确定。需要注意的是，若多个所述路由器件接收到所述触发信号，均等待第二时间时，T＝T 1-t 2，其中，T 1为所述第一时间集合中的元素，t 2为所述第二时间。若多个所述路由器件接收到所述触发信号，无需等待第二时间时，T＝T 1。
本领域技术人员应当理解的是，除了上述描述的三种方案外，还可以有其它类似的方案，在具体实际应用时选择哪种方案可根据需要选择调整，在此不做限制。
在实际应用到量子控制系统时，所述控制器件一般为中控，中控为具有数据处理能力的智能器件，例如，可以为FPGA(Field Programmable Gate Array)、MCU(Microcontroller Unit)、MPU(Microprocessor Unit)或DSP(Digital Signal Processor)等。在本实施例中，所述控制器件优选为FPGA。所述路由器件一般可为路由板卡。为了便于本领域技术人员的理解，以下结合一具体示例来说明本申请的方案：
控制器件向各个路由器件发送触发信号，设该过程耗时t，同时开始以高精度铷钟为参考时钟开始计时，在信号到达路由器件后，各个路由器件都以高精度铷钟作为时钟源做参考动作，路由器件在等待相同的时间t 2后，向控制器件输出反馈信号，设该过程耗时t 1，控制器件在接到反馈信号后停止计时，设该总耗时为T 1。由于用于传输触发信号和传输反馈信号的通信线路都是严格等长设计的，同一组都通过定制的双头SMA连接器，一对用于传输触发信号的通信线路和用于传输反馈信号的通信线路的同轴线缆都是严格控制等长且安装扭力相同，这样控制器件在得到计时结果后，可以开始计算各个路由器件的触发通道的信号延时时间，即单向单路的触发延时为t＝t 1＝(T 1-t 2)/2。当得到每个路由器件与中控器件之间的延时后，可以通过以最长的某一路延迟为基准，调节其他所有路的初始发送信号的延时和提前量，以此循环，最终实现所有触发通路的路由器件都能在同一时刻接到触发信号。
基于同一发明构思，请参考图6，本申请实施例还提出一种量子控制系统的触发同步系统，包括：
参考时钟，其被配置为提供参考时钟信号；
控制器件，其被配置为基于参考时钟信号输出触发信号给多个路由器件；
所述多个路由器件，其被配置为基于所述参考时钟信号以及所述触发信号分别输出所述反馈信号；
所述控制器件还被配置为获取第一时间集合，其中，所述第一时间集合为从所述控制器件输出所述触发信号到所述控制器件接收到来自各个所述路由器件的所述反馈信号分别消耗的时间集合；
所述控制器件还被配置为当所述第一时间集合中各个元素不完全相等时，基于所述第一时间集合校准所述控制器件发送给各个所述路由器件的触发信号的初始时刻。
具体地，所述参考时钟可为原子钟，原子钟一种精度极高的计时装置，原子钟有多种类型，例如铯原子钟、氢原子钟、铷原子钟、CPT原子钟等。在本实施例中，所述参考时钟优选为铷原子钟，在其他实施例中，还可选择其它类型的原子钟，在此不做限制，可根据实际需要来选择。所述控制器件一般为中控，中控为具有数据处理能力的智能器件，例如，可以为FPGA(Field Programmable Gate Array)、MCU(Microcontroller Unit)、MPU(Microprocessor Unit)或DSP(Digital Signal Processor)等。在本实施例中，所述控制器件优选为FPGA，所述路由器件一般可为路由板卡。
基于同一发明构思，本申请实施例还提出一种量子控制系统，利用上述特征描述中任一项所述的量子控制系统的触发同步校准方法，或上述特征描述中所述的量子控制系统的触发同步系统。
基于同一发明构思，本申请实施例还提出一种可读存储介质，其上存储有计算机程序，所述计算机程序被一处理器执行时能实现上述特征描述中任一项所述的量子控制系统的触发同步校准方法。
所述可读存储介质可以是可以保持和存储由指令执行设备使用的指令的有形设备，例如可以是但不限于电存储设备、磁存储设备、光存储设备、电磁存储设备、半导体存储设备或者上述的任意合适的组合。可读存储介质的更具体的例子(非穷举的列表)包括：便携式计算机盘、硬盘、随机存取存储器(RAM)、只读存储器(ROM)、可擦式可编程只读存储器(EPROM或闪存)、静态随机存取存储器(SRAM)、便携式压缩盘只 读存储器(CD-ROM)、数字多功能盘(DVD)、记忆棒、软盘、机械编码设备、例如其上存储有指令的打孔卡或凹槽内凸起结构、以及上述的任意合适的组合。这里所描述的计算机程序可以从可读存储介质下载到各个计算/处理设备，或者通过网络、例如因特网、局域网、广域网和/或无线网下载到外部计算机或外部存储设备。网络可以包括铜传输电缆、光纤传输、无线传输、路由器、防火墙、交换机、网关计算机和/或边缘服务器。每个计算/处理设备中的网络适配卡或者网络接口从网络接收所述计算机程序，并转发该计算机程序，以供存储在各个计算/处理设备中的可读存储介质中。用于执行本申请操作的计算机程序可以是汇编指令、指令集架构(ISA)指令、机器指令、机器相关指令、微代码、固件指令、状态设置数据、或者以一种或多种编程语言的任意组合编写的源代码或目标代码，所述编程语言包括面向对象的编程语言—诸如Smalltalk、C++等，以及常规的过程式编程语言—诸如“C”语言或类似的编程语言。所述计算机程序可以完全地在用户计算机上执行、部分地在用户计算机上执行、作为一个独立的软件包执行、部分在用户计算机上部分在远程计算机上执行、或者完全在远程计算机或服务器上执行。在涉及远程计算机的情形中，远程计算机可以通过任意种类的网络，包括局域网(LAN)或广域网(WAN)，连接到用户计算机，或者，可以连接到外部计算机(例如利用因特网服务提供商来通过因特网连接)。在一些实施例中，通过利用计算机程序的状态信息来个性化定制电子电路，例如可编程逻辑电路、现场可编程门阵列(FPGA)或可编程逻辑阵列(PLA)，该电子电路可以执行计算机可读程序指令，从而实现本申请的各个方面。
这里参照根据本申请实施例的方法、系统和计算机程序产品的流程图和/或框图描述了本申请的各个方面。应当理解，流程图和/或框图的每个方框以及流程图和/或框图中各方框的组合，都可以由计算机程序实现。这些计算机程序可以提供给通用计算机、专用计算机或其它可编程数据处理装置的处理器，从而生产出一种机器，使得这些程序在通过计算机或其它可编程数据处理装置的处理器执行时，产生了实现流程图和/或框图中的一个或多个方框中规定的功能/动作的装置。也可以把这些计算机程序存储在可读存储介质中，这些计算机程序使得计算机、可编程数据处理装置和/或其他设备以特定方式工作，从而，存储有该计算机程序的可读存储介质则包括一个制造品，其包括实现流程图和/或框图中的一个或多个方框中规定的功能/动作的各个方面的指令。
也可以把计算机程序加载到计算机、其它可编程数据处理装置、或其它设备上，使得在计算机、其它可编程数据处理装置或其它设备上执行一系列操作步骤，以产生计算机实现的过程，从而使得在计算机、其它可编程数据处理装置、或其它设备上执行的计算机程序实现流程图和/或框图中的一个或多个方框中规定的功能/动作。
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示例”或“具体示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本申请的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不必须针对的是相同的实施例或示例。而且描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施例中以合适的方式结合。此外，本领域的技术人员可以将本说明书中描述的不同实施例或示例进行接合和组合。
上述仅为本申请的优选实施例而已，并不对本申请起到任何限制作用。任何所属技术领域的技术人员，在不脱离本申请的技术方案的范围内，对本申请揭露的技术方案和技术内容做任何形式的等同替换或修改等变动，均属未脱离本申请的技术方案的内容，仍属于本申请的保护范围之内。

Claims (34)

  1. 一种量子控制系统的同步触发系统，其特征在于，包括：
    中控设备，连接若干个路由板卡，用于提供若干组触发信号给对应的路由板卡，并通过调整每组触发信号输出的初始时刻以使每个机箱接收到所述触发信号的时刻相同；
    若干个路由板卡，每个所述路由板卡连接若干个功能板卡，每个路由板卡到连接的所述若干个功能板卡的通信线路等长，所述路由板卡用于转发所述触发信号到所述功能板卡；
    若干个功能板卡，每个所述功能板卡具有与门芯片以及若干个数据处理器件，所述触发信号经所述与门芯片的与操作处理后同时到达所述若干个数据处理器件以同步触发所述数据处理器件。
  2. 如权利要求1所述的系统，其特征在于，所述同步触发系统还包括：
    参考时钟，用于给所述中控设备以及所述路由板卡提供参考时钟信号。
  3. 如权利要求2所述的系统，其特征在于，所述参考时钟还用于给所述功能板卡提供参考时钟信号。
  4. 如权利要求2所述的系统，其特征在于，所述中控设备的数量为至少两个，至少两个所述中控设备均基于同一个所述参考时钟的参考时钟信号进行工作。
  5. 如权利要求1所述的系统，其特征在于，所述路由板卡用于基于所述触发信号输出反馈信号给所述中控设备；
    所述中控设备还用于获取第一时间集合，其中，所述第一时间集合为从所述中控设备输出所述触发信号到所述中控设备接收到来自各个所述路由板卡的所述反馈信号分别消耗的时间集合；
    所述中控设备还用于在当所述第一时间集合中各个元素不完全相等时，基于所述第一时间集合校准所述中控设备发送给各个所述路由板卡的触发信号的初始时刻。
  6. 如权利要求1所述的系统，其特征在于，每个所述路由板卡以及连接在所述路由板卡上的若干个所述功能板卡设置在同一个机箱中，所述路由板卡设置在所述机箱的中间位置，若干个所述功能板卡分别设置在所述路由板卡的两侧。
  7. 如权利要求1所述的系统，其特征在于，所述功能板卡还包括板卡主体，其中，所述与门芯片以及若干个所述数据处理器件均设置在所述板卡主体上。
  8. 如权利要求7所述的系统，其特征在于，所述与门芯片具有若干个输入端，所述与门芯片的输入端用于接收触发信号，所述与门芯片的输出端与若干个数据处理器件的输入端通信连接，所述与门芯片用于使得所述触发信号同时到达所述若干个数据处理器件。
  9. 如权利要求7所述的系统，其特征在于，若干个数据处理器件，间隔设置在所述板卡主体上。
  10. 如权利要求7所述的系统，其特征在于，每个所述数据处理器件通信连接若干个功能器件，所述功能器件用于根据所述数据处理器件的指令执行相应的动作。
  11. 如权利要求10所述的系统，其特征在于，若干个功能器件，设置在所述板卡主体上。
  12. 如权利要求7-11任一项所述的系统，其特征在于，所述功能板卡还包括通信接口，所述通信接口设置在所述板卡体上，所述通信接口与所述数据处理器件连接。
  13. 如权利要求7-11任一项所述的系统，其特征在于，所述板卡主体包括PCB板，所述数据处理器件、所述与门芯片以及所述功能器件均设置在所述PCB板上。
  14. 如权利要求13所述的系统，其特征在于，所述与门芯片与所述功能器件通过在所述PCB板的顶层信号层走线连接。
  15. 如权利要求13所述的系统，其特征在于，所述与门芯片与所述数据处理器件通过在所述PCB板的顶层信号层走线连接。
  16. 如权利要求13所述的系统，其特征在于，所述数据处理器件的数量与所述与门芯片的输入端数量相等。
  17. 如权利要求13所述的系统，其特征在于，每个所述数据处理器件均与若干个所述功能器件连接。
  18. 如权利要求7所述的系统，其特征在于，所述与门芯片设置在所述板卡主体上相邻两个所述数据处理器件之间。
  19. 如权利要求7所述的系统，其特征在于，所述功能器件包括ADC或DAC。
  20. 如权利要求7所述的系统，其特征在于，所述数据处理器件包括FPGA或MCU或MPU或DSP。
  21. 一种量子控制系统的同步触发方法，其特征在于，包括：
    中控设备提供若干组触发信号给对应的路由板卡，并通过调整每组触发信号输出的初始时刻以使每个机箱接收到所述触发信号的时刻相同，其中，所述中控设备连接若干个所述路由板卡；
    所述路由板卡转发所述触发信号到所述功能板卡的与门芯片，其中，每个所述路由板卡连接若干个功能板卡，每个路由板卡到连接的所述若干个功能板卡的通信线路等长；
    所述触发信号经所述与门芯片的与操作处理后同时到达若干个数据处理器件以同步触发所述数据处理器件，其中，所述功能板卡具有所述与门芯片以及若干个所述数据处理器件。
  22. 根据权利要求21所述的方法，其特征在于，所述中控设备提供若干组触发信号给对应的路由板卡，并通过调整每组触发信号输出的初始时刻以使每个机箱接收到所述触发信号的时刻相同，包括：
    控制器件基于参考时钟信号按照设定好的初始时刻输出触发信号给多个路由器件，其中，所述参考时钟信号通过参考时钟提供；
    所述多个路由器件基于所述参考时钟信号以及所述触发信号分别输出反馈信号；
    获取第一时间集合，其中，所述第一时间集合为从所述控制器件输出所述触发信号到所述控制器件接收到来自各个所述路由器件的所述反馈信号分别消耗的时间集合；
    当所述第一时间集合中各个元素不完全相等时，基于所述第一时间集合校准所述控制器件发送给各个所述路由器件的触发信号的初始时刻。
  23. 根据权利要求22所述的方法，其特征在于，所述多个路由器件基于所述参考时钟信号以及所述触发信号分别输出反馈信号，包括：
    所述多个路由器件接收到所述触发信号，均等待第二时间后所述多个路由器件基于所述参考时钟信号分别输出反馈信号。
  24. 如权利要求23所述的方法，其特征在于，所述第二时间为若干个所述参考时钟的时钟周期。
  25. 如权利要求22所述的方法，其特征在于，所述方法还包括：
    基于校准后的初始时刻，返回执行所述控制器件基于参考时钟信号按照设定好的初始时刻输出触发信号给多个路由器件，直至所述第一时间集合中各个元素均相等。
  26. 如权利要求22所述的方法，其特征在于，所述基于所述第一时间集合调整所述控制器件发送给各个所述路由器件的触发信号的初始时刻，包括：
    基于所述第一时间集合，获取第三时间集合，其中，所述第三时间集合为从所述控制器件输出所述触发信号到各个所述路由器件接收到所述触发信号各自所消耗的时间集合；
    获取所述第三时间集合中时间最长的时间为第四时间；
    基于所述第四时间调整所述控制器件发送给各个所述路由器件的触发信号的初始时刻。
  27. 如权利要求26所述的方法，其特征在于，所述第四时间对应的所述路由器件为所述第一路由器件；所述基于所述第四时间调整所述控制器件发送给各个所述路由器件的触发信号的初始时刻，包括：
    将所述控制器件输出所述触发信号给所述多个路由器件中除第一路由器件外的所有路由器件的初始时刻做延迟发送处理，以使所述控制器件输出的所述触发信号到达各个所述路由器件的时刻相同。
  28. 如权利要求22所述的方法，其特征在于，所述基于所述第一时间集合调整所述控制器件发送给各个所述路由器件的触发信号的初始时刻，包括：
    基于所述第一时间集合，获取第三时间集合，其中，所述第三时间集合为从所述控制器件输出所述触发信号到各个所述路由器件接收到所述触发信号各自所消耗的时间集合；
    获取所述第三时间集合中时间最短的时间为第五时间；
    基于所述第五时间调整所述控制器件发送给各个所述路由器件的触发信号的初始时刻。
  29. 如权利要求28所述的方法，其特征在于，所述第五时间对应的所述路由器件为所述第二路由器件；所述基于所述第五时间调整所述控制器件发送给各个所述路由器件的触发信号的初始时刻，包括：
    将所述控制器件输出所述触发信号给所述多个路由器件中除第二路由器件外的所有路由器件的初始时刻做提前发送处理，以使所述控制器件输出的所述触发信号到达各个所述路由器件的时刻相同。
  30. 如权利要求22所述的方法，其特征在于，所述基于所述第一时间集合调整所述控制器件发送给各个所述路由器件的触发信号的初始时刻，包括：
    基于所述第一时间集合，获取第三时间集合，其中，所述第三时间集合为从所述控制器件输出所述触发信号到各个所述路由器件接收到所述触发信号各自所消耗的时间集合；
    获取所述第三时间集合中选定的第三路由器件对应的是时间为第六时间；
    基于所述第六时间调整所述控制器件发送给各个所述路由器件的触发信号的初始时刻。
  31. 如权利要求30所述的方法，其特征在于，所述基于所述第六时间调整所述控制器件发送给各个所述路由器件的触发信号的初始时刻，包括：
    将所述控制器件输出所述触发信号给所述多个路由器件中除所述第三路由器件外的所有路由器件的初始时刻做延迟发送处理或提前发送处理，以使所述控制器件输出的所述触发信号到达各个所述路由器件的时刻相同。
  32. 如权利要求26至31中任一项所述的方法，其特征在于，所述第三时间集合中的各个元素通过以下公式获取：
    t＝T/2；
    其中，t为从所述控制器件输出所述触发信号到其中一个路由器件接收到所述触发信号所消耗的时间，T根据所述第一时间集合中的元素确定。
  33. 一种量子控制系统，其特征在于，利用权利要求1-20中任一项所述的量子控制系统的同步触发系统，或包括权利要求21-32任一项所述的量子控制系统的同步触发方法。
  34. 一种量子计算机，其特征在于，包括权利要求33所述的量子控制系统。
PCT/CN2022/127936 2021-12-23 2022-10-27 同步触发系统和方法、量子控制系统和量子计算机 WO2023116190A1 (zh)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
CN202111587715.8A CN116401200A (zh) 2021-12-23 2021-12-23 量子比特控制用功能板卡、背板以及量子控制系统
CN202111587945.4A CN116400615A (zh) 2021-12-23 2021-12-23 同步触发系统和方法、量子控制系统
CN202111587715.8 2021-12-23
CN202111588000.4 2021-12-23
CN202111588000.4A CN116400776A (zh) 2021-12-23 2021-12-23 量子控制系统的触发同步校准方法以及触发同步系统
CN202111587945.4 2021-12-23

Publications (1)

Publication Number Publication Date
WO2023116190A1 true WO2023116190A1 (zh) 2023-06-29

Family

ID=86901230

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/127936 WO2023116190A1 (zh) 2021-12-23 2022-10-27 同步触发系统和方法、量子控制系统和量子计算机

Country Status (1)

Country Link
WO (1) WO2023116190A1 (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014134710A (ja) * 2013-01-11 2014-07-24 Research Organization Of Information & Systems イジングモデルの量子計算装置及びイジングモデルの量子計算方法
CN104156036A (zh) * 2014-07-08 2014-11-19 北京中科泛华测控技术有限公司 多板卡同步互连方法和主板卡、从板卡
CN108777668A (zh) * 2018-06-08 2018-11-09 烽火通信科技股份有限公司 一种三层交换机的路由资源控制方法及系统
CN112990471A (zh) * 2019-12-17 2021-06-18 霍尼韦尔国际公司 量子计算机相位跟踪和校正
CN216596285U (zh) * 2021-10-29 2022-05-24 合肥本源量子计算科技有限责任公司 一种量子控制装置和量子控制系统

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014134710A (ja) * 2013-01-11 2014-07-24 Research Organization Of Information & Systems イジングモデルの量子計算装置及びイジングモデルの量子計算方法
CN104156036A (zh) * 2014-07-08 2014-11-19 北京中科泛华测控技术有限公司 多板卡同步互连方法和主板卡、从板卡
CN108777668A (zh) * 2018-06-08 2018-11-09 烽火通信科技股份有限公司 一种三层交换机的路由资源控制方法及系统
CN112990471A (zh) * 2019-12-17 2021-06-18 霍尼韦尔国际公司 量子计算机相位跟踪和校正
CN216596285U (zh) * 2021-10-29 2022-05-24 合肥本源量子计算科技有限责任公司 一种量子控制装置和量子控制系统

Similar Documents

Publication Publication Date Title
US20150236700A1 (en) Clock management block
US9153539B2 (en) Ground-referenced single-ended signaling connected graphics processing unit multi-chip module
US8898216B2 (en) Distributed data acquisition and processing system and method
US8854123B1 (en) On-package multiprocessor ground-referenced single-ended interconnect
Boyarinov et al. The CLAS12 data acquisition system
US20140281383A1 (en) Ground-referenced single-ended signaling connected graphics processing unit multi-chip module
CN110222001B (zh) 基于PXIe机箱的反馈控制系统及反馈控制方法
US10950281B2 (en) Electronic device comprising storage devices transmitting reference clock via cascade coupling structure
EP1506503A2 (en) Method and apparatus for optimizing distributed multiplexed bus interconnects
Anulli et al. The level-1 trigger muon barrel system of the ATLAS experiment at CERN
US8593176B2 (en) One phase logic
CN105162437A (zh) 一种波形发生装置及方法
CN216596285U (zh) 一种量子控制装置和量子控制系统
WO2023116190A1 (zh) 同步触发系统和方法、量子控制系统和量子计算机
US8638138B2 (en) Hierarchical global clock tree
KR20230116903A (ko) 클럭 동기화를 위한 방법 및 이종 컴퓨팅 시스템
Turqueti et al. CAPTAN: A hardware architecture for integrated data acquisition, control, and analysis for detector development
CN116137535B (zh) 并串转换电路及并串转换时钟信号的生成方法
CN115936130A (zh) 基于fpga的多片dac脉冲输出同步与相位调节方法及系统
JP7355983B2 (ja) マルチビット量子フィードバック制御のための量子測定・制御システム
López et al. A white-rabbit network interface card for synchronized sensor networks
CN116400615A (zh) 同步触发系统和方法、量子控制系统
Song et al. A high-precision synchronous sampling approach for large-scale distributed Wire sensor networks in seismic data acquisition systems
US20110058570A1 (en) Programmable crossbar structures in asynchronous systems
JP2022529634A (ja) スイッチ漏れ補償回路

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22909508

Country of ref document: EP

Kind code of ref document: A1