WO2023116008A1 - 占空比调节电路及输出电路 - Google Patents

占空比调节电路及输出电路 Download PDF

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WO2023116008A1
WO2023116008A1 PCT/CN2022/114170 CN2022114170W WO2023116008A1 WO 2023116008 A1 WO2023116008 A1 WO 2023116008A1 CN 2022114170 W CN2022114170 W CN 2022114170W WO 2023116008 A1 WO2023116008 A1 WO 2023116008A1
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current mode
mode logic
differential signal
duty ratio
circuit
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PCT/CN2022/114170
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English (en)
French (fr)
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杨一帆
王悦
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普源精电科技股份有限公司
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Publication of WO2023116008A1 publication Critical patent/WO2023116008A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern

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  • the invention relates to the field of integrated circuits, in particular to a duty ratio adjustment circuit and an output circuit.
  • Differential signals are often used in integrated circuits, and the duty cycle adjustment of differential signals is a problem that developers need to pay attention to.
  • an analog duty ratio adjustment circuit for duty ratio adjustment can be controlled by a digital-to-analog converter (Digital to Analog Converter, DAC).
  • DAC Digital to Analog Converter
  • the design of the duty ratio adjustment circuit controlled by the digital-to-analog converter DAC is complicated, and the layout takes up more resources.
  • the present invention provides a duty ratio adjustment circuit and an output circuit with simpler designs.
  • the present invention provides a duty ratio adjustment circuit, and the duty ratio adjustment circuit includes:
  • the current mode logic module includes at least two current mode logic circuits, the at least two current mode logic circuits have different adjustment degrees to the duty cycle of the differential signal, and the current mode logic circuit is connected to the input module , to receive the initial differential signal input by the input module;
  • An output module is connected to at least one of the current mode logic circuits to output a target differential signal, and the target differential signal is a differential signal adjusted by the initial differential signal through at least one of the current mode logic circuits .
  • the present invention provides an output circuit, including an initial differential signal and the duty cycle adjustment circuit as described in any one of the above items, the initial differential signal is input to the duty cycle adjustment circuit through the input module, According to the duty cycle of the initial differential signal, select one of the current mode logic circuits in the duty cycle adjustment circuit to adjust the duty cycle of the initial differential signal, and the output module is used to output The target differential signal that meets the preset duty cycle conditions.
  • each current mode logic circuit adjusts the duty ratio of the differential signal to a different degree, so that the duty ratio adjustment circuit can accurately and flexibly adjust the duty ratio adjustment range of the initial differential signal, Simple design, high reproducibility, more convenient in layout design.
  • FIG. 1 is a schematic structural diagram of a first implementation of a duty ratio adjustment circuit according to an embodiment of the present invention
  • FIG. 2 is a schematic structural diagram of a second implementation manner of a duty ratio adjustment circuit according to an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of a waveform of a target differential signal obtained through a single current mode logic circuit in an embodiment of the present invention
  • FIG. 4 is another schematic diagram of a waveform of a target differential signal obtained through a single current mode logic circuit in an embodiment of the present invention.
  • 100-duty ratio adjustment circuit 10-input module; 20-output module; 30-current mode logic module; 31-first current mode logic circuit; 32-second current mode logic circuit; 33-third current mode logic Circuit; 3N-the Nth current mode logic circuit;
  • VCC-power supply terminal GND-ground terminal; Q-transistor; Rc-collector resistance; Idc-current source; MUX-multiplexer; VC-switch; VC 1 -first switch; - second switch; VIP - first input terminal; VIN - second input terminal; VOP - first output terminal; VON - second output terminal.
  • the duty ratio adjustment includes a digital duty ratio adjustment circuit based on a complementary metal oxide semiconductor (Complementary Metal-Oxide-SemicoNductor, CMOS) circuit and a digital-to-analog converter (Digital to Analog Converter, DAC) to control the duty cycle Analog duty cycle adjustment circuit for duty cycle adjustment.
  • CMOS complementary metal oxide semiconductor
  • DAC Digital to Analog Converter
  • an embodiment of the present invention provides a duty ratio adjustment circuit 100 .
  • an embodiment of the present invention provides a duty ratio adjustment circuit 100 , including an input module 10 , a current mode logic module 30 and an output module 20 .
  • the input module 10 is used for inputting the differential signal source to the current mode logic module 30 .
  • the current mode logic module 30 includes at least two current mode logic circuits. In FIG. Take this as an example. When the first current mode logic circuit 31 , the second current mode logic circuit 32 , the third current mode logic circuit 33 and the Nth current mode logic circuit 3N work, they adjust the duty cycle of the differential signal to different degrees.
  • the current module logic circuit is connected to the input module 10 to receive the initial differential signal input by the input module 10, and the output module 20 is connected to at least one current mode logic circuit to output the target differential signal, and the target differential signal is the initial differential signal via The current mode logic circuit regulates the differential signal.
  • the second current mode logic circuit 32 in FIG. 1 is connected to the input module 10, and the output module 20 is connected to the second current mode logic circuit 32 for outputting a target differential signal.
  • the target differential signal is the initial differential signal passed through the second current mode Logic circuit 32 conditions the differential signal.
  • first current mode logic circuit 31, the second current mode logic circuit 32, the third current mode logic circuit 33 and the Nth current mode logic circuit 3N are all connected to the input module 10, or the first current mode logic circuit The circuit 31 , the second current mode logic circuit 32 , the third current mode logic circuit 33 and the Nth current mode logic circuit 3N are all connected to the output module 20 .
  • the first current mode logic circuit 31, the second current mode logic circuit 32, the third current mode logic circuit 33 and the Nth current mode logic circuit 3N work on the duty of the differential signal
  • the degree of adjustment of the ratio is different, so that the duty cycle can be adjusted by one of the current mode logic circuits after the initial differential signal input.
  • different current mode logic circuits can be selected to adjust the duty cycle of the differential signal to different degrees according to the degree of difference in duty cycle between the initial differential signal and the target differential signal; or The duty cycle of the initial differential signal is adjusted to different degrees to obtain different target differential signals.
  • each current mode logic circuit adjusts the duty cycle of the differential signal to a different degree, and the current mode logic circuit that adjusts the duty cycle can be selected according to the needs.
  • the range of the duty cycle adjustment circuit for the initial differential signal can be adjusted accurately and flexibly, and the design is simpler.
  • the current mode logic module 30 includes at least two current mode logic circuits, so it has a higher reproducibility It is more convenient in layout design.
  • the current mode logic circuit can be obtained based on setting different collector resistors in the existing current mode logic (CML, CurreNt Mode Logic). Since CML can be applied to high-frequency signals, the duty cycle adjustment of the present application The circuit 100 may be suitable for high frequency differential signals.
  • each current mode logic circuit adjusts the duty cycle of the differential signal to the same extent or only one current mode logic circuit is set, then only the current mode logic module can realize A single adjustment of the duty ratio; and in the duty ratio adjustment circuit 100 of the present application, in the current mode logic module 30, because each current mode logic circuit adjusts the duty ratio of the differential signal to a different degree, it can be adjusted in the duty ratio adjustment process. Flexible selection of different current mode logic circuits to adjust the initial duty cycle.
  • a current mode logic circuit can be selected in one current mode logic module 30 to adjust the ratio, that is, the initial differential signal can be adjusted to obtain the target differential signal after one adjustment, or the current mode logic circuit can be sequentially selected in multiple current mode logic modules
  • the mode logic circuit adjusts the duty cycle, that is, the initial differential signal can be adjusted multiple times to obtain the target differential signal, therefore, the duty cycle adjustment range is more accurate and flexible.
  • the number of current mode logic circuits in the current mode logic module 30 can be two, three, four or more, etc., as shown in Figure 1 or Figure 2, the current mode logic The circuit is a schematic diagram of N branches.
  • the input module 10 can be connected to one or more current mode logic circuits.
  • the output module 20 can be connected with one or more current mode logic circuits.
  • the target differential signal may be a differential signal obtained by adjusting the initial differential signal through a current mode logic circuit, specifically through a current mode logic circuit in a current mode logic module 30 at a certain moment.
  • only one current mode logic circuit may work at the same time and adjust the duty ratio of the differential signal.
  • the internal structure of the first current mode logic circuit 31, the second current mode logic circuit 32, the third current mode logic circuit 33 and the Nth current mode logic circuit 3N can be the same, and the first current mode logic circuit 31 is used as an example below to illustrate its internal structure.
  • the first current mode logic circuit 31 may include: a power supply terminal VCC, a ground terminal GND, two transistors Q, two collector resistors Rc and a current source Idc.
  • the duty ratio adjustment circuit 100 may include a power supply, which is connected to the power terminal VCC of the first current mode logic circuit 31 and used to provide the first current mode logic circuit 31 with an operating voltage.
  • each collector resistor Rc are respectively connected to the collector of a transistor Q and the power supply terminal VCC, and the two ends of the current source Idc are respectively connected to the emitter of the transistor Q and the ground terminal GND, where the emitters of the two transistors Q are connected, that is, the common emitter is set, the bases of the two transistors Q are connected to the input module 10 , and the collectors of the two transistors Q are connected to the output module 20 .
  • each current mode logic circuit includes two collector resistors Rc, and different current mode logic circuits have different ratios of the two collector resistors Rc. Since the ratio of the two collector resistors Rc in the current mode logic circuit can be used to determine the degree of adjustment to the duty cycle of the differential signal, the ratio of the two collector resistors Rc in each of the current mode logic circuits Different, so that each current mode logic circuit adjusts the duty cycle of the differential signal differently when it works.
  • resistors R 1 , R 2 , R 3 , R 4 ... R 2N-1 , R 2N can be referred to as collector resistors Rc.
  • the collector resistance Rc of the first current mode logic circuit 31 is resistance R 1 , R 2 ;
  • the collector resistance Rc of the second current mode logic circuit 32 is resistance R 3 , R 4 ;
  • the third current mode logic circuit 33 The collector resistor Rc is the resistors R 5 and R 6 ; by analogy, the collector resistor Rc of the Nth current mode logic circuit 3N is the resistors R 2N-1 and R 2N .
  • the ratio of the two collector resistors Rc of each current mode logic circuit can be regularly distributed, for example, two collector resistors Rc in each current mode logic circuit
  • the ratio of the collector resistance Rc can be an arithmetic sequence or a geometric sequence, wherein the step size of the arithmetic sequence or geometric sequence can be 0.1, 0.2, 0.5, 1, 1.2 or 1.5, etc.
  • the ratio of the two collector resistors Rc of each current mode logic circuit may also be irregularly distributed. For example, the ratio of R1 to R2 in the first current mode logic circuit 31 in FIG. 1 or FIG.
  • the ratio distribution of R 2N-1 to R 2N in the Nth current mode logic circuit 3N is any of the following situations: 1, 2, 3...N; N, N-1, N- 2...1; 1, 1.1, 1.21...1.1N-1; 1.1N-1, 1.1N-2, 1.1N-3...1.
  • N may be a natural number greater than 3.
  • the duty ratio adjustment circuit 100 may further include a multiplexer MUX, which is used for Select the differential signal regulated by a current mode logic circuit from the current mode logic module 30 as the target differential signal, that is, select a current mode logic circuit from the N current mode logic circuits in FIG. 1 for the duty of the differential signal The ratio is adjusted to output the target differential signal.
  • the multiplexer MUX may include a selection input and a selection output. The selection input terminal is connected to the collectors of all transistors Q in the current mode logic module 30 , and the selection output terminal is connected to the output module 20 .
  • the multiplexer MUX is used to select a differential signal regulated by a current mode logic circuit from the current mode logic module 30 as a target differential signal, and the target differential signal is output through the selection output terminal and the output module 20 .
  • the input module 10 Since the user of the input module 10 inputs a differential signal, according to the characteristics of the differential signal, the input module 10 should have two input terminals, namely the first input terminal VIP and the second input terminal VIN in FIG. 1 or FIG. 2 .
  • the output module 20 has two output terminals, namely the first output terminal VOP and the second output terminal VON in FIG. 1 or FIG. 2 .
  • the selection output terminal also has two terminals, and the selection input terminal has at least four terminals and is an even number.
  • FIG. 2 it is a schematic structural diagram of a second implementation manner of a duty ratio adjustment circuit 100 according to an embodiment of the present invention.
  • a switch VC can be included on each current mode logic circuit, and the switch VC is used to control the conduction or power-off of the current mode logic circuit 31.
  • the current mode logic circuit When the current mode logic circuit is turned on, it can work and then adjust the initial differential signal duty cycle. , when the current mode logic circuit is powered off, the initial differential signal duty cycle cannot be adjusted.
  • a current mode logic module 30 one of the current mode logic circuits is controlled to be turned on by the switch VC to adjust the duty ratio of the initial differential signal, and the other current mode logic circuits are powered off. For example, in FIG.
  • the number of current mode logic circuits is N, including a first current mode logic circuit 31, a second current mode logic circuit 32, a third current mode logic circuit 33...the Nth current mode logic circuit 3N , the second current mode logic circuit 32 is controlled to be turned on through the switch VC to adjust the duty ratio of the initial long signal, and the remaining N-1 current mode logic circuits are kept powered off, that is, the first current mode logic circuit 31 , the third current mode logic circuit 33 . . . the Nth current mode logic circuit 3N all remain in the power-off state.
  • each current mode logic circuit may include two switches VC, one of the two switches VC is connected to the power supply terminal VCC and Between the collector resistor Rc, the other of the two switches VC is connected between the emitter and the current source Idc.
  • first switch VC 1 includes a first switch VC 1 and a second switch
  • the first switch VC 1 is connected between the power supply terminal VCC and the resistors R 1 and R 2 , when the first switch VC 1 is disconnected, the power supply cannot supply power to the transistor Q, and the second switch Connected between the emitter and the current source Idc, the second switch When it is turned off, the current source Idc cannot be connected with the transistor Q, so as to ensure that the first current mode logic circuit 31 from the left in FIG. 2 can be completely powered off without interfering with other current mode logic circuits.
  • the second switch VC 2 also includes the first switch VC 2 and the second switch
  • the first switch VC 2 is connected between the power supply terminal VCC and the resistors R 3 and R 4 , when the first switch VC 2 is disconnected, the power supply cannot supply power to the transistor Q, and the second switch Connected between the emitter and the current source Idc; the third current mode logic circuit 33 and other current mode logic circuits are similarly provided with the first switch and the second switch, which will not be repeated here.
  • the third current mode logic circuit 33 includes a first switch VC 3 and a second switch
  • the first switch VC 3 is connected between the power supply terminal VCC and the resistors R 5 and R 6.
  • the Nth current mode logic circuit 3N includes a first switch V N and a second switch
  • the first switch V N is connected between the power supply terminal VCC and the resistors R 2N-1 and R 2N .
  • the first switch V N is disconnected, the power supply cannot supply power to the transistor Q.
  • the second switch Connected between the emitter and the current source Idc.
  • one of the two switches VC on the same current mode logic circuit can be a P-channel field effect transistor, and the other of the two switches VC can be an N-channel field effect transistor, so that the two switches can be turned on or off by using complementary voltages.
  • the on or off of the two switches VC on the current mode logic circuit can be controlled by a register or a decoder.
  • the two switches VC on the current mode logic circuit can be field effect transistors with the same channel, or not in the form of field effect transistors, but other switches VC with on or off function.
  • it may not be a register or a decoder that controls the switch VC to be turned on or off, but other devices that have a control function for the switch VC.
  • the current mode logic circuit can be obtained based on setting different collector resistors in the existing CML and setting the above-mentioned switch VC (as shown in FIG. 2 ).
  • the current mode logic module 30 may be provided with a multiplexer MUX as shown in FIG. 1 without setting the switch VC in FIG. 2, so as to select a differential signal regulated by a current mode logic circuit as the target differential signal;
  • the multiplexer MUX as in FIG. 1 may not be provided but the switch VC as in FIG. Switch VC in.
  • the initial differential signal input in the following current mode logic circuit can be a high-frequency wave, and a sine wave is used as an example for illustration. In practical applications, the initial differential signal can be a trapezoidal wave or other waveforms. Wherein, the high-frequency wave may not include the rectangular wave.
  • the waveform A1 can be approximated as the waveform diagram of the output voltage of the first output terminal VOP
  • the waveform B1 can be approximated as the waveform diagram of the output voltage of the second output terminal VON
  • the duty cycle of both the waveform A1 and the waveform B1 is 50%.
  • waveform A1 and waveform B1 are the waveforms corresponding to the two signal lines of the target differential signal
  • waveform C1 is the waveform diagram of the output target differential voltage. Referring to the horizontal line whose vertical axis value corresponds to 0 in Figure 3, it can be seen that the waveform C1 The duty cycle is 50%.
  • the ratio of the two collector resistors Rc in each current mode logic circuit is not 1.
  • the resistance values of the two collector resistors of one of the current mode logic circuits may also be set to be equal.
  • waveform A2 can be approximated as a waveform diagram of the output voltage of the first output terminal VOP
  • waveform B2 can be approximated as a waveform diagram of the output voltage of the second output terminal VON
  • the duty cycle of waveform A2 and waveform B2 is 50%.
  • waveform A2 and waveform B2 are the waveforms corresponding to the two signal lines of the target differential signal
  • waveform C2 is the waveform diagram of the output target differential voltage. Referring to the horizontal line whose vertical axis value corresponds to 0 in Figure 4, it can be known that the waveform C2 occupies The empty ratio is not 50%.
  • the duty cycle of the target differential voltage of the two is not 50%, but exceeds 50%. That is, when R1 is not equal to R2, the duty cycle of the differential signal can be adjusted by the first current mode logic circuit 31, and according to the formula in conjunction with FIG. 3 and FIG. 4, it can be seen that the adjustment degree is different from the difference between R1 and R2 Degree is relevant. Therefore, by changing the resistance values of the resistors R1 and R2 of the first current mode logic circuit 31, the duty cycle of the differential signal can be adjusted to different degrees, and the larger the ratio of the resistors R1 and R2 , the greater the effect on the duty cycle The degree of adjustment is also greater.
  • the ratio of R1 to R2 in the first current mode logic circuit 31 the ratio of R3 to R4 in the second current mode logic circuit 32, the third current mode logic circuit 33
  • the ratio of R 5 to R 6 ...
  • the ratio of R 2N-1 to R 2N in the Nth current mode logic circuit 3N is set to different values, and different current mode logic circuits can be selected according to needs to achieve different duty ratios degree of adjustment.
  • the parameter on the abscissa is time
  • the parameter on the ordinate is voltage
  • the coefficient of 0.5 is set so that the voltage values of VOP and VON do not exceed the voltage value provided by the power supply terminal VCC.
  • the embodiment of the present invention provides the aforementioned duty ratio adjustment circuit 100 , and the embodiment of the present invention also provides an output circuit, which may include an initial differential signal and the aforementioned duty ratio adjustment circuit 100 .
  • the initial differential signal is input through the input module 10 of the duty ratio adjustment circuit 100.
  • the duty ratio of a current mode logic circuit in the duty ratio adjustment circuit 100 to the initial differential signal can be selected according to the duty ratio of the initial differential signal.
  • the ratio is adjusted so as to output a target differential signal that meets a preset duty ratio condition at the output module 20 .
  • the duty cycle of the target differential signal that conforms to the preset duty cycle adjustment can be 50%, thus, a current mode logic circuit can be selected according to the duty cycle of the initial differential signal, thereby making the target differential signal duty cycle is 50%, therefore, the duty cycle of the initial differential signal and the adjustment degree of the duty cycle corresponding to the selected current mode logic circuit 31 should be complementary under ideal conditions.
  • the duty cycle of the initial differential signal is 45%.
  • the current mode logic circuit with a duty cycle adjustment degree of 55% should be selected to adjust the duty cycle of the differential signal.
  • the duty cycle of the initial differential signal is 65%
  • the current mode logic circuit with a duty cycle adjustment degree of 35% should be selected for the differential signal.
  • the air ratio is adjusted.
  • the duty cycle of the initial differential signal and the adjustment degree of the duty cycle corresponding to the selected current mode logic circuit may not be completely complementary, but there is a certain error range.
  • the duty cycle of the target differential signal conforming to the preset duty cycle adjustment may not be 50%, but 60%, 55%, 45% or 40%.
  • the duty cycle of the initial differential signal may not be complementary to the adjustment degree of the duty cycle corresponding to the selected one of the current mode logic circuits.
  • the embodiment of the present invention can also provide an integrated circuit, and the integrated circuit can have the above-mentioned duty ratio adjustment circuit 100, or have the above-mentioned output circuit.

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Abstract

本发明提供一种占空比调节电路及输出电路。占空比调节电路包括：输入模块、电流模式逻辑模块和输出模块。电流模式逻辑模块，包括至少两支电流模式逻辑电路，至少两支电流模式逻辑电路工作时对差分信号占空比的调节程度不同，电流模式逻辑电路与输入模块连接，以接收输入模块输入的初始差分信号；输出模块，输出模块与至少一支电流模式逻辑电路连接，以输出目标差分信号。该占空比调节电路，各电流模式逻辑电路对差分信号占空比的调节程度不同，使得占空比调节电路对初始差分信号的占空比调节的范围可准确、灵活地调节，设计简单，具有较高的可复制性，在版图设计时更加便捷。

Description

占空比调节电路及输出电路 技术领域
本发明涉及集成电路领域，尤其涉及一种占空比调节电路及输出电路。
背景技术
差分信号常用于集成电路中，对差分信号的占空比调节是研发人员需要关注的问题。
为了实现占空比调节，可以以数模转换器(Digital to Analog Converter，DAC)控制占空比调节的模拟占空比调节电路。然而，利用数模转换器DAC控制占空比调节电路的设计复杂、版图占用资源较多。
发明内容
为了解决上述问题，本发明提供一种设计更简单的占空比调节电路及输出电路。
为解决上述技术问题，本发明是这样实现的：
第一方面，本发明提供一种占空比调节电路，所述占空比调节电路包括：
输入模块，用于将初始差分信号输入至电流模式逻辑模块；
所述电流模式逻辑模块，包括至少两支电流模式逻辑电路，所述至少两支电流模式逻辑电路工作时对差分信号占空比的调节程度不同，所述电流模式逻辑电路与所述输入模块连接，以接收所述输入模块输入的初始差分信号；
输出模块，所述输出模块与至少一支所述电流模式逻辑电路连接，以输出目标差分信号，所述目标差分信号为所述初始差分信号经至少一支所述电流模式逻辑电路调节的差分信号。
第二方面，本发明提供一种输出电路，包括初始差分信号和如上任一项所述的占空比调节电路，所述初始差分信号经所述输入模块输入至所述占空 比调节电路，根据所述初始差分信号的占空比，选择所述占空比调节电路中的一支所述电流模式逻辑电路以对所述初始差分信号的占空比进行调节，所述输出模块用于输出符合预设占空比条件的目标差分信号。
本发明提供的占空比调节电路，各电流模式逻辑电路对差分信号占空比的调节程度不同，使得占空比调节电路对初始差分信号的占空比调节的范围可准确、灵活地调节，设计简单，具有较高的可复制性，在版图设计时更加便捷。
附图说明
此处所说明的附图用来提供对本发明的进一步理解，构成本发明的一部件，本发明的示意性实施例及其说明用于解释本发明，并不构成对本发明的不当限定。
在附图中：
图1为本发明实施例占空比调节电路的第一种实施方式的结构示意图；
图2为本发明实施例占空比调节电路的第二种实施方式的结构示意图。
附图标记：
图3为本发明实施例中经过单个电流模式逻辑电路得到目标差分信号的一种波形示意图；
图4为本发明实施例中经过单个电流模式逻辑电路得到目标差分信号的又一种波形示意图。
附图标记：
100-占空比调节电路；10-输入模块；20-输出模块；30-电流模式逻辑模块；31-第一电流模式逻辑电路；32-第二电流模式逻辑电路；33-第三电流模式逻辑电路；3N-第N电流模式逻辑电路；
VCC-电源端；GND-接地端；Q-晶体管；Rc-集电极电阻；Idc-电流源；MUX-多路选择器；VC-开关；VC 1-第一开关；
Figure PCTCN2022114170-appb-000001
-第二开关；VIP-第一输 入端子；VIN-第二输入端子；VOP-第一输出端子；VON-第二输出端子。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，下面将结合本发明具体实施例及相应的附图对本发明技术方案进行清楚、完整地描述。显然，所描述的实施例仅是本发明一部件实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
为了实现占空比调节，包括以互补金属氧化物半导体(ComplemeNtary Metal-Oxide-SemicoNductor，CMOS)电路为主的数字占空比调节电路和以数模转换器(Digital to Analog Converter，DAC)控制占空比调节的模拟占空比调节电路。CMOS逻辑电路由于采用单端输入单端输出导致工作频率不能太高，使其在高频应用受限，而利用数模转换器DAC控制占空比调节的设计复杂，可见相关占空比调节电路存在无法适用于高频段或设计复杂的问题。
为此，本发明实施例提供一种占空比调节电路100。
如图1和图2所示，本发明实施例提供一种占空比调节电路100，包括输入模块10、电流模式逻辑模块30和输出模块20。其中，输入模块10用于将差分信号源输入至电流模式逻辑模块30。电流模式逻辑模块30包括至少两支电流模式逻辑电路，图1中以包括第一电流模式逻辑电路31、第二电流模式逻辑电路32、第三电流模式逻辑电路33和第N电流模式逻辑电路3N为例进行说明。第一电流模式逻辑电路31、第二电流模式逻辑电路32、第三电流模式逻辑电路33和第N电流模式逻辑电路3N工作时对差分信号占空比的调节程度不同。电流模块逻辑电路与输入模块10连接，以接收输入模块10输入的初始差分信号，输出模块20与至少一支电流模式逻辑电路连接，用于输出目标差分信号，该目标差分信号为初始差分信号经该电流模式逻辑电路调节的差分信号。例如图1中第二电流模式逻辑电路32与输入模块10 连接，输出模块20与第二电流模式逻辑电路32连接，用于输出目标差分信号，该目标差分信号为初始差分信号经第二电流模式逻辑电路32调节的差分信号。当然，也可以是第一电流模式逻辑电路31、第二电流模式逻辑电路32、第三电流模式逻辑电路33和第N电流模式逻辑电路3N均与输入模块10连接，或者，第一电流模式逻辑电路31、第二电流模式逻辑电路32、第三电流模式逻辑电路33和第N电流模式逻辑电路3N均与输出模块20连接。
本发明实施例的占空比调节电路100，第一电流模式逻辑电路31、第二电流模式逻辑电路32、第三电流模式逻辑电路33和第N电流模式逻辑电路3N工作时对差分信号占空比的调节程度不同，使得初始差分信号输入后占空比可以被其中一个电流模式逻辑电路调节。在占空比调节电路100中，可以根据初始差分信号与目标差分信号之间的占空比差异程度，选择不同的电流模式逻辑电路以对差分信号的占空比进行不同程度的调节；或者对初始差分信号进行不同程度的占空比调节以得到不同的目标差分信号。相比相关技术，本发明实施例提供的占空比调节电路100，各电流模式逻辑电路对差分信号占空比的调节程度不同，可以根据需要选择对占空比进行调节的电流模式逻辑电路，使得占空比调节电路对初始差分信号的占空比调节的范围可准确、灵活地调节，设计更简单，电流模式逻辑模块30中包括至少两支电流模式逻辑电路，因此具有较高的可复制性，在版图设计时更加便捷。
此外，电流模式逻辑电路可以是基于现有的电流模式逻辑(CML，CurreNt Mode Logic)中设置不同的集电极电阻得到的，由于CML能够适用于高频信号，因此，本申请的占空比调节电路100可以适用于高频的差分信号。
若占空比调节电路的电流模式逻辑模块中，多个电流模式逻辑电路对差分信号占空比的调节程度完全相同或者只设置一个电流模式逻辑电路，则在电流模式逻辑模块中只能实现对占空比的单一调节；而本申请的占空比调节电路100中，电流模式逻辑模块30中因各电流模式逻辑电路对差分信号占空比的调节程度不同，在占空比调节过程中可以灵活选择不同的电流模式逻辑 电路对初始占空比进行调节。
其中，可以在一个电流模式逻辑模块30中选择一个电流模式逻辑电路对占比进行调节，即初始差分信号经过一次调节后得到目标差分信号，也可以经在多个电流模式逻辑模块中依次选择电流模式逻辑电路对占空比进行调节，即初始差分信号可以经多次调节后得到目标差分信号，因此，对占空比调节的范围更加准确和灵活。
在本发明实施例中，电流模式逻辑模块30中的电流模式逻辑电路的支数可以是两支、三支、四支及以上等等，如图1或图2中，给出了电流模式逻辑电路为N支的示意图。输入模块10可以与一支或多支电流模式逻辑电路连接。同理，输出模块20可以与一支或多支电流模式逻辑电路连接。
本发明实施例所举的实施例中，目标差分信号可以是初始差分信号经一支电流模式逻辑电路调节得到的差分信号，具体在某一时刻经一个电流模式逻辑模块30中的一支电流模式逻辑电路调节得到的差分信号，或者在前后不同时刻经一个电流模式逻辑模块30中的多支电流模式逻辑电路调节得到的差分信号，或者在前后不同时刻依次经不同的电流模式逻辑模块30调节得到的差分信号。当然，同一电流模式逻辑模块30中，为了对占空比的调节不受干扰，在同一时刻可以仅有一支电流模式逻辑电路工作并对差分信号占空比进行调节。
第一电流模式逻辑电路31、第二电流模式逻辑电路32、第三电流模式逻辑电路33和第N电流模式逻辑电路3N的内部结构可以相同，以下以第一电流模式逻辑电路31的为例说明其内部结构。第一电流模式逻辑电路31可以包括：电源端VCC、接地端GND、两个晶体管Q、两个集电极电阻Rc和电流源Idc。在占空比调节电路100中可以包括供电电源，供电电源连接第一电流模式逻辑电路31的电源端VCC，用于为第一电流模式逻辑电路31提供工作电压。
针对第一电流模式逻辑电路31而言，每一集电极电阻Rc的两端分别连 接一个晶体管Q的集电极和电源端VCC，电流源Idc的两端则分别连接晶体管Q的发射极和接地端GND，其中，两个晶体管Q的发射极相连，即共发射极设置，两个晶体管Q的基极连接输入模块10，两个晶体管Q的集电极连接输出模块20。
在同一电流模式逻辑模块30中，每一电流模式逻辑电路都包括两个集电极电阻Rc，且不同的电流模式逻辑电路中其两个集电极电阻Rc的比值各异。由于电流模式逻辑电路中的两个集电极电阻Rc的比值可以用于确定对差分信号占空比的调节程度，因此，各所述电流模式逻辑电路中的两个所述集电极电阻Rc的比值各异，从而使得各电流模式逻辑电路工作时对差分信号占空比的调节程度不同。
在图1或图2中，电阻R 1、R 2、R 3、R 4……R 2N-1、R 2N可以充称为集电极电阻Rc。其中，第一电流模式逻辑电路31的集电极电阻Rc为电阻R 1、R 2；第二电流模式逻辑电路32的集电极电阻Rc为电阻R 3、R 4；第三电流模式逻辑电路33的集电极电阻Rc为电阻R 5、R 6；以此类推，第N电流模式逻辑电路3N的集电极电阻Rc为电阻R 2N-1、R 2N。
本发明实施例中，为了方便获取对初始差分信号占空比的不同调节程度，各电流模式逻辑电路的两个集电极电阻Rc的比值可以呈规律分布，例如各电流模式逻辑电路中的两个集电极电阻Rc的比值可以呈等差数列或等比数列，其中等差数列或等比数列的步长值可以为0.1、0.2、0.5、1、1.2或1.5等。当然，各电流模式逻辑电路的两个集电极电阻Rc的比值也可以不按规律分布。例如，图1或图2中的第一电流模式逻辑电路31中R 1与R 2的比值、第二电流模式逻辑电路32中R 3与R 4的比值、第三电流模式逻辑电路33中R 5与R 6的比值……第N电流模式逻辑电路3N中R 2N-1与R 2N的比值分布为以下任一种情况：1、2、3……N；N、N-1、N-2……1；1、1.1、1.21……1.1N-1；1.1N-1、1.1N-2、1.1N-3……1。本申请文件中，N可以为大于3的自然数。
再参图1，本发明实施例占空比调节电路100的第一种实施方式的结构 示意图，该占空比调节电路100中还可以包括多路选择器MUX，该多路选择器MUX用于从电流模式逻辑模块30中选择经一支电流模式逻辑电路调节的差分信号作为目标差分信号，即从图1中的N支电流模式逻辑电路中选择一支电流模式逻辑电路对差分信号的占空比进行调节以输出目标差分信号。该多路选择器MUX可以包括选择输入端和选择输出端。选择输入端连接电流模式逻辑模块30中所有的晶体管Q的集电极，选择输出端连接输出模块20。该多路选择器MUX用于从电流模式逻辑模块30中选择经一支电流模式逻辑电路调节的差分信号作为目标差分信号，且该目标差分信号经选择输出端、输出模块20输出。
由于输入模块10用户输入差分信号，根据差分信号的特性，输入模块10应有两个输入端子，即为图1或图2上的第一输入端子VIP和第二输入端子VIN。同理，输出模块20有两个输出端子，即为图1或图2上的第一输出端子VOP和第二输出端子VON。选择输出端也有可以两个端子，选择输入端至少有四个端子且为偶数个。
参图2，本发明实施例占空比调节电路100的第二种实施方式的结构示意图。在各电流模式逻辑电路上可以包括开关VC，开关VC用于控制电流模式逻辑电路31的导通或断电，当电流模式逻辑电路导通时可以工作进而可以对初始差分信号占空比进行调节，当电流模式逻辑电路断电时则无法对初始差分信号占空比进行调节。在一电流模式逻辑模块30中，通过开关VC控制其中一支电流模式逻辑电路导通以对初始差分信号占空比进行调节，其余电流模式逻辑电路断电。例如，在图2中，电流模式逻辑电路的数量为N支，包括第一电流模式逻辑电路31、第二电流模式逻辑电路32、第三电流模式逻辑电路33……第N电流模式逻辑电路3N，通过开关VC控制其中的第二电流模式逻辑电路32导通以对初始长信号占空比进行调节，其余的N-1个电流模式逻辑电路均保持断电，即第一电流模式逻辑电路31、第三电流模式逻辑电路33……第N电流模式逻辑电路3N均保持断电状态。
为了确保电流模式逻辑电路能够完全断电而不对其他处于导通工作的电流模式逻辑电路产生干扰，各电流模式逻辑电路上可以包括两个开关VC，两个开关VC之一连接于电源端VCC与集电极电阻Rc之间，两个开关VC之另一连接于发射极与电流源Idc之间。例如，图2第一电流模式逻辑电路31中包括第一开关VC 1和第二开关
Figure PCTCN2022114170-appb-000002
第一开关VC 1接于电源端VCC与电阻R 1、R 2之间，第一开关VC 1断开时使得供电电源无法对晶体管Q供电，第二开关
Figure PCTCN2022114170-appb-000003
连接于发射极与电流源Idc之间，第二开关
Figure PCTCN2022114170-appb-000004
断开时使得电流源Idc无法与晶体管Q导通，从而确保图2左起第一电流模式逻辑电路31能够完全断电而不对其他电流模式逻辑电路产生干扰。同理，图2中第二电流模式逻辑电路32中也包括第一开关VC 2和第二开关
Figure PCTCN2022114170-appb-000005
第一开关VC 2接于电源端VCC与电阻R 3、R 4之间，第一开关VC 2断开时使得供电电源无法对晶体管Q供电，第二开关
Figure PCTCN2022114170-appb-000006
连接于发射极与电流源Idc之间；第三电流模式逻辑电路33及其它电流模式逻辑电路类似设置第一开关和第二开关，此处不再赘述。
如图2所示，第三电流模式逻辑电路33中包括第一开关VC 3和第二开关
Figure PCTCN2022114170-appb-000007
第一开关VC 3接于电源端VCC与电阻R 5、R 6之间，第一开关VC 3断开时使得供电电源无法对晶体管Q供电，第二开关
Figure PCTCN2022114170-appb-000008
连接于发射极与电流源Idc之间。第N电流模式逻辑电路3N包括第一开关VC N和第二开关
Figure PCTCN2022114170-appb-000009
第一开关VC N接于电源端VCC与电阻R 2N-1、R 2N之间，第一开关VC N断开时使得供电电源无法对晶体管Q供电，第二开关
Figure PCTCN2022114170-appb-000010
连接于发射极与电流源Idc之间。
其中，同一电流模式逻辑电路上的两个开关VC之一可以为P沟道场效应管，两开关VC之另一可以为N沟道场效应管，由此可以采用互补的电压导通或断开两个开关VC。其中，电流模式逻辑电路上的两个开关VC的导通 或断开可以由寄存器或译码器控制。当然，作为变形，电流模式逻辑电路上的两个开关VC可以是相同沟道的场效应管，或者不是为场效应管形式的开关VC，而是其他具有导通或断开功能的开关VC。同样，控制开关VC导通或断开的可以不是寄存器或译码器，而是其他对开关VC具有控制功能的器件。
本发明实施例中，电流模式逻辑电路可以是基于现有的CML中设置不同的集电极电阻且设置上述开关VC得到的(如图2)。
实际应用中，电流模式逻辑模块30中可以设置如图1中的多路选择器MUX而不设置图2中的开关VC，以选择经一支电流模式逻辑电路调节的差分信号作为目标差分信号；电流模式逻辑模块30中也可以不设置如图1中的多路选择器MUX而设置如图2中的开关VC；或者，既设置有如图1中的多路选择器MUX，又设置有如图2中的开关VC。
以上说明了本发明实施例中占空比调节电路100的具体实施方式，以下就电流模式逻辑电路中的两个集电极电阻Rc的比值对差分信号占空比的调节程度如何影响进行说明。以下电流模式逻辑电路中输入的初始差分信号可以是高频波，并以正弦波为例进行说明，实际应用中，初始差分信号可以是梯形波或其他波形。其中，高频波中可以不包括矩形波。
对于如图1中第一电流模式逻辑电路31而言，设第一电流模式逻辑电路31与输入模块10、输出模块20连接，它的单端输出摆幅为I DC×R。若电阻R 1＝R 2＝R时，第一输出端子VOP的输出电压可近似为：VOP＝VCC-I DC·R·(0.5-0.5·sin(t))，而第二输出端子VON的输出电压可近似为：VON＝VCC-I DC·R·(0.5+0.5·sin(t))，那么目标差分输出电压即为VODM＝I DC·R·sin(t)。参考图3，波形A1可近似为第一输出端子VOP的输出电压波形图，波形B1可近似为第二输出端子VON的输出电压的波形图，波形A1和波形B1的占空比均为50％，且波形A1和波形B1为目标差分信号的两根信号线对应的波形，波形C1则为输出的目标差分电压的波形图，参 照图3中纵轴数值对应为0的横线可知波形C1的占空比为50％，可以看到，对于占空比均为50％的波形A1和波形B1，两者的目标差分电压的占空比仍为50％。因此，在R1等于R2时，第一电流模式逻辑电路31对差分信号的占空比调节程度近乎为零。
因此，为了能够对占空比实现调节，通常各电流模式逻辑电路中的两个集电极电阻Rc的比值不为1。当然，在部分实施方式中，为了使得初始差分信号和目标差分信号的占空比一致，也可以将其中一支电流模式逻辑电路的两个集电极电阻的阻值设置成相等。
对于如图1中第一电流模式逻辑电路31而言，它的单端输出摆幅为I DC×R。若R 1＝2R 2＝2R时，第一输出端子VOP的输出电压可近似为VOP＝VCC-I DC·R·(0.5-0.5·sin(t))，而第二输出端子VON的输出电压可近似为VON＝VCC-2·I DC·R·(0.5+0.5·sin(t))，那么目标差分输出电压即为VODM＝0.5·I DC·R+1.5·I DC·R·sin(t)。参考图4，波形A2可近似为第一输出端子VOP的输出电压的波形图，波形B2可近似为第二输出端子VON的输出电压的波形图，波形A2和波形B2的占空比为50％，且波形A2和波形B2为目标差分信号的两根信号线对应的波形，波形C2为输出的目标差分电压的波形图，参照图4中纵轴数值对应为0的横线可知波形C2的占空比不是50％。可以看到，对于占空比均为50％的波形A2和波形B2，两者的目标差分电压的占空比不为再50％，而是超过50％。也就是，在R1不等于R2时，第一电流模式逻辑电路31对差分信号的占空比可以实现调节，且根据公式结合图3和图4可知，该调节程度与R 1和R 2的差异程度相关。因此，通过改变第一电流模式逻辑电路31电阻R 1和R 2的阻值，可以对差分信号的占空比进行不同程度调节，而且，电阻R 1和R 2比值越大，对占空比的调节程度也越大。
因此，在电流模式逻辑模块30中，将第一电流模式逻辑电路31中R 1与R 2的比值、第二电流模式逻辑电路32中R 3与R 4的比值、第三电流模式 逻辑电路33中R 5与R 6的比值……第N电流模式逻辑电路3N中R 2N-1与R 2N的比值设置为不同数值，可以根据需要选择不同的电流模式逻辑电路进而实现对占空比的不同程度的调节。
其中，图3和图4中，横坐标的参数为时间time，纵坐标的参数为电压voltage。
需要说明的是，上述公式中求得VOP、VON的过程中，系数0.5的设置是为了使得VOP、VON的电压值不超过电源端VCC所提供的电压值。借助上述分析可知，电流模式逻辑电路中，改变集电极电阻Rc可以改变对差分信号的占空比调节程度。
简而言之，在单个电流模式逻辑电路中，输入差分信号后，改变集电极电阻Rc可以改变该单个电流模式逻辑电路中对应的集电极端的电压幅度，进而使得差分信号中的两个信号的交点位于发生偏移，也就是差分信号关于0的位置发生偏移，从而调节了差分信号的占空比。
本发明实施例提供了上述的一种占空比调节电路100，本发明实施例还提供一种输出电路，该输出电路可以包括初始差分信号和上述占空比调节电路100。初始差分信号经占空比调节电路100的输入模块10输入，使用中，可以根据初始差分信号的占空比选择占空比调节电路100中的一支电流模式逻辑电路对初始差分信号的占空比进行调节，以在输出模块20输出符合预设占空比条件的目标差分信号。
其中，符合预设占空比调节的目标差分信号的占空比可以为50％，由此，可以根据初始差分信号的占空比选择一支电流模式逻辑电路，进而使得目标差分信号占空比为50％，由此，初始差分信号的占空比与所选择的一支电流模式逻辑电路31对应的占空比调节程度在理想情况下应当互补。例如，初始差分信号的占空比为45％，为了使得目标差分信号的占空比可以达到50％，应选择对占空比调节程度为55％的电流模式逻辑电路对差分信号占空比进行调节；又例如，初始差分信号的占空比为65％，为了使得目标差分信号的占 空比可以达到50％，应选择对占空比调节程度为35％的电流模式逻辑电路对差分信号占空比进行调节。当然，实际应用中，初始差分信号的占空比与所选中的一支电流模式逻辑电路对应的占空比调节程度可以并不完全地互补，而是存在一定的误差区间。
当然，部分实施方式中，符合预设占空比调节的目标差分信号的占空比可以不是50％，而是60％、55％、45％或40％。则对应的，初始差分信号的占空比与所选中的一支所述电流模式逻辑电路对应的占空比调节程度可以不是互补的。
此外，本发明实施例还可以提供一种集成电路，该集成电路可具有上述的占空比调节电路100，或者具有上述的输出电路。
以上所述仅为本发明的实施例而已，并不用于限制本发明。对于本领域技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原理之内所作的任何修改、等同替换、改进等，均应包含在本发明的权利要求范围之内。

Claims (8)

  1. 一种占空比调节电路，其特征在于，所述占空比调节电路包括：
    输入模块，用于将初始差分信号输入至电流模式逻辑模块；
    所述电流模式逻辑模块，包括至少两支电流模式逻辑电路，所述至少两支电流模式逻辑电路工作时对差分信号占空比的调节程度不同，所述电流模式逻辑电路与所述输入模块连接，以接收所述输入模块输入的初始差分信号；
    输出模块，所述输出模块与至少一支所述电流模式逻辑电路连接，以输出目标差分信号，所述目标差分信号为所述初始差分信号经至少一支所述电流模式逻辑电路调节的差分信号。
  2. 根据权利要求1所述的占空比调节电路，其特征在于，所述电流模式逻辑电路中包括：电源端、接地端、两个晶体管、两个集电极电阻和电流源；
    在各所述电流模式逻辑电路中，各所述集电极电阻的两端分别连接各所述晶体管的集电极和所述电源端，所述电流源的两端分别连接所述晶体管的发射极和所述接地端，各所述电流模式逻辑电路中的两个所述晶体管共发射极设置；两个所述晶体管的基极连接所述输入模块；两个所述晶体管的集电极连接所述输出模块；
    各所述电流模式逻辑电路中的两个所述集电极电阻的比值各异，所述电流模式逻辑电路中的两个所述集电极电阻的比值用于确定对差分信号占空比的调节程度。
  3. 根据权利要求2所述的占空比调节电路，其特征在于，所述占空比调节电路还包括多路选择器，所述多路选择器包括选择输入端和选择输出端，所述选择输入端连接所述电流模式逻辑模块中的所述晶体管的集电极，所述选择输出端连接所述输出模块；所述多路选择器用于从所述电流模式逻辑模 块中选择经一支所述电流模式逻辑电路调节的差分信号作为所述目标差分信号，并经所述选择输出端、所述输出模块输出。
  4. 根据权利要求2所述的占空比调节电路，其特征在于，各所述电流模式逻辑电路上包括开关，用于控制所述电流模式逻辑电路导通或断电；通过所述开关控制其中一支电流模式逻辑电路导通对初始差分信号占空比进行调节，其余所述电流模式逻辑电路断电。
  5. 根据权利要求4所述的占空比调节电路，其特征在于，各所述电流模式逻辑电路上包括两个所述开关，两个所述开关之一连接于所述电源端与所述集电极电阻之间、另一连接于所述发射极与所述电流源之间。
  6. 根据权利要求5所述的占空比调节电路，其特征在于，两个所述开关之一为P沟道场效应管，另一为N沟通场效应管。
  7. 根据权利要求4所述的占空比调节电路，其特征在于，所述开关的导通与断开由寄存器或译码器控制。
  8. 一种输出电路，其特征在于，包括初始差分信号和如权利要求1-7任一项所述的占空比调节电路，所述初始差分信号经所述输入模块输入至所述占空比调节电路，根据所述初始差分信号的占空比，选择所述占空比调节电路中的一支所述电流模式逻辑电路以对所述初始差分信号的占空比进行调节，所述输出模块用于输出符合预设占空比条件的目标差分信号。
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