WO2023115887A1

WO2023115887A1 - Optical switch design method, optical switch, electronic device, and storage medium

Info

Publication number: WO2023115887A1
Application number: PCT/CN2022/102616
Authority: WO
Inventors: 李军阳
Original assignee: 苏州浪潮智能科技有限公司
Priority date: 2021-12-24
Filing date: 2022-06-30
Publication date: 2023-06-29
Also published as: CN114217390B; CN114217390A

Abstract

An optical switch design method, comprising: performing segmentation processing on a PCB on the basis of an optical port module and a high-speed signal line; and on the basis of the distribution of the optical port module on the PCB, determining a housing connection scheme corresponding to the optical port module, wherein the PCB at least comprises a top layer, a bottom layer, a GND layer, and an inner electric layer, and the optical port module comprises a plurality of optical ports. Projection boundaries of the optical ports on the PCB are used as segmentation boundaries; and if the segmentation boundaries do not have an overlapping area with the high-speed signal line, the PCB is segmented according to the segmentation boundaries. The present invention ensures that an internal signal does not cross an area formed by GND segmentation; in addition, external noise cannot interfere with an internal circuit. Also provided is an optical switch designed using the method.

Description

Optical switch design method, optical switch, electronic equipment and storage medium

Cross References to Related Applications

This application claims the priority of the Chinese patent application filed on December 24, 2021 with the application number 202111600900.6 and titled "Optical Switch Design Method, Optical Switch, Electronic Equipment, and Storage Medium" with the Chinese Patent Office, the entire content of which is passed References are incorporated in this application.

technical field

The present application relates to the technical field of integrated circuits, in particular to an optical switch design method, an optical switch, electronic equipment and a storage medium.

Background technique

With the development of science and technology, the performance requirements for switches are getting higher and higher. In order to meet the requirements, the working speed of switches is also getting higher and higher. In terms of the development of switches today, the rate of the previous 1G electrical port has been developed to At present, the rate of 10G optical port, 25G or even 100G optical port is accompanied by the fact that the requirements for electromagnetic compatibility of the switch are becoming more and more difficult to achieve, and because the switch interface is more and dense, the design requirements for the switch are getting higher and higher. The previous design may not be able to meet its electromagnetic compatibility requirements well.

The inventor realized that in the prior art, some switches have no division of the PCB board below the port, and the corresponding GND layer has no division, so that the internal noise of the switch can radiate to the outside through the port, and at the same time, external interference can also pass through the GND layer of the port. The crosstalk to the GND layer of the motherboard causes the decline of the anti-interference ability of the switch; some switches also cede the entire PCB board, which will cause some signals to have to cross the divided area, which will affect the transmission of the signal.

Therefore, there is an urgent need for an optical switch design method that can improve the anti-interference ability of the switch, so as to solve the above-mentioned technical problems in the prior art.

Contents of the invention

The present application provides an optical switch design method, an optical switch, electronic equipment and a storage medium.

In the first aspect, the present application provides a method for designing an optical switch, the method comprising:

Based on the optical port module and the high-speed signal line, the PCB board is divided; and

Based on the distribution of the optical port module on the PCB board, determine the shell lapping scheme corresponding to the optical port module;

Wherein, the PCB board includes at least a top layer, a bottom layer, a GND layer and an internal electric layer, and the optical port module includes a plurality of optical ports.

In some embodiments, based on the optical port module and the high-speed signal line, the PCB board is divided, including:

The projection boundary of the optical port on the PCB board is used as the division boundary;

When there is no overlapping area between the division boundary and the high-speed signal line, divide the PCB board according to the division boundary.

In some embodiments, the above method also includes:

When there is an overlapping area between the division boundary and the high-speed signal line, the PCB board is not divided according to the division boundary.

In some embodiments, the projection boundary of the optical port on the PCB is used as the division boundary, including:

When the optical port is on the top layer of the PCB board, the projection boundary of the optical port on the top layer of the PCB board is used as the division boundary;

When the optical port is at the bottom layer of the PCB board, the projection boundary of the optical port at the bottom layer of the PCB board is used as the division boundary.

In some embodiments, when there is no overlapping area between the division boundary and the high-speed signal line, the PCB board is divided according to the division boundary, including:

Segment the top layer with the projection boundary of the light port on the top layer as the first segmentation boundary; and/or

The bottom layer is divided by using the projection boundary of the light port on the bottom layer as the second segmentation boundary.

In some embodiments, the method also includes:

Segmenting the first GND layer adjacent to the top layer according to the first segmentation boundary; and/or

The second GND layer adjacent to the bottom layer is divided according to the second division boundary.

In some embodiments, the method also includes:

performing ground paving treatment on the first internal electrical layer adjacent to the first GND layer, and dividing the first internal electrical layer after ground paving treatment according to the first division boundary; and/or

The second internal electrical layer adjacent to the second GND layer is subjected to ground paving treatment, and the second internal electrical layer after ground paving treatment is divided according to the second division boundary.

In some embodiments, based on the distribution of the optical port module on the PCB board, the shell lapping scheme corresponding to the optical port module is determined, including:

When the optical port module exists only on the top layer of the PCB, the area where the optical port module does not touch the top layer is lapped with the shell.

When the optical port module exists only on the bottom layer of the PCB board, the area where the optical port module does not touch the bottom layer is overlapped with the shell.

When there are optical port modules on both the top layer and the bottom layer of the PCB board, the shell is lapped at the area where the optical port module does not contact the PCB board.

In some embodiments, methods include:

The high-speed signal line is used to transmit data signals and clock signals related to the optical port module; and

Case ground.

In the second aspect, the present application provides an optical switch, and the optical switch divides the PCB board based on the optical port module and the high-speed signal line; and

Based on the distribution of the optical port modules on the PCB board, the optical switch determines the shell lapping scheme corresponding to the optical port modules;

Wherein, the PCB board at least includes a top layer, a bottom layer, a GND layer and an internal electrical layer.

In a third aspect, the present application provides an electronic device, including a memory and one or more processors, where computer-readable instructions are stored in the memory, and when the computer-readable instructions are executed by one or more processors, one or more A processor executes the steps of any one of the above optical switch design methods.

In a fourth aspect, the present application provides one or more non-volatile storage media storing computer-readable instructions. When the computer-readable instructions are executed by one or more processors, the one or more processors perform any of the above-mentioned The steps of an optical switch design method.

The details of one or more embodiments of the application are set forth in the accompanying drawings and the description below. Other features and advantages of the application will be apparent from the description, drawings, and claims.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings that need to be used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings without creative work, in which:

FIG. 1 is a schematic diagram of PCB board cutting provided in one or more embodiments of the present application;

FIG. 2 is a flowchart of a method provided in one or more embodiments of the present application;

FIG. 3 is a structural diagram of an electronic device provided in one or more embodiments of the present application;

Detailed ways

In order to make the purpose, technical solutions and advantages of the application clearer, the technical solutions in the embodiments of the application will be clearly and completely described below in conjunction with the drawings in the embodiments of the application. Obviously, the described embodiments are only Some embodiments of this application are not all embodiments. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of this application.

The English abbreviations involved in this application are:

PCB (Printed Circuit Board, printed circuit board);

GND (Ground, ground).

Embodiment one

This embodiment provides a method for designing an optical switch:

S100. Determine the division boundary according to the projection boundary of the optical port in the optical port module on the PCB board.

Among them, there are multiple optical ports on the optical port module. Generally, the PCB layer of the switch has more than 10 layers. When N>=10, the optical ports are distributed on the upper and lower layers of the PCB (ie, the top layer and the bottom layer). The board at least includes a top layer, a bottom layer, a GND layer and an internal electrical layer.

S200. Perform segmentation processing on the PCB board according to the segmentation boundary and the high-speed signal line.

Since the optical ports of a large number of optical port modules are integrated in the switch, the wiring of the connector part on the PCB is relatively dense. In order to make the high-speed wiring of the connector part refer to the GND completely, when considering dividing the GND, only consider no high-speed signal routing. Below the optical port of the line part, there is no GND division where there are high-speed signal traces. The high-speed signal line is used to transmit the data signal and clock signal related to the optical port module.

Therefore, if the projection boundary of the optical port on the PCB board (that is, the division boundary) overlaps with the high-speed signal line, the PCB board will not be divided according to the division boundary corresponding to the optical port, that is, the division corresponding to the division boundary will be discarded. Segmentation of the optical port area. Only when there is no overlapping area between the high-speed signal line and the division boundary, divide the PCB board according to the division boundary. Specifically, refer to Figure 1. The dotted line in the figure is the division line. The methods for dividing the PCB board include:

S210. When the optical port is on the top layer of the PCB, the projection boundary of the optical port on the top layer of the PCB is the division boundary. Divide the top layer of the PCB board according to the division boundary; at the same time, divide the GND layer adjacent to the top layer according to the division boundary, and perform ground paving treatment on the internal electric layer adjacent to the GND layer, and do the same ground paving treatment The subsequent internal electric layer is divided according to the division boundary.

Specifically, the application may determine that the optical port is on the top layer of the PCB, and based on the determination result, the projection limit of the optical port on the top layer of the PCB is the division limit.

What needs to be explained is that the projection of the optical port on the top layer of the PCB will not be projected to the bottom layer of the PCB.

S220. When the optical port is at the bottom layer of the PCB board, the projection boundary of the optical port at the bottom layer of the PCB board is the division boundary. Divide the bottom layer of the PCB board according to the division boundary; at the same time, divide the GND layer adjacent to the bottom layer according to the division boundary, and perform ground paving treatment on the internal electric layer adjacent to the GND layer, and do the same ground paving treatment The subsequent internal electric layer is divided according to the division boundary.

Specifically, the application can determine that the optical port is at the bottom layer of the PCB, and based on the determination result, the projection limit of the optical port on the bottom layer of the PCB is the division limit.

What needs to be explained is that the projection of the optical port on the bottom layer of the PCB will not be projected to the top layer of the PCB.

S300. According to the distribution of the optical port modules on the PCB board, determine a shell lapping scheme corresponding to the optical port modules.

Specifically, after the PCB board is divided, it is necessary to overlap the housing of the optical port module, so as to improve the shielding effect on interference signals. When there is an optical port module only on the top layer of the PCB, except for the place under the optical port Except the place where the bottom of the optical port module is in contact with the bottom layer of the PCB board, the rest of the area must overlap the shell; when there are only optical port modules on the top and bottom layers of the PCB, except for the place where the bottom of the optical port module is in contact with the PCB board, the rest of the area It is necessary to overlap the shell to achieve an approximate 360-degree overlap.

Among them, the overlapping shell can realize the connection with the GND layer adjacent to the top or bottom layer of the PCB board, and has a grounding function. The above-mentioned overlapping shell can be a metal shell that is overlapped with the optical port module, or it can be added conductive foam to make the optical port Module and housing overlap.

Based on the optical switch design method disclosed in the embodiment of the present application, the integrity of the shielding effect can be achieved only by partial segmentation of the PCB board, and the PCB board can be used to the maximum extent. On the premise of improving the performance of electromagnetic compatibility, Reduced development material costs.

Embodiment two

Corresponding to the above-mentioned embodiments, the present application provides a method for designing an optical switch, as shown in FIG. 2 , the method includes:

2100. Based on the optical port module and the high-speed signal line, the PCB board is divided;

Preferably, based on the optical port module and the high-speed signal line, the PCB board is divided, including:

2110. Taking the projection boundary of the optical port on the PCB as the division boundary;

2120. If there is no overlapping area between the division boundary and the high-speed signal line, then divide the PCB board according to the division boundary; preferably, if there is no overlapping area between the division boundary and the high-speed signal line, then divide the PCB board according to the division boundary, including :

2121. Take the projection boundary of the optical port on the top layer as the first segmentation boundary, and divide the top layer; and/or

2122. Use the projection boundary of the optical port on the bottom layer as the second segmentation boundary, and divide the bottom layer.

Specifically, the present application may determine that there is no overlapping area between the division boundary and the high-speed signal line, and divide the PCB board according to the division boundary based on the determination result.

Preferably, the method also includes:

2123. Divide the first GND layer adjacent to the top layer according to the first division boundary; and/or

2124. Divide the second GND layer adjacent to the bottom layer according to the second division boundary.

Preferably, the method also includes:

2125. Perform ground paving treatment on the first internal electrical layer adjacent to the first GND layer, and divide the first internal electrical layer after ground paving treatment according to the first segmentation boundary; and/or

2126. Perform ground paving treatment on the second internal electrical layer adjacent to the second GND layer, and divide the ground paved second internal electrical layer according to the second division boundary.

2130. If there is an overlapping area between the division boundary and the high-speed signal line, do not divide the PCB board according to the division boundary.

Specifically, the present application may determine that there is an overlapping area between the division boundary and the high-speed signal line, and based on the determination result, the PCB board is not divided according to the division boundary.

Preferably, the method also includes:

2200. Based on the distribution of the optical port modules on the PCB board, determine the shell lapping scheme corresponding to the optical port modules;

Preferably, based on the distribution of the optical port module on the PCB board, determine the shell lapping scheme corresponding to the optical port module, including:

2210. If there is only an optical port module on the top layer of the PCB board, then overlap the shell in the area where the optical port module does not touch the top layer;

2220. If there is only an optical port module on the bottom layer of the PCB board, then overlap the shell on the area where the optical port module does not touch the bottom layer;

2230. If there are optical port modules on both the top layer and the bottom layer of the PCB board, overlap the shell in a region where the optical port module does not contact the PCB board.

Specifically, the present application can determine that the optical interface module exists only on the top layer of the PCB, and based on the determination result, overlap the shell in the area where the optical interface module does not touch the top layer.

The present application can determine that the optical port module exists only on the bottom layer of the PCB, and based on the result of the judgment, the area where the optical port module does not touch the bottom layer is overlapped with the shell.

The present application can determine that the optical port module exists on both the top layer and the bottom layer of the PCB board, and based on the judgment result, the housing is overlapped in the area where the optical port module does not contact the PCB board.

Preferably, the method includes:

2240, the high-speed signal line is used to transmit the data signal and clock signal related to the optical port module;

2250. The casing is grounded.

Embodiment three

Corresponding to all the above-mentioned embodiments, an embodiment of the present application provides an electronic device, including: one or more processors; and a memory associated with the one or more processors, the memory is used to store program instructions, and the program instructions are used by one or more When multiple processors read and execute, perform the following operations:

Based on the optical port module and high-speed signal line, the PCB board is divided and processed;

Wherein, FIG. 3 exemplarily shows the architecture of an electronic device, which may specifically include at least one processor 310 and a memory 320; computer-readable instructions are stored in the memory 320, and the computer-readable instructions are executed by one or more processors 310 , make one or more processors 310 execute the optical switch design method provided in the above embodiment.

The electronic device above also includes a video display adapter 311 , a disk drive 312 , an input/output interface 313 and a network interface 314 . The above-mentioned processor 310 , video display adapter 311 , disk drive 312 , input/output interface 313 , network interface 314 , and the memory 320 can be communicatively connected through the bus 330 .

Wherein, the processor 310 may be implemented by a general-purpose CPU (Central Processing Unit, central processing unit), a microprocessor, an application-specific integrated circuit (Application Specific Integrated Circuit, ASIC), or one or more integrated circuits, etc., for Relevant programs are executed to realize the technical solutions provided by this application.

The memory 320 can be implemented in the form of ROM (Read Only Memory, read-only memory), RAM (Random Access Memory, random access memory), static storage device, dynamic storage device, etc. The memory 320 may store an operating system 321 for controlling the operation of the electronic device 300 , and a basic input output system (BIOS) 322 for controlling low-level operations of the electronic device 300 . In addition, a web browser 323, a data storage management system 324, an icon font processing system 325, etc. can also be stored. The above-mentioned icon font processing system 325 may be an application program in the embodiment of the present application that specifically implements the operations of the aforementioned steps. In a word, when implementing the technical solution provided by the present application through software or firmware, related program codes are stored in the memory 320 and invoked by the processor 310 for execution.

The input/output interface 313 is used to connect the input/output module to realize information input and output. The input/output/module can be configured in the device as a component (not shown in the figure), or can be externally connected to the device to provide corresponding functions. The input device may include a keyboard, mouse, touch screen, microphone, various sensors, etc., and the output device may include a display, a speaker, a vibrator, an indicator light, and the like.

The network interface 314 is used to connect the communication module (not shown in the figure), so as to realize the communication interaction between the device and other devices. The communication module can realize communication through wired means (such as USB, network cable, etc.), and can also realize communication through wireless means (such as mobile network, WIFI, Bluetooth, etc.).

Bus 330 includes a path for transferring information between the various components of the device (eg, processor 310, video display adapter 311, disk drive 312, input/output interface 313, network interface 314, and memory 320).

In addition, the electronic device 300 can also obtain information about specific receiving conditions from the virtual resource object receiving condition information database, so as to judge the conditions, and so on.

It should be noted that although the above-mentioned devices only show the processor 310, the video display adapter 311, the disk drive 312, the input/output interface 313, the network interface 314, the memory 320, the bus 330, etc., in the specific implementation process, the A device may also include other components necessary for proper operation. In addition, those skilled in the art can understand that the above-mentioned device may only include components necessary to realize the solution of the present application, and does not necessarily include all the components shown in the figure.

In all the above-mentioned embodiments, the present application also provides one or more non-volatile storage media storing computer-readable instructions. When the computer-readable instructions are executed by one or more processors, the one or more processors execute The optical switch design method provided in any one of the above embodiments.

It can be known from the above description of the implementation manners that those skilled in the art can clearly understand that the present application can be implemented by means of software plus a necessary general-purpose hardware platform. Based on this understanding, the essence of the technical solution of this application or the part that contributes to the prior art can be embodied in the form of software products, and the computer software products can be stored in storage media, such as ROM/RAM, disk , optical disc, etc., including several instructions to make a computer device (which may be a personal computer, cloud server, or network device, etc.) execute the methods of various embodiments or some parts of the embodiments of the present application.

Each embodiment in this specification is described in a progressive manner, the same and similar parts of each embodiment can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system or the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and for related parts, please refer to the part of the description of the method embodiment. The above-described systems and system embodiments are only illustrative, where the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in One place, or it can be distributed to multiple network elements. Part or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. It can be understood and implemented by those skilled in the art without creative effort.

The above are only preferred embodiments of the application, and are not intended to limit the application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the application shall be included in the protection scope of the application. Inside.

Claims

A method for designing an optical switch, characterized in that the method comprises:

Based on the optical port module and the high-speed signal line, the PCB board is divided; and

Based on the distribution of the optical port module on the PCB board, determine the shell lapping scheme corresponding to the optical port module;

Wherein, the PCB board at least includes a top layer, a bottom layer, a GND layer and an internal electrical layer, and the optical port module includes a plurality of optical ports.
The method according to claim 1, wherein said dividing the PCB board based on the optical port module and the high-speed signal line includes:

Taking the projection boundary of the optical port on the PCB as the division boundary; and

When there is no overlapping area between the division boundary and the high-speed signal line, the PCB board is divided according to the division boundary.
The method according to claim 2, further comprising:

When there is an overlapping area between the division boundary and the high-speed signal line, the PCB board is not divided according to the division boundary.
The method according to claim 2, characterized in that, taking the projection limit of the optical port on the PCB board as the dividing limit includes:

When the optical port is on the top layer of the PCB board, the projection limit of the optical port on the top layer of the PCB board is the division limit;

When the optical port is at the bottom layer of the PCB board, the projection boundary of the optical port at the bottom layer of the PCB board is used as the division boundary.
The method according to claim 2, wherein when there is no overlapping area between the division boundary and the high-speed signal line, dividing the PCB board according to the division boundary includes:

dividing the top layer by using the projection boundary of the optical port on the top layer as a first segmentation boundary; and/or

The bottom layer is divided by using the projection boundary of the light port on the bottom layer as a second division boundary.
The method according to claim 5, wherein the method further comprises:

Segmenting the first GND layer adjacent to the top layer according to the first segmentation boundary; and/or

The second GND layer adjacent to the bottom layer is divided according to the second division boundary.
The method according to claim 6, further comprising:

performing ground paving treatment on the first internal electrical layer adjacent to the first GND layer, and dividing the first internal electrical layer after ground paving treatment according to the first division boundary; and/or

The second internal electrical layer adjacent to the second GND layer is subjected to ground paving treatment, and the second internal electrical layer after ground paving treatment is divided according to the second division boundary.
The method according to any one of claims 1-7, wherein, based on the distribution of the optical port module on the PCB board, determining the shell lapping scheme corresponding to the optical port module includes:

When the optical port module exists only on the top layer of the PCB, the area where the optical port module does not contact the top layer is overlapped with the shell.
The method according to any one of claims 1-7, wherein, based on the distribution of the optical port module on the PCB board, determining the shell lapping scheme corresponding to the optical port module includes:

When the optical interface module exists only on the bottom layer of the PCB board, the area where the optical interface module does not contact the bottom layer overlaps the shell.
The method according to any one of claims 1-7, wherein, based on the distribution of the optical port module on the PCB board, determining the shell lapping scheme corresponding to the optical port module includes:

When the optical port module exists on both the top layer and the bottom layer of the PCB board, the shell is overlapped at a region where the optical port module does not contact the PCB board.
The method according to any one of claims 1-7, wherein the method comprises:

The high-speed signal line is used to transmit data signals and clock signals related to the optical port module; and

The housing is grounded.
An optical switch, characterized in that,

The optical switch divides the PCB board based on the optical port module and the high-speed signal line; and

The optical switch determines the shell lapping scheme corresponding to the optical port module based on the distribution of the optical port module on the PCB board;

Wherein, the PCB board at least includes a top layer, a bottom layer, a GND layer and an internal electrical layer.
An electronic device, the electronic device comprising: a memory and one or more processors, computer readable instructions are stored in the memory, and when the computer readable instructions are executed by the one or more processors, the one or more processors Carrying out the steps of the method according to any one of claims 1 to 11.
One or more non-volatile computer-readable storage media storing computer-readable instructions, which, when executed by one or more processors, cause one or more processors to perform any of claims 1 to 11 A step of said method.