JP3209597B2 - Printed circuit board design method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for reducing electromagnetic radiation noise in a printed circuit board. More specifically, low electromagnetic radiation noise levels,
The present invention relates to a high-density mounting printed circuit board and a technique for designing the printed circuit board.

[0002]

2. Description of the Related Art The frequency of a square wave clock used in a digital circuit constituting an information processing apparatus or the like is high speed. Therefore, the energy of electromagnetic radiation noise generated on the printed circuit board that realizes the digital circuit is large,
Electromagnetic interference to a wireless communication device or the like caused by this cannot be ignored.

Conventionally, as a countermeasure against such electromagnetic radiation noise, for example, as described in the paragraph “4. Multilayering” on page 87, “EMC Countermeasure Up to Here” (published by Taisei Corporation in 1988) It has been thought that the mere use of a multilayer substrate is perfect.

[0004]

Heretofore, the component mounting density of a printed circuit board has been low, and it has generally been sufficient to use a multilayer board having a pair of power ground layers as a measure against electromagnetic radiation noise. .

However, in recent years, in order to realize high-performance and high-performance information processing apparatuses, the density of components mounted on a printed circuit board and the density of wiring have been increased, and the energy of generated electromagnetic waves has increased as compared with conventional ones. ing. For this reason, it is not possible to say that the use of a multilayer substrate alone is a perfect measure against electromagnetic radiation noise.

On the other hand, the number of via holes used for connection between layers of a multi-layer board is increasing due to the increase in component mounting density and wiring density of a printed board. For this reason, many holes and cut lines are being generated in the power ground layer, which should be a plain conductor.

The modes of the electromagnetic noise generated from the digital circuit include a differential mode and a common mode.

[0008] The electromagnetic wave generation model in the differential mode is a loop antenna that can be regarded as a small magnetic dipole. One method of reducing the electromagnetic wave radiation efficiency of the loop antenna to reduce the generated electromagnetic wave is to reduce the cross-sectional area of the high-frequency current loop. However, if there are many holes and cut lines in the power supply ground layer through which the return current of the digital signal flows, the cross-sectional area of the high-frequency current loop increases,
The energy of the emitted electromagnetic wave increases.

Here, the term "cut line" refers to a groove having no conductor formed in a ground layer or a power supply layer which should be a single plane conductor. Some cut lines are provided intentionally by the designer, and others are generated even though the designer does not intend.

In the cut line intentionally provided, for example, a power supply layer of 5 V and a power supply layer of 12 V are not prepared.
There is a cut line or the like created when a single power supply layer is separately used for a 5V power supply region and a 12V power supply region.

On the other hand, as the mounting density of the printed circuit board increases, unintended cut lines are generated for various reasons.

The reason why unintended cut lines are generated in the ground layer and the power supply layer will be described with reference to FIG.

FIGS. 14 (a), 14 (b) and 14 (c) show examples of unintentionally generated cut lines. FIG. 14D shows a cut line actually generated in a ground layer of a digital circuit board constituting a certain information processing apparatus.

FIG. 14A shows a high-density connector for a connector having a large number of pins, such as an additional memory slot, an additional memory slot, and an expansion bus slot, for which a module such as a memory or an I / O device needs to be inserted and removed. This is an example that occurs when an insertion type connector having a vertical pitch suitable for mounting is adopted.

FIG. 14 (b) shows a case where the wiring layers are continuously switched from the surface wiring layer to the inner wiring layer when the surface mounting parts having a vertical pitch are employed. 2.54 mm (1/10 inch) or 1.
0.317 on 27 mm (1/20 inch) grid
Unit system using channels of 5 mm (1/80 inch) spacing (3/7 channel unit system; 7 wires for 1/10 inch, 3 wires for insertion pins at 1/10 inch spacing) This is an example of a cut line that occurs when wiring is not supported in a unit system other than wiring design (manufacturing rules).
This occurs when the automatic wiring apparatus moves the via to the channel position of the supported coordinate system so that it can be regarded as a reference point of the pin.

FIG. 14 (c) shows a 3/7 channel unit system (design and manufacture in which seven wires are arranged between 1/10 inch and three wires are inserted between insertion pins spaced at intervals of 1/10 inch). Rules)
2 shows an example of a cut line generated when via holes are generated at an interval of two channels.

On the other hand, the electromagnetic wave generation model in the common mode is a small electric dipole type dipole antenna or unipole antenna. A method of reducing electromagnetic waves radiated in this mode is to lower the impedance of a power supply ground layer, which is a common line. However, if there are many holes and cut lines in the power ground layer, the inductance component increases and the impedance increases, and the high-frequency current flowing through the antenna due to the electromotive force due to the inductance component increases, and the energy of the radiated electromagnetic wave also increases.

As described above, when the shape of the power ground layer becomes full of holes and cut lines, the electromagnetic radiation in the differential mode and the electromagnetic radiation in the common mode increase, so that the electromagnetic radiation level increases.

On the other hand, in order to reduce the number of holes and cut lines in the power ground layer, the mounting density must be reduced.

An object of the present invention is to provide a printed circuit board capable of reducing radiated electromagnetic noise without lowering the component mounting density of the printed circuit board, and a method of designing and inspecting the printed circuit board. And

[0021]

To achieve the above object,
The present invention is a method for designing a multilayer printed wiring board including a power supply layer, a ground layer, and a wiring layer, wherein a specific region for wiring a signal line for a signal having a high frequency component is provided in the wiring layer by one or more. In each of the specified regions, a traveling direction of a signal line for a signal having a large high-frequency component in the specified region is set in the X direction or the Y direction orthogonal to the X direction.
Each signal line for a signal having a large high frequency component is wired in the specific region so as to be in one of the directions, and for each specific region, in a region overlapping the specific region in the vertical direction of the printed circuit board surface. The power supply layer such that the non-conductive line of the power supply layer or the ground layer in the overlapping region has the same running direction as the running direction of the signal line for a signal having a large high frequency component in the specific region. Another object of the present invention is to provide a method for designing a printed wiring board, wherein a non-conductor line is arranged on a ground layer.

[0022]

According to one embodiment of the design method according to the present invention,
Wiring between components such as ICs and LSIs on a printed circuit board is classified according to the magnitude of electromagnetic radiation noise. For example, when constructing a digital circuit such as a computer circuit, a free-running clock signal group having a high signal rising speed, a high repetition frequency of rising and falling, and a large amount of electromagnetic radiation noise is classified into a first rank. In addition, the bus control signal group having the second highest signal rising speed and the second highest repetition frequency after the clock signal group and having a large electromagnetic radiation noise amount is set as the second rank, and the bus signal group and the fourth rank are level interrupted. Other signal groups such as request signals are classified into a third rank.

The plane of the printed circuit board is designated and divided into specific wiring direction designating regions. In one region, only one of the X direction and the Y direction is determined by the wiring direction of a signal group of a rank having a large electromagnetic radiation noise amount. The longitudinal direction of the elongated cut line that is specified and has no conductor in the power and ground layers constituted by the conductor plane of the printed circuit board is set only in the same direction as the wiring direction of the signal group.

Here, the high-frequency component and the radiated electromagnetic wave energy of the digital signal are not at the same level as all the signals, and the free-running clock signal has a fast rising speed, a high repetition frequency of rising and falling, and a large amount of electromagnetic radiation noise. From "H" as in the operation mode selection signal
(High Level = 5 in a TTL logic circuit)
V) or 'L' (Low Level = normally 0 V in a TTL logic circuit) during operation, and the radiated electromagnetic wave energy is present up to what can be regarded as 0. Therefore, each signal line can be ranked according to the level of radiated electromagnetic wave energy.

The basic principle of reducing the radiated electromagnetic energy is to reduce the current loop of a signal having a high frequency current component. Therefore, by the method according to the present invention, while allowing the generation of a cut line in a fixed direction, if the wiring direction and the cut line direction of a signal having a high frequency current component are limited to the same fixed direction, the conductor of the printed circuit board can be formed. The current loop can be reduced by setting the longitudinal direction of the cut line, which is a conductor-less portion of the power supply ground layer composed of planes, to the same direction as the wiring direction of the signal group having many high-frequency current components. Energy can be reduced.

From the viewpoint of reducing the current loop, the signal wiring having a large number of high-frequency current components is not limited to the region but also to the wiring layer, as described in the later-described embodiment. Can be expected.

Also, since the impedance of the power supply ground layer in a certain direction can be reduced, the high-frequency current flowing through the unipole antenna can be reduced, and the energy of the radiated electromagnetic wave also decreases.

[0028]

Embodiments of the present invention will be described below.

FIG. 1 shows an arrangement of component blocks on a printed circuit board.

FIG. 1 shows a multilayer printed circuit board which implements a processing device circuit which is a main component of an information processing device.

In the figure, 1 is a printed circuit board, 2 is a central processing unit (hereinafter referred to as “CPU”), 3 is a clock for supplying a square wave to each sequential circuit in the processing unit circuit, 4 is a memory controller, Reference numeral 5 denotes a memory group including memories such as DRAM and SRAM, 6 denotes an additional memory slot 1, 7 denotes an additional memory slot 2, 8 denotes a system bus controller, 9
Is an expansion bus slot, 10 is an I / O controller 1, 1
1 is an I / O controller 2; 12 is an external interface connector 1 of the I / O controller 1 (10);
This is the external interface connector 2 of the / O controller 2 (11).

In FIG. 1, solid lines vertically and horizontally drawn from component blocks such as the CPU 2 and the memory controller 4 represent signal wiring between the component blocks.

Reference numeral 101 denotes X-direction wiring regions 1 and 10
2 is a Y-direction wiring region 2, 103 is a Y-direction wiring region 3, 1
Reference numeral 04 denotes the X-direction wiring region 3. The X-direction wiring area and the Y-direction wiring area will be described later. Also, 201
Is a cut line in the X direction, and 202 is a cut line in the Y direction.

Here, the X direction and the Y direction correspond to the X direction of the printed circuit board 1 shown at the lower left of FIG.
Follow the Y coordinate axis.

FIG. 1 shows an example in which a processing device circuit for controlling an auxiliary storage device, an input / output device and the like is realized by one printed circuit board, but the processing device circuit includes a plurality of printed circuit devices. In some cases, it is realized by a mounting board.

First, the arrangement of the component blocks 1 to 13 on the printed circuit board will be described.

The CPU 2 is arranged such that the bus control signal pins and the clock signal pins are located on the right side of an LSI package or a multi-chip module package embodying the CPU 2. The bus control signal pin and the clock signal pin for the system bus are located below the package of the CPU 2. Here, when the CPU 2 is custom-made, since the pin arrangement can be freely designed, there is no problem in the arrangement of the CPU 2. If the CPU 2 is an off-the-shelf standard product, it is handled by rotating the CPU package or selecting a mounting surface. Even if the CPU 2 is an existing standard product, if a package of a different type with a pin arrangement is prepared, it can be handled by selecting from among the packages.

Next, in FIG. 1, the clock 3 is
It is arranged on the right of the PU 2, on the left of the memory controller 4, and near the center of the CPU 2 and the memory controller 4. This takes into account that it is a synchronous clock shared by the CPU 2 and the memory controller 4. However, when the clock signal generated by the clock 3 is a high-speed clock (a clock having a small delay margin), the necessity of a one-stroke wiring pattern and the necessity of equal-length wiring, etc.
In some cases, it is arranged extremely close to the CPU 2 or the memory controller 4 side. When the clock signal generated by the clock 3 is common to the clock signal for the system bus, the clock 3 may be arranged at the lower right corner of the CPU 2 in some cases.

Regarding the memory controller 4 and the system bus controller 8, if the system (information processing device) has a certain size, it is often custom-made compared to the CPU 2. Can be done. On the other hand, the I / O controller 1
(10) and the probability of whether or not to adopt a custom made I / O controller 2 (11) are as follows:
It will be about the middle of the case of the memory controller 4 and the system bus controller 8.

Although the illustration is omitted for the sake of clarity, the I / O controller 1 (1
0) and near the I / O controller 2 (11), a dedicated clock having a frequency different from that of the synchronous clock used by the CPU 2, the memory controller 4, and the system bus controller 8 is substantially provided for each type of I / O. Are located in

The signals between the circuit blocks can be classified into three ranks depending on the high-frequency components of the signals. That is, from the rank of the signal having many high-frequency components, rank 1; clock of the original oscillation of clock 3 (free-run), and a clock obtained by dividing the phase of the divided clock or the clock of the original oscillation, etc. Rank 2: address Strobes such as strobes and data strobes Rank 3; addresses, data signals (bus), etc. Between the CPU 2 and the memory controller 4, a free-run clock to which rank 1 belongs, a divided clock thereof, and a free rank having a different phase. There are locks, address strobes and data strobes belonging to rank 2, addresses and data signals (buses) belonging to rank 3, and the like.

In this embodiment, the signal pins of the signal group having a higher rank are preferentially arranged on the right of the CPU 2 package and on the left of the memory controller 4 package. Therefore, CPU
2 bus control signal pins and clock signal pins etc.
It is arranged on the right side of the package of PU2. The bus control signal pins and the clock signal pins of the memory controller 4 are arranged on the left side of the package of the memory controller 4.

Next, the wiring between the signal pins having a high frequency component, which is arranged on the right side of the CPU2 package and the left side of the memory controller 4 package, is connected to the area 1 (101).
Is provided so as to run in the X direction.

Accordingly, even if the presence of the X-direction cut line in the power supply ground layer in the area 1 (101) is permitted, the size of the high-frequency current loop hardly changes and does not become extremely large. Also, regarding the common mode electromagnetic radiation, since the inductance in the X direction of the ground layer hardly increases as compared with the Y direction, the radiated electromagnetic wave hardly increases.

Therefore, in the present embodiment, the area 1 (101)
As for the power ground layer adjacent to the layer in which the wiring runs in the X direction as described later, only the power ground layer that runs along the cut line in the X direction is provided.

On the other hand, the memory controller 4 and the memory group 5
In between, there is usually no free-run clock corresponding to rank 1 described above, and row address strobe signals and column address strobe signals belonging to rank 2 (a DRAM is generally used for a large-capacity memory) And an address signal, a data signal, a refresh control signal, etc. belonging to rank 3.

Here, the wiring of the signal having many high frequency components between the memory controller 4 and the memory group 5 is located in the region 2 (10
In the specific layer of 2), it is provided so as to run in the Y direction.

Accordingly, even if the presence of the Y-direction cut line in the ground layer in the area 2 (102) is permitted, the size of the high-frequency current loop hardly changes and does not become extremely large. Also, regarding the common mode electromagnetic radiation, since the Y-direction inductance of the ground layer hardly increases as compared with the X-direction, the radiated electromagnetic wave hardly increases.

Therefore, in the region 2 (102), only the power ground layer adjacent to the layer in which the wiring runs in the Y direction is provided so as to run along the cut line in the Y direction as described later.

In the regions 3 (103) and 4 (104), similarly to the regions 1 (101) and 2 (102), the direction of the wiring and the cut line is restricted to prevent the increase of the radiated electromagnetic waves. Can be. In this embodiment, the direction of the cut line is limited, but the number of via holes is not limited, and the area for limiting the direction of the cut line is also a digital signal wiring with a large number of high frequency components arranged collectively. Therefore, the mounting density does not decrease so much because it is limited to only the region where the exists.

Next, a description will be given of how wiring and cut lines are generated in each layer of the multilayer printed circuit board according to this embodiment.

FIG. 2 shows a typical example of a layer structure of a multilayer board, which is frequently used as a printed circuit board for realizing a digital circuit of an information processing apparatus.

FIG. 2 shows an example of a multi-layer board having six layers.
There may be various cases such as a layer and a 12 layer. FIG. 2 shows the case where there is one pair of a power supply layer and a ground layer. However, a case where a plurality of pairs of a power supply layer and a ground layer are provided on a multilayer substrate, In some cases, layers are provided.

FIGS. 2 (a) and 2 (b) each show a six-layer multilayer substrate, and the first to sixth layers are given names from the A layer to the F layer.

In the multilayer substrate of FIG. 2A, a C layer is allocated to a ground layer and a D layer is allocated to a power supply layer.
In the multi-layer board of (b), the ground layer is the B layer and the power supply layer is the E layer.
Tiers are assigned.

Normally, in a multilayer substrate, when automatic wiring is performed by a wiring pattern generation device, wiring is performed only in the X direction in a certain layer and only in the Y direction in a certain layer. Such wiring directions are indicated by thick arrows in the figure. 2A and 2B, A
In the layer, wiring is performed only in the X direction, and in the F layer, wiring is performed only in the Y direction.

FIG. 3 shows the wiring and cut lines of a printed wiring board manufactured using the multilayer board shown in FIG. 2A. Also, FIG.
1 shows the wiring and cut lines of a printed wiring board manufactured using the multilayer board shown in FIG. here,
In the printed circuit boards shown in FIGS. 3 and 4, non-through vias are used to connect wiring between layers.

In the printed circuit board shown in FIG. 3, a signal having many high-frequency components and high energy is wired to the BE layer closest to the power supply-ground layer, and in the printed circuit board shown in FIG. High signal is power-
Wiring is performed on the C and D layers sandwiched between the ground layers to efficiently suppress radiated electromagnetic wave energy.

Further, a solid (plane) layer (layer C, layer D, layer E in FIG. 4B) adjacent to a signal wiring layer (layer B in FIG. 3B, layer E, layer C in FIG. 4C) having a large number of high frequency components. layer)
However, the direction of the cut line in the region corresponding to the signal wiring having a high high frequency component is restricted as described above.

The difference between the printed circuit boards of FIGS. 3 and 4 is in which layer the signal wiring having a high frequency component (rank) is performed.

As described above, the method of permitting only the specific traveling direction of the cut line to only one of the power supply and ground layers is applicable mainly when a non-penetrating via hole is employed.

Further, in the two layers sandwiching the high-energy signal wiring with many high-frequency components (in the case of a multi-layer substrate having two or more power-ground layers), a region corresponding to the signal wiring with many high-frequency components is provided. The running direction of the cut line
Both may be restricted. In the examples of FIGS. 3 and 4, a signal having many high-frequency components and high energy is arranged in the wiring layer adjacent to the power / ground layer, and the direction of the cut line of the power layer / ground layer adjacent to the wiring layer is changed. However, even when the power / ground layer is not adjacent to the wiring layer on which a high-energy signal having a lot of high-frequency components is arranged, if the direction of the cut line of the power / ground layer is restricted, the radiated electromagnetic wave energy is reduced. Can be suppressed to a low level.

Now, the wiring and mounting density of printed circuit boards are increasing due to the high performance, high function, large scale, and downsizing of information processing apparatuses. Designing patterns is difficult. Therefore, implementation,
Wiring needs to be implemented by an automatic or interactive wiring pattern generation device by incorporating its function.

Hereinafter, such a wiring pattern generating apparatus will be described.

FIG. 5 shows the configuration of the wiring pattern generation device.

In the figure, 51 is a display device, 52 is a data processing device, 53 is a keyboard, 54 is a position information input device such as a mouse pointer, 55 is an audio output device 56 is a printing device,
Reference numeral 57 denotes a file input device, and 58 denotes other various input devices. Such a wiring pattern generation device can be configured using a general-purpose computer.

Now, as shown in FIG. 6, the data processing device converts the component data 63, connection information and the like fetched from the file input device 57 and the like in accordance with the sequence described in the CAD program 61 operating on the OS. Based on the board design data 64 including the design rule data 64,
A wiring pattern is generated in accordance with an input from the keyboard 53 or the position information input device 54. Further, according to the algorithm described in the CAD program 61, it is determined whether or not the generated wiring pattern complies with the design rule by referring to the design rule data.

FIG. 7 shows a wiring pattern generation processing procedure of the wiring pattern generation apparatus according to this embodiment.

The wiring pattern generating apparatus first displays a display simulating the design target substrate as shown in FIG. 8 on the display device 51, and on this display, the keyboard 53 and the position information input device 54 are displayed. In addition to the specification of the arrangement of the component blocks, the specification of the X-direction area and the Y-direction area, the specification of the signal rank, the specification of a specific signal or a layer to which a signal belonging to a specific rank is wired, and the specification of Wiring conditions such as designation of an area where generation of cut lines other than (intended) cut lines is prohibited, designation of cut lines, designation of an area where cut lines may be provided in the X direction and Y direction, etc. The designation is received (step 70).

Next, based on the sequence described in the CAD program 61, the design rule data 64 is referred to based on the component data 63 fetched from the file input device 57 and the like and the board design data 64 including connection information and the like. Then, a wiring pattern is generated in accordance with the designation in step 70, and the position of the via hole (through hole) is determined (steps 71 and 73). Here, in the wiring pattern generation processing of step 71, as shown in FIG. 9B, in the layer adjacent to the signal wiring, the designated cut line exists so as to cross the traveling direction of the signal wiring. To detect
The signal wiring for pattern design is set so as to bypass the cut line. This detour is performed so that the wiring length of the signal wiring becomes the shortest.

Then, it is checked whether the generated wiring pattern satisfies the conventional design rule with reference to the design rule data 64 (step 74). Wiring pattern
Is changed (step 72), and the via hole (through
The position of the hole is determined (step 73), and the design rule is checked again.

If the conventional design rules are adhered to, the designation of the X-direction area and the Y-direction area accepted in step 70, the designation of the rank of the signal, and the belonging to a specific signal or a specific rank are performed. For example, designation of a layer to which a signal is to be wired, designation of a region in which generation of a cut line other than a specified (intended) cut line is prohibited, and a region in which cut lines may be provided in the X and Y directions in a mixed manner. Check that the designation is respected.

For example, if the Y direction area (Y area)
When a cut line continuous in the X direction is generated (steps 76 and 77) or when a cut line continuous in the Y direction is generated in the X direction area (X area) (steps 76 and 78). Changes the wiring pattern (step 72). And viahole (sulfur-
Is determined (step 73), and the design rule is again
Check the file. The finally generated wiring pattern data is output from the file input / output device 57.

As shown in FIG. 9A, the change of the wiring pattern in step 72 is performed by using a signal having many high-frequency components and high energy (hereinafter simply referred to as "signal" in FIG. 9).
The CAD program 61 has a function to detect whether a cut line due to the clearance of a via hole is generated immediately below (e.g., an adjacent ground layer) orthogonally to the signal (meaning that the cut line is not parallel) and to automatically move the via hole immediately below the signal. It is realized by preparing. This detection is performed on the conductor plane layer of the conductor plane layer adjacent to the wiring layer of the signal line.
The presence or absence of the conductor around the position overlapping the signal line can be determined by referring to the generated wiring pattern data.

If the wiring pattern generation apparatus interactively accepts a change in the wiring pattern from the designer, a specific display is displayed on the display device 51 when an attempt is made to generate a via hole immediately below. And a function for notifying the designer of the error is provided. Also, as shown in FIG. 9C, if a cut line crossing the signal wiring is specified,
A function is provided in which an error or warning is displayed on the display device 51 or generated by the audio output device 55, and a cut line crossing the signal wiring cannot be generated. Alternatively, as shown in FIG. 9B, it is detected that the designated cut line exists in the traveling direction of the signal wiring, and the signal wiring for pattern design is detoured so as to bypass the cut line. Provide a function to set. At this time, the designer can select whether to generate an error or change the signal wiring. The error or warning is output by the data processing device 50 by changing the color tone, brightness, saturation, blink cycle of the offending pattern being displayed on the display device 51, by displaying characters on the screen, or by displaying a file. This is performed by output to the top. By the way, as shown in FIG. 10, when it is necessary to provide a cut line across the signal wiring, a high-frequency wave is placed immediately below / above the signal wiring between the cut lines of the power supply and the ground layer (the position overlapping in the Z-axis projection). By mounting a capacitor having good characteristics as a bypass capacitor, radiated electromagnetic wave energy can be suppressed.

Then, it is recognized that such a measure is taken on the circuit in the wiring pattern generation apparatus. In this case, even if there is a cut line crossing the signal wiring, error processing is not performed. CAD program 61
A function may be provided. Alternatively, a function for designing the wiring pattern so that the signal may be positively overlapped with the bypass capacitor in the Z-axis projection may be provided.

As described above, according to the present embodiment,
The direction of travel of the signal having many high frequency components and the cut line is restricted as shown in FIGS.

Hereinafter, data showing that the amount of radiant energy of electromagnetic waves is reduced by such a restriction will be shown.

FIG. 11 is a schematic configuration diagram of an experimental circuit board for measuring the effect of radiated electromagnetic waves when a cut line orthogonal to a signal line exists in the power-ground layer. FIG. 12 is a schematic diagram of measurement equipment and a method for measuring the influence of radiated electromagnetic waves when a cut line orthogonal to a signal line exists in a layer, and FIG. 12 is a cut line orthogonal to a signal line in a power-ground layer. 7 is a graph of a result of measuring an influence of a radiated electromagnetic wave when the presence exists.

As shown in FIG. 11, an object to be measured is a transmission line of a digital circuit. The transmission line is supplied with an oscillation clock of 14 MHz by a TTL 74 series element 74F.
04, and transmitted a line length of 190 mm terminated with a resistance load of 37Ω. The substrate uses a two-layer substrate with a ground plane on the back side, and the characteristic impedance of the line is
It is. The width of the cut line is 1 mm and the length is Wm
m is a variable.

The measurement was performed by the 3 m method as shown in FIG. Then, the measurement data was captured by a spectrum analyzer, captured by a control computer by GPIB, and further captured by a computer for data processing to create a graph showing an increase in radiation noise.

FIG. 13 shows the length Wmm of the cut line.
The experiment result graph in the case of making it 20, 40, 60 is shown.
The peak is about 12 dB at 20 mm and 20 d at 40 mm
For B and 60 mm, the increase is about 25 dB.

As described above, when there is a cut line orthogonal to the signal line in the power supply-ground layer, the radiant energy of the electromagnetic wave increases, and when there is no orthogonal cut line, the radiant energy of the electromagnetic wave decreases. .

As described above, according to this embodiment, by limiting the direction of the cut line, it is possible to realize a digital circuit mounting board having low radiated electromagnetic wave energy. In addition, the number of via holes is not limited, and the area for limiting the direction of the cut line is also limited only to the area where the digital signal wirings with many high-frequency components are collectively arranged. , Does not decrease much.

That is, it is possible to provide a digital circuit mounting board with low radiated electromagnetic wave energy, which does not involve a decrease in mounting density and an increase in manufacturing cost, and thus it is possible to provide an inexpensive information processing apparatus with low radiated electromagnetic wave energy.

Further, by providing the above-described function in the wiring pattern generation device, the manufacturing data of the digital circuit mounting board having low radiated electromagnetic wave energy can be obtained without lowering the mounting density and increasing the manufacturing cost. It is possible to provide an information processing apparatus which can be easily created, and which is inexpensive and has low radiated electromagnetic energy.

Further, since it is easy to realize constant impedance control, a higher-speed and higher-performance information processing apparatus can be realized.

In the above description, the digital circuit board constituting the information processing apparatus is taken as an example. However, the present embodiment is not limited to the digital circuit board of the information processing apparatus but is generally applied to a multi-layer digital circuit board. can do.

[0089]

As described above, according to the present invention, a printed circuit board capable of reducing radiated electromagnetic noise without lowering the component mounting density of the printed circuit board, and a method of designing the printed circuit board are provided. Can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a printed circuit board according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram illustrating a layer configuration of a multilayer printed circuit board.

FIG. 3 is an explanatory diagram showing the running directions of wiring and cut lines on a printed circuit board according to one embodiment of the present invention.

FIG. 4 is an explanatory diagram showing the running directions of wiring and cut lines on a printed circuit board according to one embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a wiring pattern generation device according to one embodiment of the present invention.

FIG. 6 is an explanatory diagram showing data used for generating a wiring pattern.

FIG. 7 is a flowchart showing a wiring pattern generation processing procedure of the wiring pattern generation device according to one embodiment of the present invention.

FIG. 8 is an explanatory diagram showing a display example performed by the wiring pattern generation device according to one embodiment of the present invention.

FIG. 9 is an explanatory diagram showing functions of a wiring pattern generation device according to one embodiment of the present invention.

FIG. 10 is an explanatory diagram showing functions of a wiring pattern generation device according to one embodiment of the present invention.

FIG. 11 is an explanatory view showing an object of a radiation electromagnetic noise measurement experiment.

FIG. 12 is an explanatory diagram showing experimental equipment for an experiment for measuring radiation electromagnetic noise.

FIG. 13 is an explanatory diagram showing a result of a radiation electromagnetic noise measurement experiment.

FIG. 14 is an explanatory diagram showing an example of a cut pattern.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Printed circuit board 2 CPU 3 Clock 4 Memory controller 5 Memory group 6 Additional memory slot 1 7 Additional memory slot 2 8 System bus controller 9 Expansion bus slot 10 I / O controller 1 11 I / O controller 2 12 Connector 1 13 Connector 2 101 Area 1 102 area 2 103 area 3 104 area 3 201 X-direction cut line 202 Y-direction cut line

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Yoshidome, etc. 1 Horiyamashita, Hadano-shi, Kanagawa Prefecture Hitachi, Ltd. Kanagawa Plant (72) Inventor Kazuo Hirota 1st Horiyamashita, Hadano-shi, Kanagawa Hitachi, Ltd. Kanagawa Plant (72) Inventor Yutaka Akiba 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Pref. Hitachi, Ltd. Production Engineering Laboratory (56) References JP-A-4-355950 (JP, A) JP-A-4-54676 ( JP, A) JP-A-2-121393 (JP, A) JP-A-58-171888 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 17/50 H05K 3/00 H05K 3/46

Claims (5)

(57) [Claims] 1. A method of designing a multilayer printed wiring board including a power supply layer, a ground layer, and a wiring layer, wherein a specific region for wiring a signal line for a signal having a large high frequency component is provided in the wiring layer. Alternatively, a plurality of signals are set, and in each of the set specific regions, the traveling direction of the signal line for a signal having a large high-frequency component in the specific region is one of the X direction and the Y direction orthogonal to the X direction. A signal line for a signal having a large high-frequency component is wired in the specific region; and for each specific region, in a region overlapping the specific region in a direction perpendicular to the printed circuit board surface, the power supply layer in the overlapping region Alternatively, the power supply layer or the power supply layer may be so arranged that the non-conductor line of the ground layer has the same running direction as the running direction of the signal line for a signal having a high high frequency component in the specific area. Printed circuit board design method characterized by placing a non-conductive line command layer. 2. A wiring so as to satisfy a given constraint condition.
Using a wiring pattern generator that generates patterns,
Multi-layer printing including source layer, ground layer and multiple wiring layers
Printed wiring board that automatically generates wiring patterns for wiring boards
This is a board design method, in which the direction of travel of the wiring of each wiring layer is set in one direction, and the signal lines to be wired are set according to the easiness of electromagnetic radiation noise.
Te, classified into a plurality of ranks, setting a signal line belonging to occur easily rank of the electromagnetic radiation noise
Wiring signal lines of a rank that is likely to generate electromagnetic radiation noise
One or more specific regions to be
Set on the wiring layer adjacent to the land layer, and in the specific area, in the vertical direction of the printed circuit board surface
A wiring layer in which the specific region is provided in an overlapping region
Area on the power supply layer or ground layer adjacent to
The power supply layer or the graph in the overlapping area.
Non-conductor lines in the
Traveling in the same direction as the traveling direction of the signal line for large signals
In the power supply layer or the ground layer so that
With or without conductor lines, the vertical direction of the printed circuit board surface should be
Area that overlaps in the
Above the power supply layer or ground layer adjacent to the wiring layer
About the specific area in the area specific area that is the area of
Other than running in the same direction as the wiring running direction of the set wiring layer
The generation of the non-conductor line in the traveling direction is set to be prohibited, and each setting content is set as a constraint condition, and the wiring pattern generation device is set.
Automatically generate wiring patterns
Printed wiring board design method. 3. A method for designing a printed wiring board according to claim 2.
A law, the printed wiring board includes at least a CPU and a memory
Pre-computer for forming a circuit including a bus and a computer
A plurality of printed circuit boards, each of which is classified according to the likelihood of occurrence of the electromagnetic radiation noise.
Rank is the most electromagnetic to which the signal line for the free-running clock signal group belongs.
The rank at which radiation noise is likely to occur and the second to which the bus control signal group signal line belongs
And the third to which the bus signal group signal line belongs
For ranks that are likely to occur, and for signal lines for level interrupt request signals and other signal groups
The rank to which the signal line belongs, which is the least likely to generate electromagnetic radiation noise
And a method of designing a printed wiring board characterized by including
Law. 4. A multilayer including a power supply layer, a ground layer, and a wiring layer.
Pattern that generates the wiring pattern of a printed wiring board
Means for receiving designation of a specific signal, and for generating the wiring pattern,
Power supply layer or
Across any of the wiring for the specific signal
Means for inspecting whether a cut line exists; and, as a result of the inspection, traversing one of the wirings for a specific signal.
If there is a cut line that
Formed by the clearance between the conductors in the via hole
The via hole arrangement,
The cut line formed by the interbody clearance is in front
Not to cross the specified signal wiring
Means for changing the position to satisfy the condition.
Wiring pattern generator. 5. A first layer including a cut line and said cut layer.
Install a capacitor at the position connecting both sides of the
Means for connecting both terminals of the capacitor to the first layer;
And a second layer provided.
Board.