CN113923898B - Manufacturing method and application of dual-channel memory bank - Google Patents
Manufacturing method and application of dual-channel memory bank Download PDFInfo
- Publication number
- CN113923898B CN113923898B CN202111136826.7A CN202111136826A CN113923898B CN 113923898 B CN113923898 B CN 113923898B CN 202111136826 A CN202111136826 A CN 202111136826A CN 113923898 B CN113923898 B CN 113923898B
- Authority
- CN
- China
- Prior art keywords
- layer
- pcb
- board
- manufacturing
- inner layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000015654 memory Effects 0.000 title claims abstract description 39
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 32
- 238000003475 lamination Methods 0.000 claims abstract description 16
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 24
- 229910052802 copper Inorganic materials 0.000 claims description 24
- 239000010949 copper Substances 0.000 claims description 24
- 238000000151 deposition Methods 0.000 claims description 18
- 230000008021 deposition Effects 0.000 claims description 15
- 238000005553 drilling Methods 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 12
- 239000000047 product Substances 0.000 claims description 9
- 238000004381 surface treatment Methods 0.000 claims description 9
- 238000009713 electroplating Methods 0.000 claims description 8
- 238000010030 laminating Methods 0.000 claims description 8
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 6
- 238000007747 plating Methods 0.000 claims description 6
- 229910000679 solder Inorganic materials 0.000 claims description 5
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 239000011265 semifinished product Substances 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 239000004332 silver Substances 0.000 claims description 3
- 238000005507 spraying Methods 0.000 claims description 3
- 230000009286 beneficial effect Effects 0.000 abstract description 3
- 230000002787 reinforcement Effects 0.000 abstract description 3
- 238000002360 preparation method Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 384
- 238000004891 communication Methods 0.000 description 9
- 238000011161 development Methods 0.000 description 7
- 239000000758 substrate Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 230000001681 protective effect Effects 0.000 description 4
- 238000013461 design Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 238000005530 etching Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 230000003993 interaction Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000006479 redox reaction Methods 0.000 description 1
- 230000003014 reinforcing effect Effects 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/16—Constructional details or arrangements
- G06F1/18—Packaging or power distribution
- G06F1/183—Internal mounting support structures, e.g. for printed circuit boards, internal connecting means
- G06F1/185—Mounting of expansion boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
- H05K3/0047—Drilling of holes
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Human Computer Interaction (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The invention relates to a manufacturing method of a dual-channel memory bar, and belongs to the technical field of printed circuit board preparation. The manufacturing method of the dual-channel memory strip comprises the steps of dividing the dual-channel memory strip into two parts which are vertically symmetrical based on the middle according to the lamination number of the PCB: the first PCB primary product plate comprises an A-layer PCB inner layer plate, a top layer and a bottom layer of first PCB outer layer plate, and the second PCB primary product plate comprises a B-layer PCB inner layer plate, a top layer and a bottom layer of second PCB outer layer plate; and respectively manufacturing inner-layer circuits of the A-layer PCB inner layer board and the B-layer PCB inner layer board, and respectively performing lamination treatment on the A-layer PCB inner layer board, the top and bottom two-layer first PCB outer layer boards, the B-layer PCB inner layer board and the top and bottom two-layer second PCB outer layer boards to obtain an outer A-layer PCB board and an outer B-layer PCB board. The beneficial effects are that: 2 channel memories can be made on one memory bar, so that the reinforced memory bar in the horizontal buckling mode fully utilizes the number of memory bar channels of the CPU and achieves the aim of reinforcement.
Description
Technical Field
The invention belongs to the field of preparation of printed circuit boards, and particularly relates to a manufacturing method of a dual-channel memory bank.
Background
The traditional memory is inserted on the connector of the main board in a golden finger mode, and the memory is not shock-proof and shock-proof, and is generally only provided with one channel. In order to improve the shock resistance and impact resistance of the memory, the invention adopts a horizontal buckling mode to buckle the memory on the main board. Because the snap-in mode occupies the original 2 memory channels, it requires 2 channels to be implemented on the horizontal memory.
Disclosure of Invention
In order to solve the technical problems, the invention provides a manufacturing method of a dual-channel memory bar, wherein 2 channel memories can be manufactured on one memory bar, so that the horizontal type fastening type memory bar is reinforced, the number of memory bar channels of a CPU is fully utilized, and the aim of reinforcement is achieved.
The technical scheme for solving the technical problems is as follows: the manufacturing method of the dual-channel memory bank comprises the following steps: comprising
S1: the PCB is divided into two parts which are symmetrical up and down based on the middle according to the lamination number of the PCB: the first PCB primary product plate comprises an A-layer PCB inner layer plate, a top layer and a bottom layer of first PCB outer layer plate, and the second PCB primary product plate comprises a B-layer PCB inner layer plate, a top layer and a bottom layer of second PCB outer layer plate;
s2: respectively manufacturing an inner layer circuit of the A-layer PCB inner layer board and an inner layer circuit of the B-layer PCB inner layer board, and respectively performing lamination treatment on the A-layer PCB inner layer board, the top layer, the bottom layer, the first PCB outer layer board, the B-layer PCB inner layer board, the top layer, the bottom layer and the second PCB outer layer board to obtain an outer A-layer PCB board and an outer B-layer PCB board;
s3: drilling holes on the outer A-layer PCB and the outer B-layer PCB respectively, and manufacturing a first outer layer board circuit of a bottom layer of the outer A-layer PCB and a second outer layer board circuit of a top layer of the outer B-layer PCB;
s4: performing secondary lamination on the outer layer A PCB and the outer layer B PCB to obtain a semi-finished board;
s5: drilling holes on the semi-finished product board, manufacturing a top first PCB outer layer board, a bottom second PCB outer layer board outer layer circuit, electroplating, and performing surface treatment to obtain the finished product PCB.
On the basis of the technical scheme, the invention can be improved as follows.
In step S1, the inner layer board of the PCB a and the top and bottom two outer layers of the first PCB include an L1 layer, an L2 layer, an L3 layer, an L4 layer, an L5 layer, an L6 layer, an L7 layer, and an L8 layer, which are sequentially disposed from top to bottom; the B-layer PCB inner layer board and the top and bottom two-layer second PCB outer layer board comprise an L9 layer, an L10 layer, an L11 layer, an L12 layer, an L13 layer, an L14 layer, an L15 layer and an L16 layer which are sequentially arranged from top to bottom.
In step S2, the inner layer circuit of the inner layer board of the PCB of the a layer specifically includes an L2 layer and an L3 layer, an L4 layer and an L5 layer, and an L6 layer and an L7 layer, which are sequentially and individually subjected to inner layer dry film and browning, and then the adjacent layers of the L1 layer, the L2 layer and the L3 layer, the L4 layer and the L5 layer, the L6 layer and the L7 layer, and the L8 layer are laminated by PP; and the inner layer circuit of the B-layer PCB inner layer board is manufactured by sequentially and independently carrying out inner layer dry film and browning on an L10 layer, an L11 layer, an L12 layer, an L13 layer, an L14 layer and an L15 layer, and then laminating adjacent layers of an L9 layer, an L10 layer, an L11 layer, an L12 layer, an L13 layer, an L14 layer, an L15 layer and an L16 layer by using PP.
Further, in step S3, copper deposition is required after the outer layer a PCB and the outer layer B PCB are drilled, and finally plating is performed.
Further, in step S4, PP lamination is adopted between the outer layer a PCB and the outer layer B PCB.
In step S5, a green solder resist is applied after plating and before surface treatment.
Further, in step S5, the surface treatment specifically includes tin spraying, gold deposition, OSP, tin deposition, and silver deposition.
The beneficial effects are that:
2 channel memories can be made on one memory bar, so that the reinforced memory bar in the horizontal buckling mode fully utilizes the number of memory bar channels of the CPU and achieves the aim of reinforcement.
Drawings
FIG. 1 is a schematic diagram of a 16-layer PCB laminate structure;
FIG. 2 is a schematic diagram of drilling a PCB;
FIG. 3 is a schematic diagram of a communication mode between the A channel and the motherboard;
FIG. 4 is a schematic diagram of a communication mode between the B channel and the motherboard;
Detailed Description
The principles and features of the present invention are described below with reference to the drawings, the examples are illustrated for the purpose of illustrating the invention and are not to be construed as limiting the scope of the invention.
Examples
As shown in fig. 1-4, this embodiment provides a method for manufacturing a dual-channel memory bank, including:
s1: the PCB is divided into two parts which are symmetrical up and down based on the middle according to the lamination number of the PCB: the first PCB primary product plate comprises an A-layer PCB inner layer plate, a top layer and a bottom layer of first PCB outer layer plate, and the second PCB primary product plate comprises a B-layer PCB inner layer plate, a top layer and a bottom layer of second PCB outer layer plate;
s2: respectively manufacturing an inner layer circuit of the A-layer PCB inner layer board and an inner layer circuit of the B-layer PCB inner layer board, and respectively performing lamination treatment on the A-layer PCB inner layer board, the top layer, the bottom layer, the first PCB outer layer board, the B-layer PCB inner layer board, the top layer, the bottom layer and the second PCB outer layer board to obtain an outer A-layer PCB board and an outer B-layer PCB board;
s3: drilling holes on the outer A-layer PCB and the outer B-layer PCB respectively, and manufacturing a first outer layer board circuit of a bottom layer of the outer A-layer PCB and a second outer layer board circuit of a top layer of the outer B-layer PCB;
s4: performing secondary lamination on the outer layer A PCB and the outer layer B PCB to obtain a semi-finished board;
s5: drilling holes on the semi-finished product board, manufacturing a top first PCB outer layer board, a bottom second PCB outer layer board outer layer circuit, electroplating, and performing surface treatment to obtain the finished product PCB.
Further, the inner layer circuit of the A-layer PCB inner layer plate is manufactured by sequentially and independently carrying out inner layer dry film and browning on an L2 layer, an L3 layer, an L4 layer, an L5 layer and an L6 layer and an L7 layer, and then laminating adjacent layers of the L1 layer, the L2 layer, the L3 layer, the L4 layer, the L5 layer, the L6 layer, the L7 layer and the L8 layer by PP; and the inner layer circuit of the B-layer PCB inner layer board is manufactured by sequentially and independently carrying out inner layer dry film and browning on an L10 layer, an L11 layer, an L12 layer, an L13 layer, an L14 layer and an L15 layer, and then laminating adjacent layers of an L9 layer, an L10 layer, an L11 layer, an L12 layer, an L13 layer, an L14 layer, an L15 layer and an L16 layer by using PP.
Specifically, the inner layer dry film comprises multiple procedures of inner layer film pasting, exposure and development, inner layer etching and the like. The inner layer film is a special photosensitive film, namely a dry film, is stuck on the surface of the copper plate. The film cures when exposed to light, forming a protective film on the board. The exposure and development are to expose the film-attached plate, the light-transmitting portion is cured, and the light-non-transmitting portion is a dry film. The uncured dry film is then removed by development, and the plate with the cured protective film attached is etched. Then the film is removed, and the circuit pattern of the inner layer is transferred to the board.
Brown oxide purpose: the copper surface of the inner layer is formed into a microcosmic rough and organic metal layer, so that the adhesion between layers is enhanced. The flow principle is as follows: an organic metal layer structure with uniform and good bonding characteristics is generated through chemical treatment, so that the surface of the copper layer before the inner layer is bonded is roughened in a controlled way, and the bonding strength between the copper layer of the inner layer and the prepreg after the pressing plate is enhanced.
In step S1, the inner layer board of the PCB a and the top and bottom two outer layers of the first PCB include an L1 layer, an L2 layer, an L3 layer, an L4 layer, an L5 layer, an L6 layer, an L7 layer, and an L8 layer, which are sequentially disposed from top to bottom; the B-layer PCB inner layer board and the top and bottom two-layer second PCB outer layer board comprise an L9 layer, an L10 layer, an L11 layer, an L12 layer, an L13 layer, an L14 layer, an L15 layer and an L16 layer which are sequentially arranged from top to bottom.
In step S2, the inner layer circuit of the inner layer board of the PCB of the a layer specifically includes an L2 layer and an L3 layer, an L4 layer and an L5 layer, and an L6 layer and an L7 layer, which are sequentially and individually subjected to inner layer dry film and browning, and then the adjacent layers of the L1 layer, the L2 layer and the L3 layer, the L4 layer and the L5 layer, the L6 layer and the L7 layer, and the L8 layer are laminated by PP; and the inner layer circuit of the B-layer PCB inner layer board is manufactured by sequentially and independently carrying out inner layer dry film and browning on an L10 layer, an L11 layer, an L12 layer, an L13 layer, an L14 layer and an L15 layer, and then laminating adjacent layers of an L9 layer, an L10 layer, an L11 layer, an L12 layer, an L13 layer, an L14 layer, an L15 layer and an L16 layer by using PP.
Specifically, the inner layer dry film comprises multiple procedures of inner layer film pasting, exposure and development, inner layer etching and the like. The inner layer film is a special photosensitive film, namely a dry film, is stuck on the surface of the copper plate. The film cures when exposed to light, forming a protective film on the board. The exposure and development are to expose the film-attached plate, the light-transmitting portion is cured, and the light-non-transmitting portion is a dry film. The uncured dry film is then removed by development, and the plate with the cured protective film attached is etched. Then the film is removed, and the circuit pattern of the inner layer is transferred to the board.
Brown oxide purpose: the copper surface of the inner layer is formed into a microcosmic rough and organic metal layer, so that the adhesion between layers is enhanced. The flow principle is as follows: an organic metal layer structure with uniform and good bonding characteristics is generated through chemical treatment, so that the surface of the copper layer before the inner layer is bonded is roughened in a controlled way, and the bonding strength between the copper layer of the inner layer and the prepreg after the pressing plate is enhanced.
In step S1, the inner layer board of the PCB a and the top and bottom two outer layers of the first PCB include an L1 layer, an L2 layer, an L3 layer, an L4 layer, an L5 layer, an L6 layer, an L7 layer, and an L8 layer, which are sequentially disposed from top to bottom; the B-layer PCB inner layer board and the top and bottom two-layer second PCB outer layer board comprise an L9 layer, an L10 layer, an L11 layer, an L12 layer, an L13 layer, an L14 layer, an L15 layer and an L16 layer which are sequentially arranged from top to bottom.
In step S2, the inner layer circuit of the inner layer board of the PCB of the a layer specifically includes an L2 layer and an L3 layer, an L4 layer and an L5 layer, and an L6 layer and an L7 layer, which are sequentially and individually subjected to inner layer dry film and browning, and then the adjacent layers of the L1 layer, the L2 layer and the L3 layer, the L4 layer and the L5 layer, the L6 layer and the L7 layer, and the L8 layer are laminated by PP; and the inner layer circuit of the B-layer PCB inner layer board is manufactured by sequentially and independently carrying out inner layer dry film and browning on an L10 layer, an L11 layer, an L12 layer, an L13 layer, an L14 layer and an L15 layer, and then laminating adjacent layers of an L9 layer, an L10 layer, an L11 layer, an L12 layer, an L13 layer, an L14 layer, an L15 layer and an L16 layer by using PP.
Further, in step S3, copper deposition is required after the outer layer a PCB and the outer layer B PCB are drilled, and finally plating is performed.
Specifically, copper deposition: also called chemical copper, the drilled PCB board generates oxidation-reduction reaction in a copper deposition cylinder to form a copper layer so as to carry out hole metallization on the holes, and copper is deposited on the surface of the original insulated substrate to achieve interlayer electrical communication.
Plating: the copper in the plate surface and the hole of the PCB just deposited with copper is thickened to 5-8um, so that the thin copper in the hole is prevented from being oxidized and micro-etched to leak the substrate before pattern electroplating.
Further, in step S4, PP lamination is adopted between the outer layer a PCB and the outer layer B PCB.
In step S5, a layer of solder resist is coated on the plate surface by screen printing or solder resist ink, and the plate and holes to be soldered are exposed by exposure and development, and the solder resist layer is covered on other places to prevent short circuit during soldering.
Further, in step S5, the surface treatment specifically includes tin spraying, gold deposition, OSP, tin deposition, and silver deposition.
As can be seen from fig. 1, the present invention divides the PCB structure into two parts symmetrical up and down, and is limited by PP in the middle of L8 and L9, the upper 8 layers are an independent board, the lower 8 layers are also independent boards, and all are completed by the conventional PCB process; after the completion, the upper PCB and the lower PCB are pressed together through the middle PP, and then the drilling electroplating is carried out. The invention adopts a mode of externally adding through holes (see fig. 3 and 4 in detail) in a mode similar to blind holes, and realizes that the memory strips with 2 channels are manufactured on the same PCB through 2 times of electroplating on the surface layer.
Of course, the number of A, B layers can be an odd number layer and an even number layer, the number of the layers is not limited, and the number of the layers is determined according to actual situation requirements.
For the AB number of layers is an odd number of layers: for example, the total number of layers of the PCB is 18.
The layer A comprises the top layers of L2 and L3, L4 and L5, L6 and L7, L8 and L9 and L1, wherein the layer L9 is the bottom layer of the layer A.
Respectively manufacturing lines on the inner-layer substrates L2 and L3, L4 and L5, and L6 and L7, and manufacturing only L8-layer lines when manufacturing the inner-layer substrates L8 and L9;
and (3) laminating the layer A: the middle parts of L1, L2 and L3, L4 and L5, L6 and L7, and L8 and L9 are integrated by PP lamination;
and (3) drilling a layer A, and depositing copper: drilling holes on the layer A in the drilling design, and depositing copper;
manufacturing a bottom layer L9 layer circuit of the A;
and (5) electroplating the layer A.
The layer B comprises the bottom layers of the PCB substrate layers L10 and L11, L12 and L13, L14 and L15, L16 and L17 and L18, wherein L10 is the top layer of B.
The circuit fabrication is carried out on the inner layer substrates L12 and L13, L14 and L15, L16 and L17 respectively, and only L11 layers of circuits are fabricated when the inner layer substrates L10 and L11 are fabricated;
laminating the B layers: the middle of the layers L10 and L11, L12 and L13, L14 and L15, L16 and L17 and the layer L18 are pressed into a whole by PP;
b layer drilling and copper deposition: drilling holes on the B layer part in the drilling design, and depositing copper;
b, manufacturing a top layer L10 layer circuit;
and B, electroplating.
Thus, the PCB of the layer A and the PCB of the layer B are manufactured, the layer A and the layer B are pressed by PP for the second time, holes of the through hole part in the drilling design are drilled, and copper is deposited; then, manufacturing a top layer circuit and a bottom layer circuit of the whole PCB; and finally, performing green oil resistance welding and surface treatment.
As can be seen in fig. 2, this PCB fabrication method solves the problem that 2 channels work on the same PCB board. The borehole 1 is a type of borehole, and is a plurality of boreholes, not a single borehole. Similarly, borehole 2 and borehole 3 are also referred to as a type of borehole.
In fig. 3, in the communication mode between the channel a and the motherboard, signals from the motherboard reach the portion a of the PCB through the drill hole 1, and then the drill hole 2 of the portion a can be connected with the drill hole 1 through any one of the layers L1-L8, so as to achieve the communication between the motherboard and the memory channel a. Borehole 2 and borehole 3 are separated by a Prepreg between L8 and L9, which have no electrical connection between them, so borehole 2 can only connect all signals of the a-channel.
In fig. 4, the communication mode is that the B channel is communicated with the motherboard, the signal from the motherboard passes through the drill hole 1 to reach the B part of the PCB board, and then the drill hole 3 of the B part can be connected with the drill hole 1 through any one of the layers L9-L16 to achieve the communication between the motherboard and the memory a channel. Borehole 2 and borehole 3 are separated by a Prepreg between L8 and L9, which have no electrical connection between them, so borehole 3 can only connect all signals of the B channel.
In summary, the memory a and B are completely separated due to the presence of the PP in the middle. If communication is required between memory parts a and B, then signals need to travel from borehole 2 to borehole 1 and then to borehole 3.
The beneficial effects are that: the PCB is divided into symmetrical structures, the symmetrical structures are manufactured respectively, then the PCB is pressed, drilled and electroplated, so that 2 channel memories can be manufactured on one memory bar perfectly, the reinforced memory bar in the horizontal buckling and clamping mode fully utilizes the number of memory bar channels of the CPU, and the reinforcing purpose is achieved.
In the description of the present invention, it should be understood that the terms "center", "length", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "inner", "outer", "peripheral side", "circumferential", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the system or element in question must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention.
In the description of the present invention, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.
In the present invention, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly, through intermediaries, or both, may be in communication with each other or in interaction with each other, unless expressly defined otherwise. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
The foregoing description of the preferred embodiments of the invention is not intended to limit the invention to the precise form disclosed, and any such modifications, equivalents, and alternatives falling within the spirit and scope of the invention are intended to be included within the scope of the invention.
Claims (7)
1. A method for manufacturing a dual-channel memory bank, comprising:
s1: the PCB is divided into two parts which are symmetrical up and down based on the middle according to the lamination number of the PCB: the first PCB primary product plate comprises an A-layer PCB inner layer plate, a top layer and a bottom layer of first PCB outer layer plate, and the second PCB primary product plate comprises a B-layer PCB inner layer plate, a top layer and a bottom layer of second PCB outer layer plate;
s2: respectively manufacturing an inner layer circuit of the A-layer PCB inner layer board and an inner layer circuit of the B-layer PCB inner layer board, and respectively performing lamination treatment on the A-layer PCB inner layer board, the top layer, the bottom layer, the first PCB outer layer board, the B-layer PCB inner layer board, the top layer, the bottom layer and the second PCB outer layer board to obtain an outer A-layer PCB board and an outer B-layer PCB board;
s3: drilling holes on the outer A-layer PCB and the outer B-layer PCB respectively, and manufacturing a first outer layer board circuit of a bottom layer of the outer A-layer PCB and a second outer layer board circuit of a top layer of the outer B-layer PCB;
s4: performing secondary lamination on the outer layer A PCB and the outer layer B PCB to obtain a semi-finished board;
s5: drilling holes on the semi-finished product board, manufacturing a top first PCB outer layer board, a bottom second PCB outer layer board outer layer circuit, electroplating, and performing surface treatment to obtain the finished product PCB.
2. The method for manufacturing the dual-channel memory bank according to claim 1, wherein in the step S1, the a-layer PCB inner layer board and the top and bottom two-layer first PCB outer layer boards include an L1 layer, an L2 layer, an L3 layer, an L4 layer, an L5 layer, an L6 layer, an L7 layer, and an L8 layer, which are sequentially arranged from top to bottom; the B-layer PCB inner layer board and the top and bottom two-layer second PCB outer layer board comprise an L9 layer, an L10 layer, an L11 layer, an L12 layer, an L13 layer, an L14 layer, an L15 layer and an L16 layer which are sequentially arranged from top to bottom.
3. The method for manufacturing the dual-channel memory bank according to claim 2, wherein in step S2, the inner layer circuit manufacturing of the a-layer PCB inner layer board specifically comprises sequentially and individually performing inner layer dry film and browning on the L2 layer and the L3 layer, the L4 layer and the L5 layer, the L6 layer and the L7 layer, and adjacent between the L8 layer by PP lamination; and the inner layer circuit of the B-layer PCB inner layer board is manufactured by sequentially and independently carrying out inner layer dry film and browning on an L10 layer, an L11 layer, an L12 layer, an L13 layer, an L14 layer and an L15 layer, and then laminating adjacent layers of an L9 layer, an L10 layer, an L11 layer, an L12 layer, an L13 layer, an L14 layer, an L15 layer and an L16 layer by using PP.
4. The method for manufacturing a dual-channel memory chip as claimed in claim 1, wherein in the step S3, copper deposition is required after the outer layer a PCB and the outer layer B PCB are drilled, and finally plating is performed.
5. The method for manufacturing a dual-channel memory chip as claimed in claim 1, wherein in step S4, PP lamination is adopted between the outer layer a PCB and the outer layer B PCB.
6. The method of claim 1, wherein in step S5, a solder resist green oil is used after the plating and before the surface treatment.
7. The method of claim 1, wherein in step S5, the surface treatment includes tin spraying, gold deposition, OSP, tin deposition and silver deposition.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111136826.7A CN113923898B (en) | 2021-09-27 | 2021-09-27 | Manufacturing method and application of dual-channel memory bank |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111136826.7A CN113923898B (en) | 2021-09-27 | 2021-09-27 | Manufacturing method and application of dual-channel memory bank |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113923898A CN113923898A (en) | 2022-01-11 |
| CN113923898B true CN113923898B (en) | 2024-02-06 |
Family
ID=79236436
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111136826.7A Active CN113923898B (en) | 2021-09-27 | 2021-09-27 | Manufacturing method and application of dual-channel memory bank |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113923898B (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06203102A (en) * | 1992-12-28 | 1994-07-22 | Hitachi Ltd | Designing method for printed wiring board |
| CN103392385A (en) * | 2012-02-13 | 2013-11-13 | Cedal装置有限责任公司 | Improvements in the manufacturing of stacks of multiplayer plastic laminates for printed circuits |
| CN104768332A (en) * | 2014-01-08 | 2015-07-08 | 深圳崇达多层线路板有限公司 | Printed circuit board with long and short metal pins, and manufacture method of printed circuit board |
| WO2017071393A1 (en) * | 2015-10-29 | 2017-05-04 | 广州兴森快捷电路科技有限公司 | Printed circuit board and fabrication method therefor |
| CN107079584A (en) * | 2016-03-14 | 2017-08-18 | 深圳崇达多层线路板有限公司 | The folded hole preparation method of wiring board |
| CN109661128A (en) * | 2018-12-20 | 2019-04-19 | 深圳市通为信电路科技有限公司 | A kind of multi-layer PCB board preparation method and multi-layer PCB board |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7256354B2 (en) * | 2000-06-19 | 2007-08-14 | Wyrzykowska Aneta O | Technique for reducing the number of layers in a multilayer circuit board |
-
2021
- 2021-09-27 CN CN202111136826.7A patent/CN113923898B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06203102A (en) * | 1992-12-28 | 1994-07-22 | Hitachi Ltd | Designing method for printed wiring board |
| CN103392385A (en) * | 2012-02-13 | 2013-11-13 | Cedal装置有限责任公司 | Improvements in the manufacturing of stacks of multiplayer plastic laminates for printed circuits |
| CN104768332A (en) * | 2014-01-08 | 2015-07-08 | 深圳崇达多层线路板有限公司 | Printed circuit board with long and short metal pins, and manufacture method of printed circuit board |
| WO2017071393A1 (en) * | 2015-10-29 | 2017-05-04 | 广州兴森快捷电路科技有限公司 | Printed circuit board and fabrication method therefor |
| CN107079584A (en) * | 2016-03-14 | 2017-08-18 | 深圳崇达多层线路板有限公司 | The folded hole preparation method of wiring board |
| CN109661128A (en) * | 2018-12-20 | 2019-04-19 | 深圳市通为信电路科技有限公司 | A kind of multi-layer PCB board preparation method and multi-layer PCB board |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113923898A (en) | 2022-01-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| DE60031949T2 (en) | Printed circuit board and its manufacture | |
| KR100919797B1 (en) | Semiconductor device package and method of production and semiconductor device of same | |
| US7211289B2 (en) | Method of making multilayered printed circuit board with filled conductive holes | |
| KR100978774B1 (en) | Multilayer printed wiring board | |
| JP5213094B2 (en) | Method and process for embedding conductive vias in a dielectric layer | |
| US20090229862A1 (en) | Multilayer printed wiring board and method of manufacturing the same | |
| JPH04148590A (en) | Multilayer printed circuit board and manufacture thereof | |
| CN101272661B (en) | Method for manufacturing multi-layer wiring substrate and the multi-layer wiring substrate | |
| EP0331909A1 (en) | High performance circuit boards | |
| CN106409688A (en) | Processing method of ultrathin coreless package substrate and structure | |
| US6593534B2 (en) | Printed wiring board structure with z-axis interconnections | |
| US20200305289A1 (en) | Flexible substrate and method for fabricating the same | |
| CN106340461A (en) | Processing method of ultra-thin coreless encapsulation substrate and ultra-thin coreless encapsulation substrate structure | |
| CN113923898B (en) | Manufacturing method and application of dual-channel memory bank | |
| US6388205B1 (en) | Printed circuit board with shielded circuitry | |
| US11903146B2 (en) | Printed wiring board and method for manufacturing printed wiring board | |
| US20090071603A1 (en) | Method of manufacturing printed circuit board and electromagnetic bandgap structure | |
| TWI578873B (en) | Manufacturing method of high-density multilayer board | |
| KR100726239B1 (en) | Manufacturing method of electronic chip embedded type multi layer printed circuit board | |
| CN110366310B (en) | Soft and hard composite board and its making method | |
| KR100699240B1 (en) | Chip embedded PCB and method of the same | |
| US7958626B1 (en) | Embedded passive component network substrate fabrication method | |
| US6492007B1 (en) | Multi-layer printed circuit bare board enabling higher density wiring and a method of manufacturing the same | |
| CN210899825U (en) | Blind buried hole printed circuit board | |
| CN110072326B (en) | Multilayer circuit board and method for manufacturing same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |