CN110072326B - Multilayer circuit board and method for manufacturing same - Google Patents

Multilayer circuit board and method for manufacturing same Download PDF

Info

Publication number
CN110072326B
CN110072326B CN201810056221.9A CN201810056221A CN110072326B CN 110072326 B CN110072326 B CN 110072326B CN 201810056221 A CN201810056221 A CN 201810056221A CN 110072326 B CN110072326 B CN 110072326B
Authority
CN
China
Prior art keywords
layer
circuit substrate
area
protective layer
hollow
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201810056221.9A
Other languages
Chinese (zh)
Other versions
CN110072326A (en
Inventor
刘瑞武
周琼
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Avary Holding Shenzhen Co Ltd
Qing Ding Precision Electronics Huaian Co Ltd
Original Assignee
Avary Holding Shenzhen Co Ltd
Qing Ding Precision Electronics Huaian Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Avary Holding Shenzhen Co Ltd, Qing Ding Precision Electronics Huaian Co Ltd filed Critical Avary Holding Shenzhen Co Ltd
Priority to CN201810056221.9A priority Critical patent/CN110072326B/en
Publication of CN110072326A publication Critical patent/CN110072326A/en
Application granted granted Critical
Publication of CN110072326B publication Critical patent/CN110072326B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0296Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298Multilayer circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/28Applying non-metallic protective coatings
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4673Application methods or materials of intermediate insulating layers not specially adapted to any one of the previous methods of adding a circuit layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

The utility model provides a multilayer circuit board, includes inlayer circuit substrate, is formed respectively in outer circuit substrate and the solder mask of inlayer circuit substrate both sides, at least, form a weld zone on the inlayer circuit substrate, set up on at least one outer circuit substrate and form the fretwork area that exposes the weld zone, multilayer circuit board still includes the protective layer, the protective layer form in inlayer circuit substrate with set up the fretwork area between the outer circuit substrate, protective layer on the weld zone further towards set up the fretwork area outer circuit substrate extends and forms the extension, the extension expose in the fretwork area and the outside periphery of extension with the inboard interval in fretwork area, the solder mask fill in the extension with between the inboard in fretwork area, and the solder mask sets up on the protective layer.

Description

Multilayer circuit board and method for manufacturing same
Technical Field
The present disclosure relates to circuit boards, and particularly to a multilayer circuit board and a method for manufacturing the same.
Background
Generally, a multilayer circuit board is composed of a multilayer wiring substrate. And the circuit substrate of the multilayer circuit board part needs to be subjected to tin treatment.
After most of the prior multilayer circuit boards are manufactured, the areas needing tin melting are exposed by opening the front cover or opening the rear cover, and then tin melting treatment is carried out. However, the areas of the multi-layer circuit board portion requiring tin melting are covered by a covering layer, which includes an inner layer of glue layer, and an outer layer of solder mask, glue layer, or ink layer, etc. In this way, when tin plating is performed on the multilayer circuit board, galvanic corrosion occurs at the edge of the cover layer due to a displacement reaction caused by the tin plating, and a corrosion depth of 7 μm or more is generally generated, and a large difference is generated in the corrosion depth depending on the tin plating thickness. Therefore, the stability of the covering layer on the multilayer circuit board is reduced, and the risk of wire breakage is easy to occur.
Therefore, it is desirable to provide a multilayer circuit board and a method of manufacturing the same, which have a low risk of wire breakage due to tin melting.
Disclosure of Invention
In view of the above, the present invention provides a multilayer circuit board with a stable structure and a method for manufacturing the same.
The utility model provides a multilayer circuit board, includes inlayer circuit substrate, is formed respectively in outer circuit substrate and the solder mask of inlayer circuit substrate both sides, at least, form a weld zone on the inlayer circuit substrate, set up on at least one outer circuit substrate and form the fretwork area that exposes the weld zone, multilayer circuit board still includes the protective layer, the protective layer form in inlayer circuit substrate with set up the fretwork area between the outer circuit substrate, protective layer on the weld zone further towards set up the fretwork area outer circuit substrate extends and forms the extension, the extension expose in the fretwork area and the outside periphery of extension with the inboard interval in fretwork area, the solder mask fill in the extension with between the inboard in fretwork area, and the solder mask sets up on the protective layer.
Further, the outer-layer circuit substrate includes a first outer-layer circuit substrate and a second outer-layer circuit substrate respectively formed on two sides of the inner-layer circuit substrate, the inner-layer circuit substrate includes an insulating layer, a first metal layer and a second metal layer respectively disposed on two side surfaces of the insulating layer, and the welding region includes a first welding region formed on the first metal layer and a second welding region formed on the second metal layer.
Further, the protective layer is made of tin, the protective layer includes a first protective layer formed on the first metal layer and a second protective layer formed on the second metal layer, the first protective layer further includes a first main body portion and a first extension portion connected to the first metal layer, and the second protective layer includes a second main body portion and a second extension portion connected to the second metal layer.
Further, the hollow area including form in first hollow area on the first outer circuit substrate and be formed at second hollow area on the second outer circuit substrate, the solder mask including accept in first solder mask in the first hollow area with accept in the second solder mask in the second hollow area, first solder mask is located the outer peripheral edges of first extension with between the inboard in first hollow area, the second solder mask accept in the outer peripheral edges of second extension with between the inboard in second hollow area.
Further, the top surface of the first extending portion is flush with the top surface of the first solder mask layer, and the top surface of the second extending portion is flush with the top surface of the second solder mask layer.
A manufacturing method of the multilayer circuit board comprises the following steps:
providing an inner layer circuit substrate, and at least forming a welding area on the inner layer circuit substrate;
respectively forming protective layers on two sides of the inner layer circuit substrate;
forming at least one outer-layer circuit substrate on the protective layers on the two sides of the inner-layer circuit substrate respectively, wherein hollow areas corresponding to the welding areas are formed in the outer-layer circuit substrate, and the protective layers are exposed out of the hollow areas;
forming a solder mask layer on the periphery of the protective layer exposed in the hollow area;
and forming a protective layer on the protective layer of the hollow area for the second time.
Further, the outer layer circuit substrate includes a first outer layer circuit substrate and a second outer layer circuit substrate, the inner layer circuit substrate includes an insulating layer and a first metal layer and a second metal layer respectively disposed on two sides of the insulating layer, the bonding pad includes a first bonding pad and a second bonding pad, the first bonding pad is formed on the first metal layer, and the second bonding pad is formed on the second metal layer.
Further, the protective layer is made of tin, the protective layer is deposited on the inner circuit substrate in a chemical reaction mode, the protective layer comprises a first protective layer deposited on the first metal layer and a second protective layer deposited on the second metal layer, the first outer circuit substrate is formed on the first protective layer, and the second outer circuit substrate is formed on the second protective layer.
Further, the hollow-out areas include a first hollow-out area formed on the first outer layer circuit substrate and a second hollow-out area formed on the second outer layer circuit substrate.
Further, the solder mask layer comprises a first solder mask layer formed on the first protective layer in the first hollow area and a second solder mask layer formed on the second protective layer in the second hollow area, and the top surface of the protective layer is flush with the top surfaces of the first solder mask layer and the second solder mask layer.
In the method for manufacturing the multilayer circuit board in the embodiment of the invention, the protective layer is deposited on the inner-layer circuit substrate, and the first outer-layer circuit substrate, the second outer-layer circuit substrate or other covering layers are not formed on the inner-layer circuit substrate, so that the circuit substrate of the multilayer circuit board is prevented from being corroded due to the formation of the protective layer. Further, after the first outer layer circuit substrate and the second outer layer circuit substrate are formed on the inner layer circuit substrate, the protective layer is deposited for the second time on the basis of the first protective layer in the first hollow-out area and the second hollow-out area to form the first extending portion and the second extending portion, so that the phenomenon that the protective layer 20 is directly formed on the solder mask layer of the multilayer circuit board or other circuit substrates to cause larger circuit corrosion is avoided. Therefore, when the protective layer is deposited on the multilayer circuit board, the corrosion to a circuit substrate is greatly reduced, the risk of wire breakage of the multilayer circuit board is reduced, and the strength and the stability of the formed circuit board are improved.
Drawings
Fig. 1 is a sectional view showing a multilayer circuit board according to an embodiment of the present invention.
Fig. 2 to 6 are schematic views illustrating a method of manufacturing the multilayer circuit board according to the embodiment of the present invention.
Description of the main elements
Figure GDA0002448814410000061
Figure GDA0002448814410000071
The following detailed description further illustrates the invention with reference to the above figures.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
The terms "first" and "second" as used herein are defined with respect to the position of the first substrate when in use, and are not limiting.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
As shown in fig. 1, the multilayer circuit board 100 according to the embodiment of the invention includes an inner circuit substrate 10, a passivation layer 20 respectively disposed on two opposite sides of the inner circuit substrate 10, a first outer circuit substrate 30, a second outer circuit substrate 40, and a solder mask layer 50.
The inner circuit substrate 10 includes an insulating layer 11, and a first metal layer 12 and a second metal layer 13 respectively disposed on two opposite side surfaces of the insulating layer 11. in the embodiment of the present invention, the insulating layer 11 is P L, and the first metal layer 12 and the second metal layer 13 are copper, it is understood that, in other embodiments, the insulating layer 11 may be made of other insulating materials, and the first metal layer 12 and the second metal layer 13 may also be made of other conductive materials.
A plurality of first through holes 121 spaced from each other are formed in the first metal layer 12. The first via hole 121 penetrates both side surfaces of the first metal layer 12 to communicate with the insulating layer 11. The first via 121 partially divides the first metal layer 12 into a plurality of first lands 122. A plurality of second through holes 131 are formed in the second metal layer 13 and spaced from each other. The second via hole 131 penetrates through both side surfaces of the second metal layer 13 and communicates with the insulating layer 11. The second via 131 partially divides the second metal layer 13 to form a plurality of second lands 132.
In the embodiment of the present invention, the first through hole 121 and the second through hole 131 are disposed in a staggered manner, and a projection of the first through hole 121 on the insulating layer 11 is spaced from a projection of the second through hole 131 on the insulating layer 11.
In the embodiment of the present invention, the material of the protective layer 20 is tin. The protective layer 20 is deposited on the inner wiring substrate 10 by a chemical reaction. Specifically, the protection layer 20 includes a first protection layer 21 deposited on the first metal layer 12 and a second protection layer 22 deposited on the second metal layer 13.
Further, the first protective layer 21 includes a first main body portion 211 connected to the first metal layer 12, and a first extension portion 212 extending from the first main body portion 211 toward the first outer layer circuit board 30. The first extension 212 corresponds to the first land 122. The second passivation layer 22 includes a second main body portion 221 connected to the second metal layer 13 and a second extension portion 222 extending from the second main body portion 221 toward the second outer-layer wiring board 40. The second extension 222 corresponds to the second land 132.
The first outer layer circuit substrate 30 is disposed on the first protective layer 21. The first outer layer circuit substrate 30 is formed with a first hollow area 31. The first hollow-out regions 31 penetrate through both side surfaces of the first outer layer circuit substrate 30 to divide the first outer layer circuit substrate 30. The first hollow area 31 corresponds to the first land 122. The first extending portion 212 is accommodated in the first hollow-out area 31, and the periphery of the first extending portion 212 is spaced from the inner side of the first hollow-out area 31.
The second outer circuit substrate 40 is disposed on the second passivation layer 22. The second outer circuit substrate 40 is provided with a second hollow area 41. The second hollow-out regions 41 penetrate through the two side surfaces of the first outer layer circuit substrate. The second hollow area 41 corresponds to the second land 132. The second extending portion 222 is accommodated in the second hollow-out area 41, and an outer periphery of the second extending portion 222 is spaced from an inner side of the second hollow-out area 41.
The solder mask layer 50 includes a first solder mask layer 51 received in the first hollow area 31 and a second solder mask layer 52 received in the second hollow area 41. Specifically, the first solder mask layer 51 is accommodated between the inner side of the first hollow area 31 and the outer periphery of the first extending portion 212 of the first passivation 21. The top surface of the first solder mask layer 51 is flush with the top surface of the first extension 212. The second solder mask layer 52 is contained between the inner side of the second hollow area 41 and the outer periphery of the second extending portion 222. The top surface of the second solder mask layer 52 is flush with the top surface of the second extension 222.
As shown in fig. 2 to 5, the present invention further provides a method for manufacturing the multilayer circuit board 100, comprising the steps of:
the method comprises the following steps: as shown in fig. 2, an inner-layer wiring substrate 10 is provided, and a first land 122 and a second land 132 are formed on the inner-layer wiring substrate 10.
The inner circuit substrate 10 includes an insulating layer 11, and a first metal layer 12 and a second metal layer 13 respectively disposed on two sides of the insulating layer 11. A plurality of first vias 121 spaced apart from each other are opened in the first metal layer 12, and the first vias partially divide the first metal layer 12 into the first lands 122. The second metal layer 13 is opened with a plurality of spaced second through holes 131, and the second through holes partially divide the second metal layer 13 into a plurality of second lands 132.
Step two: as shown in fig. 3, protective layers 20 are formed on both sides of the inner layer circuit board 10.
In the embodiment of the present invention, the material of the protective layer 20 is tin. The protective layer 20 is deposited on the inner circuit substrate 10 by a chemical reaction. The protective layers include a first protective layer 21 deposited on the first metal layer 12 and a second protective layer 22 deposited on the second metal layer 13.
Step three: as shown in fig. 4, a first outer layer circuit substrate 30 and a second outer layer circuit substrate 40 are respectively formed on the protective layer 20 on both sides of the inner layer circuit substrate 10, a first hollow area 31 corresponding to the first land 122 is formed on the first outer layer circuit substrate 30, a second hollow area 41 corresponding to the second land 132 is formed on the second outer layer circuit substrate 40, and the protective layer 20 formed on the first land 122 and the second land 132 is exposed in the first hollow area 31 and the second hollow area 41, respectively.
The first outer layer circuit substrate 30 is formed on the first protective layer 21. The second outer-layer wiring substrate 40 is formed on the second protective layer 22. The first hollow-out areas 31 penetrate through the two side surfaces of the first outer layer circuit substrate 30. The lateral width of the first hollow area 31 is greater than the lateral width of the first welding area 122. The second hollow-out region 41 penetrates through both side surfaces of the second outer-layer circuit substrate 40. The lateral width of the second hollow area 41 is greater than the lateral width of the second welding area 132.
Step three: as shown in fig. 5, a solder mask layer 50 is formed on the periphery of the exposed passivation layer 20 in the first and second hollow areas 31 and 41.
The solder mask 50 includes a first solder mask 51 formed on the first passivation layer 21 in the first hollow area 31 and a second solder mask 52 formed on the second passivation layer 22 in the second hollow area 41. The first through hole 121 and the first land 122 are exposed in the first hollow area 31 through the first solder mask layer 51. The second through hole 131 and the second land 132 are exposed in the second hollow area 41 through the second solder mask 52.
Step four: as shown in fig. 1, the protection layer 20 is deposited for the second time on the protection layer 20 exposed in the first and second hollow-out areas 31 and 41, and the manufacturing of the multilayer circuit board 100 is completed.
The top surface of the passivation layer 20 deposited for the second time is flush with the top surface of the solder mask layer 50. The first protective layer 21 includes a first main body portion 211 disposed on the first metal layer 12, and a first extending portion 212 extending from the first main body portion 211 toward the first outer layer circuit board 30. The second passivation layer 22 includes a second main body portion 221 and a second extending portion 222 extending from the second main body portion 221 toward the second outer circuit board 40.
In the method for manufacturing the multilayer circuit board 100 according to the embodiment of the invention, the protective layer 20 is deposited on the inner circuit substrate 10, and the first outer circuit substrate 30, the second outer circuit substrate 40 or other covering layers are not formed on the inner circuit substrate 10, so that corrosion of the circuit substrate of the multilayer circuit board 100 caused by the formation of the protective layer 20 is avoided. Further, after the first outer circuit substrate 30 and the second outer circuit substrate 40 are formed on the inner circuit substrate 10, the passivation layer 20 is deposited for the second time on the basis of the first passivation layer 21 in the first hollow-out area 31 and the second hollow-out area 41 to form the first extending portion 212 and the second extending portion 222, so as to avoid the formation of the passivation layer 20 on the solder mask 50 or other circuit substrates of the multi-layer circuit board 100 directly to cause the larger circuit corrosion. Thus, the multilayer circuit board 100 of the present invention greatly reduces corrosion to the circuit substrate when the protective layer 20 is deposited, reduces the risk of wire breakage of the multilayer circuit board 100, and improves the strength and stability of forming the multilayer circuit board 100.
It is understood that various other changes and modifications may be made by those skilled in the art based on the technical idea of the present invention, and all such changes and modifications should fall within the protective scope of the claims of the present invention.

Claims (10)

1. The utility model provides a multilayer circuit board, includes inlayer circuit substrate, is formed at respectively outer circuit substrate and the solder mask of inlayer circuit substrate both sides, at least, form a weld zone on the inlayer circuit substrate, set up on at least one outer circuit substrate and form and expose the hollow area of weld zone, its characterized in that: the multilayer circuit board further comprises a protective layer, the protective layer is formed between the inner layer circuit substrate and the outer layer circuit substrate provided with the hollowed-out area, the protective layer on the welding area further extends towards the outer layer circuit substrate provided with the hollowed-out area to form an extending portion, the extending portion is exposed in the hollowed-out area, the periphery of the outer side of the extending portion is spaced from the inner side of the hollowed-out area, the anti-welding layer is filled between the extending portion and the inner side of the hollowed-out area, and the anti-welding layer is arranged on the protective layer.
2. The multilayer circuit board of claim 1, wherein: the outer-layer circuit substrate comprises a first outer-layer circuit substrate and a second outer-layer circuit substrate which are respectively formed on two sides of the inner-layer circuit substrate, the inner-layer circuit substrate comprises an insulating layer, a first metal layer and a second metal layer, the first metal layer and the second metal layer are respectively arranged on the surfaces of the two sides of the insulating layer, and the welding area comprises a first welding area formed on the first metal layer and a second welding area formed on the second metal layer.
3. The multilayer circuit board of claim 2, wherein: the protective layer is made of tin, the protective layer comprises a first protective layer formed on the first metal layer and a second protective layer formed on the second metal layer, the first protective layer further comprises a first main body part and a first extension part which are connected with the first metal layer, and the second protective layer comprises a second main body part and a second extension part which are connected with the second metal layer.
4. The multilayer circuit board of claim 3, wherein: the hollow area including form in first hollow area on the first outer circuit substrate and be formed at second hollow area on the second outer circuit substrate, the solder mask including accept in first solder mask in the first hollow area with accept in second solder mask in the second hollow area, first solder mask is located the outer peripheral edges of first extension with between the inboard of first hollow area, the second solder mask accept in the outer peripheral edges of second extension with between the inboard of second hollow area.
5. The multilayer circuit board of claim 4, wherein: the top surface of the first extending portion is flush with the top surface of the first solder mask layer, and the top surface of the second extending portion is flush with the top surface of the second solder mask layer.
6. A method of manufacturing a multilayer circuit board according to any one of claims 1 to 5, comprising the steps of:
providing an inner layer circuit substrate, and at least forming a welding area on the inner layer circuit substrate;
respectively forming protective layers on two sides of the inner layer circuit substrate;
forming at least one outer-layer circuit substrate on the protective layers on the two sides of the inner-layer circuit substrate respectively, wherein hollow areas corresponding to the welding areas are formed in the outer-layer circuit substrate, and the protective layers are exposed out of the hollow areas;
forming a solder mask layer on the periphery of the protective layer exposed in the hollow area;
and forming a protective layer on the protective layer of the hollow area for the second time.
7. The method for manufacturing a multilayer circuit board according to claim 6, wherein: the outer-layer circuit substrate comprises a first outer-layer circuit substrate and a second outer-layer circuit substrate, the inner-layer circuit substrate comprises an insulating layer, a first metal layer and a second metal layer, the first metal layer and the second metal layer are arranged on two sides of the insulating layer respectively, the welding area comprises a first welding area and a second welding area, the first welding area is formed on the first metal layer, and the second welding area is formed on the second metal layer.
8. The method for manufacturing a multilayer circuit board according to claim 7, wherein: the protective layer is made of tin, the protective layer is deposited on the inner layer circuit substrate in a chemical reaction mode and comprises a first protective layer deposited on the first metal layer and a second protective layer deposited on the second metal layer, the first outer layer circuit substrate is formed on the first protective layer, and the second outer layer circuit substrate is formed on the second protective layer.
9. The method for manufacturing a multilayer circuit board according to claim 8, wherein: the hollow-out areas comprise a first hollow-out area formed on the first outer layer circuit substrate and a second hollow-out area formed on the second outer layer circuit substrate.
10. The method for manufacturing a multilayer circuit board according to claim 9, wherein: the anti-welding layer comprises a first anti-welding layer formed on a first protective layer in the first hollow area and a second anti-welding layer formed on a second protective layer in the second hollow area, and the top surface of the protective layer is flush with the top surface of the first anti-welding layer and the top surface of the second anti-welding layer.
CN201810056221.9A 2018-01-20 2018-01-20 Multilayer circuit board and method for manufacturing same Active CN110072326B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201810056221.9A CN110072326B (en) 2018-01-20 2018-01-20 Multilayer circuit board and method for manufacturing same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201810056221.9A CN110072326B (en) 2018-01-20 2018-01-20 Multilayer circuit board and method for manufacturing same

Publications (2)

Publication Number Publication Date
CN110072326A CN110072326A (en) 2019-07-30
CN110072326B true CN110072326B (en) 2020-07-24

Family

ID=67364888

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201810056221.9A Active CN110072326B (en) 2018-01-20 2018-01-20 Multilayer circuit board and method for manufacturing same

Country Status (1)

Country Link
CN (1) CN110072326B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111818735A (en) * 2020-06-11 2020-10-23 珠海斗门超毅实业有限公司 Cavity plate resistance welding manufacturing method and circuit board

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104684240A (en) * 2013-11-27 2015-06-03 富葵精密组件(深圳)有限公司 Circuit board and circuit board manufacturing method
CN106231790A (en) * 2016-07-27 2016-12-14 上海摩软通讯技术有限公司 A kind of printed circuit board and manufacture method and mobile terminal
JP2017120879A (en) * 2015-11-20 2017-07-06 住友ベークライト株式会社 Protection element, manufacturing method of protection element, mounting substrate, and electronic device

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7427717B2 (en) * 2004-05-19 2008-09-23 Matsushita Electric Industrial Co., Ltd. Flexible printed wiring board and manufacturing method thereof
JP2017050313A (en) * 2015-08-31 2017-03-09 イビデン株式会社 Printed wiring board and manufacturing method for printed wiring board

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104684240A (en) * 2013-11-27 2015-06-03 富葵精密组件(深圳)有限公司 Circuit board and circuit board manufacturing method
JP2017120879A (en) * 2015-11-20 2017-07-06 住友ベークライト株式会社 Protection element, manufacturing method of protection element, mounting substrate, and electronic device
CN106231790A (en) * 2016-07-27 2016-12-14 上海摩软通讯技术有限公司 A kind of printed circuit board and manufacture method and mobile terminal

Also Published As

Publication number Publication date
CN110072326A (en) 2019-07-30

Similar Documents

Publication Publication Date Title
US7211289B2 (en) Method of making multilayered printed circuit board with filled conductive holes
US7528069B2 (en) Fine pitch interconnect and method of making
CN110972414B (en) Composite circuit board and method for manufacturing the same
US20040219342A1 (en) Electronic substrate with direct inner layer component interconnection
US6585903B1 (en) Electrical circuit board and a method for making the same
CN110072326B (en) Multilayer circuit board and method for manufacturing same
CN101567356B (en) Circuit board structure and manufacture method thereof
KR920005072B1 (en) Manufacture of double sided wiring substrate
US6501031B1 (en) Electrical circuit board and a method for making the same
CN110278659B (en) Composite circuit board and method for manufacturing the same
US8004851B2 (en) Multi-layer flexible printed circuit board and manufacturing method thereof
TWI710291B (en) Connecting structure and method for connecting stacked circuits boards using the same
CN111199948A (en) Package substrate and method for manufacturing the same
TWI383724B (en) Printed circuit board and manufacturing method thereof
JP4760393B2 (en) Printed wiring board and semiconductor device
CN113630977B (en) Thick copper circuit board and manufacturing method thereof
CN101370356B (en) Circuit board and its manufacturing method
JP4457739B2 (en) Electronic component and manufacturing method thereof
US20240032193A1 (en) Electronic component
US6518672B2 (en) Multi-layer wiring board substrate and semiconductor device using the multi-layer wiring substrate
JP4330713B2 (en) Via-on-via structure of wiring board and manufacturing method thereof
JP4330712B2 (en) Via-on-via structure of wiring board
US6612025B1 (en) Method for creating a connection within a multilayer circuit board assembly
US6412168B1 (en) Method of making an electrical circuit board
CN116491227A (en) Wiring circuit board

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant