CN114217390A - Optical switch designing method, optical switch, electronic device, and storage medium - Google Patents
Optical switch designing method, optical switch, electronic device, and storage medium Download PDFInfo
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- CN114217390A CN114217390A CN202111600900.6A CN202111600900A CN114217390A CN 114217390 A CN114217390 A CN 114217390A CN 202111600900 A CN202111600900 A CN 202111600900A CN 114217390 A CN114217390 A CN 114217390A
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- 238000000034 method Methods 0.000 title claims abstract description 45
- 238000013461 design Methods 0.000 claims abstract description 12
- 230000011218 segmentation Effects 0.000 claims abstract description 9
- 238000012545 processing Methods 0.000 claims abstract description 7
- 238000005192 partition Methods 0.000 claims description 16
- 238000000638 solvent extraction Methods 0.000 claims description 9
- 238000004590 computer program Methods 0.000 claims description 5
- 230000005855 radiation Effects 0.000 abstract description 2
- 238000012360 testing method Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 113
- 238000004891 communication Methods 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 239000002344 surface layer Substances 0.000 description 4
- 238000005520 cutting process Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 230000018109 developmental process Effects 0.000 description 2
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- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/24—Coupling light guides
- G02B6/42—Coupling light guides with opto-electronic elements
- G02B6/4201—Packages, e.g. shape, construction, internal or external details
- G02B6/4274—Electrical aspects
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- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/24—Coupling light guides
- G02B6/42—Coupling light guides with opto-electronic elements
- G02B6/4201—Packages, e.g. shape, construction, internal or external details
- G02B6/4274—Electrical aspects
- G02B6/428—Electrical aspects containing printed circuit boards [PCB]
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
- H05K3/0052—Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
Abstract
The application provides a design method of an optical switch, which comprises the steps of carrying out segmentation processing on a PCB based on an optical interface module and a high-speed signal wire; determining a shell lapping scheme corresponding to the optical port modules based on the distribution condition of the optical port modules on the PCB; the PCB board at least comprises a top layer, a bottom layer, a GND layer and an internal electric layer, and the optical port module comprises a plurality of optical ports. The method and the device ensure that the internal signal cannot cross the area divided by GND, and avoid the problem that the radiation test is poor due to the fact that the internal signal noise of the mainboard is possibly conducted to the optical port; meanwhile, even if external noise is transmitted to the optical port, the external noise can be directly transmitted to the shell through the GND at the outermost layer, so that the noise cannot interfere with an internal circuit; under the premise that the shielding effectiveness is not reduced, the PCB is utilized to the maximum extent, and the cost is reduced.
Description
Technical Field
The present invention relates to the field of integrated circuit technologies, and in particular, to an optical switch design method, an optical switch, an electronic device, and a storage medium.
Background
Along with the development of scientific technology, the performance requirement on the switch is higher and higher, in order to meet the requirement, the working speed of the switch is higher and higher, and in the case that the switch is developed to the present, the speed of the prior 1G electrical port is developed to the speed of the prior 10G optical port, 25G optical port or even 100G optical port, and along with the realization of the requirement of the switch on electromagnetic compatibility is more and more difficult, and because the interfaces of the switch are more and more dense, the design requirement on the switch is higher and more, the electromagnetic compatibility requirement of the prior design can not be well met.
In the prior art, a PCB (printed circuit board) below a port of some switches is not divided, and a corresponding GND (ground potential) layer is also not divided, so that internal noise of the switches can be radiated to the outside through the port of the port, and meanwhile, external interference can also be interfered to the GND layer of a mainboard through the GND layer of the port, so that the anti-interference capability of the switches is reduced; some switches also cut the whole PCB, which results in some signals having to cross the cutting area, and affects the transmission of the signals.
Therefore, an optical switch design method capable of improving the anti-interference capability of the switch is needed to solve the above technical problems in the prior art.
Disclosure of Invention
In order to solve the above-mentioned problems, it is a primary object of the present invention to provide an optical switch design method, an optical switch, an electronic device and a storage medium, so as to solve the above-mentioned problems.
In order to achieve the above object, a first aspect of the present invention provides an optical switch design method, including:
based on the optical interface module and the high-speed signal line, the PCB is divided;
determining a shell lapping scheme corresponding to the optical port modules based on the distribution condition of the optical port modules on the PCB;
the PCB board at least comprises a top layer, a bottom layer, a GND layer and an internal electric layer, and the optical port module comprises a plurality of optical ports.
In some embodiments, the dividing process for the PCB board based on the optical interface module and the high-speed signal line includes:
taking the projection limit of the light port on the PCB as a partition limit;
if the segmentation boundary and the high-speed signal line do not have an overlapping area, segmenting the PCB according to the segmentation boundary;
and if the division boundary and the high-speed signal line have an overlapping area, the PCB is not divided according to the division boundary.
In some embodiments, if there is no overlapping area between the dividing boundary and the high-speed signal line, dividing the PCB according to the dividing boundary includes:
dividing the top layer by taking the projection limit of the light port on the top layer as a first division limit; and/or
And dividing the bottom layer by taking the projection limit of the light port on the bottom layer as a second division limit.
In some embodiments, the method further comprises:
partitioning a first GND layer adjacent to the top layer according to the first partition boundary; and/or
And partitioning a second GND layer adjacent to the bottom layer according to the second partition limit.
In some embodiments, the method further comprises:
carrying out paving treatment on a first internal electrical layer adjacent to the first GND layer, and dividing the first internal electrical layer after the paving treatment according to the first division limit; and/or
And carrying out paving treatment on a second internal electric layer adjacent to the second GND layer, and dividing the second internal electric layer after the paving treatment according to the second division limit.
In some embodiments, the determining a housing overlapping scheme corresponding to the optical port modules based on the distribution of the optical port modules on the PCB includes:
if the PCB only has the optical port module on the top layer, overlapping the shell on the area where the optical port module does not contact the top layer;
if the PCB only has the optical port module on the bottom layer, overlapping the shell on the area where the optical port module does not contact the bottom layer;
and if the top layer and the bottom layer in the PCB are both provided with the optical port modules, overlapping the shell in the area where the optical port modules do not contact the PCB.
In some embodiments, the method comprises:
the high-speed signal line is used for transmitting a data signal and a clock signal related to the optical interface module;
the housing is grounded.
In a second aspect, the present application provides an optical switch, which performs a splitting process on a PCB based on an optical interface module and a high-speed signal line;
the optical switch determines a shell lapping scheme corresponding to the optical port module based on the distribution condition of the optical port module on the PCB;
the PCB at least comprises a top layer, a bottom layer, a GND layer and an internal electric layer.
In a third aspect, the present application provides an electronic device, comprising:
one or more processors;
and memory associated with the one or more processors for storing program instructions that, when read and executed by the one or more processors, perform implementing the method of any of claims 1-7.
In a fourth aspect, the present application provides a computer-readable storage medium having stored thereon a computer program for implementing the method of any one of claims 1-7 when executed by a processor.
The beneficial effect that this application realized does:
the application provides a design method of an optical switch, which comprises the steps of carrying out segmentation processing on a PCB based on an optical interface module and a high-speed signal wire; determining a shell lapping scheme corresponding to the optical port modules based on the distribution condition of the optical port modules on the PCB; the PCB board at least comprises a top layer, a bottom layer, a GND layer and an internal electric layer, and the optical port module comprises a plurality of optical ports. According to the method, the PCB is only divided in the area without high-speed signal wiring, and then the upper surface layer, the lower surface layer, the GND layer adjacent to the upper surface layer and the lower surface layer of the PCB and the inner layer adjacent to the GND layer are only divided, so that the area divided by the GND is not crossed by internal signals, and the problem that radiation testing is poor due to the fact that internal signal noise of a main board is possibly transmitted to an optical port is solved; meanwhile, the optical port module is lapped on the shell and grounded, so that even if external noise is transmitted to the optical port, the external noise can be directly transmitted to the shell through the GND on the outermost layer, and the noise cannot interfere with an internal circuit; under the premise that the shielding effectiveness is not reduced, the PCB is utilized to the maximum extent, and the cost is reduced.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without inventive efforts, wherein:
FIG. 1 is a schematic diagram of a PCB cutting process provided by an embodiment of the present application;
FIG. 2 is a flow chart of a method provided by an embodiment of the present application;
FIG. 3 is a block diagram of an electronic device provided in an embodiment of the present application;
Detailed Description
In order to make the purpose, technical solutions and advantages of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The english abbreviations referred to in this application are:
PCB (Printed circuit board);
GND (Ground).
Example one
The embodiment provides an optical switch design method, comprising the following steps:
s100, determining a partition boundary according to a projection boundary of an optical port in the optical port module on the PCB.
The optical port module is provided with a plurality of optical ports, generally, a PCB (printed circuit board) layer of the switch is more than 10 layers, when N is 10, the optical ports are distributed on an upper layer and a lower layer (namely a top layer and a bottom layer) of the PCB, and the PCB at least comprises a top layer, a bottom layer, a GND (ground) layer and an inner electric layer.
And S200, carrying out division processing on the PCB according to the division boundary and the high-speed signal wire.
Because the switch integrates the optical ports of a large number of optical port modules, the wiring of the connector part on the PCB is dense, and in order to enable the high-speed wiring of the connector part to be capable of completely referring to GND, when the GND is considered to be divided, only the lower part of the optical port without the high-speed signal wiring part is considered, and the GND is not divided at the place where the high-speed signal wiring exists. The high speed signal line is used for transmitting data signals and clock signals related to the optical interface module.
Therefore, if there is an overlapping region between the projection limit (i.e., the division limit) of the optical port on the PCB and the high-speed signal line, the PCB is not divided into the division limits corresponding to the optical port, that is, the division of the optical port region corresponding to the division limit is abandoned. Only when the high-speed signal line and the division boundary have no overlapping region, the PCB is divided according to the division boundary, specifically, referring to fig. 1, a dotted line in the drawing is a division line, and the method for dividing the PCB includes:
s210, when the light port is on the top layer of the PCB, the projection limit of the light port on the top layer of the PCB is a partition limit. Dividing the top layer of the PCB according to a dividing boundary; meanwhile, the GND layer adjacent to the top layer is divided by the division boundary, the internal electric layer adjacent to the GND layer is subjected to the floor-covering process, and the internal electric layer subjected to the floor-covering process is similarly divided by the division boundary.
It should be noted that the projection of the optical port on the top layer of the PCB does not project on the bottom layer of the PCB.
S220, when the light port is arranged at the bottom layer of the PCB, the projection limit of the light port at the bottom layer of the PCB is a partition limit. Dividing the bottom layer of the PCB according to a dividing boundary; at the same time, the GND layer adjacent to the bottom layer is divided by the division boundary, the internal electrical layer adjacent to the GND layer is subjected to the floor-covering treatment, and the internal electrical layer subjected to the floor-covering treatment is similarly divided by the division boundary.
It should be noted that the projection of the optical port on the bottom layer of the PCB does not project on the top layer of the PCB.
S300, determining a shell lapping scheme corresponding to the optical port modules according to the distribution condition of the optical port modules on the PCB.
Specifically, after the PCB is cut, the optical module needs to be lapped on the housing to improve the shielding effect on the interference signal. When only the top layer of the PCB is provided with the optical port module, the shell is lapped in other areas except the place below the optical port module, which is in contact with the top layer of the PCB, and the shell is lapped in other areas; when only the bottom layer of the PCB is provided with the optical port module, the shell is lapped in other areas except the part, contacting with the bottom layer of the PCB, below the optical port module; when only the top layer and the bottom layer of the PCB are provided with the optical port modules, the shell is lapped in other areas except the place where the lower part of the optical port module is contacted with the PCB, so that the lapping of approximate 360 degrees is realized.
Wherein, the overlap joint shell can realize meeting with the adjacent GND layer of PCB board top layer or bottom, has the ground connection function, and above-mentioned overlap joint shell can be to light mouthful module overlap joint metal casing, can also increase the cotton messenger light mouthful module of electrically conductive bubble and shell overlap joint.
According to the optical switch design method disclosed by the embodiment of the application, the integrity of the shielding effect can be achieved only by locally dividing the PCB, the PCB can be utilized to the maximum extent, and the material development cost is reduced on the premise of improving the electromagnetic compatibility.
Example two
Corresponding to the above embodiments, the present application provides a method for designing an optical switch, as shown in fig. 2, the method includes:
2100. based on the optical interface module and the high-speed signal line, the PCB is divided;
preferably, the dividing process performed on the PCB based on the optical interface module and the high-speed signal line includes:
2110. taking the projection limit of the light port on the PCB as a partition limit;
2120. if the segmentation boundary and the high-speed signal line do not have an overlapping area, segmenting the PCB according to the segmentation boundary; preferably, if there is no overlapping area between the dividing boundary and the high-speed signal line, dividing the PCB according to the dividing boundary, including:
2121. dividing the top layer by taking the projection limit of the light port on the top layer as a first division limit; and/or
2122. And dividing the bottom layer by taking the projection limit of the light port on the bottom layer as a second division limit.
Preferably, the method further comprises:
2123. partitioning a first GND layer adjacent to the top layer according to the first partition boundary; and/or
2124. And partitioning a second GND layer adjacent to the bottom layer according to the second partition limit.
Preferably, the method further comprises:
2125. carrying out paving treatment on a first internal electrical layer adjacent to the first GND layer, and dividing the first internal electrical layer after the paving treatment according to the first division limit; and/or
2126. And carrying out paving treatment on a second internal electric layer adjacent to the second GND layer, and dividing the second internal electric layer after the paving treatment according to the second division limit.
2130. And if the division boundary and the high-speed signal line have an overlapping area, the PCB is not divided according to the division boundary.
Preferably, the method further comprises:
partitioning a first GND layer adjacent to the top layer according to the first partition boundary; and/or
And partitioning a second GND layer adjacent to the bottom layer according to the second partition limit.
2200. Determining a shell lapping scheme corresponding to the optical port modules based on the distribution condition of the optical port modules on the PCB;
preferably, the determining a housing overlapping scheme corresponding to the optical port module based on the distribution of the optical port module on the PCB includes:
2210. if the PCB only has the optical port module on the top layer, overlapping the shell on the area where the optical port module does not contact the top layer;
2220. if the PCB only has the optical port module on the bottom layer, overlapping the shell on the area where the optical port module does not contact the bottom layer;
2230. and if the top layer and the bottom layer in the PCB are both provided with the optical port modules, overlapping the shell in the area where the optical port modules do not contact the PCB.
Preferably, the method comprises:
2240. the high-speed signal line is used for transmitting a data signal and a clock signal related to the optical interface module;
2250. the housing is grounded.
The PCB board at least comprises a top layer, a bottom layer, a GND layer and an internal electric layer, and the optical port module comprises a plurality of optical ports.
EXAMPLE III
Corresponding to all the above embodiments, an embodiment of the present application provides an electronic device, including:
one or more processors; and memory associated with the one or more processors for storing program instructions that, when read and executed by the one or more processors, perform operations comprising:
based on the optical interface module and the high-speed signal line, the PCB is divided;
determining a shell lapping scheme corresponding to the optical port modules based on the distribution condition of the optical port modules on the PCB;
the PCB board at least comprises a top layer, a bottom layer, a GND layer and an internal electric layer, and the optical port module comprises a plurality of optical ports.
Fig. 3 schematically shows an architecture of an electronic device, which may specifically include a processor 310, a video display adapter 311, a disk drive 312, an input/output interface 313, a network interface 314, and a memory 320. The processor 310, the video display adapter 311, the disk drive 312, the input/output interface 313, the network interface 314, and the memory 320 may be communicatively connected by a bus 330.
The processor 310 may be implemented by a general-purpose CPU (Central Processing Unit), a microprocessor, an Application Specific Integrated Circuit (ASIC), or one or more Integrated circuits, and is configured to execute related programs to implement the technical solution provided in the present Application.
The Memory 320 may be implemented in the form of a ROM (Read Only Memory), a RAM (Random Access Memory), a static storage device, a dynamic storage device, or the like. The memory 320 may store an operating system 321 for controlling the operation of the electronic device 300, and a Basic Input Output System (BIOS)322 for controlling low-level operations of the electronic device 300. In addition, a web browser 323, a data storage management system 324, an icon font processing system 325, and the like may also be stored. The icon font processing system 325 may be an application program that implements the operations of the foregoing steps in this embodiment of the application. In summary, when the technical solution provided by the present application is implemented by software or firmware, the relevant program code is stored in the memory 320 and called to be executed by the processor 310.
The input/output interface 313 is used for connecting an input/output module to realize information input and output. The i/o module may be configured as a component in a device (not shown) or may be external to the device to provide a corresponding function. The input devices may include a keyboard, a mouse, a touch screen, a microphone, various sensors, etc., and the output devices may include a display, a speaker, a vibrator, an indicator light, etc.
The network interface 314 is used for connecting a communication module (not shown in the figure) to realize communication interaction between the device and other devices. The communication module can realize communication in a wired mode (such as USB, network cable and the like) and also can realize communication in a wireless mode (such as mobile network, WIFI, Bluetooth and the like).
Bus 330 includes a path that transfers information between various components of the device, such as processor 310, video display adapter 311, disk drive 312, input/output interface 313, network interface 314, and memory 320.
In addition, the electronic device 300 may also obtain information of specific pickup conditions from a virtual resource object pickup condition information database for performing condition judgment, and the like.
It should be noted that although the above devices only show the processor 310, the video display adapter 311, the disk drive 312, the input/output interface 313, the network interface 314, the memory 320, the bus 330, etc., in a specific implementation, the devices may also include other components necessary for normal operation. Furthermore, it will be understood by those skilled in the art that the apparatus described above may also include only the components necessary to implement the solution of the present application, and not necessarily all of the components shown in the figures.
In all of the above embodiments, the present application further provides a computer-readable storage medium, in which a computer program is stored, and the computer program is used for the following operations when executed by a processor:
based on the optical interface module and the high-speed signal line, the PCB is divided;
determining a shell lapping scheme corresponding to the optical port modules based on the distribution condition of the optical port modules on the PCB;
the PCB board at least comprises a top layer, a bottom layer, a GND layer and an internal electric layer, and the optical port module comprises a plurality of optical ports.
Specifically, when being read and executed by the processor, the computer may further perform each step or operation in the method shown in the first embodiment or the second embodiment, and for simplicity and convenience of description, details are not described here.
From the above description of the embodiments, it is clear to those skilled in the art that the present application can be implemented by software plus necessary general hardware platform. Based on such understanding, the technical solutions of the present application may be embodied in the form of a software product, which may be stored in a storage medium, such as a ROM/RAM, a magnetic disk, an optical disk, or the like, and includes several instructions for enabling a computer device (which may be a personal computer, a cloud server, or a network device) to execute the method according to the embodiments or some parts of the embodiments of the present application.
The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, the system or system embodiments are substantially similar to the method embodiments and therefore are described in a relatively simple manner, and reference may be made to some of the descriptions of the method embodiments for related points. The above-described system and system embodiments are only illustrative, wherein the units described as separate parts may or may not be physically separate, and the parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.
The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the protection scope of the present application.
Claims (10)
1. A method for designing an optical switch, the method comprising:
based on the optical interface module and the high-speed signal line, the PCB is divided;
determining a shell lapping scheme corresponding to the optical port modules based on the distribution condition of the optical port modules on the PCB;
the PCB board at least comprises a top layer, a bottom layer, a GND layer and an internal electric layer, and the optical port module comprises a plurality of optical ports.
2. The method of claim 1, wherein the dividing the PCB board based on the optical interface module and the high-speed signal line comprises:
taking the projection limit of the light port on the PCB as a partition limit;
if the segmentation boundary and the high-speed signal line do not have an overlapping area, segmenting the PCB according to the segmentation boundary;
and if the division boundary and the high-speed signal line have an overlapping area, the PCB is not divided according to the division boundary.
3. The method of claim 2, wherein if there is no overlapping area between the partition boundary and the high-speed signal line, the partitioning the PCB according to the partition boundary comprises:
dividing the top layer by taking the projection limit of the light port on the top layer as a first division limit; and/or
And dividing the bottom layer by taking the projection limit of the light port on the bottom layer as a second division limit.
4. The method of claim 3, further comprising:
partitioning a first GND layer adjacent to the top layer according to the first partition boundary; and/or
And partitioning a second GND layer adjacent to the bottom layer according to the second partition limit.
5. The method of claim 4, further comprising:
carrying out paving treatment on a first internal electrical layer adjacent to the first GND layer, and dividing the first internal electrical layer after the paving treatment according to the first division limit; and/or
And carrying out paving treatment on a second internal electric layer adjacent to the second GND layer, and dividing the second internal electric layer after the paving treatment according to the second division limit.
6. The method according to any one of claims 1 to 5, wherein the determining the housing overlapping scheme corresponding to the optical port module based on the distribution of the optical port module on the PCB comprises:
if the PCB only has the optical port module on the top layer, overlapping the shell on the area where the optical port module does not contact the top layer;
if the PCB only has the optical port module on the bottom layer, overlapping the shell on the area where the optical port module does not contact the bottom layer;
and if the top layer and the bottom layer in the PCB are both provided with the optical port modules, overlapping the shell in the area where the optical port modules do not contact the PCB.
7. The method according to any one of claims 1 to 5, characterized in that the method comprises:
the high-speed signal line is used for transmitting a data signal and a clock signal related to the optical interface module;
the housing is grounded.
8. An optical switch, characterized in that,
the optical switch is used for carrying out segmentation processing on the PCB based on the optical port module and the high-speed signal wire;
the optical switch determines a shell lapping scheme corresponding to the optical port module based on the distribution condition of the optical port module on the PCB;
the PCB at least comprises a top layer, a bottom layer, a GND layer and an internal electric layer.
9. An electronic device, the electronic device comprising:
one or more processors;
and a memory associated with the one or more processors for storing program instructions that, when read and executed by the one or more processors, perform the optical switch design method of any of claims 1-7.
10. A computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the optical switch design method of any of claims 1-7.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
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| CN202111600900.6A CN114217390B (en) | 2021-12-24 | 2021-12-24 | Optical switch design method, optical switch, electronic device, and storage medium |
| PCT/CN2022/102616 WO2023115887A1 (en) | 2021-12-24 | 2022-06-30 | Optical switch design method, optical switch, electronic device, and storage medium |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111600900.6A CN114217390B (en) | 2021-12-24 | 2021-12-24 | Optical switch design method, optical switch, electronic device, and storage medium |
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| CN114217390A true CN114217390A (en) | 2022-03-22 |
| CN114217390B CN114217390B (en) | 2024-02-23 |
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|---|---|---|---|---|
| WO2023115887A1 (en) * | 2021-12-24 | 2023-06-29 | 苏州浪潮智能科技有限公司 | Optical switch design method, optical switch, electronic device, and storage medium |
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| WO2023115887A1 (en) * | 2021-12-24 | 2023-06-29 | 苏州浪潮智能科技有限公司 | Optical switch design method, optical switch, electronic device, and storage medium |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114217390B (en) | 2024-02-23 |
| WO2023115887A1 (en) | 2023-06-29 |
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