CN110333843B - Method and device for realizing high-precision timer of virtual machine and electronic equipment - Google Patents
Method and device for realizing high-precision timer of virtual machine and electronic equipment Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 56
- 230000006870 function Effects 0.000 claims abstract description 44
- 238000005316 response function Methods 0.000 claims abstract description 12
- 238000013507 mapping Methods 0.000 claims description 2
- 238000012545 processing Methods 0.000 abstract description 11
- 238000004590 computer program Methods 0.000 description 24
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- 238000004891 communication Methods 0.000 description 6
- 238000011156 evaluation Methods 0.000 description 5
- 230000003287 optical effect Effects 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 230000000644 propagated effect Effects 0.000 description 2
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- G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
- G06F9/45533—Hypervisors; Virtual machine monitors
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- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
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- G06F2009/45562—Creating, deleting, cloning virtual machine instances
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Abstract
The embodiment of the invention discloses a method and a device for realizing a high-precision timer of a virtual machine and electronic equipment, and relates to the technical field of data processing. The method comprises the following steps: creating a timer of nanosecond precision in the main operating system using a timer generating function; a timer signal receiving function is established in the main operating system, after receiving a timing signal sent by the timer, the timer signal receiving function triggers the main operating system to map I/O interruption to a memory of a slave operating system, and the slave operating system runs in the main operating system; and receiving a memory mapped I/O interrupt sent by the master operating system in an interrupt response function of the slave operating system, and determining a clock value of a timer in the slave operating system based on the content sent in the memory mapped I/O interrupt. According to the scheme, the precision of the timer in the slave operating system is improved.
Description
Technical Field
The invention relates to the technical field of data processing, in particular to a technology for realizing a high-precision timer of a virtual machine.
Background
As virtualization technologies become more and more popular, virtualization technologies are used more and more slowly in data centers, mobile phones, and automobiles. The clock above the virtualization is generally implemented by hypervisor, and a virtual timer (timer) is provided at the hypervisor layer for the slave operating system (guest os) to use. If no virtualization exists, the hrtimer is used when the slave operating system runs on the bare computer, the accuracy of the hrtimer can reach the nanosecond level originally, but the high-accuracy clock accuracy in the slave operating system cannot be guaranteed generally. For the slave operating system of the existing qnx host system plus android, a 16ms hrtimer is set, the obtained result is very uncertain, when the system load is low and the system interruption is less, the precision error is about 6ms, when the system load is high and the interruption is more, the obtained actual value is only 6ms or 36ms, and the error reaches dozens of ms.
In view of the above problems, a new technique for implementing a high-precision timer of a virtual machine is needed.
Disclosure of Invention
In view of the above, embodiments of the present invention provide a method and an apparatus for implementing a high-precision timer of a virtual machine, an electronic device, a non-transitory computer-readable storage medium, and a computer program, which at least partially solve the problems in the prior art.
In a first aspect, an embodiment of the present invention provides a method for implementing a high-precision timer of a virtual machine, including:
creating a timer of nanosecond precision using a timer generating function in a main operating system running in a hardware device containing the hardware timer;
a timer signal receiving function is established in the main operating system, after the timer signal receiving function receives a timing signal sent by the timer, the timer signal receiving function triggers the main operating system to map I/O interruption to a memory of a slave operating system, and the slave operating system runs in the main operating system;
and receiving a memory mapped I/O interrupt sent by the master operating system in an interrupt response function of the slave operating system, and determining a clock value of a timer in the slave operating system based on the content sent in the memory mapped I/O interrupt.
According to a specific implementation of the embodiments of the present disclosure, the tolerance of the timer is less than one tick time unit.
According to a specific implementation manner of the embodiment of the present disclosure, the method further includes:
setting a timer in the slave operating system, wherein the value in the slave timer is obtained from the memory mapped I/O interrupt.
According to a specific implementation of the embodiment of the present disclosure, the main operating system is a hyper operating system.
According to a specific implementation manner of the embodiment of the present disclosure, the method further includes:
setting a frequency parameter in the slave operating system, and sending a memory mapped I/O interrupt to the slave operating system by the master operating system based on the frequency parameter.
According to a specific implementation manner of the embodiment of the present disclosure, the method further includes:
and writing the frequency parameter into a preset address, and triggering I/O interruption to the main operating system after the comment parameter is written into the preset address.
In a second aspect, an embodiment of the present invention further provides an apparatus for implementing a high-precision timer of a virtual machine, where the apparatus includes:
the generating module is used for creating a timer with nanosecond precision by using a timer generating function in a main operating system, and the main operating system runs in hardware equipment containing a hardware timer;
a creating module, configured to create a timer signal receiving function in the master operating system, where the timer signal receiving function triggers a memory mapped I/O interrupt from the master operating system to a slave operating system after receiving a timing signal sent by the timer, and the slave operating system runs in the master operating system;
a receiving module, configured to receive, in an interrupt response function of the slave operating system, a memory mapped I/O interrupt sent by the master operating system, and determine, based on content sent in the memory mapped I/O interrupt, a clock value of a timer in the slave operating system.
In a third aspect, an embodiment of the present invention further provides an electronic device, where the electronic device includes:
at least one processor; and the number of the first and second groups,
a memory communicatively coupled to the at least one processor; wherein,
the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the method for implementing a virtual machine high-precision timer according to any one of the first aspect or any implementation manner of the first aspect.
In a fourth aspect, an embodiment of the present invention further provides a non-transitory computer-readable storage medium, which stores computer instructions for causing the computer to execute an implementation method of the virtual machine high-precision timer according to the foregoing first aspect or any implementation manner of the first aspect.
In a fifth aspect, the present invention further provides a computer program product, where the computer program product includes a computer program stored on a non-transitory computer-readable storage medium, where the computer program includes program instructions, and when the program instructions are executed by a computer, the computer executes an implementation method of a virtual machine high-precision timer according to the foregoing first aspect or any implementation manner of the first aspect.
The implementation method, the implementation device, the electronic device, the non-transitory computer readable storage medium and the computer program of the high-precision timer of the virtual machine provided by the embodiment of the invention comprise the steps of using a timer generating function to create a timer with nanosecond precision in a main operating system, wherein the main operating system runs in hardware equipment comprising a hardware timer; a timer signal receiving function is established in the main operating system, after receiving a timing signal sent by the timer, the timer signal receiving function triggers the main operating system to map I/O interruption to a memory of a slave operating system, and the slave operating system runs in the main operating system; and receiving a memory mapped I/O interrupt sent by the master operating system in an interrupt response function of the slave operating system, and determining a clock value of a timer in the slave operating system based on the content sent in the memory mapped I/O interrupt. According to the scheme, under the condition that no hardware timer exists in the slave operating system, the high-precision timer in the master operating system is used, and then the slave operating system is notified in an independent interrupt mode.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic diagram of an implementation flow of a high-precision timer of a virtual machine according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a virtual machine architecture according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of an implementation apparatus of a high-precision timer of a virtual machine according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of an electronic device according to an embodiment of the present invention.
Detailed Description
The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.
The embodiments of the present disclosure are described below with specific examples, and other advantages and effects of the present disclosure will be readily apparent to those skilled in the art from the disclosure in the specification. It is to be understood that the described embodiments are merely illustrative of some, and not restrictive, of the embodiments of the disclosure. The disclosure may be embodied or carried out in various other specific embodiments, and various modifications and changes may be made in the details within the description without departing from the spirit of the disclosure. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure.
It is noted that various aspects of the embodiments are described below within the scope of the appended claims. It should be apparent that the aspects described herein may be embodied in a wide variety of forms and that any specific structure and/or function described herein is merely illustrative. Based on the disclosure, one skilled in the art should appreciate that one aspect described herein may be implemented independently of any other aspects and that two or more of these aspects may be combined in various ways. For example, an apparatus may be implemented and/or a method practiced using any number of the aspects set forth herein. Additionally, such an apparatus may be implemented and/or such a method may be practiced using other structure and/or functionality in addition to one or more of the aspects set forth herein.
It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present disclosure, and the drawings only show the components related to the present disclosure rather than the number, shape and size of the components in actual implementation, and the type, amount and ratio of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
In addition, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the aspects may be practiced without these specific details.
The embodiment of the disclosure provides a method for realizing a high-precision timer of a virtual machine. The implementation method of the high-precision timer of the virtual machine provided by the embodiment can be executed by a computing device, the computing device can be implemented as software, or implemented as a combination of software and hardware, and the computing device can be integrally arranged in a server, a terminal device, and the like.
Referring to fig. 1, an implementation method of a high-precision timer of a virtual machine provided in the embodiment of the present disclosure includes the following steps:
s101, a timer with nanosecond precision is created in a main operating system by using a timer generating function, and the main operating system runs in hardware equipment comprising a hardware timer.
Referring to fig. 2, the master operating system is an operating system running on a hardware device, and as an example, the master operating system may be a hypervector operating system, and on the master operating system, one or more slave operating systems may be installed, and these slave operating systems run in a manner of a virtual operating system, and the slave operating system may be an Android operating system.
Since the slave operating system runs on top of the master operating system, it cannot directly call the hardware timer in the hardware device in some specific scenarios, resulting in low clock accuracy in the slave operating system.
Based on the method, a timer function is used in the main operating system to create a timer in a nanosecond level, the timer in the main operating system can directly call a hardware timer module in the hardware equipment through the main operating system, and the timer function in the main operating system can obtain accurate clock information based on the hardware timer module.
S102, a timer signal receiving function is established in the main operating system, after the timer signal receiving function receives a timing signal sent by the timer, I/O interruption of memory mapping from the main operating system to a slave operating system is triggered, and the slave operating system runs in the main operating system.
After the timer in the main operating system is set, a timer signal receiving function can be created in the main operating system, and an interrupt signal sent by the timer in the main operating system can be received by the timer signal receiving function when the time of the timer in the main operating system reaches.
After receiving the interrupt signal of the timer of the master operating system, it indicates that the timing operation is completed, and at this time, an instruction for completing the timing needs to be sent to the corresponding timer in the slave operating system. For this purpose, a memory mapped I/O interrupt is set in the master operating system, and a corresponding interrupt signal is transferred to the slave operating system through the memory mapped I/O interrupt.
S103, receiving the memory mapped I/O interrupt sent by the main operating system in the interrupt response function of the slave operating system, and determining the clock value of the timer in the slave operating system based on the content sent in the memory mapped I/O interrupt.
In order to receive an interrupt signal sent by a main operating system, a special interrupt response function is set in a slave operating system, a memory mapped I/O interrupt sent by the main operating system is received in the interrupt response function, and the clock value of a timer in the slave operating system can be determined based on the content sent in the memory mapped I/O interrupt.
According to the scheme, a high-precision clock is established in a main operating system, the precision is in a nanosecond level, when the clock interrupt of the main operating system arrives, an I/O interrupt of a shared memory is used for informing a slave operating system, and after the interrupt is received in the slave operating system, tasks with high requirements on time sequence are processed in an interrupt processing function. The slave operating system may modify the time of the timer of the master operating system, for example, 1696s, 30ms, etc. may be set to different values.
The method has the advantages that under the condition that no hardware timer is arranged in the slave operating system, the high-precision timer of the master operating system is used for acquiring the precise timer, and then the slave operating system is informed in an independent interrupt mode. May not be affected by the timer of the slave operating system.
To limit the accuracy of the timer, according to a specific implementation of the embodiment of the present disclosure, the tolerance of the timer set in the main operating system is less than one tick time unit.
According to a specific implementation manner of the embodiment of the present disclosure, the method further includes: setting a timer in the slave operating system, wherein the value in the slave timer is obtained from the memory mapped I/O interrupt.
According to a specific implementation of the embodiment of the present disclosure, the main operating system is a hyper operating system.
According to a specific implementation manner of the embodiment of the present disclosure, the method further includes: setting a frequency parameter in the slave operating system, and sending a memory mapped I/O interrupt to the slave operating system by the master operating system based on the frequency parameter.
According to a specific implementation manner of the embodiment of the present disclosure, the method further includes: and writing the frequency parameter into a preset address, and triggering I/O interruption to the main operating system after the comment parameter is written into the preset address.
Corresponding to the above method embodiment, referring to fig. 3, an embodiment of the present invention further provides an apparatus 30 for implementing a high-precision timer of a virtual machine, including:
a generating module 301, configured to create a timer with nanosecond precision using a timer generating function in a main operating system running in a hardware device including a hardware timer.
Referring to fig. 2, the master operating system is an operating system running on a hardware device, and as an example, the master operating system may be a hyperreservoir operating system, and on the master operating system, one or more slave operating systems may be installed, and the slave operating systems run in a virtual operating system manner, and the slave operating systems may be Android operating systems.
Since the slave operating system runs on top of the master operating system, it cannot directly call the hardware timer in the hardware device in some specific scenarios, resulting in low clock accuracy in the slave operating system.
Based on the method, a timer function is used in the main operating system to create a timer in a nanosecond level, the timer in the main operating system can directly call a hardware timer module in the hardware equipment through the main operating system, and the timer function in the main operating system can obtain accurate clock information based on the hardware timer module.
A creating module 302, configured to create a timer signal receiving function in the master operating system, where the timer signal receiving function triggers a memory mapped I/O interrupt from the master operating system to a slave operating system after receiving a timing signal sent by the timer, where the slave operating system runs in the master operating system.
After the timer in the main operating system is set, a timer signal receiving function can be created in the main operating system, and an interrupt signal sent by the timer in the main operating system can be received by the timer signal receiving function when the time of the timer in the main operating system reaches.
After receiving the interrupt signal of the timer of the master operating system, it indicates that the timing operation has been completed, and at this time, an instruction for completing timing needs to be sent to the corresponding timer in the slave operating system. For this purpose, a memory mapped I/O interrupt is set in the master operating system, and a corresponding interrupt signal is passed to the slave operating system via the memory mapped I/O interrupt.
A receiving module 303, configured to receive, in an interrupt response function of the slave operating system, a memory mapped I/O interrupt sent by the master operating system, and determine, based on content sent in the memory mapped I/O interrupt, a clock value of a timer in the slave operating system.
In order to receive an interrupt signal sent by a main operating system, a special interrupt response function is set in a slave operating system, a memory mapped I/O interrupt sent by the main operating system is received in the interrupt response function, and the clock value of a timer in the slave operating system can be determined based on the content sent in the memory mapped I/O interrupt.
The apparatus shown in fig. 3 may correspondingly execute the content in the above method embodiment, and details of the part not described in detail in this embodiment refer to the content described in the above method embodiment, which is not described again here.
Referring to fig. 4, an embodiment of the present disclosure also provides an electronic device 40, including:
at least one processor; and the number of the first and second groups,
a memory communicatively coupled to the at least one processor; wherein,
the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the method for implementing the high-precision timer of the virtual machine in the foregoing method embodiments.
The disclosed embodiments also provide a non-transitory computer-readable storage medium storing computer instructions for causing the computer to perform the foregoing method embodiments.
The disclosed embodiments also provide a computer program product comprising a computer program stored on a non-transitory computer-readable storage medium, the computer program comprising program instructions that, when executed by a computer, cause the computer to perform a method for implementing a high-precision timer of a virtual machine in the aforementioned method embodiments.
Referring now to FIG. 4, a block diagram of an electronic device 40 suitable for use in implementing embodiments of the present disclosure is shown. The electronic devices in the embodiments of the present disclosure may include, but are not limited to, mobile terminals such as mobile phones, notebook computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), in-vehicle terminals (e.g., car navigation terminals), and the like, and fixed terminals such as digital TVs, desktop computers, and the like. The electronic device shown in fig. 4 is only an example, and should not bring any limitation to the functions and the scope of use of the embodiments of the present disclosure.
As shown in fig. 4, the electronic device 40 may include a processing means (e.g., a central processing unit, a graphics processor, etc.) 401 that may perform various appropriate actions and processes in accordance with a program stored in a Read Only Memory (ROM) 402 or a program loaded from a storage means 408 into a Random Access Memory (RAM) 403. In the RAM 403, various programs and data necessary for the operation of the electronic apparatus 40 are also stored. The processing device 401, the ROM 402, and the RAM 403 are connected to each other via a bus 404. An input/output (I/O) interface 405 is also connected to bus 404.
Generally, the following devices may be connected to the I/O interface 405: input devices 406 including, for example, a touch screen, touch pad, keyboard, mouse, image sensor, microphone, accelerometer, gyroscope, etc.; an output device 407 including, for example, a Liquid Crystal Display (LCD), a speaker, a vibrator, and the like; storage 408 including, for example, tape, hard disk, etc.; and a communication device 409. The communication device 409 may allow the electronic device 40 to communicate wirelessly or by wire with other devices to exchange data. While the figures illustrate an electronic device 40 having various means, it is to be understood that not all illustrated means are required to be implemented or provided. More or fewer devices may alternatively be implemented or provided.
In particular, according to an embodiment of the present disclosure, the processes described above with reference to the flowcharts may be implemented as computer software programs. For example, embodiments of the present disclosure include a computer program product comprising a computer program embodied on a computer readable medium, the computer program comprising program code for performing the method illustrated in the flow chart. In such an embodiment, the computer program may be downloaded and installed from a network via the communication device 409, or from the storage device 408, or from the ROM 402. The computer program performs the above-described functions defined in the methods of the embodiments of the present disclosure when executed by the processing device 401. Referring to fig. 4, an embodiment of the present disclosure also provides an electronic device 40, including:
at least one processor; and the number of the first and second groups,
a memory communicatively coupled to the at least one processor; wherein,
the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the method for implementing the high-precision timer of the virtual machine in the foregoing method embodiments.
The disclosed embodiments also provide a non-transitory computer-readable storage medium storing computer instructions for causing the computer to perform the foregoing method embodiments.
The disclosed embodiments also provide a computer program product comprising a computer program stored on a non-transitory computer readable storage medium, the computer program comprising program instructions that, when executed by a computer, cause the computer to perform the method for implementing a high-precision timer of a virtual machine in the foregoing method embodiments.
Referring now to FIG. 4, a block diagram of an electronic device 40 suitable for use in implementing embodiments of the present disclosure is shown. The electronic devices in the embodiments of the present disclosure may include, but are not limited to, mobile terminals such as mobile phones, notebook computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), in-vehicle terminals (e.g., car navigation terminals), and the like, and fixed terminals such as digital TVs, desktop computers, and the like. The electronic device shown in fig. 4 is only an example, and should not bring any limitation to the functions and the scope of use of the embodiments of the present disclosure.
As shown in fig. 4, the electronic device 40 may include a processing means (e.g., a central processing unit, a graphics processor, etc.) 401 that may perform various appropriate actions and processes in accordance with a program stored in a Read Only Memory (ROM) 402 or a program loaded from a storage means 408 into a Random Access Memory (RAM) 403. In the RAM 403, various programs and data necessary for the operation of the electronic apparatus 40 are also stored. The processing device 401, the ROM 402, and the RAM 403 are connected to each other via a bus 404. An input/output (I/O) interface 405 is also connected to bus 404.
Generally, the following devices may be connected to the I/O interface 405: input devices 406 including, for example, a touch screen, touch pad, keyboard, mouse, image sensor, microphone, accelerometer, gyroscope, etc.; an output device 407 including, for example, a Liquid Crystal Display (LCD), a speaker, a vibrator, and the like; storage 408 including, for example, tape, hard disk, etc.; and a communication device 409. The communication device 409 may allow the electronic device 40 to communicate wirelessly or by wire with other devices to exchange data. While the figures illustrate an electronic device 40 having various means, it is understood that not all illustrated means are required to be implemented or provided. More or fewer devices may alternatively be implemented or provided.
In particular, according to an embodiment of the present disclosure, the processes described above with reference to the flowcharts may be implemented as computer software programs. For example, embodiments of the present disclosure include a computer program product comprising a computer program embodied on a computer readable medium, the computer program comprising program code for performing the method illustrated in the flow chart. In such an embodiment, the computer program may be downloaded and installed from a network via the communication device 409, or from the storage device 408, or from the ROM 402. The computer program performs the above-described functions defined in the methods of the embodiments of the present disclosure when executed by the processing device 401.
It should be noted that the computer readable medium in the present disclosure can be a computer readable signal medium or a computer readable storage medium or any combination of the two. A computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples of the computer readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the present disclosure, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. In contrast, in the present disclosure, a computer readable signal medium may comprise a propagated data signal with computer readable program code embodied therein, either in baseband or as part of a carrier wave. Such a propagated data signal may take many forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to: electrical wires, optical cables, RF (radio frequency), etc., or any suitable combination of the foregoing.
The computer readable medium may be embodied in the electronic device; or may exist separately without being assembled into the electronic device.
The computer readable medium carries one or more programs which, when executed by the electronic device, cause the electronic device to: acquiring at least two internet protocol addresses; sending a node evaluation request comprising the at least two internet protocol addresses to node evaluation equipment, wherein the node evaluation equipment selects the internet protocol addresses from the at least two internet protocol addresses and returns the internet protocol addresses; receiving an internet protocol address returned by the node evaluation equipment; wherein the obtained internet protocol address indicates an edge node in the content distribution network.
Alternatively, the computer readable medium carries one or more programs which, when executed by the electronic device, cause the electronic device to: receiving a node evaluation request comprising at least two internet protocol addresses; selecting an internet protocol address from the at least two internet protocol addresses; returning the selected internet protocol address; wherein the received internet protocol address indicates an edge node in the content distribution network.
Computer program code for carrying out operations for aspects of the present disclosure may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, smalltalk, C + +, and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet service provider).
The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
The units described in the embodiments of the present disclosure may be implemented by software or hardware. Where the name of a unit does not in some cases constitute a limitation of the unit itself, for example, the first retrieving unit may also be described as a "unit for retrieving at least two internet protocol addresses".
It should be understood that portions of the present disclosure may be implemented in hardware, software, firmware, or a combination thereof.
The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present disclosure should be covered within the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.
Claims (9)
1. A method for realizing a high-precision timer of a virtual machine is characterized by comprising the following steps:
the method comprises the steps that a timer generating function is used in a main operating system to create a timer with nanosecond precision, the main operating system runs in hardware equipment comprising a hardware timer, the timer in the main operating system directly calls a hardware timer module in the hardware equipment through the main operating system, and based on the hardware timer module, the timer function in the main operating system can obtain clock information;
a timer signal receiving function is established in the main operating system, the timer signal receiving function triggers the main operating system to map I/O interruption to the memory of a slave operating system after receiving a timing signal sent by the hardware timer, the slave operating system runs in the main operating system, after receiving the interruption signal of the hardware timer of the main operating system, the timing operation is completed, a timed completed instruction is sent to a corresponding timer in the slave operating system, the memory mapped I/O interruption is set in the main operating system, and the corresponding interruption signal is transmitted to the slave operating system through the memory mapped I/O interruption;
receiving a memory mapped I/O interrupt sent by the master operating system in an interrupt response function of the slave operating system, determining a clock value of a timer in the slave operating system based on the content sent in the memory mapped I/O interrupt, so that the timer of the master operating system is used under the condition that no hardware timer exists in the slave operating system, and then informing the slave operating system in an independent interrupt mode.
2. The method for implementing the high-precision timer of the virtual machine according to claim 1, wherein:
the tolerance of the hardware timer is less than one tick time unit.
3. The method for implementing the high-precision timer of the virtual machine according to claim 1, further comprising:
and setting a slave timer in the slave operating system, wherein the value in the slave timer is obtained from the memory mapping I/O interrupt.
4. The method for implementing the high-precision timer of the virtual machine according to claim 1, wherein:
the main operating system is a HYPERVISOR operating system.
5. The method for implementing the high-precision timer of the virtual machine according to claim 1, further comprising:
setting a frequency parameter in the slave operating system, and sending a memory mapped I/O interrupt to the slave operating system by the master operating system based on the frequency parameter.
6. The method for implementing the high-precision timer of the virtual machine according to claim 5, further comprising:
and writing the frequency parameter into a preset address, and triggering I/O interruption to the main operating system after the frequency parameter is written into the preset address.
7. An implementation device of a high-precision timer of a virtual machine is characterized by comprising:
the generating module is used for creating a timer with nanosecond precision by using a timer generating function in a main operating system, the main operating system runs in hardware equipment containing a hardware timer, the timer in the main operating system directly calls the hardware timer module in the hardware equipment through the main operating system, and the timer function in the main operating system can obtain clock information based on the hardware timer module;
a creating module, configured to create a timer signal receiving function in the master operating system, where the timer signal receiving function, after receiving a timing signal sent by the hardware timer, triggers a memory mapped I/O interrupt from the master operating system to a slave operating system, where the slave operating system runs in the master operating system, and after receiving an interrupt signal of the hardware timer of the master operating system, indicates that the timing operation has been completed, sends a timed-completed instruction to a corresponding timer in the slave operating system, sets a memory mapped I/O interrupt in the master operating system, and transmits the corresponding interrupt signal to the slave operating system through the memory mapped I/O interrupt;
a receiving module, configured to receive, in an interrupt response function of the slave operating system, a memory mapped I/O interrupt sent by the master operating system, determine, based on content sent in the memory mapped I/O interrupt, a clock value of a timer in the slave operating system, so that, in a case where there is no hardware timer in the slave operating system, the timer of the master operating system is used, and then notify the slave operating system in an independent interrupt manner.
8. An electronic device, characterized in that the electronic device comprises:
at least one processor; and the number of the first and second groups,
a memory communicatively coupled to the at least one processor; wherein,
the memory stores instructions executable by the at least one processor to enable the at least one processor to perform a method for implementing a virtual machine high accuracy timer as claimed in any one of claims 1-6.
9. A non-transitory computer-readable storage medium storing computer instructions for causing the computer to perform a method of implementing the virtual machine high accuracy timer of any one of the preceding claims 1-6.
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| CN112463125B (en) * | 2020-12-09 | 2023-09-15 | 百富计算机技术（深圳）有限公司 | Timing method and equipment of virtual timer |
| CN112817701B (en) * | 2021-02-25 | 2024-03-12 | 北京火山引擎科技有限公司 | Timer processing method, device, electronic equipment and computer readable medium |
| CN114489816B (en) * | 2021-12-22 | 2024-05-14 | 瑞芯微电子股份有限公司 | Timer device and method for providing timing |
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