WO2023115701A1 - 可降低泄露电流的iii族氮化物晶体管结构及其制作方法 - Google Patents

可降低泄露电流的iii族氮化物晶体管结构及其制作方法 Download PDF

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WO2023115701A1
WO2023115701A1 PCT/CN2022/078927 CN2022078927W WO2023115701A1 WO 2023115701 A1 WO2023115701 A1 WO 2023115701A1 CN 2022078927 W CN2022078927 W CN 2022078927W WO 2023115701 A1 WO2023115701 A1 WO 2023115701A1
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semiconductor
layer
type
heterojunction
resistance
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PCT/CN2022/078927
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English (en)
French (fr)
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魏星
张晓东
赵德胜
张宝顺
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中国科学院苏州纳米技术与纳米仿生研究所
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Priority to US18/012,240 priority Critical patent/US11810910B2/en
Priority to JP2022568406A priority patent/JP7505808B2/ja
Publication of WO2023115701A1 publication Critical patent/WO2023115701A1/zh

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Definitions

  • the present application relates to a transistor structure, in particular to a Group III nitride transistor structure capable of reducing leakage current and a manufacturing method thereof, belonging to the field of semiconductor technology.
  • Group III nitrides such as gallium nitride GaN
  • Group III nitrides have excellent material properties such as large band gap, high breakdown field strength, high electron mobility, and high electron saturation drift velocity, and are considered to be very suitable for the application of next-generation power electronic systems .
  • Transistor devices in power electronic systems such as synchronous buck or boost converters will inevitably work in the reverse conduction state.
  • GaN-based high electron mobility transistors due to the lack of body diode, the reverse recovery is fast, but the source-to-drain voltage drop depends on the gate bias, which makes its values compared with Si-based and SiC Compared with the base power device, it reaches a higher value and brings power loss. Therefore, improving the reverse conduction capability of GaN HEMTs is crucial to further reduce the power loss of GaN-based power electronic systems.
  • the substrate Si is used to prepare Schottky diodes (SBDs).
  • SBDs Schottky diodes
  • the drain of the HEMT is shared with the cathode of the SBD, but the Si-based SBD is limited by the material properties.
  • the advantages of GaN cannot be brought into full play, and it will cause problems such as reliability.
  • the cross structure of HEMT and SBD or lateral rectifier is effective, but it seems that the larger occupied area is an inevitable problem, and the reverse conduction required
  • the source-drain voltage drop depends on the gate bias voltage, and the value is large, resulting in higher power consumption; horizontally integrated SBD usually leads to an increase in leakage current, or an increase in the forward on-resistance of HEMT; vertically integrated SBD through The leakage current is also difficult to control, and the current report is integrated with the Si Schottky diode on the substrate, which cannot take advantage of the GaN material.
  • the main purpose of the present application is to provide a III-nitride transistor structure and its manufacturing method which can reduce the leakage current, so as to overcome the deficiencies in the prior art.
  • Embodiments of the present application provide, on the one hand, a III-nitride transistor structure capable of reducing leakage current, which includes:
  • the first heterojunction and the second heterojunction are stacked, and the first heterojunction and the second heterojunction are electrically isolated by a high-resistance material and/or an insertion layer;
  • the drain is also electrically connected to the first gate and the second electrode respectively, and a sixth semiconductor is arranged between the second gate and the second heterojunction, and the sixth semiconductor can connect A portion of the second two-dimensional electron gas located below it is depleted.
  • the embodiment of the present application also provides a method for fabricating a III-nitride transistor structure capable of reducing leakage current, which includes:
  • first electrode Fabricate a first electrode, a second electrode, a first gate, and a third semiconductor that cooperate with the first heterojunction, the first electrode and the second electrode pass through the first two-dimensional electrons in the first heterojunction Gas and electrical connection, the third semiconductor is arranged between the first gate and the first heterojunction, the first gate is also electrically connected to the first electrode, and the third semiconductor can be located below it a portion of the first two-dimensional electron gas is depleted;
  • the sixth semiconductor is disposed between the second gate and the second heterojunction, and the sixth semiconductor is capable of depleting the second two-dimensional electron gas of a portion located therebelow;
  • the first gate is electrically connected to the source, and the second electrode is electrically connected to the drain.
  • a III-nitride transistor structure provided in the embodiment of the present application integrates the diode and the triode in a direction perpendicular to the substrate, so that the wafer area occupied by the III-nitride transistor is smaller, which is beneficial to the device Miniaturized applications;
  • a group III nitride transistor structure provided in the embodiment of the present application, the overall structure of the device has the characteristics of direct growth and process compatibility, which effectively reduces the complexity and manufacturing cost of the device;
  • a III-nitride transistor structure provided in the embodiment of the present application can effectively reduce the leakage current and power consumption of the device, thereby improving the reliability and stability of the device;
  • III-nitride transistor structure provided in the embodiment of the present application has better process compatibility and is more convenient in design.
  • Fig. 1a is a schematic structural diagram of a III-nitride transistor structure capable of reducing leakage current provided in Embodiment 1 of the present application;
  • Fig. 1b is a TCAD simulation test result of a III-nitride transistor structure that can reduce the leakage current provided in Example 1 of the present application and a traditional transistor;
  • FIGS. 2a-2g are schematic structural diagrams of the fabrication process of a Group III nitride transistor structure capable of reducing leakage current in Example 1 of the present application;
  • FIG. 3 is a schematic structural diagram of a III-nitride transistor structure that can reduce leakage current provided in Embodiment 2 of the present application;
  • FIG. 4 is a schematic structural diagram of a III-nitride transistor structure capable of reducing leakage current provided in Embodiment 3 of the present application;
  • Fig. 5 is the performance test result of device in comparative example 1;
  • Fig. 6 is the performance test result of device in comparative example 2.
  • FIG. 7 is a schematic structural diagram of a III-nitride transistor structure capable of reducing leakage current provided in Embodiment 4 of the present application;
  • FIG. 8 is a schematic structural diagram of a III-nitride transistor structure capable of reducing leakage current provided in Embodiment 5 of the present application;
  • Fig. 9 is a corresponding curve between hole distribution, H atom distribution and p-GaN spacing in the P-type layer;
  • Fig. 10 is a corresponding curve between the electric field intensity in the p-type layer and the distance between p-GaN.
  • the embodiment of the present application provides a III-nitride transistor structure that can reduce the leakage current.
  • the embodiment of the present application provides a parallel connection of the transistor and the diode.
  • Device structure in order to reduce the wafer area occupied by the device as much as possible, the embodiment of the present application stacks transistors and diodes vertically to achieve vertical integration, avoiding the problem of increasing the area in the lateral direction; and, in order to avoid leakage current
  • the embodiment of the present application adopts a hybrid anode diode structure similar to the HEMT device structure and compatible with the process.
  • the diode has an in-situ high-resistance passivation layer (which can be understood as a high-resistance material), which greatly reduces the device
  • an in-situ high-resistance passivation layer which can be understood as a high-resistance material
  • the embodiment of this application adopts a hybrid anode diode structure similar to the HEMT device structure and compatible with the process.
  • the diode is also made of GaN material and AlGaN/GaN form the basic structure.
  • the first heterojunction and the second heterojunction are electrically isolated through a high-resistance material and/or an insertion layer, and the insertion layer can also reduce stress.”
  • the inventors of this case found that for material epitaxy It is difficult to achieve vertical integration, because the thickness of the epitaxial material structure needs to be thick enough, but the thick epitaxial material structure will cause cracks in the sample, and the insertion layer between the first heterojunction and the second heterojunction can be Effectively alleviate the problem of sample cracking.
  • Embodiments of the present application provide, on the one hand, a III-nitride transistor structure capable of reducing leakage current, which includes:
  • the first heterojunction and the second heterojunction are stacked, and the first heterojunction and the second heterojunction are electrically isolated by a high-resistance material and/or an insertion layer;
  • the drain is also electrically connected to the first gate and the second electrode respectively, and a sixth semiconductor is arranged between the second gate and the second heterojunction, and the sixth semiconductor can connect A portion of the second two-dimensional electron gas located below it is depleted.
  • the III-nitride transistor structure includes a first semiconductor, a second semiconductor, a high-resistance material layer or an insertion layer, a fourth semiconductor, and a fifth semiconductor that are sequentially grown along a predetermined direction, or,
  • the III-nitride transistor structure includes a fourth semiconductor, a fifth semiconductor, a high-resistance material layer or an insertion layer, a first semiconductor, and a second semiconductor that are sequentially grown along a set direction; or, the III-nitride transistor The structure includes a first semiconductor, a second semiconductor, a high-resistance material layer, an insertion layer, a fourth semiconductor, and a fifth semiconductor that are sequentially grown along a set direction, or, the III-nitride transistor structure includes sequentially growing along a set direction The fourth semiconductor, the fifth semiconductor, the high-resistance material layer, the insertion layer, the first semiconductor, and the second semiconductor formed by growth;
  • the first semiconductor cooperates with the second semiconductor to form a first heterojunction
  • the fourth semiconductor cooperates with the fifth semiconductor to form a second heterojunction
  • the high-resistance material layer is formed by transforming the first region of a continuous third semiconductor layer, and the third semiconductor is distributed in the second region of the third semiconductor layer;
  • the third semiconductor is formed by transforming the second region of a continuous high-resistance material layer, and the high-resistance material is distributed in the first region of the high-resistance material layer.
  • the third semiconductor is a p-type semiconductor.
  • the material of the third semiconductor includes a p-type wide bandgap semiconductor.
  • the p-type wide bandgap semiconductor includes p-type group III nitride.
  • the p-type Group III nitride includes p-type GaN, p-type AlGaN, p-type InGaN, or p-type InN.
  • the p-type semiconductor includes p-type polysilicon, p-type amorphous silicon, p-type oxide, p-type diamond, or p-type semiconductor polymer.
  • the third semiconductor includes a plurality of strip-shaped p-type semiconductors arranged at intervals, and the plurality of strip-shaped p-type semiconductors are distributed in an array.
  • the doping concentration of the third semiconductor is 10 16 to 10 20 cm -3 .
  • the thickness of the third semiconductor is 10 nm ⁇ 500 nm.
  • the high-resistance material includes high-resistance GaN, high-resistance AlGaN, high-resistance Ga 2 O 3 , high-resistance InGaN, or high-resistance InN.
  • the high-resistance material layer is formed by transforming the third region of a continuous sixth semiconductor layer, and the sixth semiconductor is distributed in the fourth region of the sixth semiconductor layer;
  • the sixth semiconductor is formed by transforming the fourth region of a continuous high-resistance material layer, and the high-resistance material is distributed in the third region of the high-resistance material layer.
  • the sixth semiconductor is a p-type semiconductor.
  • the material of the sixth semiconductor includes a p-type wide bandgap semiconductor.
  • the p-type wide bandgap semiconductor includes p-type group III nitride.
  • the p-type Group III nitride includes p-type GaN, p-type AlGaN, p-type InGaN, or p-type InN.
  • the p-type semiconductor includes p-type polysilicon, p-type amorphous silicon, p-type oxide, p-type diamond, or p-type semiconductor polymer.
  • the high-resistance material includes high-resistance GaN, high-resistance AlGaN, high-resistance Ga 2 O 3 , high-resistance InGaN, or high-resistance InN.
  • the high-resistance material layer is distributed between the third semiconductor and the second electrode, and the third semiconductor is also electrically isolated from the second electrode by the high-resistance material;
  • the high-resistance material layer is distributed between the sixth semiconductor and the source and drain, and the sixth semiconductor is also electrically isolated from the source and drain by the high-resistance material.
  • the insertion layer includes any one of a metal layer, a dielectric layer, and a two-dimensional material layer.
  • the metal layer includes a single-layer metal layer or a multi-layer metal layer, and the material of the metal layer includes any one of Mo, Mg, and Al, but is not limited thereto.
  • the metal layer has a thickness of 2 nm ⁇ 10 ⁇ m.
  • the material of the dielectric layer includes any one of AlN, BN, AlBN, AlPN, BCN, high-resistance AlGaN, and high-resistance GaN, but is not limited thereto.
  • the thickness of the dielectric layer is 0.5 nm ⁇ 1 ⁇ m.
  • the material of the two-dimensional material layer includes any one of BN, graphene, fluorinated graphene, graphene oxide, and black phosphorus, but is not limited thereto.
  • the thickness of the two-dimensional material layer is 0.5 nm ⁇ 500 nm.
  • an insulating dielectric layer is further disposed on the second heterojunction, and the source and drain are disposed on the insulating dielectric layer.
  • the thickness of the insulating medium layer is 1-1000 nm.
  • the material of the insulating dielectric layer includes any one or a combination of two or more of SiO 2 , AlN, and Si 3 N 4 , but is not limited thereto.
  • a two-dimensional material is further disposed on the sixth semiconductor, and the source and drain are disposed on the two-dimensional material.
  • a two-dimensional material is disposed on the third semiconductor.
  • the number of layers of the two-dimensional material is 1-100 layers.
  • the two-dimensional material is a single type of two-dimensional material or a heterojunction of two-dimensional materials.
  • the two-dimensional material includes any one or a combination of two or more of graphene, MoS 2 , and WS 2 , but is not limited thereto.
  • a seventh semiconductor is further disposed between the first semiconductor and the second semiconductor and/or between the fourth semiconductor and the fifth semiconductor.
  • the materials of the first semiconductor, the second semiconductor, the fourth semiconductor and the fifth semiconductor are all selected from group III-V compounds.
  • the materials of the first semiconductor and the fourth semiconductor include GaN or GaAs, but are not limited thereto.
  • the material of the second semiconductor and the fifth semiconductor includes AlGaN or AlGaAs, but is not limited thereto.
  • the material of the seventh semiconductor includes AlN, but is not limited thereto.
  • the first heterojunction cooperates with the first electrode and the second electrode to form a diode
  • the second heterojunction cooperates with the source, drain and gate to form a transistor (also can be understood as triode, the same below)
  • the first electrode may be an anode
  • the second electrode may be a cathode.
  • a lower p-type doping concentration and/or a thinner p-type material thickness can be set in the third semiconductor, which weakens its control on the 2DEG channel one, thereby causing the conduction of the diode
  • the diode will be turned on preferentially when the transistor conducts in reverse, that is, the first channel formed by the first two-dimensional electron gas in the first heterojunction will be turned on first, Therefore, the reverse conduction source-drain voltage drop of the transistor is reduced.
  • the electrical connection between the first electrode and the source may be through a metal interconnection on the chip, or an external circuit metal connection; the electrical connection between the second electrode and the drain may be It is through the metal interconnection on the chip, or it can be the metal connection of the external circuit.
  • the thickness of the gate is 10-1000nm
  • the material of the gate can be any one or two of Ti, Al, Ni, Au, Cr, Pt, Mo, Pd, etc.
  • the above combination for example, can be selected from the following group: Ni/Au, Mo/Au, Cr/Au, Pd/Au, but not limited thereto; the thickness of the first electrode, the second electrode, the source electrode and the drain electrode It can be 10-1000nm, and the material of the first electrode, the second electrode, the source electrode, and the drain electrode can be any one of Au, Cr, Pt, Ag, Ti, Al, TiN or an alloy formed by two or more , for example, may be selected from the following group: Ti/Al/Ni/Au, Ti/Al/Ti/Au, Ti/Al/Ti/TiN but not limited thereto.
  • the first heterojunction or the second heterojunction is formed on a substrate, and a buffer layer is distributed between the first heterojunction or the second heterojunction and the substrate.
  • the transistor may be vertically stacked on the diode, or the diode may be vertically stacked on the transistor, and the relative positions of the two in the vertical direction may be interchanged.
  • the embodiment of the present application also provides a method for fabricating a III-nitride transistor structure capable of reducing leakage current, which includes:
  • first electrode Fabricate a first electrode, a second electrode, a first gate, and a third semiconductor that cooperate with the first heterojunction, the first electrode and the second electrode pass through the first two-dimensional electrons in the first heterojunction Gas and electrical connection, the third semiconductor is arranged between the first gate and the first heterojunction, the first gate is also electrically connected to the first electrode, and the third semiconductor can be located below it a portion of the first two-dimensional electron gas is depleted;
  • the sixth semiconductor is disposed between the second gate and the second heterojunction, and the sixth semiconductor is capable of depleting the second two-dimensional electron gas of a portion located therebelow;
  • the first gate is electrically connected to the source, and the second electrode is electrically connected to the drain.
  • the manufacturing method specifically includes:
  • the fourth semiconductor growing sequentially along the set direction to form the first semiconductor, the second semiconductor, the high-resistance material layer or the insertion layer, the fourth semiconductor, and the fifth semiconductor that are stacked, or growing sequentially along the set direction to form the fourth semiconductor,
  • the fifth semiconductor, the high-resistance material layer or the insertion layer, the first semiconductor, and the second semiconductor, or the first semiconductor, the second semiconductor, the high-resistance material layer, the insertion layer, and the fourth semiconductor are sequentially grown along a set direction to form a stacked arrangement.
  • the semiconductor, the fifth semiconductor, or the fourth semiconductor, the fifth semiconductor, the high-resistance material layer, the insertion layer, the first semiconductor, and the second semiconductor are sequentially grown along a set direction to form a stacked arrangement,
  • the first semiconductor cooperates with the second semiconductor to form a first heterojunction
  • the fourth semiconductor cooperates with the fifth semiconductor to form a second heterojunction
  • the manufacturing method specifically includes:
  • the third semiconductor layer including a first region and a second region, and converting the first region to form the high-resistance material layer; or, forming a continuous high-resistance material layer on the second semiconductor, the high-resistance material layer including a first region and a second region, and converting the second region to form the third semiconductor;
  • the manufacturing method specifically includes:
  • the sixth semiconductor layer including a third region and a fourth region, performing conversion treatment on the third region to form the high-resistance material layer;
  • a continuous high-resistance material layer is formed on the fifth semiconductor, the high-resistance material layer includes a third region and a fourth region, and conversion treatment is performed on the fourth region to form the sixth semiconductor.
  • the method for performing the conversion treatment includes H ion implantation, H plasma treatment, H doping annealing, N ion implantation, F ion implantation, Ar ion implantation, Fe ion implantation, O plasma Any one or combination of treatment and thermal oxidation.
  • the third semiconductor and the sixth semiconductor generally use p-GaN material, which can be obtained by selective activation or NH 3 annealing, H plasma treatment, H ion implantation, O plasma treatment, thermal oxidation, secondary epitaxy, ion implantation, etc.
  • In-situ passivation is carried out by means of in-situ passivation, and the method of in-situ passivation is selective passivation, so as to weaken its control on 2DEG and reduce the conduction voltage drop of the diode.
  • the third semiconductor and the sixth semiconductor can also use p-type materials such as p-type polysilicon and p-type oxide. These materials can be deposited by sputtering, LPCVD, PECVD, etc., and their concentration can be controlled by deposition conditions. It can also be regulated by means of ion implantation, annealing, etc., and then the voltage drop of the diode can be regulated.
  • p-type materials such as p-type polysilicon and p-type oxide.
  • These materials can be deposited by sputtering, LPCVD, PECVD, etc., and their concentration can be controlled by deposition conditions. It can also be regulated by means of ion implantation, annealing, etc., and then the voltage drop of the diode can be regulated.
  • the p-type semiconductor (third semiconductor) under the second part of the first electrode can also be patterned, and then NH 3 annealing, H plasma treatment, H ion implantation, O plasma treatment, thermal In-situ passivation or partial removal by dry etching (ICP, RIE, NLD, etc.) or wet etching (PEC etching, KOH, etc.) Concentration, thereby regulating the voltage drop of the diode.
  • in-situ passivation can be performed by means of NH 3 annealing, H plasma treatment, H ion implantation, O plasma treatment, thermal oxidation, etc., to reduce the leakage current; for the sixth semiconductor , can be activated by post-process annealing, only the sixth semiconductor under the second gate is reserved, and the rest is in an unactivated state, that is, a high-resistance area, so as to reduce leakage current.
  • the manufacturing method further includes: patterning the third semiconductor, so that the third semiconductor is processed to form a bar array structure.
  • the manufacturing method further includes:
  • the sixth semiconductor and the high-resistance material layer are selectively epitaxially grown on the fifth semiconductor.
  • the manufacturing method further includes: forming an insertion layer on the high-resistance material layer, and then manufacturing a first heterojunction or a second heterojunction on the insertion layer.
  • the insertion layer includes any one of a metal layer, a dielectric layer, and a two-dimensional material layer.
  • the metal layer includes a single-layer metal layer or a multi-layer metal layer, and the material of the metal layer includes any one of Mo, Mg, and Al, but is not limited thereto.
  • the metal layer has a thickness of 2 nm ⁇ 10 ⁇ m.
  • the material of the dielectric layer includes any one of AlN, BN, AlBN, AlPN, BCN, high-resistance AlGaN, and high-resistance GaN, but is not limited thereto.
  • the thickness of the dielectric layer is 0.5 nm ⁇ 1 ⁇ m.
  • the material of the two-dimensional material layer includes any one of BN, graphene, fluorinated graphene, graphene oxide, and black phosphorus, but is not limited thereto.
  • the thickness of the two-dimensional material layer is 0.5 nm ⁇ 500 nm.
  • the third semiconductor is also electrically isolated from the second electrode through the high-resistance material, or the sixth semiconductor is also electrically isolated from the source and drain through the high-resistance material .
  • the third semiconductor and the sixth semiconductor are p-type semiconductors.
  • the material of the third semiconductor and the sixth semiconductor includes a p-type wide bandgap semiconductor.
  • the p-type wide bandgap semiconductor includes p-type group III nitride.
  • the p-type Group III nitride includes p-type GaN, p-type AlGaN, p-type InGaN or p-type InN.
  • the p-type semiconductor includes p-type polysilicon, p-type amorphous silicon, p-type oxide, p-type diamond, or p-type semiconductor polymer.
  • the first high-resistance material and the second high-resistance material include high-resistance GaN, high-resistance AlGaN, high-resistance Ga 2 O 3 , high-resistance InGaN, or high-resistance InN.
  • the transistor part and the diode part in the III-nitride transistor that can reduce the leakage current provided by the embodiment of the present application can be formed on the same wafer, or they can be formed on different wafers. Manufactured and formed separately, and then the diode part and the transistor part are integrated in the vertical direction by bonding; among them, the p-type semiconductor of the upper device part in the vertical direction can be activated as a whole first, and then etching or Passivation is used to preserve selective regions; of course, p-type semiconductors can also be obtained by selective region epitaxy or lateral epitaxy.
  • the structure of a III-nitride transistor can include:
  • the first buffer layer, the first channel layer (i.e. the aforementioned first semiconductor, the same below) 1, the first barrier layer (i.e. the aforementioned second semiconductor, the same below) 2, and the first p-type layer are sequentially stacked on the substrate.
  • the first channel layer 1 and the first barrier layer 2 cooperate to form a first heterogeneous junction, and a first two-dimensional electron gas (2DEG) is formed between the first channel layer 1 and the first barrier layer 2, and the second channel layer 4 and the second barrier layer 5 cooperate to form the first Two heterojunctions, and a second two-dimensional electron gas (2DEG) is formed between the second channel layer 4 and the second barrier layer 5;
  • 2DEG first two-dimensional electron gas
  • the first barrier layer 2 is provided with an anode (i.e. the aforementioned first electrode, the same below) and a cathode (i.e. the aforementioned second electrode, the same below) at intervals, and the cathode and the anode are electrically connected through the first 2DEG,
  • the first p-type layer is also provided with a first gate (that is, gate one in the figure, the same below), the first gate is electrically connected to the anode, and completely covers the first p-type layer,
  • the first grid is in electrical contact with the first p-type layer, and the first p-type layer is electrically isolated from the cathode by the first high-resistance layer;
  • a source and a drain are arranged at intervals on the second barrier layer 5, and the source and the drain are electrically connected through a second 2DEG, and a second gate is arranged on the second p-type layer ( Gate 2 in the figure), the second p-type layer is electrically isolated from the source and drain by a second high resistance layer; and
  • the first heterojunction and the second heterojunction are electrically isolated by the first high-resistance layer and the insertion layer, the first gate is also electrically connected to the source, and the cathode is also electrically connected to the drain. sexual connection.
  • first heterojunction cooperates with the anode, cathode and first gate to form a diode
  • second heterojunction cooperates with the source, drain and second gate to form a transistor.
  • III The surface of the group nitride transistor structure is also covered with a passivation layer.
  • the insertion layer may be any one of a metal layer, a dielectric layer, and a two-dimensional material layer.
  • the metal layer includes a single-layer metal layer or a multi-layer metal layer arranged in layers.
  • the material of the metal layer Any one of Mo, Mg and Al is included, and the thickness of the metal layer is 2nm-10 ⁇ m.
  • the metal Mg layer can be thermally annealed in a nitrogen environment to alloy it with the underlying material.
  • the temperature of the thermal annealing can be 400-800° C., and the time can be 5-120 minutes.
  • the metal Al layer can be thermally annealed in an oxygen environment to make it oxidized, the temperature can be from room temperature to 800°C, and the time is 5 to 120 minutes.
  • the subsequent plasma treatment can be continued on the metal Al layer.
  • the plasma treatment adopts The plasma can be N 2 , N 2 O, NH 3 , NO, etc.
  • the equipment can be ICP, RIE, PECVD, etc., and the ultraviolet ozone treatment can also be continued on the metal Al layer, and the treatment time can be 30min to 300min.
  • the metal of the insertion layer can be used as a back electrode, and a wide range of uses include voltage application and temperature detection. Stacked metals such as (Mg/Mo/Mg, etc.) can also be used to improve the heat dissipation capability of the device.
  • the material of the dielectric layer includes any one of AlN, BN, AlBN, AlPN, BCN, high-resistance AlGaN, and high-resistance GaN, and the thickness of the dielectric layer is 0.5 nm to 1 ⁇ m;
  • the two-dimensional material includes any one of BN, graphene, fluorinated graphene, graphene oxide, and black phosphorus, and the thickness of the two-dimensional material layer is 0.5 nm to 500 nm.
  • the method for fabricating the structure of a III-nitride transistor provided in this embodiment may include the following steps:
  • MOCVD metal organic compound chemical vapor deposition
  • MBE molecular beam epitaxy
  • HVPE hydride vapor phase epitaxy
  • the substrate can be silicon wafer, sapphire, etc.
  • the material of the first/second channel layer can be GaN or GaAs, etc.
  • the material of the first/second barrier layer can be AlGaN or AlGaAs, etc., in the A first two-dimensional electron gas is formed between the first channel layer and the first potential barrier layer, and a second two-dimensional electron gas is formed between the second channel layer and the second potential barrier layer; the first/second potential
  • the conductivity of the barrier layer is poor, for example, the conductivity of AlGaN is 10 ⁇ /m or above
  • the first/second high resistance layer is an unactivated p-type doped layer
  • the material can be Mg-doped GaN, the conductivity of the first/second high-resistance layer is poor, and the material of the first/second buffer layer can be known by those skilled in the art;
  • the formed material structure is as follows As shown in Figure 2b;
  • Reactive ion etching technology is used to remove the second high-resistance layer of the source region and the drain region and the first high-resistance layer of the cathode region and the anode region, and the source region, drain region/cathode region and Part or all of the first/second barrier layer in the anode region, and even part of the first/second channel layer can be etched;
  • Electron beam evaporation or sputtering and other metal deposition techniques are used to make source, drain, cathode and anode correspondingly in the source region, drain region, cathode region and anode region, and perform rapid annealing treatment.
  • the annealing temperature of the annealing treatment is 500-1000°C, the time is 0.1-100min, so that the source, drain, cathode and anode form an ohmic contact with the material in contact with them, and at the same time make the source and drain electrically connected with the second two-dimensional electrons, so
  • the cathode and the anode are gas-electrically connected through the first two-dimensional electrons, and the device structure after the electrode is formed is shown in Figure 2c;
  • the thickness of the source/drain/cathode/anode is 10-1000nm
  • the material of the source/drain/cathode/anode can be Ti/Al/Ni/Au, Ti/Al/Ti/Au, Ti Any one of /Al/Cr/Au, Ti/Al/Pt/Au, Ti/Al/Mo/Au, Ti/Al/Pd/Au; it should be noted that the anode and the cathode pass through the first two Dimensional electronic gas and electrical connections;
  • the thickness of the protective layer is 10-1000nm.
  • the material of the protective layer can be SiO 2 , AlN, Si 3 N 4 Any combination of one or more of the above, but not limited thereto;
  • an etching method such as reactive ion etching or ion beam etching is used to remove part of the protective layer to expose a part of the first high-resistance layer/second high-resistance layer that needs to be activated;
  • Use high-temperature equipment such as rapid annealing furnace or MOCVD to anneal and activate the exposed first high-resistance layer/second high-resistance layer with p-type material, so that the corresponding area of the first high-resistance layer/second high-resistance layer is transformed into the first p-type layer/second p-type layer; wherein, the annealing temperature is 300-1000° C., and the formed device structure is shown in FIG. 2d;
  • the thickness of the second grid and the first grid is 10-1000 nm, and the material can be any one or a combination of two or more of Ti, Al, Ni, Au, Cr, Pt, Mo, Pd, Ni/Au is usually used; the formed device structure is shown in Figure 2e;
  • the thickness of the interconnected metal electrode is 500-3000nm, and the material includes any one or a combination of two or more of Ti, Al, Ni, Au, Cr, Pt, Mo, Pd, Cu; usually Cu or Ti /Al, the resulting device structure is shown in Figure 2g.
  • Comparative Example 1 is a commercial EPC device disclosed in Zhang, H., and R.S.Balog.” Loss analysis during dead time and thermal study of gallium nitride devices.” Applied Power Electronics Conference & Exposition IEEE, 2015. The test result of the device As shown in Figure 5
  • the picture shows the test data of the p-GaN gate transistor made by our research group, and the comparative example 2 is one disclosed in "Hao Ronghui. Research on New Enhanced p-GaN Gate HEMT Power Switching Device [D]. Nanjing University of Science and Technology, 2019."
  • a p-GaN gate transistor, the test results are shown in Figure 6.
  • the structure of a III-nitride transistor structure provided in this embodiment is shown in FIG. 3 .
  • the difference between the III-nitride transistor structure provided in this embodiment and the transistor in Embodiment 1 is:
  • the diode part formed by the junction with the anode, the cathode, and the first gate is different from the position of the transistor formed by the second heterojunction and the source, the drain, and the second gate.
  • the III-nitride compound provided by this embodiment The preparation method of the transistor structure is basically the same as that of Example 1.
  • FIG. 4 The structure of a III-nitride transistor structure provided in this embodiment is shown in FIG. 4 , which is different from the III-nitride transistor in Embodiment 1 in that: the second buffer layer can be replaced by a high-resistance material, and the The preparation method of the III-nitride transistor structure provided in the embodiment is basically the same as that in the embodiment 1.
  • a III-nitride transistor structure includes a first buffer layer, a first channel layer, First barrier layer, first p-type layer and first high resistance layer, passivation layer, second p-type layer and second high resistance layer, second barrier layer, second channel layer, second buffer layer , a second substrate, the first channel layer and the first barrier layer cooperate to form a first heterojunction, and a first two-dimensional electron gas is formed between the first channel layer and the first barrier layer (2DEG), the second channel layer and the second barrier layer cooperate to form a second heterojunction, and a second two-dimensional electron gas is formed between the second channel layer and the second barrier layer ( 2DEG);
  • 2DEG two-dimensional electron gas
  • the second barrier layer is provided with an anode (i.e. the aforementioned first electrode, the same below) and a cathode (i.e. the aforementioned second electrode, the same below) at intervals, and the cathode and the anode are electrically connected through the second 2DEG, so
  • a second gate i.e. gate 2 in the figure, the same below
  • the second grid is in electrical contact with the second p-type layer, and the second p-type layer is electrically isolated from the cathode by the second high-resistance layer;
  • a source and a drain are arranged at intervals on the first barrier layer, and the source and the drain are electrically connected through the first 2DEG, and a first gate is arranged on the first p-type layer (Fig. Shown as gate 1), the first p-type layer is electrically isolated from the source and drain by the first high-resistance layer; and
  • the second gate is also electrically connected to the source, and the cathode is also connected to the drain through interconnection metal.
  • the second heterojunction cooperates with the anode, cathode and second gate to form a diode
  • the first heterojunction cooperates with the source, drain and first gate to form a transistor
  • FIG. 1 The structure of a III-nitride transistor structure provided in this embodiment is shown in FIG.
  • a plurality of P-type layers are arranged at intervals in the first high-resistance layer or the second high-resistance layer in the transistor, and the material of the plurality of P-type layers and the material of the first or second P-type layer in the transistor or diode can be are the same, the volume and spacing of the plurality of P-type layers gradually decrease along the direction away from the first gate or the second gate.
  • the p-type layer is p-GaN, wherein the intervals between multiple p-GaN are passivated by H plasma, and the diffusion of H plasma conforms to the Gaussian distribution:
  • C is the concentration
  • x is the space size
  • Q is the content of H
  • L is the diffusion width
  • the inventors of this case found that if the interval between multiple p-GaNs is gradually reduced away from the first gate or the second gate, concentration gradients can be generated in multiple p-type layers by means of diffusion. , it can be seen from Figure 9 that the concentration distribution of the p-type layer can be adjusted very well by setting multiple p-GaNs at specific intervals, and it can be seen from Figure 10 that making multiple p-GaNs at specific intervals When the intervals are set and the concentration is distributed according to a specified method, the electric field strength of the III-nitride transistor also gradually decreases, but the platform characteristic is retained, so that it can withstand high voltage.
  • a III-nitride transistor structure provided in the embodiment of the present application integrates the diode and the triode in a direction perpendicular to the substrate, so that the wafer area occupied by the III-nitride transistor is smaller, which is beneficial to the miniaturization of the device application; and, the overall structure of the device has the characteristics of direct growth and process compatibility, which effectively reduces the complexity and manufacturing cost of the device; and, a III-nitride transistor structure provided by the embodiment of the present application can effectively reduce the leakage of the device Current, reduce power consumption, thereby improving the reliability and stability of the device.

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Abstract

本申请公开了一种可降低泄露电流的III族氮化物晶体管结构及其制作方法。所述III族氮化物晶体管结构包括：层叠设置的第一异质结和第二异质结，且所述第一异质结与第二异质结经高阻材料和/或插入层电性隔离；与所述第一异质结配合的第一电极、第二电极、第一栅极，所述第一栅极与第一异质结之间设有第三半导体，所述第一栅极还与第一电极电性连接；与所述第二异质结配合的源极、漏极、第二栅极，所述源极、漏极还分别与所述第一栅极、第二电极电性连接，所述第二栅极与第二异质结之间设置有第六半导体上。本申请提供的III族氮化物晶体管结构能够有效低器件反向导通电压，减小器件的面积。

Description

可降低泄露电流的III族氮化物晶体管结构及其制作方法
本申请基于并要求于2021年12月22日递交的申请号为202111577242.3、发明名称为“可降低泄露电流的III族氮化物晶体管结构及其制作方法”的中国专利申请的优先权。
技术领域
本申请涉及一种晶体管结构，特别涉及一种可降低泄露电流的III族氮化物晶体管结构及其制作方法，属于半导体技术领域。
背景技术
III族氮化物(如氮化镓GaN)具有大禁带宽度、高击穿场强、高电子迁移率、高电子饱和漂移速度等出色的材料特性，被认为非常适合下一代电力电子系统的应用。在同步降压或升压转换器等电力电子系统晶体管器件将不可避免地工作在反向导通状态。而对于基于GaN的高电子迁移率晶体管(HEMT)，由于缺少体二极管，反向恢复速度快，但源极至漏极电压降而取决于栅极偏置，这使得其数值较Si基和SiC基的功率器件相比，达到了更高的值并带来功率损耗。因此，提高GaN HEMT的反向传导能力对于进一步降低基于GaN的电力电子系统的功率损耗至关重要。
目前已经有一些方法被报道，例如，在Si上GaN HEMT结构中，利用衬底Si制备肖特基二极管(SBD),HEMT的漏极与SBD的阴极共用，但Si基SBD受材料特性的限制无法发挥出GaN的优势，更会带来可靠性等问题，其中，HEMT和SBD或者横向整流器的交叉结构是有效的，但似乎占用面积变大是不可避免的问题，以及，反向导通所需的源漏电压降取决于栅极偏压，并且数值较大，导致了较高的功耗；横向集成SBD通常会导致泄露电流增加，或者是HEMT正向的导通电阻增加；垂直集成SBD通过泄露电流也不易控制，且目前报道是与衬底的Si肖特基二极管集成，无法发挥GaN材料的优势。
发明内容
本申请的主要目的在于提供一种可降低泄露电流的III族氮化物晶体管结构及其制作方法，以克服现有技术中的不足。
为实现前述发明目的，本申请采用的技术方案包括：
本申请实施例一方面提供了一种可降低泄露电流的III族氮化物晶体管结构，其包括：
层叠设置的第一异质结和第二异质结，且所述第一异质结与第二异质结经高阻材料和/或插入层电性隔离；
与所述第一异质结配合的第一电极、第二电极、第一栅极，所述第一电极与第二电极通过第一异质结内的第一二维电子气电连接，以及，所述第一栅极与第一异质结之间设有第三半导体，所述第三半导体能够将位于其下方的部分所述第一二维电子气耗尽，所述第一栅极还与第一电极电性连接；
与所述第二异质结配合的源极、漏极、第二栅极，所述源极与漏极通过第二异质结内的第二二维电子气电连接，且所述源极、漏极还分别与所述第一栅极、第二电极电性连接，以及，所述第二栅极与第二异质结之间设置有第六半导体上，所述第六半导体能够将位于其下方的部分所述第二二维电子气耗尽。
本申请实施例还提供了一种可降低泄露电流的III族氮化物晶体管结构的制作方法，其包括：
制作沿设定方向层叠设置的第一异质结、高阻材料和/或插入层和第二异质结的步骤，所述第一异质结和第二异质结之间经所述高阻材料和/或插入层电性隔离；
制作与第一异质结配合的第一电极、第二电极、第一栅极和第三半导体，所述第一电极和第二电极通过所述第一异质结内的第一二维电子气电连接，所述第三半导体设置在所述第一栅极与第一异质结之间，所述第一栅极还与第一电极电连接，所述第三半导体能够将位于其下方的部分所述第一二维电子气耗尽；
制作与第二异质结配合的源极、漏极、第二栅极和第六半导体，所述源极、漏极通过所述第二异质结内的第二二维电子气电连接，所述第六半导体设置在所述第二栅极与第二异质结之间，所述第六半导体能够将位于其下方的部分的所述第二二维电子气耗尽；以及
将所述第一栅极与源极电性连接，将所述第二电极与漏极电性连接。
与现有技术相比，本申请的优点包括：
1)本申请实施例提供的一种III族氮化物晶体管结构，将二极管和三极管在垂直于基底的方向上进行集成，使III族氮化物晶体管的占用的晶圆面积更小，有利于器件的小型化应用；
2)本申请实施例提供的一种III族氮化物晶体管结构，器件整体结构具有直接生长和工艺兼容等特点，有效地降低了器件的复杂性和制备成本；
3)本申请实施例提供的一种III族氮化物晶体管结构能够有效降低器件的泄漏电流、降低功耗，从而提高了器件的可靠性和稳定性；
4)本申请实施例提供的一种III族氮化物晶体管结构，工艺兼容性更好，在设计上更为方便。
附图说明
图1a是本申请实施例1中提供的一种可降低泄露电流的III族氮化物晶体管结构的结构示意图；
图1b是本申请实施例1中提供的一种可降低泄露电流的III族氮化物晶体管结构与传统晶体管的TCAD仿真测试结果；
图2a-图2g是本申请实施例1中的一种可降低泄露电流的III族氮化物晶体管结构的制作流程结构示意图；
图3是本申请实施例2中提供的一种可降低泄露电流的III族氮化物晶体管结构的结构示意图；
图4是本申请实施例3中提供的一种可降低泄露电流的III族氮化物晶体管结构的结构示意图；
图5是对比例1中器件的性能测试结果；
图6是对比例2中器件的性能测试结果；
图7是本申请实施例4中提供的一种可降低泄露电流的III族氮化物晶体管结构的结构示意图；
图8是本申请实施例5中提供的一种可降低泄露电流的III族氮化物晶体管结构的结构示意图；
图9是P型层内空穴分布、H原子分布与p-GaN间距之间的对应曲线；
图10是P型层内电场强度与p-GaN间距之间的对应曲线。
具体实施方式
鉴于现有技术中的不足，本案发明人经长期研究和大量实践，得以提出本申请的技术方案。如下将对该技术方案、其实施过程及原理等作进一步的解释说明。
本申请实施例提供了一种可降低泄露电流的III族氮化物晶体管结构，为了提升晶体管结构的传导特性，降低晶体管结构的反向导通压降，本申请实施例提供了将晶体管与二极管并联的器件结构；为了尽可能缩小器件所占用的晶圆面积，本申请实施例将晶体管和二极管进行了垂直堆叠设置，实现垂直集成，避免了在横向方向上增加面积的问题；以及，为了避免泄露电流增加的问题，本申请实施例采用了与HEMT器件结构类似且工艺兼容的混合阳极二极管结构，该二极管有着原位的高阻钝化层(可以理解为高阻材料)，极大的降低了器件的表面漏电；另外，为了发挥GaN器件的优势，本申请实施例采用了与HEMT器件结构类似且工艺兼容的混合阳极二极管结构，该二极管作为横向的整流器件同样以GaN材料和AlGaN/GaN异质结为基本结构。
本申请实施例中的第一异质结和第二异质结经高阻材料和/插入层实现电性隔离，且该插入层还能够减少应力”，本案发明人研究发现，对于材料外延来说垂直集成很难实现，因为需要外延的材料结构厚度足够厚，但厚的外延材料结构会导致样品出现开裂等现象，而在第一异质结和第二异质结之间设置插入层可以有效地缓解样品开裂的问题。
本申请实施例一方面提供了一种可降低泄露电流的III族氮化物晶体管结构，其包括：
层叠设置的第一异质结和第二异质结，且所述第一异质结与第二异质结经高阻材料和/或插入层电性隔离；
与所述第一异质结配合的第一电极、第二电极、第一栅极，所述第一电极与第二电极通过第一异质结内的第一二维电子气电连接，以及，所述第一栅极与第一异质结之间设有第三半导 体，所述第三半导体能够将位于其下方的部分所述第一二维电子气耗尽，所述第一栅极还与第一电极电性连接；
与所述第二异质结配合的源极、漏极、第二栅极，所述源极与漏极通过第二异质结内的第二二维电子气电连接，且所述源极、漏极还分别与所述第一栅极、第二电极电性连接，以及，所述第二栅极与第二异质结之间设置有第六半导体上，所述第六半导体能够将位于其下方的部分所述第二二维电子气耗尽。
在一具体实施方式中，所述III族氮化物晶体管结构包括沿设定方向依次生长形成的第一半导体、第二半导体、高阻材料层或插入层、第四半导体、第五半导体，或者，所述III族氮化物晶体管结构包括沿设定方向依次生长形成的第四半导体、第五半导体、高阻材料层或插入层、第一半导体、第二半导体；或者，所述III族氮化物晶体管结构包括沿设定方向依次生长形成的第一半导体、第二半导体、高阻材料层、插入层、第四半导体、第五半导体，或者，所述III族氮化物晶体管结构包括沿设定方向依次生长形成的第四半导体、第五半导体、高阻材料层、插入层、第一半导体、第二半导体；
其中，所述第一半导体与第二半导体配合形成第一异质结，所述第四半导体与第五半导体配合形成第二异质结。
在一具体实施方式中，所述高阻材料层由一连续的第三半导体层的第一区域转化形成，所述第三半导体分布于所述第三半导体层的第二区域内；
或者，所述第三半导体由一连续的高阻材料层的第二区域转化形成，所述高阻材料分布于所述高阻材料层的第一域内。
在一具体实施方式中，所述第三半导体为p型半导体。
在一具体实施方式中，所述第三半导体的材质包括p型宽禁带半导体。
在一具体实施方式中，所述p型宽禁带半导体包括p型Ⅲ族氮化物。
在一具体实施方式中，所述p型Ⅲ族氮化物包括p型GaN、p型AlGaN、p型InGaN或p型InN等。
在一具体实施方式中，所述p型半导体包括p型多晶硅、p型非晶硅、p型氧化物、p型金刚石或p型半导体聚合物等。
在一具体实施方式中，所述第三半导体包括多个间隔设置的条形p型半导体，该多个条形p型半导体呈阵列分布。
在一具体实施方式中，所述第三半导体的掺杂浓度为10 16～10 20cm -3。
在一具体实施方式中，所述第三半导体的厚度为10nm～500nm。
在一具体实施方式中，所述高阻材料包括高阻GaN、高阻AlGaN、高阻Ga 2O 3、高阻InGaN或高阻InN等。
在一具体实施方式中，所述高阻材料层由一连续的第六半导体层的第三区域转化形成，所述第六半导体分布于所述第六半导体层的第四区域内；
或者，所述第六半导体由一连续的高阻材料层的第四区域转化形成，所述高阻材料分布于所述高阻材料层的第三域内。
在一具体实施方式中，所述第六半导体为p型半导体。
在一具体实施方式中，所述第六半导体的材质包括p型宽禁带半导体。
在一具体实施方式中，所述p型宽禁带半导体包括p型Ⅲ族氮化物。
在一具体实施方式中，所述p型Ⅲ族氮化物包括p型GaN、p型AlGaN、p型InGaN或p型InN等。
在一具体实施方式中，所述p型半导体包括p型多晶硅、p型非晶硅、p型氧化物、p型金刚石或p型半导体聚合物等。
在一具体实施方式中，所述高阻材料包括高阻GaN、高阻AlGaN、高阻Ga 2O 3、高阻InGaN或高阻InN等。
在一具体实施方式中，所述高阻材料层分布在所述第三半导体与第二电极之间，所述第三半导体还经所述高阻材料与第二电极电性隔离；
或者，所述高阻材料层分布在所述第六半导体与源极、漏极之间，所述第六半导体还经所述高阻材料与源极、漏极电性隔离。
在一具体实施方式中，所述插入层包括金属层、介质层、二维材料层中的任意一种。
在一具体实施方式中，所述金属层包括单层金属层或叠层设置的多层金属层，所述金属层的材质包括Mo、Mg、Al中的任意一种，但不限于此。
在一具体实施方式中，所述金属层的厚度为2nm～10μm。
在一具体实施方式中，所述介质层的材质包括AlN、BN、AlBN、AlPN、BCN、高阻AlGaN、高阻GaN中的任意一种，但不限于此。
在一具体实施方式中，所述介质层的厚度为0.5nm～1μm。
在一具体实施方式中，所述二维材料层的材质包括BN、石墨烯、氟化石墨烯、氧化石墨烯、黑磷中的任意一种，但不限于此。
在一具体实施方式中，所述二维材料层的厚度为0.5nm～500nm。
在一具体实施方式中，所述第二异质结上还设置有绝缘介质层，所述源极、漏极设置在所述绝缘介质层上。
在一具体实施方式中，所述绝缘介质层的厚度为1-1000nm。
在一具体实施方式中，所述绝缘介质层的材质包括SiO 2、AlN、Si 3N 4中的任意一种或两种以上的组合，但不限于此。
在一具体实施方式中，所述第六半导体上还设置有二维材料，所述源极和漏极设置在所述二维材料上。
在一具体实施方式中，所述第三半导体上设置有二维材料。
在一具体实施方式中，所述二维材料的层数为1-100层。
在一具体实施方式中，所述二维材料为单一种类的二维材料或二维材料异质结。
在一具体实施方式中，所述二维材料包括石墨烯、MoS 2、WS 2中的任意一种或两种以上的组合，但不限于此。
在一具体实施方式中，所述第一半导体和第二半导体之间和/或第四半导体和第五半导体之间还设置有第七半导体。
在一具体实施方式中，所述第一半导体、第二半导体、第四半导体和第五半导体的材质均选自Ⅲ-Ⅴ族化合物。
在一具体实施方式中，所述第一半导体和第四半导体的材质包括GaN或GaAs，但不限于此。
在一具体实施方式中，所述第二半导体和第五半导体的材质包括AlGaN或AlGaAs，但不 限于此。
在一具体实施方式中，所述第七半导体的材质包括AlN，但不限于此。
在一具体实施方式中，所述第一异质结与第一电极、第二电极配合形成二极管，所述第二异质结与源极、漏极、栅极配合形成晶体管(也可以理解为三极管，下同)，所述第一电极可以阳极，所述第二电极可以是阴极。
在一具体实施方式中，在所述的第三半导体中可以设置较低的p型掺杂浓度和/或较薄的p型材料厚度，削弱其对2DEG通道一的控制，进而导致二极管的导通压降降低，二极管的导通压降降低后，在晶体管反向导通时，二极管会优先导通，即第一异质结内的第一二维电子气形成的第一通道会先导通，故晶体管的反向导通源漏压降降低。
在一具体实施方式中，所述第一电极与源极的电性连接可以是通过芯片上的金属互连，也可以是外部电路金属连接；所述第二电极与漏极的电性连接可以是通过芯片上的金属互连，也可以是外部电路金属连接。
在一具体实施方式中，所述栅极的厚度为10-1000nm，所述栅极的材质可以是Ti、Al、Ni、Au、Cr、Pt、Mo、Pd等中的任意一种或两种以上的组合，例如可以选自如下的组：Ni/Au、Mo/Au、Cr/Au、Pd/Au，但不限于此；所述第一电极、第二电极、源极、漏极的厚度可以是10-1000nm，所述第一电极、第二电极、源极、漏极的材质可以是Au、Cr、Pt、Ag、Ti、Al、TiN中的任意一种或两种以上形成的合金，例如可以选自如下的组：Ti/Al/Ni/Au、Ti/Al/Ti/Au，Ti/Al/Ti/TiN但不限于此。
在一具体实施方式中，所述第一异质结或第二异质结形成在基底上，并且所述第一异质结或第二异质结与基底之间还分布有缓冲层。
需要说明的是，所述的晶体管可以是沿垂直方向叠设在二极管上，或者，所述二极管沿垂直方向叠设在晶体管上，两者在垂直方向上的相对位置可以互换。
本申请实施例还提供了一种可降低泄露电流的III族氮化物晶体管结构的制作方法，其包括：
制作沿设定方向层叠设置的第一异质结、高阻材料和/或插入层和第二异质结的步骤，所述第一异质结和第二异质结之间经所述高阻材料和/或插入层电性隔离；
制作与第一异质结配合的第一电极、第二电极、第一栅极和第三半导体，所述第一电极和第二电极通过所述第一异质结内的第一二维电子气电连接，所述第三半导体设置在所述第一栅极与第一异质结之间，所述第一栅极还与第一电极电连接，所述第三半导体能够将位于其下方的部分所述第一二维电子气耗尽；
制作与第二异质结配合的源极、漏极、第二栅极和第六半导体，所述源极、漏极通过所述第二异质结内的第二二维电子气电连接，所述第六半导体设置在所述第二栅极与第二异质结之间，所述第六半导体能够将位于其下方的部分的所述第二二维电子气耗尽；以及
将所述第一栅极与源极电性连接，将所述第二电极与漏极电性连接。
在一具体实施方式中，所述的制作方法具体包括：
沿设定方向依次生长形成层叠设置的第一半导体、第二半导体、高阻材料层或插入层、第四半导体、第五半导体，或者，沿设定方向依次生长形成层叠设置的第四半导体、第五半导体、高阻材料层或插入层、第一半导体、第二半导体，或者，沿设定方向依次生长形成层叠设置的第一半导体、第二半导体、高阻材料层、插入层、第四半导体、第五半导体，或者，沿设定方向依次生长形成层叠设置的第四半导体、第五半导体、高阻材料层、插入层、第一半导体、第二半导体，
其中，所述第一半导体与第二半导体配合形成第一异质结，所述第四半导体与第五半导体配合形成第二异质结。
在一具体实施方式中，所述的制作方法具体包括：
在所述第二半导体上形成连续的第三半导体层，所述第三半导体层包括第一区域和第二区域，对所述第一区域进行转化处理以形成所述高阻材料层；或者，在所述第二半导体上形成连续的高阻材料层，所述高阻材料层包括第一区域和第二区域，对所述第二区域进行转化处理以形成所述的第三半导体；
在一具体实施方式中，所述的制作方法具体包括：
在所述第五半导体上形成连续的第六半导体层，所述第六半导体层包括第三区域和第四区域，对所述第三区域进行转化处理以形成所述高阻材料层；
或者，在所述第五半导体上形成连续的高阻材料层，所述高阻材料层包括第三区域和第四 区域，对所述第四区域进行转化处理以形成所述的第六半导体。
在一具体实施方式中，用于进行所述转化处理的方法包括H离子注入、H等离子体处理、H掺杂退火，N离子注入、F离子注入、Ar离子注入、Fe离子注入、O等离子体处理、热氧化中的任意一种或多种的组合。
例如，所述第三半导体和第六半导体一般采用p-GaN材料，可以通过选区激活或者NH 3退火、H等离子处理、H离子注入、O等离子体处理、热氧化、二次外延、离子注入等方式进行原位钝化，原位钝化的方法为选区钝化，以削弱其对2DEG的控制，降低二极管的导通压降。
当然，所述第三半导体和第六半导体也可以采用p型多晶硅、p型氧化物等p型材料，这些材料可以通过溅射、LPCVD、PECVD等方式进行沉积，其浓度可以通过沉积条件控制，也可以后续通过离子注入、退火等手段进行调控，进而调控二极管的压降。
需要说明的是，还可以对第一电极第二部分下方的p型半导体(第三半导体)进行图案化处理，再通过NH 3退火、H等离子体处理、H离子注入、O等离子体处理、热氧化等方式进行部分地原位钝化或者干法刻蚀(ICP、RIE、NLD等)或者湿法刻蚀(PEC刻蚀、KOH等)进行部分地去除，调以节其下方沟道电子的浓度，进而调控二极管的压降。
在一具体实施方式中，对于第三半导体，可以通过NH 3退火、H等离子体处理、H离子注入、O等离子体处理、热氧化等方式进行原位钝化，降低泄露电流；对于第六半导体，可以采用后工艺退火激活的方式进行选区激活，只保留第二栅极下方的第六半导体，其余部分处于未被激活状态，即高阻区，以降低泄露电流。
在一具体实施方式中，所述的制作方法还包括：对所述第三半导体进行图案化处理，从而将所述第三半导体加工形成条形阵列结构。
在一具体实施方式中，所述的制作方法还包括：
在所述第二半导体上选区外延生长所述的第三半导体和高阻材料层；
或者，在所述第五半导体上选区外延生长所述的第六半导体和高阻材料层。
在一具体实施方式中，所述的制作方法还包括：在所述高阻材料层上形成插入层，之后在所述插入层上制作第一异质结或第二异质结。
在一具体实施方式中，所述插入层包括金属层、介质层、二维材料层中的任意一种。
在一具体实施方式中，所述金属层包括单层金属层或叠层设置的多层金属层，所述金属层的材质包括Mo、Mg、Al中的任意一种，但不限于此。
在一具体实施方式中，所述金属层的厚度为2nm～10μm。
在一具体实施方式中，所述介质层的材质包括AlN、BN、AlBN、AlPN、BCN、高阻AlGaN、高阻GaN中的任意一种，但不限于此。
在一具体实施方式中，所述介质层的厚度为0.5nm～1μm。
在一具体实施方式中，所述二维材料层的材质包括BN、石墨烯、氟化石墨烯、氧化石墨烯、黑磷中的任意一种，但不限于此。
在一具体实施方式中，所述二维材料层的厚度为0.5nm～500nm。
在一具体实施方式中，所述第三半导体还经所述高阻材料与第二电极电性隔离，或者，所述第六半导体还经所述高阻材料与源极、漏极电性隔离。
在一具体实施方式中，所述第三半导体和第六半导体为p型半导体。
在一具体实施方式中，所述第三半导体和第六半导体的材质包括p型宽禁带半导体。
在一具体实施方式中，所述p型宽禁带半导体包括p型Ⅲ族氮化物。
在一具体实施方式中，所述p型Ⅲ族氮化物包括p型GaN、p型AlGaN、p型InGaN或p型InN。
在一具体实施方式中，所述p型半导体包括p型多晶硅、p型非晶硅、p型氧化物、p型金刚石或p型半导体聚合物等。
在一具体实施方式中，所述第一高阻材料和第二高阻材料包括高阻GaN、高阻AlGaN、高阻Ga 2O 3、高阻InGaN或高阻InN等。
需要说明的是，本申请实施例提供的一种可降低泄露电流的III族氮化物晶体管中的晶体管部分和二极管部分可以是在同一晶圆上制作形成，也可以是分别在不同的晶圆上分别制作形成，之后再通过键合的方式将二极管部分和晶体管部分在垂直方向上进行集成；其中，在垂直方向上的上层器件部分的p型半导体可以先整体激活得到，后续可以采用刻蚀或者钝化的方式进行选择区域保留；当然，p型半导体也可以通过选择区域外延或者横向外延得到。
如下将结合附图以及具体实施案例对该技术方案、其实施过程及原理等作进一步的解释说 明，除非特别说明的之外，本申请实施例所采用的沉积、外延、刻蚀等工艺均可以是本领域技术人员已知的。
实施例1
请参阅图1a，一种III族氮化物晶体管的结构可以包括：
于基底上依次层叠设置的第一缓冲层、第一沟道层(即前述第一半导体，下同)1、第一势垒层(即前述第二半导体，下同)2、第一p型层(即前述第三半导体，下同)3和第一高阻层(即第一高阻材料或第一高阻材料层，下同)、插入层(当然也可以不设置插入层)、第二缓冲层、第二沟道层(即前述第四半导体，下同)4、第二势垒层(即前述第五半导体，下同)5、第二p型层(即前述第六半导体，下同)6和第二高阻层(即第二高阻材料或第二高阻材料层，下同)，所述第一沟道层1和第一势垒层2配合形成第一异质结，且所述第一沟道层1和第一势垒层2之间形成有第一二维电子气(2DEG)，所述第二沟道层4和第二势垒层5配合形成第二异质结，且所述第二沟道层4和第二势垒层5之间形成有第二二维电子气(2DEG)；
所述第一势垒层2上间隔设置有阳极(即前述第一电极，下同)、阴极(即前述第二电极，下同)，所述阴极和阳极之间经第一2DEG电连接，所述第一p型层上还设置有第一栅极(即图示中的栅一，下同)，所述第一栅极与阳极电连接，且完全掩盖所述第一p型层，所述第一栅极与所述第一p型层电性接触，所述第一p型层与阴极之间还经所述第一高阻层电性隔离；
所述的第二势垒层5上间隔设置有源极和漏极，所述源极与漏极之间经第二2DEG电连接，所述第二p型层上设置有第二栅极(图示中为栅二)，所述第二p型层与源极、漏极之间还经第二高阻层电性隔离；以及
所述第一异质结和第二异质结经所述第一高阻层和插入层电性隔离，所述第一栅极还与源极电性连接，所述阴极还与漏极电性连接。
需要说明的是，所述第一异质结和阳极、阴极、第一栅极配合形成二极管，所述第二异质结与源极、漏极和第二栅极配合形成晶体管，所述III族氮化物晶体管的结构的表面还覆设有钝化层。
具体的，所述插入层可以是金属层、介质层、二维材料层中的任意一种，所述金属层包括 单层金属层或叠层设置的多层金属层，所述金属层的材质包括Mo、Mg、Al中的任意一种，，所述金属层的厚度为2nm～10μm。
具体的，对于金属Mg层，可以在氮气环境中对金属Mg层进行热退火处理，使其与下层材料进行合金化，热退火的温度可以是400～800℃，时间可以是5～120min，对于金属Al层可以在氧气环境中进行热退火处理，使其氧化，温度可以是室温～800℃，时间为5～120min，当然，后续可以继续对金属Al层进行等离子体处理，等离子体处理所采用的等离子体可以是N 2、N 2O、NH 3、NO等，设备可以是ICP，RIE，PECVD等，也可继续对金属Al层进行紫外线臭氧处理，处理时间可以是30min～300min，其中，插入层的金属可以作为背电极使用，广泛的用途包括施加电压、温度探测。也可采用叠层金属如(Mg/Mo/Mg等)提高器件散热能力。
具体的，所述介质层的材质包括AlN、BN、AlBN、AlPN、BCN、高阻AlGaN、高阻GaN中的任意一种，所述介质层的厚度为0.5nm～1μm；所述二维材料层的材质包括BN、石墨烯、氟化石墨烯、氧化石墨烯、黑磷中的任意一种，所述二维材料层的厚度为0.5nm～500nm。
请参阅图2a-图2g，本实施例提供的一种III族氮化物晶体管的结构的制作方法可以包括如下步骤：
1)采用金属有机化合物化学气相沉积(MOCVD)或分子束外延(MBE)或氢化物气相外延(HVPE)等外延技术，生长如图2a所示的基底/第一缓冲层/第一沟道层/第一势垒层/第一高阻层/第二缓冲层/第二沟道层/第二势垒层/第二高阻层的材料结构；
其中，所述基底可以是硅片、蓝宝石等，第一/第二沟道层的材质可以是GaN或GaAs等，第一/第二势垒层的材质可以是AlGaN或AlGaAs等，在所述第一沟道层和第一势垒层之间形成有第一二维电子气，第二沟道层和第二势垒层之间形成有第二二维电子气；第一/第二势垒层的导电性较差，如AlGaN的电导率为10Ω/m或10Ω/m以上；所述第一/第二高阻层为未激活的p型掺杂层，材质可以是Mg掺杂的GaN，第一/第二高阻层的导电性差，所述第一/第二缓冲层的材质可以采用本领域技术人员已知的；
2)采用反应离子刻蚀技术除去指定区域的部分第二缓冲层/第二沟道层/第二势垒层/第二高阻层，以暴露出第一高阻层，形成的材料结构如图2b所示；
3)采用反应离子刻蚀技术除去源极区域、漏极区域的第二高阻层以及阴极区域和阳极区域的第一高阻层，也可以除去位于源极区域、漏极区域/阴极区域和阳极区域的部分或全部第一/第二势垒层，甚至可以刻蚀部分第一/第二沟道层；
采用电子束蒸发或溅射等金属沉积技术，在源极区域、漏极区域、阴极区域、阳极区域对应制作源极、漏极、阴极和阳极，并进行快速退火处理，退火处理的退火温度为500-1000℃，时间为0.1-100min，从而使源极、漏极、阴极和阳极与与之接触的材料形成欧姆接触，同时使源极与漏极与第二二维电子气电连接，所述阴极和阳极通过第一二维电子气电连接，制作形成电极后的器件结构如图2c所示；
其中，所述源极/漏极/阴极/阳极的厚度为10-1000nm，源极/漏极/阴极/阳极的材质可以是Ti/Al/Ni/Au、Ti/Al/Ti/Au、Ti/Al/Cr/Au、Ti/Al/Pt/Au、Ti/Al/Mo/Au、Ti/Al/Pd/Au中的任意一种；需要说明的是，所述阳极与阴极通过第一二维电子气电连接；
4)采用PECVD、ALD、LPCVD等薄膜沉积技术在图2c所示的器件结构表面沉积保护层，保护层的厚度10-1000nm，保护层材质可以是包括SiO 2、AlN、Si 3N 4中的任意一种或多种以上的组合，但不限于此；
随后，采用反应离子刻蚀或离子束刻蚀等刻蚀方法，去除部分保护层，以暴露出需要被激活的部分第一高阻层/第二高阻层部分；
采用快速退火炉或者MOCVD等高温设备对暴露出的第一高阻层/第二高阻层进行p型材料的退火激活，使第一高阻层/第二高阻层对应区域转变为第一p型层/第二p型层；其中，退火温度为300～1000℃，形成的器件结构如图2d所示；
5)除去所述保护层，并采用电子束蒸发或溅射等金属沉积技术在第一p型层上制作第一栅极(图示中为栅一)，在第二p型层上制作第二栅极(图示中为栅二)，并使所述第一栅极与阳极电连接，所述第一栅极与第一p型层电性接触并完全掩盖所述第一p型层；
其中，所述第二栅极和第一栅极的厚度为10-1000nm，材质可以是Ti、Al、Ni、Au、Cr、Pt、Mo、Pd中的任意一种或两种以上的组合，通常采用Ni/Au；形成的器件结构如图2e所示；
6)采用PECVD、ALD、LPCVD等薄膜沉积技术，在图2e示出的器件结构表面沉积钝化 层，钝化层的厚度10-1000nm，材质可以是包括SiO 2、AlN、Al 2O 3、Si 3N 4中的任意一种或多种以上的组合，但不限于此；形成的器件结构如图2f所示；
7)采用反应离子刻蚀或离子束刻蚀等刻蚀方法除去与阳极第二部分和源极对应区域的部分钝化层，以暴露出第一栅极和源极；之后采用电子束蒸发或溅射等金属沉积技术沉积互联金属电极，并使所述互联金属电极分别与第一栅极、源极电性连接；
其中，所述互联金属电极的厚度为500-3000nm，材质包括Ti、Al、Ni、Au、Cr、Pt、Mo、Pd、Cu中的任意一种或两种以上的组合；通常选择Cu或者Ti/Al，形成的器件结构如图2g所示。
对比例1
对比例1为Zhang,H.,and R.S.Balog."Loss analysis during dead time and thermal study of gallium nitride devices."Applied Power Electronics Conference&Exposition IEEE,2015.中公开的一种商用EPC器件，该器件的测试结果如图5所示
对比例2
该图为本课题组做的p-GaN栅晶体管测试数据，对比例2为“郝荣晖.新型增强型p-GaN栅HEMT功率开关器件研究[D].南京理工大学,2019.”中公开的一种p-GaN栅晶体管，其测试结果如图6所示。
实施例2
该实施例提供的一种III族氮化物晶体管结构的结构如图3示，该实施例提供的一种III族氮化物晶体管结构与实施例1的晶体管的区别之处在于：由第一异质结与阳极、阴极、第一栅极配合形成的二极管部分与由第二异质结和源极、漏极和第二栅极配合形成的晶体管的位置不同，该实施例提供的III族氮化物晶体管结构的制备方法与实施例1基本相同。
实施例3
该实施例提供的一种III族氮化物晶体管结构的结构如图4所示，其与实施例1的III族氮化物晶体管的区别之处在于：第二缓冲层可以采用高阻材料替代，该实施例提供的III族氮化物晶体管结构的制备方法与实施例1基本相同。
实施例4
该实施例提供的一种III族氮化物晶体管结构的结构如图7所示，一种III族氮化物晶体管结构包括依次层叠设置在第一基底上的第一缓冲层、第一沟道层、第一势垒层、第一p型层和第一高阻层、钝化层、第二p型层和第二高阻层、第二势垒层、第二沟道层、第二缓冲层、第二基底，所述第一沟道层和第一势垒层配合形成第一异质结，且所述第一沟道层和第一势垒层之间形成有第一二维电子气(2DEG)，所述第二沟道层和第二势垒层配合形成第二异质结，且所述第二沟道层和第二势垒层之间形成有第二二维电子气(2DEG)；
所述第二势垒层上间隔设置有阳极(即前述第一电极，下同)、阴极(即前述第二电极，下同)，所述阴极和阳极之间经第二2DEG电连接，所述第二p型层上还设置有第二栅极(即图示中的栅二，下同)，所述第二栅极与阳极电连接，且完全掩盖所述第二p型层，所述第二栅极与所述第二p型层电性接触，所述第二p型层与阴极之间还经所述第二高阻层电性隔离；
所述的第一势垒层上间隔设置有源极和漏极，所述源极与漏极之间经第一2DEG电连接，所述第一p型层上设置有第一栅极(图示中为栅一)，所述第一p型层与源极、漏极之间还经第一高阻层电性隔离；以及
所述第二栅极还与源极、所述阴极还与漏极还经互联金属电性连接。
需要说明的是，所述第二异质结和阳极、阴极、第二栅极配合形成二极管，所述第一异质结与源极、漏极和第一栅极配合形成晶体管。
实施例5
该实施例提供的一种III族氮化物晶体管结构的结构如图8所示，其与实施例1的III族氮化物晶体管的结构基本相同，两者的区别之处在于：位于上层的二极管或晶体管中的第一高阻层或第二高阻层内间隔设置有多个P型层，该多个P型层的材质与其所在的晶体管或二极管中第一或第二P型层的材质可以是相同的，该多个P型层的体积和间距均沿远离第一栅极或第二栅极的方向逐渐减小。
例如，在本实施例中，所述p型层为p-GaN，其中多个p-GaN之间的间隔采用H等离子体钝化处理，H等离子体的扩散是符合高斯分布：
Figure PCTCN2022078927-appb-000001
其中，C是浓度，x是间隔大小，Q是H的含量，L是扩散宽度。
本案发明人研究发现，如果使多个p-GaN之间的间隔沿远离第一栅极或者第二栅极逐渐减小的方案，则可以通过扩散的方式，使得多个p型层产生浓度梯度，由图9可以看出，使多个p-GaN以特定的间距间隔设置，可以非常好的调节p型层的浓度分布，由图10可以看出，使多个p-GaN以特定的间距间隔设置，且使其浓度按照指定方式分布的情况下，III族氮化物晶体管的电场强度也是逐渐下降，但保留平台特性，从而可耐受高压。
本申请实施例提供的一种III族氮化物晶体管结构，将二极管和三极管在垂直于基底的方向上进行集成，使III族氮化物晶体管的占用的晶圆面积更小，有利于器件的小型化应用；并且，器件整体结构具有直接生长和工艺兼容等特点，有效地降低了器件的复杂性和制备成本；以及，本申请实施例提供的一种III族氮化物晶体管结构能够有效降低器件的泄漏电流、降低功耗，从而提高了器件的可靠性和稳定性。

Claims (15)

  1. 一种可降低泄露电流的III族氮化物晶体管结构，其特征在于包括：
    层叠设置的第一异质结和第二异质结，且所述第一异质结与第二异质结经高阻材料和/或插入层电性隔离；
    与所述第一异质结配合的第一电极、第二电极、第一栅极，所述第一电极与第二电极通过第一异质结内的第一二维电子气电连接，以及，所述第一栅极与第一异质结之间设有第三半导体，所述第三半导体能够将位于其下方的部分所述第一二维电子气耗尽，所述第一栅极还与第一电极电性连接；
    与所述第二异质结配合的源极、漏极、第二栅极，所述源极与漏极通过第二异质结内的第二二维电子气电连接，且所述源极、漏极还分别与所述第一栅极、第二电极电性连接，以及，所述第二栅极与第二异质结之间设置有第六半导体上，所述第六半导体能够将位于其下方的部分所述第二二维电子气耗尽。
  2. 根据权利要求1所述的III族氮化物晶体管结构，其特征在于：所述III族氮化物晶体管结构包括沿设定方向依次生长形成的第一半导体、第二半导体、高阻材料层或插入层、第四半导体、第五半导体，
    或者，所述III族氮化物晶体管结构包括沿设定方向依次生长形成的第四半导体、第五半导体、高阻材料层或插入层、第一半导体、第二半导体；
    或者，所述III族氮化物晶体管结构包括沿设定方向依次生长形成的第一半导体、第二半导体、高阻材料层、插入层、第四半导体、第五半导体，
    或者，所述III族氮化物晶体管结构包括沿设定方向依次生长形成的第四半导体、第五半导体、高阻材料层、插入层、第一半导体、第二半导体；
    其中，所述第一半导体与第二半导体配合形成第一异质结，所述第四半导体与第五半导体配合形成第二异质结。
  3. 根据权利要求2所述的III族氮化物晶体管结构，其特征在于：所述高阻材料层由一连续的第三半导体层的第一区域转化形成，所述第三半导体分布于所述第三半导体层的第二区域 内；
    或者，所述第三半导体由一连续的高阻材料层的第二区域转化形成，所述高阻材料分布于所述高阻材料层的第一域内。
  4. 根据权利要求2或3所述的III族氮化物晶体管结构，其特征在于：所述第三半导体为p型半导体；优选的，所述第三半导体的材质包括p型宽禁带半导体；更优选的，所述p型宽禁带半导体包括p型Ⅲ族氮化物；更优选的，所述p型Ⅲ族氮化物包括p型GaN、p型AlGaN、p型InGaN或p型InN；优选的，所述p型半导体包括p型多晶硅、p型非晶硅、p型氧化物、p型金刚石或p型半导体聚合物；更优选的，所述第三半导体包括多个间隔设置的条形p型半导体，该多个条形p型半导体呈阵列分布。
    优选的，所述第三半导体的掺杂浓度为10 16～10 20cm -3；优选的，所述第三半导体的厚度为10nm～500nm；
    优选的，所述高阻材料包括高阻GaN、高阻AlGaN、高阻Ga 2O 3、高阻InGaN或高阻InN。
  5. 根据权利要求2所述的III族氮化物晶体管结构，其特征在于：所述高阻材料层由一连续的第六半导体层的第三区域转化形成，所述第六半导体分布于所述第六半导体层的第四区域内；
    或者，所述第六半导体由一连续的高阻材料层的第四区域转化形成，所述高阻材料分布于所述高阻材料层的第三域内。
  6. 根据权利要求5所述的III族氮化物晶体管结构，其特征在于：所述第六半导体为p型半导体；优选的，所述第六半导体的材质包括p型宽禁带半导体；更优选的，所述p型宽禁带半导体包括p型Ⅲ族氮化物；更优选的，所述p型Ⅲ族氮化物包括p型GaN、p型AlGaN、p型InGaN或p型InN；优选的，所述p型半导体包括p型多晶硅、p型非晶硅、p型氧化物、p型金刚石或p型半导体聚合物；
    优选的，所述高阻材料包括高阻GaN、高阻AlGaN、高阻Ga 2O 3、高阻InGaN或高阻InN。
  7. 根据权利要求2所述的III族氮化物晶体管结构，其特征在于：所述高阻材料层分布在所 述第三半导体与第二电极之间，所述第三半导体还经所述高阻材料与第二电极电性隔离；
    或者，所述高阻材料层分布在所述第六半导体与源极、漏极之间，所述第六半导体还经所述高阻材料与源极、漏极电性隔离；
    和/或，所述插入层包括金属层、介质层、二维材料层中的任意一种；
    优选的，所述金属层包括单层金属层或叠层设置的多层金属层，所述金属层的材质包括Mo、Mg、Al中的任意一种；优选的，所述金属层的厚度为2nm～10μm；
    优选的，所述介质层的材质包括AlN、BN、AlBN、AlPN、BCN、高阻AlGaN、高阻GaN中的任意一种；优选的，所述介质层的厚度为0.5nm～1μm；
    优选的，所述二维材料层的材质包括BN、石墨烯、氟化石墨烯、氧化石墨烯、黑磷中的任意一种；优选的，所述二维材料层的厚度为0.5nm～500nm。
  8. 根据权利要求2所述的III族氮化物晶体管结构，其特征在于：所述第二异质结上还设置有绝缘介质层，所述源极、漏极设置在所述绝缘介质层上；
    优选的，所述绝缘介质层的厚度为1-1000nm；优选的，所述绝缘介质层的材质包括SiO 2、AlN、Si 3N 4中的任意一种或两种以上的组合；
    优选的，所述第六半导体上还设置有二维材料，所述源极和漏极设置在所述二维材料上；
    优选的，所述第三半导体上设置有二维材料；
    优选的，所述二维材料的层数为1-100层；优选的，所述二维材料为单一种类的二维材料或二维材料异质结；优选的，所述二维材料包括石墨烯、MoS 2、WS 2中的任意一种或两种以上的组合。
  9. 根据权利要求2所述的III族氮化物晶体管结构，其特征在于：所述第一半导体和第二半导体之间和/或第四半导体和第五半导体之间还设置有第七半导体；
    优选的，所述第一半导体、第二半导体、第四半导体和第五半导体的材质均选自Ⅲ-Ⅴ族化合物；优选的，所述第一半导体和第四半导体的材质包括GaN或GaAs；优选的，所述第二半导体和第五半导体的材质包括AlGaN或AlGaAs；优选的，所述第七半导体的材质包括AlN。
  10. 一种可降低泄露电流的III族氮化物晶体管结构的制作方法，其特征在于包括：
    制作沿设定方向层叠设置的第一异质结、高阻材料和/或插入层和第二异质结的步骤，所述 第一异质结和第二异质结之间经所述高阻材料和/或插入层电性隔离；
    制作与第一异质结配合的第一电极、第二电极、第一栅极和第三半导体，所述第一电极和第二电极通过所述第一异质结内的第一二维电子气电连接，所述第三半导体设置在所述第一栅极与第一异质结之间，所述第一栅极还与第一电极电连接，所述第三半导体能够将位于其下方的部分所述第一二维电子气耗尽；
    制作与第二异质结配合的源极、漏极、第二栅极和第六半导体，所述源极、漏极通过所述第二异质结内的第二二维电子气电连接，所述第六半导体设置在所述第二栅极与第二异质结之间，所述第六半导体能够将位于其下方的部分的所述第二二维电子气耗尽；以及
    将所述第一栅极与源极电性连接，将所述第二电极与漏极电性连接。
  11. 根据权利要求10所述的制作方法，其特征在于具体包括：
    沿设定方向依次生长形成层叠设置的第一半导体、第二半导体、高阻材料层或插入层、第四半导体、第五半导体，
    或者，沿设定方向依次生长形成层叠设置的第四半导体、第五半导体、高阻材料层或插入层、第一半导体、第二半导体，
    或者，沿设定方向依次生长形成层叠设置的第一半导体、第二半导体、高阻材料层、插入层、第四半导体、第五半导体，
    或者，沿设定方向依次生长形成层叠设置的第四半导体、第五半导体、高阻材料层、插入层、第一半导体、第二半导体，
    其中，所述第一半导体与第二半导体配合形成第一异质结，所述第四半导体与第五半导体配合形成第二异质结。
  12. 根据权利要求11所述的制作方法，其特征在于具体包括：在所述第二半导体上形成连续的第三半导体层，所述第三半导体层包括第一区域和第二区域，对所述第一区域进行转化处理以形成所述高阻材料层；或者，在所述第二半导体上形成连续的高阻材料层，所述高阻材料层包括第一区域和第二区域，对所述第二区域进行转化处理以形成所述的第三半导体；
  13. 根据权利要求11所述的制作方法，其特征在于具体包括：在所述第五半导体上形成连续的第六半导体层，所述第六半导体层包括第三区域和第四区域，对所述第三区域进行转化处 理以形成所述高阻材料层；
    或者，在所述第五半导体上形成连续的高阻材料层，所述高阻材料层包括第三区域和第四区域，对所述第四区域进行转化处理以形成所述的第六半导体。
  14. 根据权利要求12或13所述的制作方法，其特征在于：用于进行所述转化处理的方法包括H离子注入、H等离子体处理、H掺杂退火，N离子注入、F离子注入、Ar离子注入、Fe离子注入、O等离子体处理、热氧化中的任意一种或多种的组合；
    和/或，所述制作方法还包括：对所述第三半导体进行图案化处理，从而将所述第三半导体加工形成条形阵列结构；
    和/或，所述制作方法还包括：
    在所述第二半导体上选区外延生长所述的第三半导体和高阻材料层；
    或者，在所述第五半导体上选区外延生长所述的第六半导体和高阻材料层；
    优选的，所述的制作方法还包括：在所述高阻材料层上形成插入层，之后在所述插入层上制作第一异质结或第二异质结；
    和/或，所述插入层包括金属层、介质层、二维材料层中的任意一种；
    优选的，所述金属层包括单层金属层或叠层设置的多层金属层，所述金属层的材质包括Mo、Mg、Al中的任意一种；优选的，所述金属层的厚度为2nm～10μm；
    优选的，所述介质层的材质包括AlN、BN、AlBN、AlPN、BCN、高阻AlGaN、高阻GaN中的任意一种；优选的，所述介质层的厚度为0.5nm～1μm；
    优选的，所述二维材料层的材质包括BN、石墨烯、氟化石墨烯、氧化石墨烯、黑磷中的任意一种；优选的，所述二维材料层的厚度为0.5nm～500nm。
  15. 根据权利要求11所述的制作方法，其特征在于：所述第三半导体还经所述高阻材料与第二电极电性隔离，或者，所述第六半导体还经所述高阻材料与源极、漏极电性隔离；
    和/或，所述第三半导体和第六半导体为p型半导体；优选的，所述第三半导体和第六半导体的材质包括p型宽禁带半导体；更优选的，所述p型宽禁带半导体包括p型Ⅲ族氮化物；更优选的，所述p型Ⅲ族氮化物包括p型GaN、p型AlGaN、p型InGaN或p型InN；优选的，所述p型半导体包括p型多晶硅、p型非晶硅、p型氧化物、p型金刚石或p型半导体聚合物；
    优选的，所述第一高阻材料和第二高阻材料包括高阻GaN、高阻AlGaN、高阻Ga 2O 3、高阻InGaN或高阻InN。
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