WO2023115265A1 - 铁电存储器及其制造方法 - Google Patents

铁电存储器及其制造方法 Download PDF

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WO2023115265A1
WO2023115265A1 PCT/CN2021/139737 CN2021139737W WO2023115265A1 WO 2023115265 A1 WO2023115265 A1 WO 2023115265A1 CN 2021139737 W CN2021139737 W CN 2021139737W WO 2023115265 A1 WO2023115265 A1 WO 2023115265A1
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ferroelectric
layer
solution
electrode layer
memory
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PCT/CN2021/139737
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English (en)
French (fr)
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谭万良
李宇星
蔡佳林
许俊豪
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华为技术有限公司
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Priority to PCT/CN2021/139737 priority Critical patent/WO2023115265A1/zh
Priority to CN202180043840.4A priority patent/CN117063268A/zh
Publication of WO2023115265A1 publication Critical patent/WO2023115265A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers

Definitions

  • the present disclosure relates to the field of electronics, and more particularly, to ferroelectric memory and methods of manufacturing the same.
  • FeRAM ferroelectric random access memory
  • a common FeRAM includes multiple memory cells, each of which includes at least one metal-ferroelectric layer-metal capacitor.
  • the ferroelectric layer can include a hafnium oxide film, and the metal layers on both sides of it can not only provide the basic basic electrode contact function, but also provide stress through thermal expansion during annealing and crystallization, thereby inducing the hafnium oxide film to produce a ferroelectric crystal phase, This leads to ferroelectric polarization properties.
  • a conventional method for forming a ferroelectric layer is to bombard a ferroelectric material target with plasma in a reaction chamber by physical vapor deposition (PVD) to sputter a ferroelectric layer on the electrode surface.
  • PVD physical vapor deposition
  • the ferroelectric layer prepared by the PVD method generally has a lot of oxygen vacancy defects, a certain concentration of oxygen is mixed into the argon sputtering gas to adjust the concentration of oxygen vacancy defects in the ferroelectric layer, thereby achieving the regulation of the oxygen vacancy defect concentration in the ferroelectric layer.
  • the effect of oxygen vacancy defects is
  • the PVD method itself has an ion bombardment process. On the one hand, it will cause ion bombardment damage to the lower interface between the metal electrode and the ferroelectric layer. On the other hand, it is difficult to control the ion bombardment inside the ferroelectric layer itself during the deposition process. damage. More ion bombardment damage will lead to a higher internal defect concentration of the ferroelectric layer prepared by the PVD method, which in turn leads to poor reliability of the ferroelectric layer prepared by the PVD method.
  • embodiments of the present disclosure aim to provide a method for manufacturing a ferroelectric memory, which is used to improve the reliability of the ferroelectric memory.
  • a method for manufacturing a ferroelectric memory includes: forming a first electrode layer on a substrate and forming a ferroelectric layer on the first electrode layer.
  • the method also includes: placing the ferroelectric layer into an oxidizing solution for removing at least a portion of carbon defects and oxygen vacancy defects in the ferroelectric layer; and forming a second electrode layer on the ferroelectric layer to form the ferroelectric Ferroelectric capacitors for storage cells of memory.
  • the oxidizing solution can quickly react with the carbon defects in the ferrite layer to remove them, and also react with the oxygen vacancies in the ferroelectric layer to Fill the oxygen vacancies.
  • the effect of adjusting the ferroelectric polarization characteristics and reliability of the ferroelectric layer can be achieved.
  • the production efficiency can be significantly improved and the manufacturing cost can be reduced.
  • the method further includes: after forming the second electrode layer, performing a rapid thermal annealing process on the substrate including the first electrode layer, the ferroelectric layer, and the second electrode layer.
  • a rapid thermal annealing process By using rapid thermal annealing, stress can be provided in the first electrode layer, the ferroelectric layer and the second electrode layer in a thermal expansion manner. Stress can induce more ferroelectric crystal phases in the hafnium oxide film, thereby improving the ferroelectric polarization characteristics.
  • the method further includes: before putting the ferroelectric layer into the oxidizing solution: forming a sacrificial electrode layer on the ferroelectric layer; performing a rapid thermal annealing process on the substrate of the sacrificial electrode layer; and removing the sacrificial electrode layer.
  • stress is created by rapid thermal annealing for crystallization before placing the ferroelectric layer in an oxidizing solution, and subsequently removing the sacrificial electrode and placing the ferroelectric layer in an oxidizing solution for reducing defect concentration.
  • this method does not affect the deposition process of the ferroelectric layer itself (because in this implementation, the ferroelectric layer is completed before the formation of the sacrificial electrode), which can effectively control its manufacturing production cost while improving the ferroelectric layer .
  • the ferroelectric layer includes a hafnium oxide layer.
  • Forming the ferroelectric layer on the first electrode layer includes: forming a hafnium oxide layer on the first electrode layer by using atomic layer deposition (atom layer deposition, ALD).
  • ALD atomic layer deposition
  • the hafnium oxide layer includes or is made of a hafnium oxide-based material.
  • Hafnium oxide-based materials refer to ferroelectric materials based on hafnium oxide material systems, such as silicon (Si)-doped hafnium dioxide (HfO 2 ), aluminum (Al)-doped HfO 2 , lanthanum (La)-doped doped HfO 2 , yttrium (Y) doped HfO 2 , gadolinium (Gd) doped HfO 2 , strontium (Sr) doped HfO 2 , etc.; or hafniumzirconiumoxide (HZO) system,
  • hafnium zirconium oxide HZO hafnium zirconium oxide HZO, lanthanum (La) doped HZO, yttrium (Y) doped HZO, strontium (Sr) doped HZO, gadolinium (Gd) doped HZ
  • HZO is HfO 2 -ZrO 2 solid solute. HZO can also be expressed as Hf x Zr (1-x) O 2 , where x can range from 0.1 to 0.9. HZO is a ferroelectric material, and the properties of HZO can be improved by doping it with elements such as La and Y.
  • forming the hafnium oxide layer on the first electrode layer by atomic layer deposition includes: using ozone gas in a reaction chamber to react with the hafnium oxide layer for a first period of time.
  • the hafnium oxide layer can be pretreated to pre-control its defect concentration, so as to improve the reliability of the ferrite memory.
  • the first time period is between 0.1s and 10s. In another possible implementation manner of the first aspect, the first time period is between 0.3s and 5s. In another possible implementation manner of the first aspect, the first time period is between 0.5s and 1s.
  • the etching rate of the ferroelectric layer by the oxidizing solution is not higher than 0.5 nm per minute.
  • the oxidative solution includes H 2 O 2 solution, SCl solution, H 2 SO 4 :H 2 O 2 solution or water-soluble O 3 solution.
  • the mass percentage of H 2 O 2 in the H 2 O 2 solution is between 0.1% and 60%, between 1% and 30%, or between 10%-20%.
  • the mass percentage of H 2 O 2 in the H 2 SO 4 :H 2 O 2 solution is between 0.1% and 60%, and the mass percentage of H 2 SO 4 is between 0.1% and 60%. Between 98%. In other possible implementations, the mass percentage of H 2 O 2 in the H 2 SO 4 :H 2 O 2 solution is between 1% and 30%, and the mass percentage of H 2 SO 4 is between 1% and 70%. . In some other possible implementations, the mass percentage of H 2 O 2 in the H 2 SO 4 :H 2 O 2 solution is between 10% and 20%, and the mass percentage of H 2 SO 4 is between 10% and 40%. .
  • the concentration of O 3 in the water-soluble O 3 solution is between 0.01 mg/L and 10 mg/L. In other possible implementation manners, the concentration of O 3 in the water-soluble O 3 solution is between 0.1 mg/L and 7 mg/L. In some other possible implementation manners, the concentration of O 3 in the water-soluble O 3 solution is between 1 mg/L and 3 mg/L.
  • the SC1 solution is a NH 4 OH:H 2 O 2 :H 2 O solution.
  • the NH 4 OH mass percentage of the SC1 solution is between 0.1% and 30%, and the H 2 O 2 mass percentage is between 0.1% and 60%.
  • the NH 4 OH mass percentage of the SC1 solution is between 1% and 10%, and the H 2 O 2 mass percentage is between 1% and 30%.
  • the NH 4 OH mass percentage of the SC1 solution is between 3% and 5%, and the H 2 O 2 mass percentage is between 5% and 10%.
  • the method further includes: detecting a ferroelectric polarization characteristic of the ferroelectric capacitor; and adjusting the oxidizing solution based on the ferroelectric polarization characteristic.
  • detecting a ferroelectric polarization characteristic of the ferroelectric capacitor for wafers manufactured using the same process, several wafers (as samples) can be selected to be processed in a solution, and the ferroelectric polarization of the ferroelectric capacitor after the processing can be measured. Based on the measurement results of the sample, the parameters of the oxidizing solution, such as concentration and formulation, can be adjusted accordingly. In this way, subsequent wafers can use the tuned oxidizing solution to obtain the desired ferroelectric polarization.
  • the defect handling of ferroelectric capacitors in ferrite memories can be improved in a low-cost and efficient manner, while obtaining ferroelectric memories with high ferroelectric polarization and high cycle times , standardize the manufacturing process and reduce its time cost.
  • a ferroelectric memory made by the method according to the first aspect.
  • an electronic component comprising a circuit board and a ferroelectric memory according to the second aspect, the ferroelectric memory being located on the circuit board.
  • an electronic device including a power supply device and the ferroelectric memory according to the second aspect, the ferroelectric memory being powered by the power supply device.
  • an integrated circuit chip comprising a package and a ferroelectric memory according to the second aspect, the ferroelectric memory being located in the package.
  • Figure 1 shows a block diagram of an electronic device in which some embodiments of the present disclosure may be implemented
  • Figure 2 shows a circuit diagram of a ferroelectric memory in which some embodiments of the present disclosure may be implemented
  • FIG. 3 shows a circuit diagram of a memory cell in a ferroelectric memory in which some embodiments of the present disclosure can be implemented
  • Fig. 4 shows the structural diagram of the ferroelectric capacitor in the conventional ferroelectric memory
  • Figure 5 shows a flowchart of a method according to some embodiments of the present disclosure
  • Fig. 6 shows a schematic diagram of the effect of the method according to some embodiments of the present disclosure
  • Fig. 7 shows a schematic diagram of performance comparison between a ferroelectric memory obtained by a method according to some embodiments of the present disclosure and a conventional ferroelectric memory
  • FIG. 8 shows a schematic diagram of performance comparison between a ferroelectric memory obtained by a method according to other embodiments of the present disclosure and a conventional ferroelectric memory.
  • Ferroelectric memory stores data based on the ferroelectric effect of ferroelectric materials. Due to its ultra-high storage density, low power consumption and high speed, ferroelectric memory is expected to become the main competitor to replace dynamic random access memory (DRAM).
  • a storage unit in a ferroelectric memory includes a ferroelectric capacitor, and the ferroelectric capacitor includes two electrodes, and a ferroelectric material, such as a ferroelectric film layer, disposed between the two electrodes.
  • the dielectric constant of ferroelectric materials can not only be adjusted, but also the difference before and after the polarization state of the ferroelectric film layer is very large, which makes ferroelectric capacitors smaller in size compared with other capacitors , for example, are much smaller than the capacitors used to store charge in DRAM.
  • the ferroelectric layer can be formed using common ferroelectric materials.
  • the central atoms stay in a low-energy state along the electric field, on the contrary, when the electric field reversal is applied to the ferroelectric layer, the central atoms follow the direction of the electric field in the crystal Move and stop in another low energy state.
  • a large number of central atoms move and couple in the crystal unit cell to form ferroelectric domains, and the ferroelectric domains form polarized charges under the action of an electric field.
  • the polarization charge formed by the ferroelectric domain reversal under the electric field is higher, and the polarization charge formed by the ferroelectric domain without reversal under the electric field is lower.
  • the binary stable state of this ferroelectric material makes ferroelectricity can be used as memory.
  • FIG. 1 is a kind of electronic equipment 100 that the embodiment of the present application provides, and this electronic equipment 100 can be terminal equipment, such as mobile phone, tablet computer, smart bracelet, also can be personal computer (personal computer, PC), server, workstation etc. .
  • the electronic device 100 includes a bus 105, and a system on chip (system on chip, SOC) 110 and a read-only memory (read-only memory, ROM) 120 connected to the bus 105.
  • the SOC 110 can be used to process data, such as processing application data, processing image data, and caching temporary data.
  • ROM 120 can be used to save non-volatile data, such as audio files, video files, etc.
  • the ROM 120 can be PROM (programmable read-only memory, programmable read-only memory), EPROM (erasable programmable read-only memory, erasable programmable read-only memory), flash memory (flash memory), etc.
  • the electronic device 100 may further include a communication chip 130 and a power management chip 140 .
  • the communication chip 130 can be used to process the protocol stack, or to amplify and filter the analog radio frequency signal, or to realize the above functions at the same time.
  • the power management chip 140 can be used to supply power to other chips.
  • the SOC 110 may include an application processor (application processor, AP) 111 for processing application programs, a graphics processing unit (graphics processing unit, GPU) 112 for processing image data, and a cache random access memory (RAM) 113 for data.
  • the above-mentioned AP 111, GPU 112 and RAM 113 can be integrated in one die, or respectively integrated in multiple dies, and packaged in a package structure, such as using 2.5D (dimension) , 3D packaging, or other advanced packaging technologies.
  • the above-mentioned AP 111 and GPU 112 are integrated in one die, and the RAM 113 is integrated in another die, and these two dies are packaged in a package structure to obtain a faster inter-die Data transfer rate and higher data transfer bandwidth.
  • FIG. 2 is a schematic structural diagram of a ferroelectric memory 200 provided by an embodiment of the present disclosure.
  • This ferroelectric memory 200 can be RAM 113 as shown in Figure 1, belongs to FeRAM.
  • the ferroelectric memory 200 may also be a RAM disposed outside the SOC 110.
  • the present disclosure does not limit the position of the ferroelectric memory 200 in the device and the positional relationship with the SOC 110.
  • the ferroelectric memory 200 includes a memory array 210 , a decoder 220 , a driver 230 , a timing controller 240 , a buffer 250 and an input/output driver 260 .
  • the storage array 210 includes a plurality of storage units 300 arranged in an array, wherein each storage unit 300 can be used to store 1-bit or multi-bit data.
  • the memory array 210 also includes signal lines such as wordlines (WL) and bitlines (BL). Each memory cell 300 is electrically connected to the corresponding word line WL and bit line BL.
  • One or more of the above-mentioned word line WL and bit line BL are used to select the memory cell 300 to be read and written in the memory array by receiving the control level output by the control circuit, so as to change the pole of the ferroelectric capacitor in the memory cell 300 direction, so as to realize the data read and write operations.
  • the decoder 220 is used to decode the received address to determine the memory unit 300 to be accessed.
  • the driver 230 is used to control the level of the signal line according to the decoding result generated by the decoder 220 , so as to realize the access to the designated storage unit 300 .
  • the buffer 250 is used for caching the read data, for example, first-in-first-out (FIFO) may be used for caching.
  • the timing controller 230 is used for controlling the timing of the register 250 and controlling the driver 230 to drive the signal lines in the memory array 210 .
  • the input/output driver 260 is used to drive transmission signals, such as driving received data signals and driving data signals to be sent, so that data signals can be transmitted over long distances.
  • the memory array 210 , decoder 220 , driver 230 , timing controller 240 , buffer 250 and input/output driver 260 may be integrated into one chip, or may be separately integrated into multiple chips.
  • the ferroelectric memory 200 involved in the present disclosure may be a ferroelectric random access memory (FeRAM), or a ferroelectric field-effect-transistor memory (FeFET).
  • FIG. 3 shows a circuit structure diagram of one of the memory cells 300 of FeRAM.
  • the memory cell 300 includes at least two ferroelectric capacitors C and a transistor Tr.
  • FIG. 3 exemplarily shows Three ferroelectric capacitors (such as ferroelectric capacitor C1 , ferroelectric capacitor C2 and ferroelectric capacitor C3 in FIG.
  • the memory cell 300 also includes a word line (word line, WL), a bit line (bit line, BL) and a plate line (plate line, PL) signal line, and in the memory cell 300, the first transistor Tr end is electrically connected to the bit line BL, the control end of the transistor Tr is electrically connected to the word line WL, the second end of the transistor Tr is electrically connected to the first electrode of the ferroelectric capacitor C, and the second electrode of the ferroelectric capacitor C is electrically connected to the plate line PL electrical connection.
  • word line word line
  • BL bit line
  • plate line plate line
  • one of the drain or the source of the transistor Tr is called the first terminal, the corresponding other terminal is called the second terminal, and the control terminal of the transistor Tr is the gate.
  • the drain and source of the transistor Tr can be determined according to the flow direction of the current. For example, in Figure 3, when the current flows from left to right, the left end is the drain and the right end is the source. On the contrary, when the current flows from right to left , the right end is the drain, and the left end is the source. It can be understood that the transistor Tr here is a transistor device with three terminals.
  • the transistor Tr can be selected from NMOS (N-channel metal oxide semiconductor, N-channel metal oxide semiconductor) tube, or can be selected from PMOS (P -channel metal oxide semiconductor, P channel metal oxide semiconductor) tube.
  • a storage unit 300 shown in FIG. 3 can be used to store multi-bit data, so as to increase the storage capacity of each storage unit.
  • these ferroelectric capacitors C share one transistor Tr, and further, the number of transistors in each storage unit 300 can be reduced to increase storage density.
  • FIG. 4 shows a structural diagram of a ferroelectric capacitor 400 in a conventional ferroelectric memory.
  • the ferroelectric capacitor 400 may be on a substrate, and may include a stacked first electrode 410 , a ferroelectric layer 420 and a second electrode 430 .
  • a wafer may generally include multiple ferroelectric memory dies (eg, each die on the wafer has at least one ferroelectric memory), and each ferroelectric memory may include multiple ferroelectric capacitors 400 .
  • Multiple ferroelectric capacitors 400 may be located on the same substrate, for example, multiple ferroelectric capacitors 400 may be formed on the same substrate.
  • the substrate may also include other circuit devices, which is not limited in the present disclosure. Since this disclosure focuses on the ferroelectric capacitors in the ferroelectric memory, other circuits in the wafer and other components in the ferroelectric memory will not be described here.
  • the ferroelectric capacitor 400 further includes a first isolation passivation layer and a second isolation passivation layer (not shown), and the first isolation passivation layer is formed between the first electrode 410 and the ferroelectric layer 420 In between, a second isolation passivation layer is formed between the second electrode 430 and the ferroelectric layer 420 .
  • a first isolation passivation layer is formed between the first electrode 410 and the ferroelectric layer 420
  • a second isolation passivation layer is formed between the second electrode 430 and the ferroelectric layer 420 .
  • the presence of defects such as carbon defects or oxygen vacancy defects may affect the reliability of FeRAM.
  • a conventional method for forming a ferroelectric layer is to use plasma bombardment of a ferroelectric target with a purity of 99.9% by physical vapor deposition (PVD) in a reaction chamber to sputter a ferroelectric layer on the electrode surface. layer. Since the ferroelectric layer prepared by the PVD method generally has a lot of oxygen vacancy defects, a certain concentration of oxygen is mixed into the argon sputtering gas to adjust the concentration of oxygen vacancy defects in the ferroelectric layer, thereby achieving the regulation of the oxygen vacancy in the ferroelectric layer. The effect of vacancy defects. However, the PVD method itself has an ion bombardment process.
  • Another conventional FeRAM fabrication method involves depositing the ferroelectric layer by atomic layer deposition, and adjusting the oxygen content inside the film by controlling the gas pulse time of the oxygen precursor.
  • the standard ALD single cycle consists of four steps: the metal precursor is introduced into the reaction chamber, the reaction chamber is purged with nitrogen, the oxygen precursor is introduced, and then nitrogen is purged.
  • O3 is used as the oxygen precursor, and the defect content in the ferroelectric layer is tuned by modifying the feeding time of the oxygen precursor.
  • the thickness of a hafnium oxide-based ferroelectric layer grown in a single cycle of ALD is about 0.08 nanometers (nm), which means that it takes 120 cycles to grow a 10nm hafnium oxide-based ferroelectric layer. If the total time for a single cycle needs to be greater than 5 seconds (s), for example, it takes more than 10 minutes to grow a 10 nm hafnium oxide-based ferroelectric layer. In this way, the average number of sheets produced by the ALD method per hour will be less than 6 sheets, which has low production efficiency and extremely high manufacturing costs.
  • the oxidizing solution can quickly react with the carbon defects in the iron oxide layer to remove the carbon defects, and can also interact with the ferroelectric The oxygen vacancies in the layer react to fill the oxygen vacancies.
  • the carbon defect concentration and the oxygen vacancy defect concentration in the ferroelectric layer By adjusting the carbon defect concentration and the oxygen vacancy defect concentration in the ferroelectric layer, the effect of regulating the ferroelectric polarization characteristics and reliability of the ferroelectric layer can be achieved.
  • the production efficiency can be significantly improved and the manufacturing cost can be reduced.
  • the ferroelectric layer can be made of a hafnium oxide-based material.
  • the thickness of hafnium oxide-based ferroelectric capacitors can be reduced to ten nanometers or even sub-ten nanometers. In this way, high-density integration and even three-dimensional integration can be realized, which has great advantages in the construction of ultra-high-density memory chips.
  • the preparation process of the hafnium oxide-based ferroelectric capacitor can have good compatibility with the silicon-based semiconductor process, so that the ferroelectric capacitor can be manufactured by using a mature manufacturing process without increasing the manufacturing cost.
  • crystal phases of ferroelectric layers made of materials such as hafnium oxide include: monoclinic phase (monolithic phase, m-phase), which is a non-ferroelectric crystal phase; tetragonal phase (tetragonal phase) , t-phase), which is also a non-ferroelectric crystal phase; and an orthorhombic phase (o-phase), also called an orthorhombic phase, is generally considered to be a ferroelectric crystal phase.
  • m-phase monoclinic phase
  • tetragonal phase tetragonal phase
  • t-phase which is also a non-ferroelectric crystal phase
  • an orthorhombic phase o-phase
  • the positive and negative charge centers are asymmetrical to generate electric dipoles.
  • hafnium oxide-based material involved in the ferroelectric layer of the present disclosure refers to a ferroelectric material based on a hafnium oxide material system, such as silicon (Si)-doped hafnium dioxide (HfO 2 ), aluminum (Al)-doped HfO 2 doped with lanthanum (La), HfO 2 doped with yttrium (Y), HfO 2 doped with gadolinium (Gd), HfO 2 doped with strontium (Sr), etc.; or hafnium Zirconium oxide (hafniumzirconiumoxide, HZO) system, for example, can be hafnium zirconium oxide HZO, lanthanum (La) doped HZO, yttrium (Y) doped HZO, strontium (Sr) doped HZO, gadolinium (Gd) doped Doped HZO, gadolinium-lanthanum (Gd/La) co-do
  • the materials of the first electrode layer and the second electrode layer on both sides of the ferroelectric layer can be selected from metals, for example, the following metals can be selected, but are not limited to these metal materials.
  • metals for example, you can choose titanium nitride (TiN), tantalum nitride (TaN), zirconium nitride (ZrN), hafnium nitride (HfN), tungsten nitride (WN), titanium silicon nitride (TiSiN), titanium nitrogen carbon titanium (TiCN), tungsten (W), ruthenium (Ru), molybdenum (Mo), iridium (Ir), nickel (Ni), platinum (Pt), ruthenium oxide (RuO), iridium oxide (IrO), indium tin oxide ( ITO) and so on.
  • the materials of the first electrode layer and the second electrode layer may be the same or different.
  • the thickness of the first electrode layer and the second electrode layer along the stacking direction may be, but not limited to, 2.5 nm to 100 nm.
  • the thickness of the first electrode layer and the thickness of the second electrode layer may be equal or unequal.
  • TiN can be selected to make the first electrode layer and the second electrode, and HZO can be used to make the ferroelectric layer. Because the tensile stress provided by the HZO layer is conducive to the formation of a ferroelectric phase, and the TiN material is compatible with the semiconductor CMOS process.
  • the thickness of the ferroelectric layer along the stacking direction may be, but not limited to, 1 nm to 100 nm.
  • FIG. 5 shows a flowchart of a method 500 according to some embodiments of the present disclosure. It can be understood that the various aspects described above with respect to the ferroelectric memory can be selectively applied to the method 500 , and will not be repeated here.
  • the manufacturing process of the ferroelectric memory may include many steps. However, this disclosure focuses on the manufacturing process of the ferroelectric capacitor in the ferroelectric memory, so the manufacturing process of components other than the ferroelectric capacitor of the ferroelectric memory will not be repeated here.
  • a first electrode layer is formed on a substrate.
  • a ferroelectric layer is formed on the first electrode layer.
  • the ferroelectric layer may be a hafnium oxide layer.
  • a ferroelectric layer may be formed on the first electrode layer by ALD.
  • ALD was used to deposit the HZO layer in the reaction chamber with O 3 gas flowing for 5 s.
  • a first isolation passivation layer may be formed on the first electrode layer first, and then a ferroelectric layer may be formed on the first isolation passivation layer. This disclosure is not limited in this regard.
  • the ferroelectric layer can be placed into an oxidative solution for removing at least a portion of the carbon defects and the oxygen vacancy defects in the ferroelectric layer.
  • the oxidizing solution is inert or weakly corrosive to the ferrite layer, or has an etching rate of not higher than 0.5 nm per minute for the ferroelectric layer.
  • the oxidizing solution can react with at least some of the carbon defects and oxygen vacancy defects in the ferrite layer to remove at least some of the carbon defects and oxygen vacancy defects.
  • the oxidizing solution includes a H 2 O 2 solution, a SCl solution, a H 2 SO 4 :H 2 O 2 solution, or an aqueous O 3 solution.
  • the mass percentage of H 2 O 2 in the H 2 O 2 solution is between 0.1% and 60%, between 1% and 30%, or between 10%-20%. In some embodiments, the mass percentage of H 2 O 2 in the H 2 SO 4 :H 2 O 2 solution is between 0.1% and 60%, and the mass percentage of H 2 SO 4 is between 0.1% and 98%. In other embodiments, the mass percentage of H 2 O 2 in the H 2 SO 4 :H 2 O 2 solution is between 1% and 30%, and the mass percentage of H 2 SO 4 is between 1% and 70%. In yet other embodiments, the mass percentage of H 2 O 2 in the H 2 SO 4 :H 2 O 2 solution is between 10% and 20%, and the mass percentage of H 2 SO 4 is between 10% and 40%.
  • the concentration of O 3 in the aqueous O 3 solution is between 0.01 mg/L and 10 mg/L. In other embodiments, the concentration of O 3 in the water-soluble O 3 solution is between 0.1 mg/L and 7 mg/L. In yet other embodiments, the concentration of O 3 in the aqueous O 3 solution is between 1 mg/L and 3 mg/L.
  • the SC1 solution is a NH 4 OH:H 2 O 2 :H 2 O solution. In some embodiments, the mass percent of NH 4 OH of the SC1 solution is between 0.1% and 30%, and the mass percent of H 2 O 2 is between 0.1% and 60%.
  • the mass percentage of NH 4 OH of the SC1 solution is between 1% and 10%, and the mass percentage of H 2 O 2 is between 1% and 30%. In still other embodiments, the NH 4 OH mass percentage of the SC1 solution is between 3% and 5%, and the H 2 O 2 mass percentage is between 5% and 10%.
  • a second electrode layer is formed on the ferroelectric layer to form a ferroelectric capacitor of a memory cell of the ferroelectric memory.
  • the second isolation passivation layer may be formed on the ferroelectric layer before forming the second electrode layer, and then the second electrode layer may be formed on the second isolation passivation layer.
  • a rapid thermal annealing process may be performed on the substrate including the first electrode layer, the ferroelectric layer and the second electrode layer. By performing rapid thermal annealing, stress is provided by thermal expansion, which induces a ferroelectric crystal phase in the ferrite layer, resulting in ferroelectric polarization.
  • Fig. 6 shows a schematic diagram of the effect of the method 500 according to some embodiments of the present disclosure.
  • reference numeral 620 indicates the distribution of carbon defects and oxygen vacancy defects in the iron oxide layer before the iron oxide layer is put into the above-mentioned oxidizing solution, wherein the black solid circle represents the carbon defect, and the hollow dotted line Circles indicate oxygen vacancy defects.
  • Reference numeral 640 denotes a schematic distribution of carbon defects and oxygen vacancy defects after being treated with the above-mentioned oxidative solution. It can be seen that both carbon defects and oxygen vacancy defects in the ferrite layer are significantly reduced after the treatment with the oxidizing solution.
  • the concentration of carbon defects and oxygen vacancy defects in the ferrite layer can be controlled by adjusting the oxidizing solution.
  • the oxidizing solution For example, for wafers manufactured using the same process, several wafers (as samples) can be selected to be processed in a solution, and the ferroelectric polarization of the ferroelectric capacitor after the processing can be measured. Based on the measurement results of the samples, the parameters of the oxidizing solution, such as the concentration and formulation of the oxidizing solution, or the time the wafer is placed in the oxidizing solution, can be adjusted accordingly. In this way, subsequent wafers can use the tuned oxidizing solution to obtain the desired ferroelectric polarization.
  • FIG. 7 shows a schematic diagram of performance comparison between a ferroelectric memory obtained by the method 500 and a conventional ferroelectric memory according to some embodiments of the present disclosure.
  • Reference numeral 710 denotes the ferroelectric polarization of the ferrite layer obtained by applying ALD with 0.5s O pulses in each cycle
  • reference numeral 720 denotes the intensity of ferroelectric polarization obtained by applying ALD with 5s O pulses in each cycle.
  • the ferroelectric polarization of the ferrite layer, reference numeral 730 represents the ferroelectric polarization of the ferrite layer obtained by applying 0.5s O 3 pulse ALD in each cycle after being treated with the oxidizing solution.
  • ferroelectric polarization indicated by reference numeral 730 is significantly better than that indicated by reference numeral 710 and is substantially equivalent to that indicated by reference numeral 720 . Therefore, by using the method according to the present disclosure, for example as shown in FIG. 5 , the production efficiency of the ferroelectric memory can be significantly improved. In addition, since method 500 does not involve sputtering, the reliability of ferroelectric memory can also be significantly improved compared to ferroelectric memory formed by using a PVD sputtering method.
  • a sacrificial electrode layer may be formed on the ferroelectric layer formed by, for example, ALD. Subsequently, a rapid thermal annealing process is performed on the substrate including the first electrode layer, the ferroelectric layer, and the sacrificial electrode layer, and thereafter, the sacrificial electrode layer is removed to continue the method 500 from 506 .
  • FIG. 8 is a schematic diagram showing a performance comparison between a ferroelectric memory obtained by the method of this embodiment and a conventional ferroelectric memory.
  • the polarization characteristics of the ferroelectric layer are strong, for example, it can reach more than 10 ⁇ C/cm 2 , as shown by reference numeral 810, but the cycle life is relatively low. For example below 1E8, as indicated by reference numeral 820 .
  • the polarization characteristics of the ferroelectric layer are weak, for example, below 10 ⁇ C/cm 2 , as shown by reference numeral 830, but the cycle life can be higher, for example, it can reach more than 1E8, as shown in the attached Figure number 840 shown.
  • the HZO film when the HZO film is deposited by ALD, for example, by adjusting the pulse time of O3 , it can be controlled to have an appropriate amount of defects, combined with the stress provided by the sacrificial electrode during thermal annealing, it can assist HZO crystallization to obtain more ferroelectricity crystal phase, to enhance its ferroelectric polarization characteristics, for example, it can reach more than 10 ⁇ C/cm 2 , as indicated by reference numeral 850 .
  • the sacrificial electrode is etched away and the ferroelectric layer is treated with an oxidizing solution such as H 2 O 2 solution to reduce the ferroelectric layer.
  • the concentration of defects in the defect can increase its cycle life, for example, it can reach more than 1E8, as indicated by reference numeral 860 .
  • the defect concentration in the ferroelectric layer during crystallization and the defect concentration in the ferroelectric layer after crystallization are separately controlled, which can make the ferroelectric memory have strong ferroelectric polarization characteristics and relatively high High cycle erase life.
  • the production cost of the ferroelectric layer can be effectively controlled while improving the ferroelectric layer.

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Abstract

本公开涉及一种用于制造铁电存储器的方法。该方法包括将铁氧层放入弱腐蚀性的氧化性溶液中，氧化性溶液可以与铁氧层中的碳缺陷快速反应以去除碳缺陷，并且还可以与铁电层中的氧空位发生反应，以填充氧空位。通过调控铁电层中的碳缺陷浓度与氧空位缺陷浓度，可以达到调控铁电层的铁电极化特性与可靠性的效果。此外，在可以将多个晶圆一同放入氧化性溶液中同时进行处理的情形下，可以显著提高生产效率并且降低制造成本。

Description

铁电存储器及其制造方法 技术领域
本公开涉及电子领域，更具体而言涉及铁电存储器及其制造方法。
背景技术
人们的日常生活已经离不开各类电子设备，人们每天与各类电子设备互动的次数可达上千次。传输、处理和存储这些互动中产生的海量数据是信息技术核心。因此，需要各种各样的存储器来将这些海量数据进行存储。
一种常见存储器是铁电随机存取存储器(ferroelectric randon access memory,FeRAM)。FeRAM能在非常低的电能需求下快速地存储，它有望在消费者的小型设备中得到广泛地应用，比如个人数字助理、手机、功率表、智能卡以及安全系统。一种常见的FeRAM包括多个存储单元，每个存储单元包括至少一个金属-铁电层-金属电容器。铁电层可以包括氧化铪薄膜，并且其两侧的金属层除了提供基本的基础电极接触功能，还可以在退火结晶过程中通过热膨胀来提供应力，从而诱导氧化铪薄膜产生出铁电晶相，进而产生铁电极化特性。
氧化铪薄膜内部存在一些碳杂质缺陷和氧空位缺陷。一方面，FeRAM的铁电极化特性的强弱取决其内部铁电晶相含量的多少，而其退火结晶过程受到其内部杂质含量的影响。另一方面，FeRAM的一大关键特性是可靠性，具体包括漏电电流、击穿特性、觉醒效应、反复擦写寿命、数据保持时间等。缺陷的存在可能影响FeRAM的可靠性。一种形成铁电层的常规方法是在反应室内通过物理气相沉积(physical vapor deposition,PVD)方法使用等离子体轰击铁电材料靶材，以在电极表面溅射得到一层铁电层。由于PVD方法制备的铁电层一般而言氧空位缺陷很多，所以在氩气溅射气体中混合通入一定浓度的氧气来调整铁电层中氧空位缺陷浓度，进而达到调控铁电层内的氧空位缺陷的效果。然而，PVD方法本身存在离子轰击过程，一方面会对金属电极-铁电层之间的下界面造成离子轰击损伤，另一方面在沉积过程中也很难控制铁电层自身内部受到的离子轰击损伤。离子轰击损伤较多会导致PVD方法制备的铁电层的内部缺陷浓度较高，进而导致PVD方法制备的铁电层的可靠性较差。
发明内容
鉴于上述问题，本公开的实施例旨在提供一种铁电存储器的制造方法，用于提高铁电存储器的可靠性。
根据本公开的第一方面，提供一种用于制造铁电存储器的方法。该方法包括：在衬底上形成第一电极层以及在第一电极层上形成铁电层。该方法还包括：将铁电层放入用于去除铁电层中的碳缺陷和氧空位缺陷中的至少一部分的氧化性溶液；以及在铁电层上形成第二电极层，以形成铁电存储器的存储单元的铁电电容器。通过将铁氧层放入弱腐蚀性的氧化性溶液中，氧化性溶液可以与铁氧层中的碳缺陷快速反应以去除碳缺陷，并且还可以与铁电层中的氧空位发生反应，以填充氧空位。通过在不使用PVD溅射的情形下调控铁电层中的碳缺陷浓度与氧空位缺陷浓度，可以达到调控铁电层的铁电极化特性与可靠性的效果。此外，在可以将多个晶圆一同放入氧化性溶液中同时进行处理的情形下，可以显著提高生产效率并且降低制造成本。
在第一方面的一种可能实现方式中，该方法还包括：在形成第二电极层之后，对包括第一电极层、铁电层和第二电极层的衬底执行快速热退火工艺。通过使用快速热退火，可以以热膨胀的方式在第一电极层、铁电层和第二电极层中提供应力。应力可以诱导氧化铪薄膜产生出更多的铁电晶相，进而提升铁电极化特性。
在第一方面的一种可能实现方式中，该方法还包括：在将铁电层放入氧化性溶液之前：在铁电层上形成牺牲电极层；对包括第一电极层、铁电层和牺牲电极层的衬底执行快速热退火工艺；以及去除牺牲电极层。一方面，在将铁电层放入氧化溶液之前通过快速热退火来形成应力以用于结晶，并且随后去除牺牲电极并且将铁电层置入氧化性溶液以用于降低缺陷浓度。这可以对结晶时铁电层中的缺陷浓度、以及结晶后铁电层中的缺陷浓度实现了分别控制，从而使得铁电存储器具有较强的铁电极化特性与较高的循环擦写寿命。另一方面，该方法不影响铁电层自身的沉积过程(因为在此实现方式中，铁电层在形成牺牲电极之前已完成)，可以在提升铁电层的同时，有效控制其制造生产成本。
在第一方面的一种可能实现方式中，铁电层包括氧化铪层。在第一电极层上形成铁电层包括：使用原子层沉积(atom layer deposition,ALD)在第一电极层上形成氧化铪层。通过使用ALD沉积氧化铪层，可以有效避免常规PVD溅射方式对氧化铪层造成的内部损伤，并且提高铁电存储器的可靠性。
在第一方面的一种可能实现方式中，氧化铪层包括氧化铪基材料或由其制成。氧化铪基材料是指基于氧化铪材料体系的铁电材料，比如，可以是硅(Si)掺杂的二氧化铪(HfO 2)、铝(Al)掺杂的HfO 2、镧(La)掺杂的HfO 2、钇(Y)掺杂的HfO 2、钆(Gd)掺杂的HfO 2、锶(Sr)掺杂的HfO 2等；或者也可以是铪锆氧(hafniumzirconiumoxide，HZO)体系，比如，可以是铪锆氧HZO，镧(La)掺杂的HZO、钇(Y)掺杂的HZO、锶(Sr)掺杂的HZO、钆(Gd)掺杂的HZO、钆镧(Gd/La)共掺杂的HZO、钇镧(Y/La)共掺杂的HZO等。HZO是HfO 2-ZrO 2固溶质。HZO也可以表示为Hf xZr (1-x)O 2，其中x范围可以为0.1到0.9。HZO是铁电材料，对其使用La、Y等元素掺杂之后可以改善HZO的特性。
在第一方面的一种可能实现方式中，使用原子层沉积在第一电极层上形成氧化铪层包括：在反应室内使用臭氧气体与氧化铪层反应达第一时间段。通过使得臭氧气体与氧化铪层反应达第一时间段，可以预处理氧化铪层以将其缺陷浓度预控制，以提高铁氧存储器的可靠性。
在第一方面的一种可能实现方式中，第一时间段位于0.1s和10s之间。在第一方面的另一种可能实现方式中，第一时间段位于0.3s和5s之间。在第一方面的另一种可能实现方式中，第一时间段位于0.5s和1s之间。
在第一方面的一种可能实现方式中，氧化性溶液对于铁电层的蚀刻速率不高于每分钟0.5nm。通过使用对于铁电层为惰性的氧化性溶液，可以在降低缺陷浓度的同时对铁电层本身不造成实质性影响。可以以此为前提，选择合适的氧化性溶液。
在第一方面的一种可能实现方式中，氧化性溶液包括H 2O 2溶液、SC1溶液、H 2SO 4:H 2O 2溶液或水溶O 3溶液。
在第一方面的一种可能实现方式中，H 2O 2溶液中H 2O 2的质量百分比位于0.1％和60％之间、1％和30％之间或10％-20％之间。
在第一方面的一种可能实现方式中，H 2SO 4:H 2O 2溶液中的H 2O 2质量百分比位于0.1％和60％之间，H 2SO 4的质量百分比位于0.1％和98％之间。在另一些可能实现方式中，H 2SO 4:H 2O 2溶液中的H 2O 2质量百分比位于1％和30％之间，H 2SO 4的质量百分比位于1％和70％之 间。在又一些可能实现方式中，H 2SO 4:H 2O 2溶液中的H 2O 2质量百分比位于10％和20％之间，H 2SO 4的质量百分比位于10％和40％之间。
在第一方面的一种可能实现方式中，水溶O 3溶液中的O 3的浓度位于0.01mg/L和10mg/L之间。在另一些可能实现方式中，水溶O 3溶液中的O 3的浓度位于0.1mg/L和7mg/L之间。在又一些可能实现方式中，水溶O 3溶液中的O 3的浓度位于1mg/L和3mg/L之间。
在第一方面的一种可能实现方式中，SC1溶液为NH 4OH:H 2O 2:H 2O溶液。在一些可能实现方式中，SC1溶液的NH 4OH质量百分比位于0.1％至30％之间，并且H 2O 2质量百分比位于0.1％至60％之间。在另一些可能实现方式中，SC1溶液的NH 4OH质量百分比位于1％至10％之间，并且H 2O 2质量百分比位于1％至30％之间。在又一些可能实现方式中，SC1溶液的NH 4OH质量百分比位于3％至5％之间，并且H 2O 2质量百分比位于5％至10％之间。
在第一方面的一种可能实现方式中，该方法还包括：检测铁电电容器的铁电极化特性；以及基于铁电极化特性，对氧化性溶液进行调整。在一些可能实现方式中，对于使用相同工艺制造的晶圆，可以选择将若干晶圆(作为样本)放入溶液进行处理，并且测量经该处理之后的铁电电容器的铁电极化强度。基于样本的测量结果，可以相应调整氧化性溶液的参数，例如浓度和配方等。这样，后续晶圆可以使用经调整的氧化性溶液以获得期望的铁电极化强度。通过使用样本测量并且基于测量结果调整配方，可以以低成本并且高效的方式提高铁氧存储器中的铁电电容器的缺陷处理，在获得高铁电极化强度和高循环擦写次数的铁电存储器的同时，标准化制造工艺并且降低其时间成本。
在本公开的第二方面中，提供一种铁电存储器，其由根据第一方面的方法制成。
在本公开的第三方面中，提供一种电子组件，包括电路板和根据第二方面的铁电存储器，该铁电存储器位于电路板上。
在本公开的第四方面中，提供一种电子设备，包括供电装置和根据第二方面的铁电存储器，该铁电存储器由供电装置供电。
在本公开的第五方面中，提供一种集成电路芯片，包括封装件和根据第二方面的铁电存储器，该铁电存储器位于封装件中。
应当理解，发明内容部分中所描述的内容并非旨在限定本公开的实施例的关键或重要特征，亦非用于限制本公开的范围。本公开的其它特征将通过以下的描述变得容易理解。
附图说明
结合附图并参考以下详细说明，本公开各实施例的上述和其他特征、优点及方面将变得更加明显。在附图中，相同或相似的附图标记表示相同或相似的元素，其中：
图1示出了本公开的一些实施例可以实施于其中的电子设备的框图；
图2示出了本公开的一些实施例可以实施于其中的铁电存储器的电路图；
图3示出了本公开的一些实施例可以实施于其中的铁电存储器中的一个存储单元的电路图；
图4示出了常规铁电存储器中的铁电电容器的结构图；
图5示出了根据本公开的一些实施例的方法的流程图；
图6示出了根据本公开的一些实施例的方法的效果示意图；
图7示出了根据本公开的一些实施例的方法所得的铁电存储器与常规铁电存储器的性能比对示意图；以及
图8示出了根据本公开的另一些实施例的方法所得的铁电存储器与常规铁电存储器的性能比对示意图。
具体实施方式
下面将参照附图更详细地描述本公开的实施例。虽然附图中显示了本公开的某些实施例，然而应当理解的是，本公开可以通过各种形式来实现，而且不应该被解释为限于这里阐述的实施例，相反提供这些实施例是为了更加透彻和完整地理解本公开。应当理解的是，本公开的附图及实施例仅用于示例性作用，并非用于限制本公开的保护范围。
在本公开的实施例的描述中，术语“包括”及其类似用语应当理解为开放性包含，即“包括但不限于”。术语“基于”应当理解为“至少部分地基于”。术语“一个实施例”或“该实施例”应当理解为“实施例”。术语“第一”、“第二”等等可以指代不同的或相同的对象。术语“和/或”表示由其关联的两项的至少一项。例如“A和/或B”表示A、B、或者A和B。下文还可能包括其他明确的和隐含的定义。
应理解，本申请实施例提供的技术方案，在以下具体实施例的介绍中，某些重复之处可能不再赘述，但应视为这些具体实施例之间已有相互引用，可以相互结合。
铁电存储器是基于铁电材料的铁电效应来存储数据。铁电存储器因其超高的存储密度、低功耗和高速度等优势，有望成为替代动态随机存取存储器(dynamic random access memory，DRAM)的主要竞争者。铁电存储器中的存储单元包含铁电电容，铁电电容包括两个电极，以及设置于两个电极之间的铁电材料，例如铁电膜层。由于铁电材料的非线性特性，铁电材料的介电常数不仅可以调节，而且在铁电膜层极化状态翻转前后的差值非常大，这使得铁电电容与其他电容相比体积较小，比如，比DRAM中的用于存储电荷的电容体积小很多。
在铁电存储器中，铁电层可以采用常见的铁电材料形成。当一个电场被施加到存储单元的铁电层时，中心原子顺着电场停在低能量状态，反之，当电场反转被施加到该铁电层时，中心原子顺着电场的方向在晶体里移动并停在另一低能量状态。大量中心原子在晶体单胞中移动耦合形成铁电畴(ferroelectric domains)，铁电畴在电场作用下形成极化电荷。铁电畴在电场下反转所形成的极化电荷较高，铁电畴在电场下无反转所形成的极化电荷较低，这种铁电材料的二元稳定状态使得铁电可以作为存储器。
本申请实施例提供一种包含铁电存储器的电子设备。图1为本申请实施例提供的一种电子设备100，该电子设备100可以是终端设备，例如手机，平板电脑，智能手环，也可以是个人电脑(personal computer，PC)、服务器、工作站等。电子设备100包括总线105，以及与总线105连接的片上系统(system on chip，SOC)110和只读存储器(read-only memory，ROM)120。SOC 110可以用于处理数据，例如处理应用程序的数据，处理图像数据，以及缓存临时数据。ROM 120可以用于保存非易失性数据，例如音频文件、视频文件等。ROM 120可以为PROM(programmable read-only memory，可编程序只读存储器)，EPROM(erasable programmable read-only memory，可擦除可编程只读存储器)，闪存(flash memory)等。
此外，电子设备100还可以包括通信芯片130和电源管理芯片140。通信芯片130可以用于协议栈的处理，或对模拟射频信号进行放大、滤波等处理，或同时实现上述功能。电源管理芯片140可以用于对其他芯片进行供电。
在一种实施方式中，SOC 110可以包括用于处理应用程序的应用处理器(application processor，AP)111，用于处理图像数据的图像处理单元(graphics processing unit，GPU)112， 以及用于缓存数据的随机存取存储器(random access memory，RAM)113。上述AP 111、GPU 112和RAM 113可以被集成于一个裸片(die)中，或者分别集成于多个裸片(die)中，并被封装在一个封装结构中，例如采用2.5D(dimension)，3D封装，或其他的先进封装技术。在一种实施方式中，上述AP 111和GPU 112被集成于一个die中，RAM 113被集成于另一个die中，这两个die被封装在一个封装结构中，以此获得更快的die间数据传输速率和更高的数据传输带宽。
图2为本公开实施例提供的一种铁电存储器200的结构示意图。该铁电存储器200可以是如图1所示的RAM 113，属于FeRAM。在一种实施方式中，铁电存储器200也可以是设置于SOC 110外部的RAM。本公开不对铁电存储器200在设备中的位置以及与SOC 110的位置关系进行限定。继续如图2，铁电存储器200包括存储阵列210、译码器220、驱动器230、时序控制器240、缓存器250和输入输出驱动260。存储阵列210包括多个呈阵列排列的存储单元300，其中每个存储单元300可以用于存储1bit或者多bit的数据。存储阵列210还包括字线(wordline，WL)、位线(bitline，BL)等信号线。每一个存储单元300都与对应的字线WL、位线BL电连接。上述字线WL、位线BL中的一个或多个用于通过接收控制电路输出的控制电平，选择存储阵列中待读写的存储单元300，以改变存储单元300中的铁电电容的极化方向，从而实现数据的读写操作。
在图2所示铁电存储器200结构中，译码器220用于根据接收到的地址进行译码，以确定需要访问的存储单元300。驱动器230用于根据译码器220产生的译码结果来控制信号线的电平，从而实现对指定存储单元300的访问。缓存器250用于将读取的数据进行缓存，例如可以采用先入先出(first-in first-out，FIFO)来进行缓存。时序控制器230用于控制缓存器250的时序，以及控制驱动器230驱动存储阵列210中的信号线。输入输出驱动260用于驱动传输信号，例如驱动接收的数据信号和驱动需要发送的数据信号，使得数据信号可以被远距离传输。
上述存储阵列210、译码器220、驱动器230、时序控制器240、缓存器250和输入输出驱动260可以集成于一个芯片中，也可以分别集成于多个芯片中。本公开涉及的铁电存储器200可以是铁电随机存取存储器(ferroelectric random access memory，FeRAM)，也可以是铁电场效应晶体管存储器(ferroelectric filed-effect-transistor，FeFET)。比如，图3给出了FeRAM的其中一个存储单元300的电路结构图，如图3，该存储单元300包括至少两个铁电电容器C和一个晶体管Tr，例如，图3示例性的给出了三个铁电电容(如图3的铁电电容器C1、铁电电容器C2和铁电电容器C3)，这样的存储单元可以被称为1TnC存储单元。这里的晶体管Tr可以是金属氧化物半导体场效应晶体管(metal-oxide-semiconductor field-effect transistor，MOSFET)。另外，该存储单元300还包括字线(word line，WL)、位线(bit line，BL)和板线(plate line，PL)信号线，并且在该存储单元300中，晶体管Tr的第一端与位线BL电连接，晶体管Tr的控制端与字线WL电连接，晶体管Tr的第二端与铁电电容器C的第一电极电连接，铁电电容器C的第二电极与板线PL电连接。
在本公开中，晶体管Tr的漏极(drain)或源极(source)中的一极称为第一端，相应的另一极称为第二端，晶体管Tr的控制端为栅极。晶体管Tr的漏极和源极可以根据电流的流向而确定，比如，在图3中，电流从左至右时，则左端为漏极，右端为源极，相反的，当电流从右向左时，右端为漏极，左端为源极。可以这样理解，这里的晶体管Tr是一种具有三端子的晶体管器件，那么，该晶体管Tr可以选择NMOS(N-channel metal oxide semiconductor， N沟道金属氧化物半导体)管，或者可以选择PMOS(P-channel metal oxide semiconductor，P沟道金属氧化物半导体)管。图3示出的一个存储单元300可以用于存储多bit的数据，以提升每一个存储单元的存储容量。尤其是，这些铁电电容器C共用一个晶体管Tr，进而，还可以减少每个存储单元300的晶体管的数量，以提升存储密度。
图4示出了常规铁电存储器中的铁电电容器400的结构图。铁电电容器400可以位于衬底上，并且可以包括堆叠的第一电极410、铁电层420和第二电极430。可以理解，一个晶圆通常可以包括多个铁电存储器裸片(例如晶圆上的每个裸片具有至少一个铁电存储器)，并且每个铁电存储器可以包括多个铁电电容器400。多个铁电电容器400可以位于同一衬底上，例如可以在同一衬底上形成多个铁电电容器400。该衬底还可以包括其它电路器件，本公开对此不进行限制。由于本公开聚焦于铁电存储器中的铁电电容器，因此晶圆中的其它电路以及铁电存储器中的其它部件将不在此赘述。
在一些情形下，铁电电容器400还包括第一隔离钝化层和第二隔离钝化层(未示出)，并且，第一隔离钝化层形成在第一电极410和铁电层420之间，第二隔离钝化层形成在第二电极430和铁电层420之间。如图所示，铁电层420中存在较多的碳缺陷(以黑色实心圆示出)和较多的氧空位缺陷(以空心虚线圆示出)。如上所述，诸如碳缺陷或氧空位缺陷之类的缺陷的存在可能影响FeRAM的可靠性。一种形成铁电层的常规方法是在反应室内通过物理气相沉积(physical vapor deposition,PVD)方法使用等离子体轰击纯度为99.9％的铁电靶材，以在电极表面溅射得到一层铁电层。由于PVD方法制备的铁电层一般而言氧空位缺陷很多，所以在氩气溅射气体中混合通入一定浓度的氧气来调整铁电层氧空位缺陷浓度，进而达到调控铁电层内的氧空位缺陷的效果。然而，PVD方法本身存在离子轰击过程，一方面会对金属电极-铁电层之间的下界面造成离子轰击损伤，另一方面在沉积过程中也很难控制铁电层自身内部受到的离子轰击损伤。离子轰击损伤较多会导致PVD方法制备的铁电层的内部缺陷浓度较高，进而导致PVD方法制备的铁电层的可靠性较差。
另一种常规FeRAM的制造方法涉及使用原子层沉积来进行铁电层的沉积，并通过控制氧元素前驱体的通气脉冲时间来调整薄膜内部的氧元素含量。具体而言，标准的ALD单循环包含四个步骤：向反应腔体中通入金属前驱体，氮气吹扫反应腔体，通入氧前驱体，再氮气吹扫。在此方案中，使用O 3作为氧前驱体，通过修改通入氧前驱体的通入时间来调整铁电层中的缺陷含量。虽然通过上述方式可以控制缺陷含量，但是ALD的单循环时间较长时，将导致沉积的整体效率极低。例如，ALD单循环大约生长氧化铪基铁电层的厚度为0.08纳米(nm)，那么这意味着生长10nm的氧化铪基铁电层需要120个循环。如果单循环总时间例如需要大于5秒(s)，则生长10nm的氧化铪基铁电层需要大于10分钟。这样，ALD方法每小时平均生产片数将低于6片，这种生产效率较低并且制造成本极高。
在本公开的一些实施例中，通过将铁氧层放入弱腐蚀性的氧化性溶液中，氧化性溶液可以与铁氧层中的碳缺陷快速反应以去除碳缺陷，并且还可以与铁电层中的氧空位发生反应，以填充氧空位。通过调控铁电层中的碳缺陷浓度与氧空位缺陷浓度，可以达到调控铁电层的铁电极化特性与可靠性的效果。此外，在可以将多个晶圆一同放入氧化性溶液中同时进行处理的情形下，可以显著提高生产效率并且降低制造成本。
在本公开中，铁电层可以采用氧化铪基材料制得。相比采用其他铁电材料，氧化铪基铁电电容的厚度尺寸可以微缩到十纳米乃至亚十纳米，这样的话，可以实现高密度集成乃至三维集成，在构建超高密度存储芯片方面具有较大的优势。另外，氧化铪基铁电电容的制备工 艺可以与硅基半导体工艺具有良好的兼容性，这样可以利用成熟的制造工艺制得该铁电电容，不会增加制造成本。
在本公开中，诸如氧化铪之类的材料制成的铁电层的晶相包括：单斜晶相(monolithic phase，m-phase)，其为非铁电晶相；四方晶相(tetragonal phase，t-phase)，其亦为非铁电晶相；以及正交晶相(orthorhombic phase，o-phase)，也叫斜方晶相，一般认为它是铁电晶相。在铁电晶相的铁电层晶格结构中，正负电荷中心不对称从而产生电偶极子，原本方向随机且整体净值为0的大量电偶极子在外加电场的驱动下，可以变得方向趋于一致且净值非0，并在撤去电场后依然能够保留一定的趋同性从而使得薄膜总电荷净值非0，该效应被称为铁电自发极化特性。铁电层总电荷净值又被称为铁电极化强度(polarization)。在撤去电场后的薄膜总电荷净值为剩余极化强度(remnant polarization，Pr)，Pr是常被用来衡量铁电薄膜铁电极化特性的量化参数。
本公开的铁电层所涉及的氧化铪基材料是指基于氧化铪材料体系的铁电材料，比如，可以是硅(Si)掺杂的二氧化铪(HfO 2)、铝(Al)掺杂的HfO 2、镧(La)掺杂的HfO 2、钇(Y)掺杂的HfO 2、钆(Gd)掺杂的HfO 2、锶(Sr)掺杂的HfO 2等；或者也可以是铪锆氧(hafniumzirconiumoxide，HZO)体系，比如，可以是铪锆氧HZO、镧(La)掺杂的HZO、钇(Y)掺杂的HZO、锶(Sr)掺杂的HZO、钆(Gd)掺杂的HZO、钆镧(Gd/La)共掺杂的HZO、钇镧(Y/La)共掺杂的HZO等。在本公开中，氧化铪层指代使用氧化铪基材料形成的层。
在一些实施方式中，铁电层两侧的第一电极层和第二电极层的材料可以选择金属，比如，可以选择下述金属，但是不限于这些金属材料。示例的，可以选择氮化钛(TiN)、氮化钽(TaN)、氮化锆(ZrN)、氮化铪(HfN)、氮化钨(WN)、氮硅钛(TiSiN)、氮碳钛(TiCN)、钨(W)、钌(Ru)、钼(Mo)、铱(Ir)、镍(Ni)、铂(Pt)、氧化钌(RuO)、氧化铱(IrO)、氧化铟锡(ITO)等。并且，第一电极层和第二电极层的材料可以是相同的，也可以是不同的。
在一些设计中，第一电极层和第二电极层的沿堆叠方向的厚度可为但不限于2.5nm至100nm。此外，第一电极层的厚度和第二电极层的厚度可以相等，也可以不相等。在一些场景中，可以选择TiN制得第一电极层和第二电极，采用HZO制得铁电层。因为HZO层提供拉应力有利于形成铁电相，并且TiN材料可以与半导体CMOS工艺相兼容。此外，铁电层沿堆叠方向的厚度可以为但不限于为1nm至100nm。
图5示出了根据本公开的一些实施例的方法500的流程图。可以理解，上面针对铁电存储器描述的各个方面可以选择性适用于方法500，在此不再赘述。铁电存储器的制造流程可以包括众多步骤，然而本公开聚焦于铁电存储器中的铁电电容器的制造工艺，因此铁电存储器的除铁电电容器之外的部件的制造工艺在此不予赘述。在502，在衬底上形成第一电极层。在504，在第一电极层上形成铁电层。在一个实施例中，铁电层可以是氧化铪层。例如，可以通过ALD在第一电极层上形成铁电层。例如在反应室内，在通入O 3气体达5s的情形下使用ALD来沉积HZO层。在另一实施例中，可以在第一电极层上先形成第一隔离钝化层，并且随后在第一隔离钝化层上形成铁电层。本公开对此不进行限制。
在506，可以将铁电层放入用于去除铁电层中的碳缺陷和氧空位缺陷中的至少一部分的氧化性溶液。在本公开中，氧化性溶液对铁氧层是惰性或弱腐蚀性的，或对于铁电层的蚀刻速率不高于每分钟0.5nm。另一方面，氧化性溶液可以对铁氧层中的碳缺陷和氧空位缺陷中的至少一部分起反应，以去除至少部分的碳缺陷和氧空位缺陷。在一些实施例中，氧化性溶 液包括H 2O 2溶液、SC1溶液、H 2SO 4:H 2O 2溶液或水溶O 3溶液。在一些实施例中，H 2O 2溶液中H 2O 2的质量百分比位于0.1％和60％之间、1％和30％之间或10％-20％之间。在一些实施例中，H 2SO 4:H 2O 2溶液中的H 2O 2质量百分比位于0.1％和60％之间，H 2SO 4的质量百分比位于0.1％和98％之间。在另一些实施例中，H 2SO 4:H 2O 2溶液中的H 2O 2质量百分比位于1％和30％之间，H 2SO 4的质量百分比位于1％和70％之间。在又一些实施例中，H 2SO 4:H 2O 2溶液中的H 2O 2质量百分比位于10％和20％之间，H 2SO 4的质量百分比位于10％和40％之间。在一些实施例中，水溶O 3溶液中的O 3的浓度位于0.01mg/L和10mg/L之间。在另一些实施例中，水溶O 3溶液中的O 3的浓度位于0.1mg/L和7mg/L之间。在又一些实施例中，水溶O 3溶液中的O 3的浓度位于1mg/L和3mg/L之间。在一些实施例中，SC1溶液为NH 4OH:H 2O 2:H 2O溶液。在一些实施例中，SC1溶液的NH 4OH质量百分比位于0.1％至30％之间，并且H 2O 2质量百分比位于0.1％至60％之间。在另一些所述中，SC1溶液的NH 4OH质量百分比位于1％至10％之间，并且H 2O 2质量百分比位于1％至30％之间。在又一些实施例中，SC1溶液的NH 4OH质量百分比位于3％至5％之间，并且H 2O 2质量百分比位于5％至10％之间。
在508，在铁电层上形成第二电极层，以形成铁电存储器的存储单元的铁电电容器。在一些实施例中，可以在形成第二电极层之前，在铁电层上形成第二隔离钝化层，并且在此之后在第二隔离钝化层上形成第二电极层，本公开对比不进行限制。在一个实施例中，可以在形成第二电极层之后，对包括第一电极层、铁电层和第二电极层的衬底执行快速热退火工艺。通过执行快速热退火，可以通过热膨胀来提供应力，从而诱导铁氧层产生出铁电晶相，进而产生铁电极化特性。
图6示出了根据本公开的一些实施例的方法500的效果示意图。如图6所示，附图标记620表示铁氧层未被放入上述氧化性溶液之前的铁氧层中的碳缺陷和氧空位缺陷的分布示意，其中黑色实心圆表示碳缺陷，而空心虚线圆表示氧空位缺陷。附图标记640表示经上述氧化性溶液处理之后的碳缺陷和氧空位缺陷的分布示意。可以看出，在经氧化性溶液处理之后，铁氧层中的碳缺陷和氧空位缺陷均显著减少。在本公开的一些实施例中，可以通过调整氧化性溶液来控制铁氧层中的碳缺陷和氧空位缺陷的浓度。例如，对于使用相同工艺制造的晶圆，可以选择将若干晶圆(作为样本)放入溶液进行处理，并且测量经该处理之后的铁电电容器的铁电极化强度。基于样本的测量结果，可以相应调整氧化性溶液的参数，例如氧化性溶液浓度和配方、或晶圆放置在氧化性溶液中的时间等。这样，后续晶圆可以使用经调整的氧化性溶液以获得期望的铁电极化强度。
图7示出了根据本公开的一些实施例的方法500所得的铁电存储器与常规铁电存储器的性能比对示意图。附图标记710表示在每个循环中施加0.5s O 3脉冲的ALD所获得的铁氧层的铁电极化强度，附图标记720表示在每个循环中施加5s O 3脉冲的ALD所获得的铁氧层的铁电极化强度，附图标记730表示在每个循环中施加0.5s O 3脉冲的ALD所获得的铁氧层在经过氧化性溶液处理后的铁电极化强度。可以看出，附图标记730所指示的铁电极化强度显著优于附图标记710所指示的铁电极化强度，并且与附图标记720所指示的铁电极化强度基本上相当。因此，通过使用根据本公开的例如如图5所示的方法，可以显著提高铁电存储器的生产效率。此外，相比于通过使用PVD溅射方法形成的铁电存储器，由于方法500不涉及溅射，因此也可以显著提高铁电存储器的可靠性。
在另一实施例中，在506之前，可以在通过例如ALD形成的铁电层上形成牺牲电极层。随后，对包括第一电极层、铁电层和牺牲电极层的衬底执行快速热退火工艺，以及在此之后， 去除牺牲电极层以从506处继续执行方法500。
图8示出了根据该实施例的方法所得的铁电存储器与常规铁电存储器的性能比对示意图。对于铁电层中的缺陷而言，当缺陷适量时，铁电层的极化特性较强，例如可以达到10μC/cm 2以上，如附图标记810所示，但是循环擦写寿命较低，例如在1E8以下，如附图标记820所示。而当缺陷较少时，铁电层的极化特性较弱，例如在10μC/cm 2以下，如附图标记830所示，但是循环擦写寿命可以较高，例如可以达到1E8以上，如附图标记840所示。在本实施例中，在ALD沉积HZO薄膜时可以例如通过调整O 3脉冲时间控制其具有适量多的缺陷，结合牺牲电极在热退火过程中提供的应力，可以辅助HZO结晶得到更多的铁电晶相，以增强其铁电极化特性，例如可以达到10μC/cm 2以上，如附图标记850所示。出于提升可靠性的考虑，需要尽量减少铁电层中的缺陷浓度，于是再刻蚀掉牺牲电极并用诸如H 2O 2溶液之类的氧化性溶液处理铁电层，从而减少该铁电层中的缺陷浓度，达到升其循环擦写寿命，例如可以达到1E8以上，如附图标记860所示。
在该实施例中，一方面，对结晶时铁电层中的缺陷浓度、以及结晶后铁电层中的缺陷浓度实现了分别控制，可以使得铁电存储器具有较强的铁电极化特性与较高的循环擦写寿命。另一方面，不影响铁电层自身的沉积过程，可以在提升铁电层的同时，有效控制其制造生产成本。
尽管已经采用特定于结构特征和/或方法逻辑动作的语言描述了本主题，但是应当理解所附权利要求书中所限定的主题未必局限于上面描述的特定特征或动作。相反，上面所描述的特定特征和动作仅仅是实现权利要求书的示例形式。

Claims (10)

  1. 一种用于制造铁电存储器的方法，包括：
    在衬底上形成第一电极层；
    在所述第一电极层上形成铁电层；
    将所述铁电层放入用于去除所述铁电层中的碳缺陷和氧空位缺陷中的至少一部分的氧化性溶液；以及
    在所述铁电层上形成第二电极层，以形成所述铁电存储器的存储单元的铁电电容器。
  2. 根据权利要求1所述的方法，还包括：
    在形成所述第二电极层之后，对包括所述第一电极层、所述铁电层和所述第二电极层的所述衬底执行快速热退火工艺。
  3. 根据权利要求1所述的方法，还包括：
    在将所述铁电层放入所述氧化性溶液之前：
    在所述铁电层上形成牺牲电极层；
    对包括所述第一电极层、所述铁电层和所述牺牲电极层的所述衬底执行快速热退火工艺；以及
    去除所述牺牲电极层。
  4. 根据权利要求1-3中任一项所述的方法，其中所述铁电层包括氧化铪层，在所述第一电极层上形成所述铁电层包括：
    使用原子层沉积在所述第一电极层上形成所述氧化铪层。
  5. 根据权利要求4所述的方法，其中使用原子层沉积在所述第一电极层上形成所述氧化铪层包括：
    在反应室内使用臭氧气体与所述氧化铪层反应达第一时间段。
  6. 根据权利要求1-5中任一项所述的方法，其中所述氧化性溶液对于所述所述铁电层的蚀刻速率不高于每分钟0.5nm。
  7. 根据权利要求1-5中任一项所述的方法，其中所述氧化性溶液包括H 2O 2溶液、SC1溶液、H 2SO 4:H 2O 2溶液或水溶O 3溶液。
  8. 根据权利要求6所述的方法，其中所述H 2O 2溶液中H 2O 2的质量百分比位于0.1％和60％之间；
    所述H 2SO 4:H 2O 2溶液中的H 2O 2质量百分比位于0.1％和60％之间，H 2SO 4的质量百分比位于0.1％和98％之间；以及
    所述水溶O 3溶液中的O 3的浓度位于0.01mg/L和10mg/L之间。
  9. 根据权利要求1-8中任一项所述的方法，还包括：
    检测所述铁电电容器的铁电极化特性；以及
    基于所述铁电极化特性，对所述氧化性溶液进行调整。
  10. 一种铁电存储器，由根据权利要求1-9中任一项所述的方法制成。
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