WO2023109089A1 - 实现外部监控和配置的flash型fpga的配置电路 - Google Patents

实现外部监控和配置的flash型fpga的配置电路 Download PDF

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Publication number
WO2023109089A1
WO2023109089A1 PCT/CN2022/102686 CN2022102686W WO2023109089A1 WO 2023109089 A1 WO2023109089 A1 WO 2023109089A1 CN 2022102686 W CN2022102686 W CN 2022102686W WO 2023109089 A1 WO2023109089 A1 WO 2023109089A1
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circuit
voltage
negative
positive
terminal
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PCT/CN2022/102686
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English (en)
French (fr)
Inventor
单悦尔
曹正州
谢文虎
张艳飞
蒋婷
涂波
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无锡中微亿芯有限公司
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Priority to US17/955,578 priority Critical patent/US20230020524A1/en
Publication of WO2023109089A1 publication Critical patent/WO2023109089A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/24—Bit-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/30—Power supply circuits

Definitions

  • the invention relates to the field of flash FPGA, in particular to a flash FPGA configuration circuit for external monitoring and configuration.
  • the flash-type FPGA is designed based on reconfigurable flash storage technology. By reprogramming the flash storage unit (flash cell), the logic relationship inside the circuit is changed, thereby realizing different logic functions of the user.
  • the core of the flash FPGA function is the programmable logic block, each programmable logic block contains m*n flash cell arrays, and these flash cell arrays are distributed in the entire flash FPGA in small blocks, as shown in the figure 1.
  • the configuration logic obtains the configuration code stream through the JTAG protocol, and uses the word line (WL) drive circuit and the bit line (BL) drive circuit to perform erasure and programming on the flash cell in the programmable logic block. operate. Since the flash FPGA chip area is very large, for a flash FPGA with a system equivalent gate number of 3 million gates and a process technology of 0.11um, the chip area reaches 12mm*15mm, which is far larger than the flash memory of the same capacity, so the configuration The word line driving circuit and the bit line driving circuit of the flash cell have relatively long traces and heavy loads, which pose a challenge to reliability.
  • the word line driving circuit and the bit line driving circuit of the cell have relatively long traces and heavy loads, which pose a challenge to reliability.
  • the inventor proposes a configuration circuit of a flash FPGA that realizes external monitoring and configuration for the above-mentioned problems and technical requirements, and the technical scheme of the present invention is as follows:
  • a configuration circuit for a flash FPGA that realizes external monitoring and configuration
  • the flash FPGA includes a positive high voltage external monitoring port and a negative high voltage external monitoring port
  • the configuration circuit includes a voltage supply circuit, a word line driver circuit and a bit line driver circuit, the voltage The positive output terminal of the supply circuit is connected to the positive voltage terminal of the word line driver circuit and the bit line driver circuit, and the negative output terminal of the voltage supply circuit is connected to the negative voltage terminal of the word line driver circuit and the bit line driver circuit.
  • the oscillator is connected to the clock signal terminals of the positive high-voltage charge pump and the negative high-voltage charge pump through the mode control circuit, and the mode control circuit also outputs a switch control signal to control the on-off of the positive high-voltage bidirectional switch circuit and the negative high-voltage bidirectional switch circuit;
  • the positive high voltage output terminal of the positive high voltage charge pump is connected to the positive high voltage external monitoring port through the positive high voltage bidirectional switch circuit, and the common terminal of the positive high voltage charge pump and the positive high voltage bidirectional switch circuit is used as the positive output terminal of the voltage supply circuit;
  • the negative high voltage output terminal of the negative high voltage charge pump is connected to the negative high voltage external monitoring port through the negative high voltage bidirectional switch circuit, and the common terminal of the negative high voltage charge pump and the negative high voltage bidirectional switch circuit is used as the negative output terminal of the voltage supply circuit;
  • the mode control circuit obtains the mode adjustment signal based on the JTAG of the flash FPGA, and controls the on-off of the path between the oscillator and the clock signal terminals of the two high-voltage charge pumps and controls the two high-voltage bidirectional switches according to the acquired mode adjustment signal
  • the circuit is turned on and off to control the flash FPGA to enter the external monitoring mode or external configuration mode:
  • the positive high voltage provided by the positive high voltage charge pump is externally monitored through the positive high voltage external monitoring port, and the negative high voltage provided by the negative high voltage charge pump is externally monitored through the negative high voltage external monitoring port;
  • This application discloses a flash FPGA configuration circuit for external monitoring and configuration. Based on the structure of the configuration circuit of this application, only a small amount of logic needs to be added on the basis of the JTAG protocol of the flash FPGA configuration circuit.
  • the FPGA monitors the positive high voltage and negative high voltage provided by the internal high voltage charge pump through the positive high voltage external monitoring port and the negative high voltage external monitoring port, so that the abnormality of positive high voltage and negative high voltage can be found in time situation and improve reliability.
  • the positive high voltage and negative high voltage can also be input from the outside through the positive high voltage external monitoring port and the negative high voltage external monitoring port, and when the external input is made, the two high voltage charge pumps are turned off to prevent conflict with the high voltage provided by the outside.
  • the positive high voltage and negative high voltage provided by the internal high-voltage charge pump are abnormal, the positive high voltage and negative voltage required by the external input during the erasing and programming operations can be adjusted in time to output to the word line driver circuit and bit line driver The range of positive high voltage and negative high voltage of the circuit further improves the reliability.
  • Fig. 1 is the schematic diagram of the layout of the programmable logic block in the flash type FPGA.
  • FIG. 2 is a schematic diagram of the circuit structure of the configuration circuit of the present application.
  • FIG. 3 is a circuit diagram of an embodiment of the voltage supply circuit of the present application.
  • the present application discloses a flash FPGA configuration circuit for external monitoring and configuration.
  • the flash FPGA also provides a positive high voltage external monitoring port HV_PAD and a negative high voltage external monitoring port LV_PAD.
  • the configuration circuit includes a voltage supply circuit, a word line driver circuit and a bit line driver circuit.
  • the positive output terminal HV_OUT of the voltage supply circuit is connected to the positive voltage of the word line driver circuit and the bit line driver circuit.
  • the terminal VPC, the negative output terminal LV_OUT of the voltage supply circuit is connected to the negative voltage terminal VGC of the word line driving circuit and the bit line driving circuit, the word line driving circuit and the bit line driving circuit can adopt the existing driving circuit structure, and this application does not expand the description .
  • the voltage supply circuit of the flash FPGA includes a mode control circuit, an oscillator OSC, a positive high voltage charge pump, a negative high voltage charge pump, a positive high voltage bidirectional switch circuit and a negative high voltage bidirectional switch circuit.
  • the positive high-voltage charge pump and the negative high-voltage charge pump may adopt existing circuit structures, and FIG. 3 takes a possible circuit structure as an example.
  • the positive high voltage output terminal of the positive high voltage charge pump is connected to the positive high voltage external monitoring port HV_PAD through the positive high voltage bidirectional switch circuit, and the common terminal of the positive high voltage charge pump and the positive high voltage bidirectional switch circuit is used as the positive output terminal HV_OUT of the voltage supply circuit.
  • the negative high voltage output terminal of the negative high voltage charge pump is connected to the negative high voltage external monitoring port LV_PAD through the negative high voltage bidirectional switch circuit, and the common terminal of the negative high voltage charge pump and the negative high voltage bidirectional switch circuit is used as the negative output terminal LV_OUT of the voltage supply circuit.
  • the oscillator provides the clock signal clk, and the oscillator is connected to the clock signal terminals of the positive high-voltage charge pump and the negative high-voltage charge pump through the mode control circuit.
  • the mode control circuit also outputs a switch control signal ctrl to control the on-off of the positive high-voltage bidirectional switch circuit and the negative high-voltage bidirectional switch circuit.
  • the mode control circuit obtains the mode adjustment signal based on the JTAG of the flash FPGA, and based on the obtained mode adjustment signal, controls the on-off of the oscillator and the clock signal terminals of the positive high-voltage charge pump and the negative high-voltage charge pump, and controls the high-voltage bidirectional
  • the on-off of the switch and the negative high-voltage bidirectional switch circuit so as to control the flash FPGA to enter different modes, including:
  • the mode control circuit controls the channel conduction between the oscillator and the clock signal terminals of the positive high-voltage charge pump and the negative high-voltage charge pump.
  • the oscillator normally provides the clock signal clk to the positive high-voltage charge pump and the negative high-voltage charge pump through the mode control circuit to make the positive high-voltage charge pump and the negative high-voltage charge pump work normally, so that the positive high voltage provided by the positive high-voltage charge pump passes through the voltage supply circuit.
  • the positive output terminal HV_OUT is output to the word line driver circuit and the bit line driver circuit, and the negative high voltage provided by the negative high voltage charge pump is provided to the word line driver circuit and the bit line driver circuit through the negative output terminal LV_OUT output of the voltage supply circuit.
  • the mode control circuit also outputs an effective level switch control signal ctrl to control the conduction of the positive high voltage bidirectional switch circuit and the negative high voltage bidirectional switch circuit, and the positive high voltage provided by the positive high voltage charge pump is also supplied by the positive high voltage external switch circuit through the positive high voltage bidirectional switch circuit.
  • the monitoring port HV_PAD is output, and the negative high voltage provided by the negative high voltage charge pump is also output by the negative high voltage external monitoring port LV_PAD through the negative high voltage bidirectional switch circuit.
  • the mode control circuit controls the oscillator to disconnect the path between the clock signal terminals of the positive high-voltage charge pump and the negative high-voltage charge pump , the clock signal provided by the oscillator is turned off by the mode control circuit, and cannot be transmitted to the positive high-voltage charge pump and the negative high-voltage charge pump, so that both the positive high-voltage charge pump and the negative high-voltage charge pump stop working.
  • the mode control circuit also outputs an effective level switch control signal to control the conduction of the positive high voltage bidirectional switch circuit and the negative high voltage bidirectional switch circuit.
  • the positive high voltage external monitoring port HV_PAD inputs external positive high voltage
  • the negative high voltage external monitoring port LV_PAD inputs external negative high voltage
  • the external positive high voltage input by the positive high voltage external monitoring port HV_PAD is transmitted to the voltage supply circuit through the positive high voltage bidirectional switch circuit
  • the positive output terminal HV_OUT of the positive output terminal is provided to the word line driving circuit and the bit line driving circuit.
  • the external negative high voltage input by the negative high voltage external monitoring port LV_PAD is transmitted to the negative output terminal LV_OUT of the voltage supply circuit through the negative high voltage bidirectional switch circuit, and the output is provided to the word line driving circuit and the bit line driving circuit.
  • the required positive high voltage and negative high voltage can be input from the outside, and when the external input is made, the two high-voltage charge pumps are turned off to prevent conflicts with the high voltage provided by the outside.
  • a typical application scenario is that when the positive and negative high voltages provided by the internal high-voltage charge pump are monitored through the external monitoring mode, the positive and negative voltages required during the erasing and programming operations can be input externally. , thereby timely adjusting the ranges of the positive high voltage and the negative high voltage output to the word line driving circuit and the bit line driving circuit.
  • the mode control circuit controls the conduction of the path between the oscillator and the clock signal terminals of the positive high-voltage charge pump and the negative high-voltage charge pump , the oscillator normally provides the clock signal clk to the positive high-voltage charge pump and the negative high-voltage charge pump through the mode control circuit to make the positive high-voltage charge pump and the negative high-voltage charge pump work normally, so that the positive high voltage provided by the positive high-voltage charge pump passes through the positive voltage supply circuit.
  • the output terminal HV_OUT is provided to the word line driver circuit and the bit line driver circuit, and the negative high voltage provided by the negative high voltage charge pump is provided to the word line driver circuit and the bit line driver circuit through the negative output terminal LV_OUT output of the voltage supply circuit.
  • the mode control circuit outputs a switch control signal ctrl at an inactive level to control the positive high voltage bidirectional switch circuit and the negative high voltage bidirectional switch circuit to be disconnected.
  • This mode is the same as the working process in which the high-voltage charge pump provides the required high voltage in the existing FPGA, that is, the flash FPGA is also compatible with the conventional mode without external monitoring and configuration functions.
  • FIG. 3 shows a specific circuit diagram of a voltage supply circuit provided by an embodiment:
  • the mode control circuit includes control logic, three-input OR gate A1 and two-input NOR gate B1.
  • the first input terminal Q0 and the second input terminal Q1 of the control logic are respectively connected to the two input terminals of the three-input OR gate A1, the oscillator is connected to the other input terminal of the three-input OR gate A1, and the output terminal of the three-input OR gate A1 is connected to Clock Signal Terminal for Positive High-Voltage Charge Pump and Negative High-Voltage Charge Pump.
  • the second input terminal Q1 and the third input terminal Q2 of the control logic are connected to the two input terminals of the two-input NOR gate B1, and the output terminal of the two-input NOR gate B1 is connected to the positive high-voltage bidirectional switch circuit and the negative high-voltage bidirectional switch circuit to Control on and off.
  • the mode control circuit obtains the mode adjustment signal through the control logic, and the control logic controls the output of the three-input OR gate A1 and the two-input NOR gate B1 based on the acquired mode adjustment signal:
  • the mode control circuit obtains the mode adjustment signal through the TDI terminal and the TRST terminal of the JTAG of the flash FPGA, and the control logic includes three shift registers dff00, dff01, dff02 and three control registers dff10, dff11, dff12, in:
  • the D terminal of dff00 is connected to the TDI terminal, the Q terminal of dff00 is connected to the D terminal of dff10, and the Q terminal of dff10 is used as the first input terminal Q0 of the control logic.
  • the Q terminal of dff00 is also connected to the D terminal of dff01, the Q terminal of dff01 is connected to the D terminal of dff11, and the Q terminal of dff11 is used as the second input terminal Q1 of the control logic.
  • the Q terminal of dff01 is also connected to the D terminal of dff02, the Q terminal of dff02 is connected to the D terminal of dff12, and the Q terminal of dff12 is used as the third input terminal Q2 of the control logic.
  • the RST terminals of dff00, dff01, dff02, dff10, dff11 and dff12 are all connected to the TRST terminal.
  • the CLK terminals of dff00, dff01, and dff02 are all connected to the data shift clock signal SHIFT_CK issued by the TAP state machine of the JTAG of the flash FPGA, and the CLK terminals of dff10, dff11, and dff12 are connected to the TAP state machine of the JTAG of the flash FPGA.
  • Another data update clock signal UPDATE_CK UPDATE_CK
  • the positive high voltage bidirectional switch circuit includes PMOS transistors P3 and P10, a first positive level conversion circuit and a second positive level conversion circuit, and the source of P3 is connected to the positive high voltage output terminal of the positive high voltage charge pump.
  • the drain of P3 is connected to the source of P10, and the drain of P10 is connected to the positive high voltage external monitoring port HV_PAD.
  • the input terminal of the first positive level conversion circuit obtains the switch control signal ctrl output by the mode control circuit, the output terminal HZ0 is connected to the gate of P3, and the power supply terminal of the first positive level conversion circuit is connected to the positive high voltage output terminal of the positive high voltage charge pump .
  • the input terminal of the second positive level conversion circuit obtains the switch control signal ctrl output by the mode control circuit, the output terminal HZ1 is connected to the gate of P10, and the power supply terminal of the second positive level conversion circuit is connected to the positive high voltage external monitoring port HV_PAD.
  • both the first positive level shifting circuit and the second positive level shifting circuit output a high level
  • the voltage at the output terminal HZ0 of the first positive level shifting circuit is equal to
  • the voltage of the output terminal HZ1 of the second positive level conversion circuit is equal to the voltage of the positive high voltage external monitoring port HV_PAD, so that the path between the positive high voltage external monitoring port HV_PAD and the positive output terminal HV_OUT can be closed. That is, the positive high-voltage bidirectional switch circuit is disconnected.
  • the switch control signal ctrl is active at low level
  • the circuit structure of the first positive level conversion circuit and the second positive level conversion circuit are the same, in each level conversion circuit: PMOS transistor P1
  • the source of the PMOS transistor P2 is connected to the source and connected to the power supply terminal of the positive level conversion circuit.
  • the drain of P1 is connected to the drain of NMOS transistor N4 and the gate of P2, and the drain of P2 is connected to the drain of NMOS transistor N5 and the gate of P1.
  • the source of N4 is grounded, the source of N5 is grounded, the gate of N4 is connected to the input terminal of the positive level conversion circuit, the input terminal of the positive level conversion circuit is also connected to the gate of N5 through the inverter I3, and the gate of N5 The drain is also connected to the output terminal of the positive level conversion circuit.
  • the first positive level conversion circuit is represented by P1, P2, N4 and N5
  • the second positive level conversion circuit is correspondingly represented by P8, P9, N6 and N7.
  • the high-voltage bidirectional switch circuit includes NMOS transistors N14 and N19, a first negative level conversion circuit and a second negative level conversion circuit.
  • the source of N19 is connected to the negative high-voltage output terminal of the negative high-voltage charge pump, and the drain of N19 is connected to the source of N14.
  • the drain of N14 is connected to the negative high voltage external monitoring port LV_PAD.
  • the switch control signal ctrl output by the mode control circuit is provided to the input terminal of the first negative level conversion circuit and the input terminal of the second negative level conversion circuit through the inverter I5, and the output terminal LZ0 of the first negative level conversion circuit is connected to the gate of N19 pole, and the power supply terminal of the first negative level conversion circuit is connected to the negative high voltage output terminal of the negative high voltage charge pump.
  • the output terminal LZ1 of the second negative level conversion circuit is connected to the gate of N14, and the power supply terminal of the second negative level conversion circuit is connected to the negative high voltage external monitoring port LV_PAD.
  • both the first negative level conversion circuit and the second negative level conversion circuit output high level, both N19 and N14 are turned on, and the negative high voltage external monitoring port LV_PAD and the negative output terminal Two-way transmission is possible between LV_OUT, that is, the negative high-voltage bidirectional switch circuit is turned on.
  • both the first negative level conversion circuit and the second negative level conversion circuit output low level, and the voltage at the output terminal LZ0 of the first negative level conversion circuit is equal to the negative high-voltage charge
  • the voltage of the output terminal LZ1 of the second negative level conversion circuit is equal to the voltage of the negative high voltage external monitoring port LV_PAD, so that the path between the negative high voltage external monitoring port LV_PAD and the negative output terminal LV_OUT can be closed, that is, The negative high voltage bidirectional switch circuit is disconnected.
  • the switch control signal ctrl is active at low level
  • the circuit structure of the first negative level conversion circuit and the second negative level conversion circuit are the same
  • the source of NMOS transistor N12 The pole is connected to the source of the NMOS transistor N13 and connected to the power supply terminal of the negative level conversion circuit.
  • the drain of N12 is connected to the drain of PMOS transistor P11 and the gate of N13
  • the drain of N13 is connected to the drain of PMOS transistor P12 and the gate of N12.
  • the source of P11 is connected to the source of P12 and connected to the chip voltage VDD, and the gate of P11 is connected to the input terminal of the negative level conversion circuit.
  • the input terminal of the negative level conversion circuit is also connected to the gate of P12 through an inverter, and the drain of N13 is used as the output terminal of the negative level conversion circuit.
  • the second negative level conversion circuit is represented by P11, P12, N12 and N13
  • the first positive level conversion circuit is correspondingly represented by P15, P16, N17 and N18.

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Abstract

本发明公开了一种实现外部监控和配置的flash型FPGA的配置电路，涉及flash型FPGA领域，该配置电路中，正高压电荷泵的正高压输出端通过正高压双向开关电路连接正高压外部监控端口、还作为电压提供电路的正输出端；负高压电荷泵的负高压输出端通过负高压双向开关电路连接负高压外部监控端口、还作为电压提供电路的负输出端；模式控制电路根据接收到的模式调整信号控制进入外部监控模式或外部配置模式，基于本申请的配置电路的结构，只需在JTAG协议基础上增加少量的逻辑即可在擦除和编程的操作过程中，对内部的高压电荷泵提供的正高压和负高压进行监控，或者由外部输入所需的正高压和负高压，从而提高可靠性。

Description

实现外部监控和配置的flash型FPGA的配置电路 技术领域
本发明涉及flash型FPGA领域，尤其是一种实现外部监控和配置的flash型FPGA的配置电路。
 背景技术
flash型FPGA基于可重复配置的flash存储技术设计，通过对flash存储单元（flash cell）的重新编程，改变电路内部的逻辑关系，从而实现用户不同的逻辑功能。flash型FPGA实现功能的核心是可编程逻辑块，每个可编程逻辑块包含m*n的flash cell阵列，这些flash cell阵列按一小块一小块分散分布在整个flash型FPGA中，如图1所示。
在研制flash型FPGA的过程中，配置逻辑通过JTAG协议获取配置码流，利用字线（WL）驱动电路和位线（BL）驱动电路对可编程逻辑块中的flash cell执行擦除和编程等操作。由于flash型FPGA芯片面积非常大，以系统等效门数为300万门、制程工艺为0.11um的flash型FPGA来说，芯片面积达到12mm*15mm，远远大于等容量的flash存储器，所以配置flash cell的字线驱动电路和位线驱动电路的走线比较长、负载大，对可靠性提出了挑战。
 技术问题
配置flash cell的字线驱动电路和位线驱动电路的走线比较长、负载大，对可靠性提出了挑战。
 技术解决方案
本发明人针对上述问题及技术需求，提出了一种实现外部监控和配置的flash型FPGA的配置电路，本发明的技术方案如下：
一种实现外部监控和配置的flash型FPGA的配置电路，该flash型FPGA包括正高压外部监控端口和负高压外部监控端口，配置电路包括电压提供电路、字线驱动电路和位线驱动电路，电压提供电路的正输出端连接字线驱动电路和位线驱动电路的正电压端，电压提供电路的负输出端连接字线驱动电路和位线驱动电路的负电压端，在flash型FPGA的电压提供电路中：
振荡器通过模式控制电路连接正高压电荷泵和负高压电荷泵的时钟信号端，模式控制电路还输出开关控制信号以控制正高压双向开关电路和负高压双向开关电路的通断；
正高压电荷泵的正高压输出端通过正高压双向开关电路连接正高压外部监控端口，正高压电荷泵和正高压双向开关电路的公共端作为电压提供电路的正输出端；
负高压电荷泵的负高压输出端通过负高压双向开关电路连接负高压外部监控端口，负高压电荷泵和负高压双向开关电路的公共端作为电压提供电路的负输出端；
模式控制电路基于flash型FPGA的JTAG获取模式调整信号，并根据获取到的模式调整信号控制振荡器与两个高压电荷泵的时钟信号端之间的通路的通断、以及控制两个高压双向开关电路的通断，以控制flash型FPGA进入外部监控模式或外部配置模式：
在外部监控模式下，通过正高压外部监控端口对正高压电荷泵提供的正高压进行外部监控、通过负高压外部监控端口对负高压电荷泵提供的负高压进行外部监控；
在外部配置模式下，通过正高压外部监控端口输入外部正高压并通过电压提供电路的正输出端输出、通过负高压外部监控端口输入外部负高压并通过电压提供电路的负输出端输出。
 有益效果
本申请公开了一种实现外部监控和配置的flash型FPGA的配置电路，基于本申请的配置电路的结构，只需在flash型FPGA的配置电路JTAG协议基础上增加少量的逻辑即可对flash型FPGA在擦除和编程的操作过程中，通过正高压外部监控端口和负高压外部监控端口对内部的高压电荷泵提供的正高压和负高压进行监控，从而可以及时发现正高压和负高压的异常情况，提高可靠性。
另外，通过正高压外部监控端口和负高压外部监控端口还可以从外部输入正高压和负高压，且在外部输入时，关闭两个高压电荷泵，防止与外部提供的高压产生冲突，当监控到内部的高压电荷泵提供的正高压和负高压异常时，可以由外部输入在擦除和编程的操作过程中所需的正高压和负电压，从而及时调整输出给字线驱动电路和位线驱动电路的正高压和负高压的范围，进一步提高可靠性。
 附图说明
图1是flash型FPGA中的可编程逻辑块的布局示意图。
图2是本申请的配置电路的电路结构示意图。
图3是本申请的电压提供电路在一个实施例中的电路图。
 本发明的实施方式
下面结合附图对本发明的具体实施方式做进一步说明。
本申请公开了一种实现外部监控和配置的flash型FPGA的配置电路，该flash型FPGA还对外提供正高压外部监控端口HV_PAD和负高压外部监控端口LV_PAD。
请参考图2，在flash型FPGA内部，该配置电路包括电压提供电路、字线驱动电路和位线驱动电路，电压提供电路的正输出端HV_OUT连接字线驱动电路和位线驱动电路的正电压端VPC，电压提供电路的负输出端LV_OUT连接字线驱动电路和位线驱动电路的负电压端VGC，字线驱动电路和位线驱动电路可以采用现有的驱动电路结构，本申请不展开描述。flash型FPGA的电压提供电路包括模式控制电路、振荡器OSC、正高压电荷泵、负高压电荷泵、正高压双向开关电路和负高压双向开关电路。其中，正高压电荷泵和负高压电荷泵具体可以采用现有的电路结构，图3以一种可能的电路结构为例。
正高压电荷泵的正高压输出端通过正高压双向开关电路连接正高压外部监控端口HV_PAD，正高压电荷泵和正高压双向开关电路的公共端作为电压提供电路的正输出端HV_OUT。负高压电荷泵的负高压输出端通过负高压双向开关电路连接负高压外部监控端口LV_PAD，负高压电荷泵和负高压双向开关电路的公共端作为电压提供电路的负输出端LV_OUT。
振荡器提供时钟信号clk，振荡器通过模式控制电路连接正高压电荷泵和负高压电荷泵的时钟信号端。模式控制电路还输出开关控制信号ctrl以控制正高压双向开关电路和负高压双向开关电路的通断。
模式控制电路基于flash型FPGA的JTAG获取模式调整信号，并基于获取到的模式调整信号控制振荡器与正高压电荷泵和负高压电荷泵的时钟信号端之间的通路通断，以及控制高压双向开关和负高压双向开关电路的通断，从而控制该flash型FPGA进入不同的模式，包括：
一、外部监控模。当模式控制电路获取到用于指示flash型FPGA进入外部监控模式的第二模式调整信号时，式模式控制电路控制振荡器与正高压电荷泵和负高压电荷泵的时钟信号端之间的通路导通，振荡器经由模式控制电路正常给正高压电荷泵和负高压电荷泵提供时钟信号clk使得正高压电荷泵和负高压电荷泵正常工作，使得正高压电荷泵提供的正高压通过电压提供电路的正输出端HV_OUT输出提供给字线驱动电路和位线驱动电路，负高压电荷泵提供的负高压通过电压提供电路的负输出端LV_OUT输出提供给字线驱动电路和位线驱动电路。
同时，模式控制电路还输出有效电平的开关控制信号ctrl以控制正高压双向开关电路和负高压双向开关电路导通，正高压电荷泵提供的正高压还经过正高压双向开关电路由正高压外部监控端口HV_PAD输出，负高压电荷泵提供的负高压还经过负高压双向开关电路由负高压外部监控端口LV_PAD输出。
利用该模式，可以实现对正高压和负高压的外部监控，从而可以及时发现正高压和负高压的异常情况，提高可靠性。
二、外部配置模式。当模式控制电路获取到用于指示flash型FPGA进入外部配置模式的第三模式调整信号时，模式控制电路控制振荡器与正高压电荷泵和负高压电荷泵的时钟信号端之间的通路断开，振荡器提供的时钟信号被模式控制电路关闭，无法传输给正高压电荷泵和负高压电荷泵，使得正高压电荷泵和负高压电荷泵均停止工作。
同时，模式控制电路还输出有效电平的开关控制信号以控制正高压双向开关电路和负高压双向开关电路导通。在该模式下，正高压外部监控端口HV_PAD输入外部正高压，负高压外部监控端口LV_PAD输入外部负高压，则正高压外部监控端口HV_PAD输入的外部正高压经由正高压双向开关电路传输到电压提供电路的正输出端HV_OUT输出提供给字线驱动电路和位线驱动电路。负高压外部监控端口LV_PAD输入的外部负高压经由负高压双向开关电路传输到电压提供电路的负输出端LV_OUT输出提供给字线驱动电路和位线驱动电路。
利用该模式，可以由外部输入所需的正高压和负高压，且在外部输入时，关闭两个高压电荷泵，防止与外部提供的高压产生冲突。比较典型的应用场景是，当通过外部监控模式监控到内部的高压电荷泵提供的正高压和负高压异常时，可以由外部输入在擦除和编程的操作过程中所需的正高压和负电压，从而及时调整输出给字线驱动电路和位线驱动电路的正高压和负高压的范围。
三、默认工作模式。当模式控制电路获取到用于指示flash型FPGA进入默认工作模式的第一模式调整信号时，模式控制电路控制振荡器与正高压电荷泵和负高压电荷泵的时钟信号端之间的通路导通，振荡器经由模式控制电路正常给正高压电荷泵和负高压电荷泵提供时钟信号clk使得正高压电荷泵和负高压电荷泵正常工作，使得正高压电荷泵提供的正高压通过电压提供电路的正输出端HV_OUT输出提供给字线驱动电路和位线驱动电路，负高压电荷泵提供的负高压通过电压提供电路的负输出端LV_OUT输出提供给字线驱动电路和位线驱动电路。同时，模式控制电路输出无效电平的开关控制信号ctrl以控制正高压双向开关电路和负高压双向开关电路断开。
该模式与现有的FPGA中由高压电荷泵提供所需高压的工作过程相同，也即该flash型FPGA同样兼容常规的无外部监控和配置功能的模式。
请参考图3，示出了一个实施例提供的电压提供电路的具体电路图：
（1）模式控制电路。
模式控制电路包括控制逻辑、三输入或门A1和二输入或非门B1。控制逻辑的第一输入端Q0和第二输入端Q1分别连接三输入或门A1的两个输入端，振荡器连接三输入或门A1的另外一个输入端，三输入或门A1的输出端连接正高压电荷泵和负高压电荷泵的时钟信号端。
控制逻辑的第二输入端Q1和第三输入端Q2连接二输入或非门B1的两个输入端，二输入或非门B1的输出端连接至正高压双向开关电路和负高压双向开关电路以控制通断。
模式控制电路通过控制逻辑获取模式调整信号，控制逻辑基于获取到的模式调整信号控制三输入或门A1和二输入或非门B1的输出：
（a）当模式控制电路通过控制逻辑获取到第一模式调整信号时，第一输入端Q0、第二输入端Q1和第三输入端Q2均为低电平，记为<Q0、Q1、Q2>=3’b000。此时三输入或门A1的输出端输出振荡器提供的时钟信号，二输入或非门B1输出高电平无效的开关控制信号使得正高压双向开关电路和负高压双向开关电路均断开。
（b）当模式控制电路通过控制逻辑获取到第二模式调整信号时，第一输入端Q0和第二输入端Q1为低电平、第三输入端Q2为高电平，记为<Q0、Q1、Q2>=3’b001。此时三输入或门A1的输出端输出振荡器提供的时钟信号，二输入或非门B1输出低电平有效的开关控制信号使得正高压双向开关电路和负高压双向开关电路均导通。
（c）当模式控制电路通过控制逻辑获取到第三模式调整信号时，第一输入端Q0和第二输入端Q1为高电平、第三输入端Q2为低电平，记为<Q0、Q1、Q2>=3’b110。此时，三输入或门A1的输出端恒定输出高电平以关断振荡器提供的时钟信号。二输入或非门B1输出低电平有效的开关控制信号使得正高压双向开关电路和负高压双向开关电路均导通。
在一个实施例中，模式控制电路通过flash型FPGA的JTAG的TDI端子和TRST端子获取模式调整信号，控制逻辑包括三个移位寄存器dff00、dff01、dff02以及三个控制寄存器dff10、dff11、dff12，其中：
dff00的D端连接TDI端子，dff00的Q端连接dff10的D端，dff10的Q端作为控制逻辑的第一输入端Q0。dff00的Q端还连接dff01的D端，dff01的Q端连接dff11的D端，dff11的Q端作为控制逻辑的第二输入端Q1。dff01的Q端还连接dff02的D端，dff02的Q端连接dff12的D端，dff12的Q端作为控制逻辑的第三输入端Q2。dff00、dff01、dff02、dff10、dff11和dff12的RST端均连接TRST端子。dff00、dff01、dff02的CLK端均连接flash型FPGA的JTAG的TAP状态机发出的一路数据移位时钟信号SHIFT_CK ，dff10、dff11和dff12的CLK端均连接flash型FPGA的JTAG的TAP状态机发出的另一路数据更新时钟信号UPDATE_CK
（2）正高压双向开关电路。
正高压双向开关电路包括PMOS管P3和P10以及第一正电平转换电路和第二正电平转换电路，P3的源极连接正高压电荷泵的正高压输出端。P3的漏极连接P10的源极，P10的漏极连接正高压外部监控端口HV_PAD。第一正电平转换电路的输入端获取模式控制电路输出的开关控制信号ctrl、输出端HZ0连接P3的栅极，第一正电平转换电路的供电端连接正高压电荷泵的正高压输出端。第二正电平转换电路的输入端获取模式控制电路输出的开关控制信号ctrl、输出端HZ1连接P10的栅极，第二正电平转换电路的供电端连接正高压外部监控端口HV_PAD。
当模式控制电路输出有效电平的开关控制信号ctrl时，第一正电平转换电路和第二正电平转换电路均输出低电平，P3和P10均导通，正高压外部监控端口HV_PAD和正输出端HV_OUT之间可以双向传输，也即使得正高压双向开关电路导通。否则当模式控制电路输出无效电平的开关控制信号ctrl时，第一正电平转换电路和第二正电平转换电路均输出高电平，第一正电平转换电路输出端HZ0的电压等于正高压电荷泵输出的正高压，第二正电平转换电路输出端HZ1的电压等于正高压外部监控端口HV_PAD的电压，这样可以将正高压外部监控端口HV_PAD和正输出端HV_OUT之间的通路关闭，也即使得正高压双向开关电路断开。
如上所述，在图3中，开关控制信号ctrl低电平有效，第一正电平转换电路和第二正电平转换电路的电路结构相同，在每个电平转换电路中：PMOS管P1的源极和PMOS管P2的源极相连并连接该正电平转换电路的供电端。P1的漏极连接NMOS管N4的漏极和P2的栅极，P2的漏极连接NMOS管N5的漏极和P1的栅极。N4的源极接地，N5的源极接地，N4的栅极连接该正电平转换电路的输入端，该正电平转换电路的输入端还通过反相器I3连接N5的栅极，N5的漏极还连接该正电平转换电路的输出端。为了区分，第一正电平转换电路中以P1、P2、N4和N5表示，第二正电平转换电路对应以P8、P9、N6和N7表示。
（3）负高压双向开关电路。
高压双向开关电路包括NMOS管N14和N19以及第一负电平转换电路和第二负电平转换电路，N19的源极连接负高压电荷泵的负高压输出端，N19的漏极连接N14的源极，N14的漏极连接负高压外部监控端口LV_PAD。
模式控制电路输出的开关控制信号ctrl通过反相器I5提供给第一负电平转换电路的输入端和第二负电平转换电路的输入端，第一负电平转换电路的输出端LZ0连接N19的栅极，第一负电平转换电路的供电端连接负高压电荷泵的负高压输出端。第二负电平转换电路的输出端LZ1连接N14的栅极，第二负电平转换电路的供电端连接负高压外部监控端口LV_PAD。
模式控制电路输出有效电平的开关控制信号ctrl时，第一负电平转换电路和第二负电平转换电路均输出高电平，N19和N14均导通，负高压外部监控端口LV_PAD和负输出端LV_OUT之间可以双向传输，也即使得负高压双向开关电路导通。否则当模式控制电路输出无效电平的开关控制信号ctrl时，第一负电平转换电路和第二负电平转换电路均输出低电平，第一负电平转换电路输出端LZ0的电压等于负高压电荷泵输出的负高压，第二负电平转换电路输出端LZ1的电压等于负高压外部监控端口LV_PAD的电压，这样可以将负高压外部监控端口LV_PAD和负输出端LV_OUT之间的通路关闭，也即使得负高压双向开关电路断开。
如上所述，在图3中，开关控制信号ctrl低电平有效，第一负电平转换电路和第二负电平转换电路的电路结构相同，在每个负电平转换电路中，NMOS管N12的源极和NMOS管N13的源极相连并连接该负电平转换电路的供电端。N12的漏极连接PMOS管P11的漏极和N13的栅极，N13的漏极连接PMOS管P12的漏极和N12的栅极。P11的源极和P12的源极相连并连接芯片电压VDD，P11的栅极连接该负电平转换电路的输入端。该负电平转换电路的输入端还通过反相器连接P12的栅极，N13的漏极作为该负电平转换电路的输出端。为了区分，第二负电平转换电路中以P11、P12、N12和N13表示，第一正电平转换电路对应以P15、P16、N17和N18表示。
以上所述的仅是本申请的优选实施方式，本发明不限于以上实施例。可以理解，本领域技术人员在不脱离本发明的精神和构思的前提下直接导出或联想到的其他改进和变化，均应认为包含在本发明的保护范围之内。

Claims (10)

  1. 一种实现外部监控和配置的flash型FPGA的配置电路，其特征在于，所述flash型FPGA包括正高压外部监控端口和负高压外部监控端口，所述配置电路包括电压提供电路、字线驱动电路和位线驱动电路，所述电压提供电路的正输出端连接所述字线驱动电路和所述位线驱动电路的正电压端，所述电压提供电路的负输出端连接所述字线驱动电路和所述位线驱动电路的负电压端，在所述flash型FPGA的电压提供电路中：
    振荡器通过模式控制电路连接正高压电荷泵和负高压电荷泵的时钟信号端，所述模式控制电路还输出开关控制信号以控制正高压双向开关电路和负高压双向开关电路的通断；
    所述正高压电荷泵的正高压输出端通过所述正高压双向开关电路连接所述正高压外部监控端口，所述正高压电荷泵和所述正高压双向开关电路的公共端作为所述电压提供电路的正输出端；
    所述负高压电荷泵的负高压输出端通过所述负高压双向开关电路连接所述负高压外部监控端口，所述负高压电荷泵和所述负高压双向开关电路的公共端作为所述电压提供电路的负输出端；
    所述模式控制电路基于所述flash型FPGA的JTAG获取模式调整信号，并根据获取到的模式调整信号控制所述振荡器与两个高压电荷泵的时钟信号端之间的通路的通断、以及控制两个高压双向开关电路的通断，以控制所述flash型FPGA进入外部监控模式或外部配置模式：
    在外部监控模式下，通过所述正高压外部监控端口对所述正高压电荷泵提供的正高压进行外部监控、通过所述负高压外部监控端口对所述负高压电荷泵提供的负高压进行外部监控；
    在外部配置模式下，通过所述正高压外部监控端口输入外部正高压并通过所述电压提供电路的正输出端输出、通过所述负高压外部监控端口输入外部负高压并通过所述电压提供电路的负输出端输出。
  2. 根据权利要求1所述的配置电路，其特征在于，当所述模式控制电路获取到用于指示所述flash型FPGA进入外部监控模式的第二模式调整信号时，所述模式控制电路控制所述振荡器与所述正高压电荷泵和所述负高压电荷泵的时钟信号端之间的通路导通，并输出有效电平的开关控制信号以控制所述正高压双向开关电路和所述负高压双向开关电路导通，所述正高压电荷泵提供的正高压通过所述电压提供电路的正输出端和所述正高压外部监控端口输出，所述负高压电荷泵提供的负高压通过所述电压提供电路的负输出端和所述负高压外部监控端口输出。
  3. 根据权利要求1所述的配置电路，其特征在于，当所述模式控制电路获取到用于指示所述flash型FPGA进入外部配置模式的第三模式调整信号时，所述模式控制电路控制所述振荡器与所述正高压电荷泵和所述负高压电荷泵的时钟信号端之间的通路断开，并输出有效电平的开关控制信号以控制所述正高压双向开关电路和所述负高压双向开关电路导通，所述正高压电荷泵和所述负高压电荷泵均停止工作，所述正高压外部监控端口输入的外部正高压通过所述电压提供电路的正输出端输出，所述负高压外部监控端口输入的外部负高压通过所述电压提供电路的负输出端输出。
  4. 根据权利要求1所述的配置电路，其特征在于，所述模式控制电路包括控制逻辑、三输入或门A1和二输入或非门B1；
    所述控制逻辑的第一输入端Q0和第二输入端Q1分别连接所述三输入或门A1的两个输入端，所述振荡器连接所述三输入或门A1的另外一个输入端，所述三输入或门A1的输出端连接所述正高压电荷泵和所述负高压电荷泵的时钟信号端；
    所述控制逻辑的第二输入端Q1和第三输入端Q2连接所述二输入或非门B1的两个输入端，所述二输入或非门B1的输出端连接至所述正高压双向开关电路和所述负高压双向开关电路以控制通断；
    当所述模式控制电路通过所述控制逻辑获取到用于指示所述flash型FPGA进入外部监控模式的第二模式调整信号时，所述控制逻辑的第一输入端Q0和第二输入端Q1均输出低电平，所述控制逻辑的第三输入端Q2输出高电平，所述三输入或门A1的输出端输出所述振荡器提供的时钟信号，所述二输入或非门B1输出低电平有效的开关控制信号使得所述正高压双向开关电路和所述负高压双向开关电路均导通；
    当所述模式控制电路通过所述控制逻辑获取到用于指示所述flash型FPGA进入外部配置模式的第三模式调整信号时，所述控制逻辑的第一输入端Q0和第二输入端Q1均输出高电平，所述控制逻辑的第三输入端Q2输出低电平，所述三输入或门A1的输出端恒定输出高电平以关断所述振荡器提供的时钟信号，所述二输入或非门B1输出低电平有效的开关控制信号使得所述正高压双向开关电路和所述负高压双向开关电路均导通。
  5. 根据权利要求4所述的配置电路，其特征在于，所述模式控制电路通过所述flash型FPGA的JTAG的TDI端子和TRST端子获取所述模式调整信号，所述控制逻辑包括三个移位寄存器dff00、dff01、dff02以及三个控制寄存器dff10、dff11、dff12，其中：
    dff00的D端连接所述TDI端子，dff00的Q端连接dff10的D端，dff10的Q端作为所述控制逻辑的第一输入端Q0；dff00的Q端还连接dff01的D端，dff01的Q端连接dff11的D端，dff11的Q端作为所述控制逻辑的第二输入端Q1；dff01的Q端还连接dff02的D端，dff02的Q端连接dff12的D端，dff12的Q端作为所述控制逻辑的第三输入端Q2；dff00、dff01、dff02、dff10、dff11和dff12的RST端均连接所述TRST端子；
    dff00、dff01、dff02的CLK端均连接所述flash型FPGA的JTAG的TAP状态机发出的一路数据移位时钟信号SHIFT_CK ，dff10、dff11和dff12的CLK端均连接所述flash型FPGA的JTAG的TAP状态机发出的另一路数据更新时钟信号UPDATE_CK。
  6. 根据权利要求1所述的配置电路，其特征在于，所述正高压双向开关电路包括PMOS管P3和P10以及第一正电平转换电路和第二正电平转换电路，P3的源极连接所述正高压电荷泵的正高压输出端，P3的漏极连接P10的源极，P10的漏极连接所述正高压外部监控端口；
    所述第一正电平转换电路的输入端获取所述模式控制电路输出的开关控制信号、输出端连接P3的栅极，所述第一正电平转换电路的供电端连接所述正高压电荷泵的正高压输出端；
    所述第二正电平转换电路的输入端获取所述模式控制电路输出的开关控制信号、输出端连接P10的栅极，所述第二正电平转换电路的供电端连接所述正高压外部监控端口；
    所述模式控制电路输出有效电平的开关控制信号时，所述第一正电平转换电路和所述第二正电平转换电路均输出低电平，P3和P10均导通使得所述正高压双向开关电路导通，否则所述正高压双向开关电路断开。
  7. 根据权利要求6所述的配置电路，其特征在于，所述开关控制信号低电平有效，所述第一正电平转换电路和所述第二正电平转换电路的电路结构相同，在每个正电平转换电路中，PMOS管P1的源极和PMOS管P2的源极相连并连接所述正电平转换电路的供电端，P1的漏极连接NMOS管N4的漏极和P2的栅极，P2的漏极连接NMOS管N5的漏极和P1的栅极，N4的源极接地，N5的源极接地，N4的栅极连接所述正电平转换电路的输入端，所述正电平转换电路的输入端还通过反相器I3连接N5的栅极，N5的漏极还连接所述正电平转换电路的输出端。
  8. 根据权利要求1所述的配置电路，其特征在于，所述负高压双向开关电路包括NMOS管N14和N19以及第一负电平转换电路和第二负电平转换电路，N19的源极连接所述负高压电荷泵的负高压输出端，N19的漏极连接N14的源极，N14的漏极连接所述负高压外部监控端口；
    所述模式控制电路输出的开关控制信号通过反相器提供给所述第一负电平转换电路的输入端和所述第二负电平转换电路的输入端，所述第一负电平转换电路的输出端连接N19的栅极，所述第一负电平转换电路的供电端连接所述负高压电荷泵的负高压输出端；
    所述第二负电平转换电路的输出端连接N14的栅极，所述第二负电平转换电路的供电端连接所述负高压外部监控端口；
    所述模式控制电路输出有效电平的开关控制信号时，所述第一负电平转换电路和所述第二负电平转换电路均输出高电平，N19和N14均导通使得所述负高压双向开关电路导通，否则所述负高压双向开关电路断开。
  9. 根据权利要求8所述的配置电路，其特征在于，所述开关控制信号低电平有效，所述第一负电平转换电路和所述第二负电平转换电路的电路结构相同，在每个负电平转换电路中，NMOS管N12的源极和NMOS管N13的源极相连并连接所述负电平转换电路的供电端，N12的漏极连接PMOS管P11的漏极和N13的栅极，N13的漏极连接PMOS管P12的漏极和N12的栅极，P11的源极和P12的源极相连并连接芯片电压VDD，P11的栅极连接所述负电平转换电路的输入端，所述负电平转换电路的输入端还通过反相器连接P12的栅极，N13的漏极作为所述负电平转换电路的输出端。
  10. 根据权利要求1所述的配置电路，其特征在于，当所述模式控制电路获取到用于指示所述flash型FPGA进入默认工作模式的第一模式调整信号时，所述模式控制电路控制所述振荡器与所述正高压电荷泵和所述负高压电荷泵的时钟信号端之间的通路导通，并输出无效电平的开关控制信号以控制所述正高压双向开关电路和所述负高压双向开关电路断开，所述正高压电荷泵提供的正高压通过所述电压提供电路的正输出端输出，所述负高压电荷泵提供的负高压通过所述电压提供电路的负输出端输出。
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