US20200372939A1 - Memory with High-Speed and Area-Efficient Read Path - Google Patents
Memory with High-Speed and Area-Efficient Read Path Download PDFInfo
- Publication number
- US20200372939A1 US20200372939A1 US16/421,365 US201916421365A US2020372939A1 US 20200372939 A1 US20200372939 A1 US 20200372939A1 US 201916421365 A US201916421365 A US 201916421365A US 2020372939 A1 US2020372939 A1 US 2020372939A1
- Authority
- US
- United States
- Prior art keywords
- transistor
- signal
- bit decision
- read path
- data latch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000015654 memory Effects 0.000 title claims abstract description 38
- 230000000295 complement effect Effects 0.000 claims description 20
- 230000004044 response Effects 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 13
- 229910044991 metal oxide Inorganic materials 0.000 claims description 3
- 150000004706 metal oxides Chemical class 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 3
- 230000001413 cellular effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
- G11C29/816—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout for an application-specific layout
- G11C29/824—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout for an application-specific layout for synchronous memories
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/419—Read-write [R-W] circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/84—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability
- G11C29/846—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability by choosing redundant lines at an output stage
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/84—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability
- G11C29/848—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability by adjacent switching
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/065—Differential amplifiers of latching type
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1039—Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/106—Data output latches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1069—I/O lines read out arrangements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
Definitions
- This application relates to memories, and more particularly to an improved memory read path.
- a sense amplifier makes a bit decision for an accessed bitcell during a read operation. But the output of the sense amplifier is only valid during a sense enable period, so the sense amplifier typically drives a sense mixing stage that passes the bit decision from the sense amplifier only while a sense enable signal is asserted.
- a redundancy shift stage can selectively shift the output of the sense mixing stage to a redundant column. Should there be no redundancy shift, the redundancy shift stage drives a data latch for latching the bit decision.
- the memory read path thus typically includes a level shifter to level shift the latched bit decision from the data latch from the memory power domain into the core logic power domain.
- a data output driver then drives the level-shifted bit decision to the core logic.
- a memory read path includes an integrated sense mixing and redundancy shift stage having a first transistor.
- a logic circuit such as a logic gate processes a sense enable signal and also a redundancy shift signal to produce a combined sense enable and shift redundancy signal that is asserted only when the sense enable signal is asserted when no redundancy shift is performed.
- the combined sense enable and shift redundancy signal controls a switching of the first transistor so that the first transistor conducts when the sense enable signal is asserted in the absence of redundancy shifting.
- the first transistor couples between a sense amplifier and a data latch for the read path.
- the sense amplifier senses a bit from a bitcell to make a bit decision while the sense enable signal is asserted. Should there be no redundancy shift, the sense amplifier can then drive a bit decision though the switched-on first transistor so that the bit decision can be latched in the data latch.
- the mixing of the redundancy shift signal and the sense enable signal by the logic gate to produce the combined sense enable signal and redundancy shift signal is quite advantageous as the resulting control of the first transistor produces relatively little delay in the conduction of the bit decision from the sense amplifier to the data latch.
- the first transistor is also relatively compact.
- the data latch is integrated with a level shifter to shift the latched bit decision from a memory domain power supply voltage to an output domain power supply voltage (for example, a core logic domain power supply voltage).
- an output domain power supply voltage for example, a core logic domain power supply voltage
- FIG. 1 illustrates a memory read path in accordance with an aspect of the disclosure.
- FIG. 2A is a circuit diagram for the sense amplifier and the integrated sense mixing and redundancy shift stage in the memory read path of FIG. 1 in accordance with an aspect of the disclosure.
- FIG. 2B is a circuit diagram for the integrated data latch and level shifter and also for the data output driver in the memory read path of FIG. 1 in accordance with an aspect of the disclosure.
- FIG. 3 is a flowchart of a method of operation for a memory read path in accordance with an aspect of the disclosure.
- FIG. 4 illustrates some example electronic systems each incorporating a memory having a read path in accordance with an aspect of the disclosure.
- sense amplifier 105 senses an accessed bitcell (not illustrated) during a read operation to output a bit decision signal.
- an integrated sense mixing and redundancy shift stage 110 processes the bit decision signal from sense amplifier 105 .
- sense mixing and redundancy shift stage 110 includes a first transistor such an n-type metal-oxide semiconductor (NMOS) first transistor M 2 that is switched on in response to a combined sense enable and redundancy shift signal (Red_sel_on).
- NMOS n-type metal-oxide semiconductor
- the combined sense enable and redundancy shift signal is only asserted when both a sense enable signal (Sense_enable) and a redundancy shift-on signal (Red on) are true.
- first transistor M 2 conducts to pass the bit decision (Int_q) from sense amplifier 105 to an input node for a redundant column.
- a second transistor such as an NMOS second transistor M 3 responds to a combined sense enable and redundancy shift-off signal (Red_sel_off) that is asserted only when both the sense enable signal and a redundancy-off signal (Red_off) are both true.
- second transistor M 3 conducts to pass the bit decision signal to a combined data output latch and level shifter stage 115 .
- Sense amplifier 105 has a relatively strong drive compared to a conventional logic gate.
- the operation of the first transistor and the second transistor in sense enable and redundancy shift stage 110 is thus quite advantageous in that the sense amplifier 105 can readily drive the bit decision through the selected first or second transistor.
- the sense amplifier in a conventional read data path would drive its bit decision into logic gates within a separate sense enable mixing stage.
- the drive of the sense amplifier is thus lost as it is the logic gates that must drive the mixed bit decision to a separate redundancy shift stage that in turn would implement the redundancy shift using logic gates.
- the resulting multiple stages of logic gates not only lose the drive of the sense amplifier but also introduce delay.
- the pass transistors in sense enable and redundancy shift stage 110 introduce less delay and occupy less die space.
- sense mixing and redundancy shift stage 110 drives its processed bit decision to a level-shifting data latch 115 that latches the processed bit decision when no redundancy shift is implemented. Should there be a redundancy shift to the remainder of a read path for a redundant column (not illustrated), it would be this other column's level-shifting data latch that would receive the processed bit decision from sense mixing and redundancy shift stage 110 .
- level-shifting data latch 115 Using a single stage, level-shifting data latch 115 not only latches the processed bit decision but also level shifts the latched bit decision from a memory domain power supply voltage to an output domain such as a core logic domain power supply voltage. In this fashion, the delay and area demand from separate latching and level shifting stages such as in a conventional read path are avoided.
- a data output driver 120 that drives the latched and level-shifted bit decision from data latch and level shifter 115 completes read path 100 .
- Sense amplifier 105 and sense mixing and redundancy shift stage 110 are shown in more detail in FIG. 2A .
- Sense amplifier 105 senses a bit from a pair of bit lines b and bl and forms a bit decision signal Int_q and its complement signal Int_qb. It will be appreciated that a single-ended sense amplifier may be used in alternative embodiments.
- Sense amplifier 105 is activated by an NMOS transistor M 1 that has a source connected to ground and a drain connected to a ground node for sense amplifier 105 .
- Sense amplifier 105 will thus have power only when transistor M 1 conducts in response to an assertion of a sense enable signal (Sense_enable).
- An inverter 225 inverts a complement sense enable signal (Sense enable n) to form the sense enable signal.
- Sense amplifier 105 drives the bit decision Int_q through second transistor M 3 in sense mixing and redundancy shift stage 110 when the sense enable signal and a redundancy shift off signal (Red off) are both asserted.
- a combined sense enable and redundancy shift-off signal controls a gate of second transistor M 3 .
- a logic gate configured to perform NOR logic such as a NOR gate 220 asserts the combined sense enable and redundancy shift-off signal only when both the complement sense enable signal and a redundancy shift-on signal (Red on) are grounded.
- the complement sense enable signal is false when the sense enable signal is true.
- the redundancy shift-on signal is false when the redundancy shift-off signal is true.
- NOR gate 220 will assert the combined sense enable and redundancy shift-off signal only when both the sense enable signal and the redundancy shift-off signal are true.
- An inverter 210 inverts the bit decision signal Int_q when second transistor M 3 conducts.
- a combined sense enable and redundancy shift-on signal controls the gate of first transistor M 2 .
- a logic gate such as a NOR gate 215 asserts the combined sense enable and redundancy shift-on signal when both the complement sense enable signal and the redundancy shift-off signal are false.
- the complement sense enable signal is of course false when the sense enable signal is true.
- the redundancy shift-off signal is false when the redundancy shift-on signal is true.
- NOR gate 215 will assert the combined sense enable and redundancy shift-on signal only when both the sense enable signal and the redundancy shift-on signal are true.
- sense amplifier 105 drives the bit decision Int_q to the input node of a read path of a redundant column (not illustrated).
- Sense mixing and redundancy shift stage 110 accommodates the complement bit decision Int_qb with two analogous transistors.
- an NMOS fourth transistor M 5 passes the complement bit decision Int_qb when the combined sense enable and redundancy shift-off signal Red_sel_off is asserted.
- An inverter 205 inverts the complement bit decision Int_qb when fourth transistor M 5 conducts.
- An NMOS third transistor M 4 passes the complement bit decision Int_qb to the redundant column when the combined sense enable and redundancy shift-on signal Red_sel_on is asserted.
- Inverter 205 drives a node A with the inverted complement bit decision.
- inverter 210 drives a node B with the inverted bit decision.
- PMOS metal-oxide semiconductor
- Transistor P 1 has its source tied to the power supply node for a memory domain power supply voltage vddmx and has its drain tied to the input of inverter 205 .
- transistor P 2 has its source tied to the memory power supply node and has its drain connected to the input of inverter 210 .
- the sense enable signal drives the gates of transistors P 1 and P 2 such that both transistors P 1 and P 2 will conduct when the sense enable signal is not asserted. Both nodes A and B are thus discharged while the sense enable signal is not asserted.
- Nodes A and B form a first input node and a second input node, respectively for level-shifting data latch 115 as shown in FIG. 2B .
- Node A couples to a gate of an NMOS transistor M 6 .
- the source of transistor M 6 couples to ground through an NMOS transistor M 10 that is controlled by an active low sleep signal for the core logic power domain (Slp_peri_cx).
- the active low sleep signal will thus be asserted to a core power domain voltage vddcx while the core logic power domain is active (not in sleep mode).
- the bit decision Int_q is a logic true signal.
- the complement bit decision Int_qb will thus be discharged such that node A is asserted to the memory power domain voltage vddmx whereas node B remains discharged.
- the drain of transistor M 6 will then be discharged to ground.
- the drain of transistor M 6 connects to a gate of a PMOS transistor P 6 and to a gate of an NMOS transistor M 9 .
- the source of transistor M 9 couples to ground through an NMOS transistor M 11 .
- the active low sleep signal drives the gate of transistor M 11 so that transistor M 11 is switched on during normal operation.
- Transistor P 6 has its source connected to a power supply node for the core logic domain power supply voltage vddcx.
- the drain of transistor P 6 connects to a source of a PMOS transistor P 5 that has its drain connected to the drain of transistor M 9 . Since the node B connects to a gate for transistor P 5 , transistor P 5 will be on. The drain of transistor P 5 will thus be charged to the core logic domain power supply voltage vddcx.
- Transistor P 6 and M 9 are thus coupled in series through the switched-on transistor P 5 to form an inverter that inverts the discharged drain voltage of transistor M 6 into the charged drain voltage of transistor P 6 (and in turn at the drain of transistor P 5 ).
- the drain of transistor P 5 connects to the gate of an NMOS transistor M 7 and to a gate of a PMOS transistor P 4 .
- Transistor M 7 couples to ground through transistor M 10 .
- the drain of transistor M 7 connects to the drain of transistor M 6 .
- the charged drain of transistor P 5 thus switches on transistor M 7 to enforce the grounding of the drain of transistors M 6 and M 7 . In turn, this grounding of the drain of transistor M 7 reinforces the switching on of transistor P 6 .
- the inverter formed by transistors P 6 and M 9 (through the switched-on transistor P 5 ) thus form a latch with transistor M 7 to latch the grounding of the drain of transistor M 7 and the charging of the drain of transistor M 9 .
- Transistor P 4 has its source connected to the power supply node for the core logic domain power supply voltage vddcx.
- the drain of transistor P 4 connects to a source of a transistor P 3 that has its drain connected to the drains of transistors M 6 and M 7 .
- the node A connects to a gate of transistor P 3 so that transistor P 3 is switched on in response to the grounding of node A.
- Transistors P 4 and M 7 are thus coupled in series through the switched-on transistor P 3 to form an inverter.
- the node B couples to a gate of an NMOS transistor M 8 .
- Transistor M 8 will thus be switched on in response to the assertion of the node B voltage whereas transistor P 5 is switched off.
- the drain of transistor M 8 connects to the drain of transistor P 5 whereas the source of transistor M 8 couples to ground through transistor M 11 . Since transistor M 8 is switched on, the drain of transistor M 8 will thus be discharged to ground.
- the discharged drain of transistor M 8 drives the gate of the inverter formed by transistors P 4 and M 7 (transistor P 3 being switched on).
- the charged output of this inverter drives the gate of transistor M 9 .
- Transistor M 9 will thus be switched on to reinforce the grounding of the drain of transistor M 8 , which in turn reinforces the charging of the drain of transistor P 3 .
- the inverter formed by transistors M 7 and P 4 thus forms a latch with transistor M 9 to latch the grounding of the drain of transistor M 9 and the charging of the drain of transistor M 7 .
- the drains of transistor P 3 and transistor M 7 drive a gate of a PMOS transistor P 7 and an NMOS transistor M 13 in data output driver 120 .
- the source of transistor M 13 connects to ground whereas its drain forms an output node DOUT for data output driver 120 .
- Transistor P 7 has its source connected to the power supply node for the core logic domain power supply vddcx and its drain connected to a source of a PMOS transistor P 8 that has a drain connected to the output node DOUT.
- An NMOS transistor M 12 has its drain connected to the output node and a source tied to ground.
- the output node B connects to a gate for transistor M 12 and to a gate for transistor P 8 .
- bit decision lnt_q be a logic false signal during a no-redundancy-shift sense enable period
- node B will be charged to the memory domain power supply voltage vddmx.
- Transistor M 12 will thus be switched on to ground the output node DOUT.
- Transistor P 8 is switched off.
- the low state for the bit decision Int_q causes the drain of transistor M 7 to be charged to the core logic domain power supply voltage vddcx.
- Transistor M 13 will thus also be switched on to reinforce the grounding of the output node DOUT whereas transistor P 7 is switched off
- node B is discharged to switch off transistor M 12 and switch on transistor P 8 .
- the drain of transistor M 7 is also discharged, which switches off transistor M 23 and switches on transistor P 7 .
- the output node DOUT will thus be charged to the core logic domain power supply voltage vddcx should the bit decision Int_q be a logic true signal.
- a PMOS transistor P 9 is switched on during a sleep mode for the core logic domain, which causes transistor M 13 to switch on to ground the output node DOUT.
- the grounding is reinforced through an NMOS transistor M 14 that has its gate controlled by a complement (Slp_peri_cx_n) of the core logic domain sleep signal.
- the output node DOUT is thus grounded during this sleep mode.
- transistors M 10 and M 11 are also switched off during this sleep mode of operation.
- the method includes an act 300 of switching on a first transistor in response to an assertion of both a sense enable signal and a redundancy shift off signal.
- the switching on of transistor M 3 or transistor M 5 is an example of act 300 .
- the method also includes an act 305 of driving a bit decision through the switched-on first transistor from a sense amplifier to a data latch.
- the conduction of the bit decision Int_q through transistor M 3 to level-shifting data latch 115 or the conduction of complement bit decision Int_qb through transistor M 5 to level-shifting data latch 115 is an example of act 305 .
- the method includes an act 310 of latching the bit decision in the data latch.
- the latching of the bit decision Int_q in level-shifting data latch 115 is an example of act 310 .
- a memory with a read path as disclosed herein may be incorporated into a wide variety of electronic systems.
- a cell phone 400 , a laptop 405 , and a tablet PC 410 may all include a memory having a read path in accordance with the disclosure.
- Other exemplary electronic systems such as a music player, a video player, a communication device, and a personal computer may also be configured with memories constructed in accordance with the disclosure.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
Description
- This application relates to memories, and more particularly to an improved memory read path.
- In a conventional memory such as a static random-access memory (SRAM), a sense amplifier makes a bit decision for an accessed bitcell during a read operation. But the output of the sense amplifier is only valid during a sense enable period, so the sense amplifier typically drives a sense mixing stage that passes the bit decision from the sense amplifier only while a sense enable signal is asserted. To implement column redundancy in case of errors, a redundancy shift stage can selectively shift the output of the sense mixing stage to a redundant column. Should there be no redundancy shift, the redundancy shift stage drives a data latch for latching the bit decision.
- It is also conventional for a memory to have an independent power supply voltage from the power supply voltage for the core logic that will receive the bit decision during the read operation. The memory read path thus typically includes a level shifter to level shift the latched bit decision from the data latch from the memory power domain into the core logic power domain. A data output driver then drives the level-shifted bit decision to the core logic.
- The various stages in the memory read path delay the read operation speed and occupy die space. There is thus a need in the art for memories with an improved data read path that reduces power consumption and increases area efficiency.
- A memory read path is provided that includes an integrated sense mixing and redundancy shift stage having a first transistor. A logic circuit such as a logic gate processes a sense enable signal and also a redundancy shift signal to produce a combined sense enable and shift redundancy signal that is asserted only when the sense enable signal is asserted when no redundancy shift is performed. The combined sense enable and shift redundancy signal controls a switching of the first transistor so that the first transistor conducts when the sense enable signal is asserted in the absence of redundancy shifting.
- The first transistor couples between a sense amplifier and a data latch for the read path. During a read operation, the sense amplifier senses a bit from a bitcell to make a bit decision while the sense enable signal is asserted. Should there be no redundancy shift, the sense amplifier can then drive a bit decision though the switched-on first transistor so that the bit decision can be latched in the data latch.
- The mixing of the redundancy shift signal and the sense enable signal by the logic gate to produce the combined sense enable signal and redundancy shift signal is quite advantageous as the resulting control of the first transistor produces relatively little delay in the conduction of the bit decision from the sense amplifier to the data latch. The first transistor is also relatively compact.
- To further increase the speed and area savings for the read path, the data latch is integrated with a level shifter to shift the latched bit decision from a memory domain power supply voltage to an output domain power supply voltage (for example, a core logic domain power supply voltage). The resulting memory data path is thus advantageously fast and compact.
- These and additional advantages may be better appreciated through the following detailed description.
-
FIG. 1 illustrates a memory read path in accordance with an aspect of the disclosure. -
FIG. 2A is a circuit diagram for the sense amplifier and the integrated sense mixing and redundancy shift stage in the memory read path ofFIG. 1 in accordance with an aspect of the disclosure. -
FIG. 2B is a circuit diagram for the integrated data latch and level shifter and also for the data output driver in the memory read path ofFIG. 1 in accordance with an aspect of the disclosure. -
FIG. 3 is a flowchart of a method of operation for a memory read path in accordance with an aspect of the disclosure. -
FIG. 4 illustrates some example electronic systems each incorporating a memory having a read path in accordance with an aspect of the disclosure. - Embodiments of the present disclosure and their advantages are best understood by referring to the detailed description that follows. It should be appreciated that like reference numerals are used to identify like elements illustrated in one or more of the figures.
- Turning now to the drawings, an improved
memory read path 100 is shown inFIG. 1 . Asense amplifier 105 senses an accessed bitcell (not illustrated) during a read operation to output a bit decision signal. To increase operating speed and density, an integrated sense mixing andredundancy shift stage 110 processes the bit decision signal fromsense amplifier 105. As will be explained further herein with reference toFIG. 2A , sense mixing andredundancy shift stage 110 includes a first transistor such an n-type metal-oxide semiconductor (NMOS) first transistor M2 that is switched on in response to a combined sense enable and redundancy shift signal (Red_sel_on). The combined sense enable and redundancy shift signal is only asserted when both a sense enable signal (Sense_enable) and a redundancy shift-on signal (Red on) are true. In that case, first transistor M2 conducts to pass the bit decision (Int_q) fromsense amplifier 105 to an input node for a redundant column. A second transistor such as an NMOS second transistor M3 responds to a combined sense enable and redundancy shift-off signal (Red_sel_off) that is asserted only when both the sense enable signal and a redundancy-off signal (Red_off) are both true. In that case, second transistor M3 conducts to pass the bit decision signal to a combined data output latch andlevel shifter stage 115. -
Sense amplifier 105 has a relatively strong drive compared to a conventional logic gate. The operation of the first transistor and the second transistor in sense enable andredundancy shift stage 110 is thus quite advantageous in that thesense amplifier 105 can readily drive the bit decision through the selected first or second transistor. In contrast, the sense amplifier in a conventional read data path would drive its bit decision into logic gates within a separate sense enable mixing stage. The drive of the sense amplifier is thus lost as it is the logic gates that must drive the mixed bit decision to a separate redundancy shift stage that in turn would implement the redundancy shift using logic gates. The resulting multiple stages of logic gates not only lose the drive of the sense amplifier but also introduce delay. In contrast, the pass transistors in sense enable andredundancy shift stage 110 introduce less delay and occupy less die space. - Referring again to
FIG. 1 , sense mixing andredundancy shift stage 110 drives its processed bit decision to a level-shiftingdata latch 115 that latches the processed bit decision when no redundancy shift is implemented. Should there be a redundancy shift to the remainder of a read path for a redundant column (not illustrated), it would be this other column's level-shifting data latch that would receive the processed bit decision from sense mixing andredundancy shift stage 110. Using a single stage, level-shiftingdata latch 115 not only latches the processed bit decision but also level shifts the latched bit decision from a memory domain power supply voltage to an output domain such as a core logic domain power supply voltage. In this fashion, the delay and area demand from separate latching and level shifting stages such as in a conventional read path are avoided. Adata output driver 120 that drives the latched and level-shifted bit decision from data latch andlevel shifter 115 completes readpath 100. -
Sense amplifier 105 and sense mixing andredundancy shift stage 110 are shown in more detail inFIG. 2A .Sense amplifier 105 senses a bit from a pair of bit lines b and bl and forms a bit decision signal Int_q and its complement signal Int_qb. It will be appreciated that a single-ended sense amplifier may be used in alternative embodiments.Sense amplifier 105 is activated by an NMOS transistor M1 that has a source connected to ground and a drain connected to a ground node forsense amplifier 105.Sense amplifier 105 will thus have power only when transistor M1 conducts in response to an assertion of a sense enable signal (Sense_enable). Aninverter 225 inverts a complement sense enable signal (Sense enable n) to form the sense enable signal. -
Sense amplifier 105 drives the bit decision Int_q through second transistor M3 in sense mixing andredundancy shift stage 110 when the sense enable signal and a redundancy shift off signal (Red off) are both asserted. In particular, a combined sense enable and redundancy shift-off signal (Red_sel_off) controls a gate of second transistor M3. A logic gate configured to perform NOR logic such as aNOR gate 220 asserts the combined sense enable and redundancy shift-off signal only when both the complement sense enable signal and a redundancy shift-on signal (Red on) are grounded. The complement sense enable signal is false when the sense enable signal is true. Similarly, the redundancy shift-on signal is false when the redundancy shift-off signal is true. Thus, NORgate 220 will assert the combined sense enable and redundancy shift-off signal only when both the sense enable signal and the redundancy shift-off signal are true. Aninverter 210 inverts the bit decision signal Int_q when second transistor M3 conducts. - If the redundancy shift-on signal is true while the sense enable signal is asserted, second transistor M3 will be shut off but first transistor M2 will conduct. A combined sense enable and redundancy shift-on signal (Red_sel_on) controls the gate of first transistor M2. A logic gate such as a NOR
gate 215 asserts the combined sense enable and redundancy shift-on signal when both the complement sense enable signal and the redundancy shift-off signal are false. The complement sense enable signal is of course false when the sense enable signal is true. Similarly, the redundancy shift-off signal is false when the redundancy shift-on signal is true. Thus, NORgate 215 will assert the combined sense enable and redundancy shift-on signal only when both the sense enable signal and the redundancy shift-on signal are true. With first transistor M2 conducting,sense amplifier 105 drives the bit decision Int_q to the input node of a read path of a redundant column (not illustrated). - Sense mixing and
redundancy shift stage 110 accommodates the complement bit decision Int_qb with two analogous transistors. In particular, an NMOS fourth transistor M5 passes the complement bit decision Int_qb when the combined sense enable and redundancy shift-off signal Red_sel_off is asserted. Aninverter 205 inverts the complement bit decision Int_qb when fourth transistor M5 conducts. An NMOS third transistor M4 passes the complement bit decision Int_qb to the redundant column when the combined sense enable and redundancy shift-on signal Red_sel_on is asserted. -
Inverter 205 drives a node A with the inverted complement bit decision. Similarly,inverter 210 drives a node B with the inverted bit decision. Prior to the sense enable period, both nodes A and B are discharged through the action of a pair of p-type metal-oxide semiconductor (PMOS) transistors P1 and P2. Transistor P1 has its source tied to the power supply node for a memory domain power supply voltage vddmx and has its drain tied to the input ofinverter 205. Similarly, transistor P2 has its source tied to the memory power supply node and has its drain connected to the input ofinverter 210. The sense enable signal drives the gates of transistors P1 and P2 such that both transistors P1 and P2 will conduct when the sense enable signal is not asserted. Both nodes A and B are thus discharged while the sense enable signal is not asserted. - Nodes A and B form a first input node and a second input node, respectively for level-shifting
data latch 115 as shown inFIG. 2B . Node A couples to a gate of an NMOS transistor M6. The source of transistor M6 couples to ground through an NMOS transistor M10 that is controlled by an active low sleep signal for the core logic power domain (Slp_peri_cx). The active low sleep signal will thus be asserted to a core power domain voltage vddcx while the core logic power domain is active (not in sleep mode). Suppose that during a no-redundancy-shift sense enable period that the bit decision Int_q is a logic true signal. The complement bit decision Int_qb will thus be discharged such that node A is asserted to the memory power domain voltage vddmx whereas node B remains discharged. The drain of transistor M6 will then be discharged to ground. The drain of transistor M6 connects to a gate of a PMOS transistor P6 and to a gate of an NMOS transistor M9. The source of transistor M9 couples to ground through an NMOS transistor M11. The active low sleep signal drives the gate of transistor M11 so that transistor M11 is switched on during normal operation. Transistor P6 has its source connected to a power supply node for the core logic domain power supply voltage vddcx. The drain of transistor P6 connects to a source of a PMOS transistor P5 that has its drain connected to the drain of transistor M9. Since the node B connects to a gate for transistor P5, transistor P5 will be on. The drain of transistor P5 will thus be charged to the core logic domain power supply voltage vddcx. - Transistor P6 and M9 are thus coupled in series through the switched-on transistor P5 to form an inverter that inverts the discharged drain voltage of transistor M6 into the charged drain voltage of transistor P6 (and in turn at the drain of transistor P5). The drain of transistor P5 connects to the gate of an NMOS transistor M7 and to a gate of a PMOS transistor P4. Transistor M7 couples to ground through transistor M10. The drain of transistor M7 connects to the drain of transistor M6. The charged drain of transistor P5 thus switches on transistor M7 to enforce the grounding of the drain of transistors M6 and M7. In turn, this grounding of the drain of transistor M7 reinforces the switching on of transistor P6. The inverter formed by transistors P6 and M9 (through the switched-on transistor P5) thus form a latch with transistor M7 to latch the grounding of the drain of transistor M7 and the charging of the drain of transistor M9.
- Should the bit decision Int_q be a logic false signal during a no-redundancy-shift sense enable period, node B will be charged to the memory domain power supply voltage vddmx. Conversely node A will be discharged to ground. Transistor P4 has its source connected to the power supply node for the core logic domain power supply voltage vddcx. The drain of transistor P4 connects to a source of a transistor P3 that has its drain connected to the drains of transistors M6 and M7. The node A connects to a gate of transistor P3 so that transistor P3 is switched on in response to the grounding of node A. Transistors P4 and M7 are thus coupled in series through the switched-on transistor P3 to form an inverter. The node B couples to a gate of an NMOS transistor M8. Transistor M8 will thus be switched on in response to the assertion of the node B voltage whereas transistor P5 is switched off. The drain of transistor M8 connects to the drain of transistor P5 whereas the source of transistor M8 couples to ground through transistor M11. Since transistor M8 is switched on, the drain of transistor M8 will thus be discharged to ground. The discharged drain of transistor M8 drives the gate of the inverter formed by transistors P4 and M7 (transistor P3 being switched on). The charged output of this inverter drives the gate of transistor M9. Transistor M9 will thus be switched on to reinforce the grounding of the drain of transistor M8, which in turn reinforces the charging of the drain of transistor P3. The inverter formed by transistors M7 and P4 thus forms a latch with transistor M9 to latch the grounding of the drain of transistor M9 and the charging of the drain of transistor M7.
- The drains of transistor P3 and transistor M7 drive a gate of a PMOS transistor P7 and an NMOS transistor M13 in
data output driver 120. The source of transistor M13 connects to ground whereas its drain forms an output node DOUT fordata output driver 120. Transistor P7 has its source connected to the power supply node for the core logic domain power supply vddcx and its drain connected to a source of a PMOS transistor P8 that has a drain connected to the output node DOUT. An NMOS transistor M12 has its drain connected to the output node and a source tied to ground. The output node B connects to a gate for transistor M12 and to a gate for transistor P8. As discussed herein, should bit decision lnt_q be a logic false signal during a no-redundancy-shift sense enable period, node B will be charged to the memory domain power supply voltage vddmx. Transistor M12 will thus be switched on to ground the output node DOUT. Transistor P8 is switched off As also discussed herein, the low state for the bit decision Int_q causes the drain of transistor M7 to be charged to the core logic domain power supply voltage vddcx. Transistor M13 will thus also be switched on to reinforce the grounding of the output node DOUT whereas transistor P7 is switched off - If the bit decision Int_q is a logic true signal, node B is discharged to switch off transistor M12 and switch on transistor P8. The drain of transistor M7 is also discharged, which switches off transistor M23 and switches on transistor P7. The output node DOUT will thus be charged to the core logic domain power supply voltage vddcx should the bit decision Int_q be a logic true signal.
- A PMOS transistor P9 is switched on during a sleep mode for the core logic domain, which causes transistor M13 to switch on to ground the output node DOUT. The grounding is reinforced through an NMOS transistor M14 that has its gate controlled by a complement (Slp_peri_cx_n) of the core logic domain sleep signal. The output node DOUT is thus grounded during this sleep mode. Similarly, transistors M10 and M11 are also switched off during this sleep mode of operation.
- A method of operation for a memory read path will now be discussed with regard to the flowchart of
FIG. 3 . The method includes anact 300 of switching on a first transistor in response to an assertion of both a sense enable signal and a redundancy shift off signal. The switching on of transistor M3 or transistor M5 is an example ofact 300. The method also includes anact 305 of driving a bit decision through the switched-on first transistor from a sense amplifier to a data latch. The conduction of the bit decision Int_q through transistor M3 to level-shiftingdata latch 115 or the conduction of complement bit decision Int_qb through transistor M5 to level-shiftingdata latch 115 is an example ofact 305. Finally, the method includes anact 310 of latching the bit decision in the data latch. The latching of the bit decision Int_q in level-shiftingdata latch 115 is an example ofact 310. - A memory with a read path as disclosed herein may be incorporated into a wide variety of electronic systems. For example, as shown in
FIG. 4 , acell phone 400, alaptop 405, and atablet PC 410 may all include a memory having a read path in accordance with the disclosure. Other exemplary electronic systems such as a music player, a video player, a communication device, and a personal computer may also be configured with memories constructed in accordance with the disclosure. - As those of some skill in this art will by now appreciate and depending on the particular application at hand, many modifications, substitutions and variations can be made in and to the materials, apparatus, configurations and methods of use of the devices of the present disclosure without departing from the scope thereof. In light of this, the scope of the present disclosure should not be limited to that of the particular embodiments illustrated and described herein, as they are merely by way of some examples thereof, but rather, should be fully commensurate with that of the claims appended hereafter and their functional equivalents.
Claims (20)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US16/421,365 US10854246B1 (en) | 2019-05-23 | 2019-05-23 | Memory with high-speed and area-efficient read path |
PCT/US2020/034378 WO2020237211A1 (en) | 2019-05-23 | 2020-05-22 | Memory with High-Speed and Area-Efficient Read Path |
US17/039,742 US11315609B2 (en) | 2019-05-23 | 2020-09-30 | Memory with high-speed and area-efficient read path |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US16/421,365 US10854246B1 (en) | 2019-05-23 | 2019-05-23 | Memory with high-speed and area-efficient read path |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US17/039,742 Division US11315609B2 (en) | 2019-05-23 | 2020-09-30 | Memory with high-speed and area-efficient read path |
Publications (2)
Publication Number | Publication Date |
---|---|
US20200372939A1 true US20200372939A1 (en) | 2020-11-26 |
US10854246B1 US10854246B1 (en) | 2020-12-01 |
Family
ID=71078648
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US16/421,365 Active US10854246B1 (en) | 2019-05-23 | 2019-05-23 | Memory with high-speed and area-efficient read path |
US17/039,742 Active US11315609B2 (en) | 2019-05-23 | 2020-09-30 | Memory with high-speed and area-efficient read path |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US17/039,742 Active US11315609B2 (en) | 2019-05-23 | 2020-09-30 | Memory with high-speed and area-efficient read path |
Country Status (2)
Country | Link |
---|---|
US (2) | US10854246B1 (en) |
WO (1) | WO2020237211A1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20220391335A1 (en) * | 2021-06-07 | 2022-12-08 | AyDeeKay LLC dba Indie Semiconductor | Interface Module with Low-Latency Communication of Electrical Signals Between Power Domains |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10854246B1 (en) | 2019-05-23 | 2020-12-01 | Qualcomm Incorporated | Memory with high-speed and area-efficient read path |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100273263B1 (en) * | 1997-12-27 | 2001-01-15 | 김영환 | Repair control circuit |
US6310805B1 (en) * | 2000-03-07 | 2001-10-30 | Advanced Micro Devices, Inc. | Architecture for a dual-bank page mode memory with redundancy |
US6714467B2 (en) * | 2002-03-19 | 2004-03-30 | Broadcom Corporation | Block redundancy implementation in heirarchical RAM's |
JP2003297083A (en) * | 2002-03-29 | 2003-10-17 | Mitsubishi Electric Corp | Semiconductor memory device |
KR20030095874A (en) * | 2002-06-15 | 2003-12-24 | 삼성전자주식회사 | Redundancy circuit of semicon memory device |
JP4383028B2 (en) * | 2002-08-15 | 2009-12-16 | Necエレクトロニクス株式会社 | Semiconductor memory device and control method thereof |
JP4467565B2 (en) * | 2004-02-20 | 2010-05-26 | スパンション エルエルシー | Semiconductor memory device and method for controlling semiconductor memory device |
US6985391B2 (en) * | 2004-05-07 | 2006-01-10 | Micron Technology, Inc. | High speed redundant data sensing method and apparatus |
JP4387250B2 (en) * | 2004-06-23 | 2009-12-16 | パナソニック株式会社 | Semiconductor memory device |
JP2008299962A (en) * | 2007-05-31 | 2008-12-11 | Oki Electric Ind Co Ltd | Semiconductor storage device |
KR20100036596A (en) * | 2008-09-30 | 2010-04-08 | 삼성전자주식회사 | Semiconductor memeory device having open bit line architecture removing edge dummy cells |
US9124276B2 (en) * | 2012-12-20 | 2015-09-01 | Qualcomm Incorporated | Sense amplifier including a level shifter |
CN104813404B (en) * | 2012-12-27 | 2017-12-26 | 英特尔公司 | For reducing the SRAM bit lines and writing-in aid and method and dual input level shifter of dynamic power and peak point current |
US9905316B2 (en) * | 2016-08-01 | 2018-02-27 | Qualcomm Incorporated | Efficient sense amplifier shifting for memory redundancy |
US10147492B1 (en) * | 2017-11-27 | 2018-12-04 | Flashsilicon Incorporation | MOSFET threshold voltage sensing scheme for non-volatile memory |
US10854246B1 (en) | 2019-05-23 | 2020-12-01 | Qualcomm Incorporated | Memory with high-speed and area-efficient read path |
-
2019
- 2019-05-23 US US16/421,365 patent/US10854246B1/en active Active
-
2020
- 2020-05-22 WO PCT/US2020/034378 patent/WO2020237211A1/en active Application Filing
- 2020-09-30 US US17/039,742 patent/US11315609B2/en active Active
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20220391335A1 (en) * | 2021-06-07 | 2022-12-08 | AyDeeKay LLC dba Indie Semiconductor | Interface Module with Low-Latency Communication of Electrical Signals Between Power Domains |
US11921651B2 (en) * | 2021-06-07 | 2024-03-05 | AyDeeKay LLC | Interface module with low-latency communication of electrical signals between power domains |
Also Published As
Publication number | Publication date |
---|---|
US11315609B2 (en) | 2022-04-26 |
US20210020206A1 (en) | 2021-01-21 |
WO2020237211A1 (en) | 2020-11-26 |
US10854246B1 (en) | 2020-12-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7453300B2 (en) | MTCMOS flip-flop, circuit including the MTCMOS flip-flop, and method of forming the MTCMOS flip-flop | |
US20090066386A1 (en) | Mtcmos flip-flop with retention function | |
US7327630B2 (en) | Memory cell power switching circuit in semiconductor memory device and method for applying memory cell power voltage | |
US8890573B2 (en) | Clock gating latch, method of operation thereof and integrated circuit employing the same | |
US7245152B2 (en) | Voltage-level shifter | |
US6842046B2 (en) | Low-to-high voltage conversion method and system | |
US7463545B2 (en) | System and method for reducing latency in a memory array decoder circuit | |
KR101651886B1 (en) | Sense amplifier including a level shifter | |
US10446196B1 (en) | Flexible power sequencing for dual-power memory | |
US11315609B2 (en) | Memory with high-speed and area-efficient read path | |
US7577013B2 (en) | Storage units and register file using the same | |
US6437604B1 (en) | Clocked differential cascode voltage switch with pass gate logic | |
KR100714021B1 (en) | Muxing circuit for reducing output delay time of output signals thereof | |
KR100311973B1 (en) | Logic interface circuit and semiconductor memory device using this circuit | |
JPH08306189A (en) | Sram memory cell with decreased inside cell voltage | |
JP2007060582A (en) | Logic circuit, semiconductor integrated circuit and portable terminal device | |
KR100346002B1 (en) | Register and latch circuits | |
US6300801B1 (en) | Or gate circuit and state machine using the same | |
JP3550168B2 (en) | Semiconductor storage device | |
CN116959518B (en) | Self-timing circuit and static random access memory | |
KR100209747B1 (en) | Output buffer circuit | |
US11972834B2 (en) | Low power and robust level-shifting pulse latch for dual-power memories | |
US20230350477A1 (en) | Power management circuit, system-on-chip device, and method of power management | |
US6784695B1 (en) | Domino circuit topology | |
JP2000090683A (en) | Sense amplifier circuit |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
FEPP | Fee payment procedure |
Free format text: ENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: BIG.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
AS | Assignment |
Owner name: QUALCOMM INCORPORATED, CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BHASKARAN, ADITHYA;NARASIMHAN, MUKUND;MOHANTY, SHIBA NARAYAN;REEL/FRAME:049677/0429 Effective date: 20190702 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
AS | Assignment |
Owner name: QUALCOMM INCORPORATED, CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BHASKARAN, ADITHYA;NARASIMHAN, MUKUND;MOHANTY, SHIBA NARAYAN;SIGNING DATES FROM 20210301 TO 20210416;REEL/FRAME:056042/0441 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 4 |