KR20030095874A - Redundancy circuit of semicon memory device - Google Patents

Abstract

PURPOSE: A redundancy apparatus of a semiconductor memory device is provided to prevent the skew due to the length difference between a normal IO(input/output) line and a redundant IO line. CONSTITUTION: A redundancy apparatus of a semiconductor memory device includes a normal IO(input/output) line(110), a redundant IO line(120), an IO sense amplifier(130), a pair of multiplexers(150,160). The normal IO line(110) arranged at the cell array unit includes an IO line and an IOB(input/output bar) line. The redundant IO line(120) arranged at one side edge of the normal IO line(110) includes a RIO(redundant input/output) line replace with during the failure of the normal IO line(110) and a RIOB(redundant input/output bar) line. The IO sense amplifier(130) connected between the normal IO line(110) and the IOB line senses the voltage difference between the IO line and the IOB line to amplify the sensed voltage. The output of the IO sense amplifier(130) and the output of the RIO sense amplifier are inputted to the pair of multiplexers(150,160). The pair of multiplexers(150,160) read the data by selecting the output of the IO sense amplifier(130) when the normal IO line(110) is normal and by selecting the output of the RIO sense amplifier when the normal IO line(110) is fail. The redundancy apparatus is characterized in that the distance between the normal IO line(110) and the IO sense amplifier(130) is equal to that of the redundant IO line and the RIO sense amplifier.

Description

Redundancy circuit of semiconductor memory devices

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device capable of preventing skew due to a difference in length between a normal IO line and a redundant IO line.

In general, when any one of a large number of fine cells constituting a DRAM occurs, the DRAM may not function properly. In this case, the yield is improved by replacing the defective cells by using the spare memory cells installed in the DRAM in advance, and this method is called a redundancy method.

In particular, in such a redundancy method, redundancy cells of memory are installed for each sub array block. For example, in case of 16M DRAM, spare rows and columns are pre-installed for each 256K cell array, and a failure occurs. Therefore, a method of replacing defective memory cells by a row / column unit with spare memory cells (ie, redundancy cells) is mainly used.

That is, when the wafer process is completed, programming is performed in the internal circuitry to change the address signal of the spare cell. Accordingly, when an address corresponding to the defective line is input in actual use, the selection is replaced by the spare line instead. These programs include electric fuses that melt and blow fuses due to overcurrent and burned fuses by laser beams.

On the other hand, depending on the spare cell type to be replaced, when replacing with a spare row, respectively, row redundancy, column redundancy to be replaced with a spare column, and spare IO (spare input / output) It can be distinguished by replacing IO redundancy.

Among them, the IO redundancy is mainly used for the wide IO structure, which is widely found in the embedded DRAM. In the wide IO structure, when the column redundancy is used, the number of cells to be allocated to one redundant column is too high. IO redundancy was introduced in place of column redundancy because of inefficiency due to chip area penality.

1 is a schematic view of a conventional semiconductor memory device. As shown in FIG. 1, a conventional semiconductor memory device may include a normal IO line 10, a redundant IO line 15, a multiplexer 20, a sense amplifier 30, and an IO driver. 40).

The normal IO line 10 transfers data to a bit line (not shown) when a word line (not shown) is activated and consists of an IO line and an input / output bar (IOB) line pair. The normal IO line 10 is located in the cell array section 50. The redundant IO line 15 is an IO line 15 for replacing a normal IO line 10 when a failure occurs, and is located at one edge of the normal IO line 10, that is, at the edge of the cell array unit 50. .

The multiplexer 20 selects one of the normal IO line 10 and the redundant IO line 15 in response to the selection signal SEL. That is, when the normal IO line 10 is normal, the multiplexer 20 selects the normal IO line 10, and when a defect occurs in the normal IO line 10, the multiplexer 20 provides a redundant IO line 15. Select).

The IO sense amplifier 30 senses a difference between the IO line 10 and the IOB line (not shown), and the IO driver 40 amplifies the written data signal and drives the cell array unit 50. .

The redundancy circuit improves the yield of the DRAM device by causing the multiplexer 20 to select and replace the redundant IO line 15 when a failure occurs in the normal IO line 10.

However, as shown in FIG. 1, since the redundant IO line 15 is located at one edge of the cell array unit, the length of the normal IO line 10 and the length of the redundant IO line 15 input to the multiplexer 20 are shown. Are different from each other. In this case, when the length difference between the normal IO line 10 and the redundant IO line 15 occurs as a small swing section A between the cell array unit 50 and the multiplexer 20, a signal delay may occur. There is a problem that the skew occurs during the read or write operation. Here, the section B represents a full swing section.

Accordingly, an object of the present invention is to provide a semiconductor memory device capable of preventing skew due to a difference in length between a normal IO line and a redundant IO line.

1 is a circuit diagram schematically illustrating a general semiconductor memory device.

2 is a circuit diagram schematically illustrating a semiconductor memory device according to the present invention.

3 is a circuit diagram conceptually illustrating a redundancy device of a semiconductor memory device according to the present invention.

4 is a circuit diagram illustrating a read operation block of a redundancy device of a semiconductor memory device of the present invention as an example.

(Explanation of symbols for the main parts of the drawing)

110: normal IO line 120: redundant IO line

130: IO sense amplifier 135: IO driver

140: RIO sense amplifier 145: RIO driver

150: lead multiplexer 160: light multiplexer

Other objects and novel features as well as the objects of the present invention will become apparent from the description of the specification and the accompanying drawings.

Among the inventions disclosed herein, a brief outline of representative features is as follows.

First, a semiconductor memory device according to an embodiment of the present invention is disposed in a cell array unit, and includes a normal IO line including an input / output (IO) line and an input / output bar (IOB) line, and the normal IO line. A redundant IO line disposed at one edge and including a redundant input / output (RIO) line and a redundant input / output bar (RIOB) line that is replaced when the normal IO line is defective, and is located at one end of the normal IO line; An IO sense amplifier that senses and amplifies the voltage difference between the IO line and the IOB line, and the output of the IO sense amplifier and the output of the RIO sense amplifier are input.When the normal IO line is normal, the output of the IO sense amplifier is selected and the normal IO line is selected. In this case, the output of the RIO sense amplifier is selected and a multiplexer is used to read data. The distance between the normal IO line and the IO sense amplifier is equal to the distance between the redundant IO line and the RIO sense amplifier. same.

In addition, a semiconductor memory device according to another embodiment of the present invention may be disposed in a cell array unit, and include a normal IO line including an input / output (IO) line and an input / output bar (IOB) line, and the normal IO line A redundant IO line disposed at an edge and including a redundant input / output (RIO) line and a redundant input / output bar (RIOB) line that is replaced when the normal IO line is defective, and an IO driver located at one end of the normal IO line; A RIO driver positioned at one end of the redundant IO line, and a data output signal written to the IO driver when the normal IO line is normal, and a data output signal written to the RIO driver when the normal IO line is defective. And a multiplexer, wherein the distance between the normal IO line and the IO driver is equal to the distance between the redundant IO line and the RIO driver.

In addition, the semiconductor memory device according to another embodiment of the present invention, a normal IO line disposed in the cell array unit, including an IO (input / output) line and IOB (input / output bar) line, and the normal IO A redundancy IO line including a redundant input / output (RIO) line and a redundant input / output bar (RIOB) line disposed at one edge of the line and replaced when the normal IO line is defective, and located at one end of the normal IO line, An IO sense amplifier for sensing and amplifying the voltage difference between the IO line and the IOB line, a RIO sense amplifier positioned at one end of the redundant IO line and sensing and amplifying a voltage difference between the RIO line and the RIOB line, and the IO sense amplifier The output of the RIO sense amplifier and the output of the RIO sense amplifier are input, and when the normal IO line is normal, the output of the IO sense amplifier is selected. a read multiplexer, an IO driver located at one end of the normal IO line, a RIO driver located at one end of the redundant IO line, and a data output signal written to the IO driver when the normal IO line is normal; And a write multiplexer for applying a data output signal written to the RIO driver when the normal IO line is defective, and the distance between the normal IO line, the IO sense amplifier, and the IO driver is the redundant IO line and the RIO sense amplifier. It is equal to the distance between the and RIO drivers.

In addition, a semiconductor memory device according to another embodiment of the present invention, the semiconductor memory device capable of replacing a defective normal memory cell with a redundant memory cell, IO line for outputting data from the normal memory cell, From a redundant IO line for outputting data from the redundant memory cell, an IO sense amplifier for amplifying data on the IO line, a redundant IO sense amplifier for sensing and amplifying data on the redundant line, and the redundant memory cell In the case of reading data, a selection circuit for selecting and outputting the output signal of the redundant IO sense amplifier is characterized in that it is provided.

In addition, the semiconductor memory device according to another embodiment of the present invention, in the semiconductor memory device capable of replacing a defective normal memory cell with a redundant memory cell, IO line for outputting data from the normal memory cell; A redundant IO line for outputting data from the redundant memory cell, a normal driver for driving write data onto the IO line, a redundant driver for driving the write data onto the redundant line, and the redundant memory When writing data from a cell, a selection circuit is provided for outputting the write data to the redundant IO line via the redundant driver.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below. Embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. Accordingly, the shape and the like of the elements in the drawings are exaggerated to emphasize a more clear description, and the elements denoted by the same reference numerals in the drawings means the same elements.

2 is a circuit diagram schematically illustrating a semiconductor memory device according to the present invention. 3 is a circuit diagram conceptually illustrating a semiconductor memory device according to the present invention. 4 is a circuit diagram illustrating an example of a read operation block of the semiconductor memory device of the present invention.

As shown in FIG. 2, the memory device according to the present invention includes a normal IO line 110, a redundant IO line 120, an IO sense amplifier 130, an IO driver 135, an RIO sense amplifier 140, RIO driver 145, lead multiplexer 150, and light multiplexer 160.

The normal IO line 110 is composed of a pair of an IO line and an IOB line, and is connected to the IO sense amplifier 130. The redundant IO line 120 also includes a pair of redundant input / output (RIO) lines and a RIOB line, and is connected to the RIO sense amplifier 140.

The IO sense amplifier 130 and the RIO sense amplifier 140 detect voltage differences between the IO line, the IOB line, the RIO line, and the RIOB line, respectively, and supply the IO voltage, the IOB line, the RIO line, and the RIOB line with a supply voltage (or ground). Amplify to " high " or " low "

The read multiplexer 150 receives the output signal of the IO sense amplifier 130 and the output signal of the RIO sense amplifier 140, selects the redundant IO line 120 when the normal IO line 110 is defective, The data contained in the line 110 or 120 is read.

The write multiplexer 160 drives the written data toward the normal IO line 110 or the redundant IO line 120 in response to the selection signal SEL. The IO driver 135 and the RIO driver 145 are connected to the output terminal of the light multiplexer 160.

When no defect occurs in the normal IO line 110, the IO driver 135 amplifies the written data and drives the normal IO line 110 toward the normal IO line 110.

When a failure occurs in the normal IO line 110, the RIO driver 145 amplifies the written data and drives the redundant IO line 120 toward the redundant IO line 120. Here, reference numeral 200 denotes a cell array unit.

The operation of the semiconductor memory device of the present invention will be described below.

First, when the normal operation of the normal IO line 110 is described as a read operation, the read multiplexer 150 selects the normal IO line 110 to read data loaded on the normal IO line 110. On the other hand, when a failure occurs in the normal IO line 110, the read operation, the read multiplexer 150 selects the redundant IO line 120 corresponding to the normal IO line 110, the redundant IO line ( Read the signal in 120).

In addition, when the write operation is described when the normal IO line 110 is normal, the write multiplexer 160 selects the normal IO line 110 to write data to the normal IO line 110 by the IO driver 135. Fill in. On the other hand, when a bad operation occurs in the normal IO line 110, the write operation, the light multiplexer 160 selects the redundant IO line 120 corresponding to the normal IO line 110, RIO driver 145 ) Writes data to the redundant IO line 110.

In the semiconductor memory device of the present invention as described above, the RIO sense amplifier 140 and the RIO driver 145 are installed in the redundancy IO line 120 like the normal IO line 110. Accordingly, the length of the normal IO line 110 connected to the IO sense amplifier 130 and the IO driver 135 and the redundancy IO line 120 connected to the RIO sense amplifier 140 and the RIO driver 145 become the same. . Since the lengths of the normal IO line 110 and the redundancy IO line 120 coincide with each other in the small swing section A between the cell array unit 200 and the sense amplifiers 130, a skew-like phenomenon does not occur.

At this time, since the RIO sense amplifier 140 and the RIO driver 145 are separately installed in the redundancy IO line 120, a read multiplexer and a write multiplexer are separately installed. As a result, the IO lines 110, 120 between the RIO sense amplifier and the RIO driver between the multiplexers 150, 160 may be somewhat longer, but the interval between the sense amplifier (or driver) and the multiplexer is a full swing period, so even if some delay occurs. Skew-like phenomena do not occur. In addition, since the enable signal is applied to the IO driver and the RIO driver at the same time during the write operation, there is no problem due to the length difference.

3 illustrates a multiplexer circuit diagram of FIG. 2. The multiplexers 150 and 160 of FIG. 3 select either the normal IO line 110 or the redundancy IO line 120 according to the selection signal SEL. In this case, the multiplexers 150 and 160 may include a first transmission gate 301 connected to the normal word line 110, a second transmission gate 303 and a first transmission gate 301 connected to the redundancy IO line 120. ) And an inverter 305 for selectively turning on the second transmission gate 303.

In accordance with the selection signal SEL, a path or redundancy IO line path of the normal IO line is formed, so that data carried on the normal IO line or redundancy IO line is read, or data is written.

4 is a circuit diagram illustrating an example of a read operation block of a semiconductor memory device according to an embodiment of the present invention, in which the read operation block includes an IO sense amplifier 130, a RIO sense amplifier 140, and a read multiplexer 150. It is composed of

The IO line and the IOB line 110 are input to the IO sense amplifier 130, and the IO sense amplifier 130 is activated by the enable signal EN. The output signal of the IO sense amplifier 130 is input to the read multiplexer 150.

Meanwhile, the RIO line and the RIOB line 120 are input to the RIO sense amplifier 140, and the RIO sense amplifier 140 is activated by the inversion enable signal REN. In addition, the output signal of the RIO sense amplifier 140 is input to the read multiplexer 150.

The multiplexer 150 includes a first selector 151, a second selector 152, and a latch unit 153. In this case, the first selector 151 and the second selector 152 have the same configuration, and include the PMOS transistors 1510 and 1520 and the NMOS transistors 1512 and 1522, respectively. Here, the PMOS transistors 1510 and 1520 and the NMOS transistors 1512 and 1522 of the first and second selectors 151 and 152 are connected in series, and the gates of the PMOS transistors 1510 and 1520 are connected to the IO sense amplifier 130 and It is connected to the positive output of RIO sense amplifier 140. Meanwhile, the sources of the PMOS transistors 1510 and 1520 are connected to the power supply voltage V _DD and the drains are connected to the drains of the NMOS transistors 1512 and 1522. Gates of the NMOS transistors 1512 and 1522 are connected to the negative outputs of the IO sense amplifier 130 and the RIO sense amplifier 140, and the source is grounded. The latch unit 135 receives the output signals of the first and second selectors 151 and 152, inverts and amplifies them, and reads and reads the data.

Referring to the operation of the reading block having such a configuration as follows.

For example, if the enable signal is "high", the invert enable signal is "low". Then, when "high" is input to the IO line (RIO line), and "low" is input to the IOB line (RIOB) line, the IO sense amplifier 130 outputs "high" for both the positive output and the negative output. Since the RIO sense amplifier 140 is not enabled, the signals output on the RIO line and the RIOB line are output as positive output and negative output values, respectively. As a result, the NMOS transistor of the first selector of the flexor 150 is turned on so that the first selector outputs a low signal while the second selector is open to output the output signal. As a result, the output signal of the second selector is inverted and amplified by the latch unit, thereby reading the output signal.

Although the writing block is not mentioned in this embodiment, the circuit can be implemented in various ways as in the reading block.

As described in detail above, in order to match the length of the normal IO line and the redundancy IO line in the small swing section, a dummy sense amplifier and a dummy driver are installed in the redundancy IO line. This prevents skew due to IO line length differences in the small swing section between the IO lines and the sense amplifier.

Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the scope of the technical idea of the present invention. .

Claims (5)

A normal IO line disposed in the cell array and including an input / output (IO) line and an input / output bar (IOB) line; A redundant IO line disposed at one edge of the normal IO line and including a redundant input / output (RIO) line and a redundant input / output bar (RIOB) line that is replaced when the normal IO line is defective; An IO sense amplifier connected to the normal IO line and the IOB line and sensing and amplifying a voltage difference between the IO line and the IOB line; The output of the IO sense amplifier and the output of the RIO sense amplifier are input, and when the normal IO line is normal, the output of the IO sense amplifier is selected, and when the normal IO line is defective, the output of the RIO sense amplifier is selected to read data. Contains a multiplexer, Wherein the distance between the normal IO line and the IO sense amplifier is equal to the distance between the redundant IO line and the RIO sense amplifier. A normal IO line disposed in the cell array and including an input / output (IO) line and an input / output bar (IOB) line; A redundant IO line disposed at one edge of the normal IO line and including a redundant input / output (RIO) line and a redundant input / output bar (RIOB) line that is replaced when the normal IO line is defective; An IO driver located at one end of the normal IO line; A RIO driver located at one end of the redundant IO line; And A multiplexer for applying a data output signal written to an IO driver when the normal IO line is normal and a data output signal written to a RIO driver when the normal IO line is defective, The distance between the normal IO line and the IO driver is the same as the distance between the redundant IO line and the RIO driver. A normal IO line disposed in the cell array unit and including an IO (input / output) line and an IOB (input / output bar) line; A redundant IO line disposed at one edge of the normal IO line and including a redundant input / output (RIO) line and a redundant input / output bar (RIOB) line that is replaced when the normal IO line is defective; An IO sense amplifier positioned at one end of the normal IO line and sensing and amplifying a voltage difference between the IO line and the IOB line; A RIO sense amplifier positioned at one end of the redundant IO line and sensing and amplifying a voltage difference between the RIO line and the RIOB line; The output of the IO sense amplifier and the output of the RIO sense amplifier are input, and when the normal IO line is normal, the output of the IO sense amplifier is selected, and when the normal IO line is defective, the output of the RIO sense amplifier is selected to read data. A read multiplexer; An IO driver located at one end of the normal IO line; A RIO driver located at one end of the redundant IO line; And A write multiplexer for applying a data output signal written to an IO driver when the normal IO line is normal and a data output signal written to the RIO driver when the normal IO line is defective; And the distance between the normal IO line and the IO sense amplifier and the IO driver is equal to the distance between the redundant IO line and the RIO sense amplifier and the RIO driver. A semiconductor memory device capable of replacing a defective normal memory cell with a redundant memory cell, An IO line for outputting data from the normal memory cell; A redundant IO line for outputting data from the redundant memory cell; An IO sense amplifier for amplifying data on the IO line; A redundant IO sense amplifier for sensing and amplifying data on the redundant line; And And a selection circuit for selecting and outputting an output signal of the redundant IO sense amplifier when reading data from the redundant memory cell. A semiconductor memory device capable of replacing a defective normal memory cell with a redundant memory cell, An IO line for outputting data from the normal memory cell; A redundant IO line for outputting data from the redundant memory cell; A normal driver for driving write data on the IO line; A redundant driver for driving the write data on the redundant line; And And a selection circuit for outputting the write data to the redundant IO line through the redundant driver when writing data from the redundant memory cell.