WO2023108990A1 - Reference voltage source - Google Patents

Reference voltage source Download PDF

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Publication number
WO2023108990A1
WO2023108990A1 PCT/CN2022/090596 CN2022090596W WO2023108990A1 WO 2023108990 A1 WO2023108990 A1 WO 2023108990A1 CN 2022090596 W CN2022090596 W CN 2022090596W WO 2023108990 A1 WO2023108990 A1 WO 2023108990A1
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WIPO (PCT)
Prior art keywords
drain
nmos transistor
transistor
pmos transistor
gate
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PCT/CN2022/090596
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French (fr)
Chinese (zh)
Inventor
吉博
郭嘉帅
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深圳飞骧科技股份有限公司
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Publication of WO2023108990A1 publication Critical patent/WO2023108990A1/en

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices

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  • the invention relates to the field of electronic technology, in particular to a reference voltage source.
  • the reference voltage source is an extremely important part of the analog circuit. It provides a reference voltage for series voltage regulator circuits, A/D and D/A converters, etc. It is also a reference for most sensors' regulated power supply or excitation source.
  • Figure 1 is a current common reference voltage source circuit, which includes an operational amplifier OP1 and a current mirror for generating a reference voltage.
  • the current mirror is composed of PMOS transistors P11, P12, and P13.
  • the operational amplifier OP1 is mainly used for clamping .
  • the existing operational amplifier OP implementation circuit consists of two stages of operational amplifiers, in which PMOS transistors P21, P22 and NMOS transistors N21, N22 form the first stage amplifier, and NMOS transistor N23 is the second stage amplifier .
  • the mismatch between the input offset voltage of the operational amplifier OP and the current mirror P11/P12/P13 will have a greater impact on the accuracy of the reference voltage source and reduce the accuracy of the reference voltage source.
  • the voltage mismatch between P21 and P22 in the structure of the operational amplifier OP itself, the mismatch between N21 and N22, and the mismatch between N2 and N3, the mismatch of these three pairs of devices will cause adverse effects on the input offset voltage of the operational amplifier OP, thus Affects the accuracy of the voltage reference.
  • An embodiment of the present invention provides a reference voltage source, which can improve the precision of the reference voltage source.
  • the present invention provides a reference voltage source on the one hand, including a telescopic operational amplifier and a reference voltage generating core circuit;
  • the telescopic operational amplifier includes a first PMOS transistor P31, a second PMOS transistor P32, a first NMOS transistor N31, a second NMOS transistor N32, and a current generating circuit;
  • the reference voltage generating core circuit includes a third PMOS transistor P33, a first resistor R31, a second resistor R32, a third resistor R33, a first conduction element and a second conduction element;
  • the gate and drain of the first PMOS transistor P31, the gate of the second PMOS transistor P32 are connected to the drain of the first NMOS transistor N31, the source of the first PMOS transistor P31 is connected to the The source of the second PMOS transistor P32 is connected to the power supply voltage VDD, the drain of the second PMOS transistor P32 is the output end of the telescopic operational amplifier, and is connected to the drain of the second NMOS transistor N32, so The source of the first NMOS transistor N31 is connected to the source of the second NMOS transistor N32 and grounded through the current generating circuit, the gate of the first NMOS transistor N31 and the gate of the second NMOS transistor N32 The poles are respectively the positive input terminal VP and the negative input terminal VN of the telescopic operational amplifier;
  • the gate of the third PMOS transistor P33 is connected to the output terminal of the telescopic operational amplifier, the source of the third PMOS transistor P33 is connected to the voltage power supply VDD, and one end of the first resistor R31 and One end of the second resistor R32 is connected to the drain of the third PMOS transistor, the other end of the first resistor R31 is connected to the negative input terminal VN, and grounded through the first conduction element, so The other end of the second resistor R32 is connected to the positive input terminal VP and one end of the third resistor R33, the other end of the third resistor R33 is grounded through the second conduction element, and the third PMOS
  • the drain of the tube is the output terminal of the reference voltage generating core circuit for outputting the reference voltage VREF.
  • the telescopic operational amplifier also includes a third NMOS transistor N33 and a fourth NMOS transistor N34, the gate and drain of the first PMOS transistor P31 are connected to the first PMOS transistor N33 through the third NMOS transistor N33.
  • a drain of the NOMS transistor N31 is connected, and the drain of the second PMOS transistor P32 is connected to the drain of the second NMOS transistor N32 through the fourth NMOS transistor N34;
  • the gate and drain of the third NMOS transistor N33, the gate of the fourth NMOS transistor N34 are connected to the gate and drain of the first PMOS transistor P31, and the gate and drain of the third NMOS transistor N33
  • the source is connected to the drain of the first NMOS transistor N31
  • the drain of the fourth NMOS transistor N34 is connected to the drain of the second PMOS transistor P32
  • the source of the fourth NMOS transistor N34 is connected to the drain of the fourth NMOS transistor N34.
  • the drain of the second NMOS transistor N32 is connected.
  • the telescopic operational amplifier also includes a third NMOS transistor N33 and a fourth NMOS transistor N34, and the first PMOS transistor P31
  • the gate and drain are connected to the drain of the first NOMS transistor N31 through the third NMOS transistor N33, and the drain of the second PMOS transistor P32 is connected to the second NMOS transistor P34 through the fourth NMOS transistor N34.
  • the gate of the third NMOS transistor N33 is connected to the gate of the fourth NMOS transistor N34 and connected to the first bias circuit, and the drain of the third NMOS transistor N33 is connected to the first bias circuit.
  • the gate of the PMOS transistor P31 is connected to the drain
  • the source of the third NMOS transistor N33 is connected to the drain of the first NMOS transistor N31
  • the drain of the fourth NMOS transistor N34 is connected to the second PMOS transistor N31.
  • the drain of the transistor P32 is connected, and the source of the fourth NMOS transistor N34 is connected to the drain of the second NMOS transistor N32.
  • the telescopic operational amplifier also includes a fourth PMOS transistor P34 and a fifth PMOS transistor P35, and the drain of the third NMOS transistor N33
  • the fourth PMOS transistor P34 is connected to the drain of the first PMOS transistor P31
  • the drain of the fourth NMOS transistor N34 is connected to the drain of the second PMOS transistor P32 through the fifth PMOS transistor P35. connect;
  • the gate of the fourth PMOS transistor P34 is connected to the gate of the fifth PMOS transistor P35 and connected to the second bias circuit, and the drain of the fourth PMOS transistor P34 is connected to the third bias circuit.
  • the drain of the NMOS transistor N33 is connected, the source of the fourth PMOS transistor P34 is connected to the drain of the first PMOS transistor P31, and the source of the fifth PMOS transistor P35 is connected to the second PMOS transistor P32.
  • the drain is connected, the drain of the fifth PMOS transistor P35 is connected to the drain of the fourth NMOS transistor N34, and the output terminal of the telescopic operational amplifier is drawn from the drain of the fifth PMOS transistor P35.
  • the first bias circuit includes a fourth resistor R34, a fifth NMOS transistor N35, and a third conduction element;
  • One end of the fourth resistor R34 is connected to the power supply voltage VDD, the other end of the fourth resistor R34 is connected to the gate and drain of the fifth NMOS transistor N35, and the drain of the fifth NMOS transistor N35
  • the pole is connected to the gate of the third NMOS transistor N33 and the gate of the fourth NMOS transistor N34, and the source of the third NMOS transistor N35 is grounded through the third conduction element.
  • the third conduction element is a diode or a PNP bipolar transistor.
  • the first conduction element is a diode or a PNP bipolar transistor
  • the second conduction element is a diode or a PNP bipolar transistor
  • the number ratio of the first conduction element to the second conduction element is 1:N, where N is an integer greater than or equal to 2.
  • the current generating circuit includes a fifth resistor R35, one end of the fifth resistor R35 is connected to the sources of the first NMOS transistor N31 and the second NMOS transistor N32, and the fifth resistor R35 The other end of the ground.
  • the current generating circuit is a current source I1, the input terminal of the current source I1 is connected to the source electrodes of the first NMOS transistor N31 and the second NMOS transistor N32, and the output of the current source I1 end grounded.
  • the reference voltage source of the present invention includes a telescopic operational amplifier and a reference voltage generating core circuit
  • the telescopic operational amplifier includes a first PMOS transistor P31, a second PMOS transistor P32, a first NMOS transistor N31, The second NMOS transistor N32 and a current generating circuit
  • the reference voltage generating core circuit includes a third PMOS transistor P33, a first resistor R31, a second resistor R32, a third resistor R33, a first conduction element and a second conduction element , the gate of the third PMOS transistor P33 is connected to the output terminal of the telescopic operational amplifier, the source of the third PMOS transistor P33 is connected to the voltage power supply VDD, and one end of the first resistor R31 One end of the second resistor R32 is connected to the drain of the third PMOS transistor, the other end of the first resistor R31 is connected to the negative input terminal VN of the telescopic operational amplifier, and is connected through the first lead The through element is grounded
  • the output terminal of the telescopic operational amplifier is directly connected to the reference voltage Generate the third PMOS transistor P33 of the core circuit, there is no current mirror P11/P12/P13 in the reference voltage generation core circuit, so the accuracy of the reference voltage source will not be affected by the current mismatch of the current mirror P11/P12/P13, which can Improve the accuracy of the voltage reference.
  • Fig. 1 is the circuit schematic diagram of a kind of reference voltage source of prior art
  • Fig. 2 is a schematic structural diagram of the operational amplifier shown in Fig. 1;
  • FIG. 3 is a schematic circuit diagram of a reference voltage source provided by an embodiment of the present invention.
  • Fig. 4 is another schematic circuit diagram of the reference voltage source provided by the embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of a telescopic operational amplifier provided by an embodiment of the present invention.
  • FIG. 6 is another schematic circuit diagram of the reference voltage source provided by the embodiment of the present invention.
  • FIG. 7 is another structural schematic diagram of the telescopic operational amplifier provided by the embodiment of the present invention, in which the circuit diagram of the second bias circuit is shown.
  • a reference voltage source 100 provided by an embodiment of the present invention includes a telescopic operational amplifier 11 and a reference voltage generating core circuit 12 .
  • the telescopic operational amplifier 11 includes a first PMOS transistor P31 , a second PMOS transistor P32 , a first NMOS transistor N31 , a second NMOS transistor N32 and a current generating circuit.
  • the reference voltage generating core circuit 12 includes a third PMOS transistor P33, a first resistor R31, a second resistor R32, a third resistor R33, a first conduction element and a second conduction element.
  • the gate and drain of the first PMOS transistor P31, the gate of the second PMOS transistor P32 are connected to the drain of the first NMOS transistor N31, the source of the first PMOS transistor P31 is connected to the The source of the second PMOS transistor P32 is connected to the power supply voltage VDD, the drain of the second PMOS transistor P32 is the output terminal OPOUT of the telescopic operational amplifier 11, and is connected to the drain of the second NMOS transistor N32 , the source of the first NMOS transistor N31 is connected to the source of the second NMOS transistor N32 and grounded through the current generating circuit, the gate of the first NMOS transistor N31 is connected to the second NMOS transistor N32 The gates of are respectively the positive input terminal VP and the negative input terminal VN of the telescopic operational amplifier 11 .
  • the current generating circuit can be realized by using the fifth resistor R35, that is, the current generating circuit includes the fifth resistor R35, and one end of the fifth resistor R35 is connected to the first NMOS transistor N31 and the The source of the second NMOS transistor N32 is connected, and the other end of the fifth resistor R35 is grounded, so as to provide the telescopic operational amplifier 11 with current required for operation through the fifth resistor R35 .
  • the current generating circuit can also be implemented with other structures. For example, as shown in FIG. The sources of the first NMOS transistor N31 and the second NMOS transistor N32 are connected, the output end of the current source I1 is grounded, and the current source I1 can provide the telescopic operational amplifier 11 with the current required for operation.
  • the gate of the third PMOS transistor P33 is connected to the output terminal OPOUT of the telescopic operational amplifier 11, and the source of the third PMOS transistor P33 is connected to the voltage power supply VDD.
  • One end of the first resistor R31 and one end of the second resistor R32 are connected to the drain of the third PMOS transistor, and the other end of the first resistor R31 is connected to the negative input terminal VN, and passes through the first A conduction element is grounded, the other end of the second resistor R32 is connected to the positive input terminal VP and one end of the third resistor R33, and the other end of the third resistor R33 passes through the second conduction element Grounded, the drain of the third PMOS transistor is the output terminal of the reference voltage generation core circuit 12 for outputting the reference voltage VREF.
  • both the first conduction element and the second conduction element can be realized by using a diode or a PNP bipolar transistor.
  • the first conduction element is a diode Q31
  • the second conduction element is a diode Q31
  • the conduction element is a diode Q32, wherein the number ratio of the first conduction element to the second conduction element can be 1:N, N is an integer greater than or equal to 2, for example, N can be 8, that is, when the first conduction element When the number is one, there are eight second conduction elements.
  • a plurality of second conduction elements are connected in parallel with the fourth resistor R33, for example, there are N diodes Q32 as the second conduction elements, the anodes of the N diodes Q32 are connected in parallel with the third resistor R33, and the N diodes Q32 The negative terminal is grounded.
  • the multiple diodes Q32 are connected in parallel.
  • V PN is the forward conduction voltage drop of the diodes Q31, Q32 or the PNP bipolar transistor
  • V T represents the thermal voltage, when the temperature is 300K
  • N is the second conduction
  • the number ratio of the element to the first conduction element, R31 and R33 represent the resistance values of the first resistor and the third resistor, respectively.
  • the reference voltage source 100 of the embodiment of the present invention is directly connected to the third PMOS transistor P33 of the reference voltage generating core circuit 12 through the output end of the telescopic operational amplifier 11, and the reference voltage generating core circuit 12 There is no current mirror P11/P12/P13, so the accuracy of the reference voltage source 100 will not be affected by the current mismatch of the current mirror P11/P12/P13, thereby improving the accuracy of the reference voltage source.
  • the source of the input offset voltage of the telescopic operational amplifier 11 in the embodiment of the present invention is only the N31/N32 voltage mismatch and the current mirror P31/P32 mismatch.
  • the lack of one pair of mismatching sources is beneficial to reduce the input offset voltage.
  • the input offset voltage can be reduced by 1/3, thereby further reducing the impact of the input offset voltage on the accuracy of the reference voltage source 100 .
  • V DSP represents the voltage difference between the source and drain of the PMOS device, and the general design value is 0.2V.
  • the telescopic operational amplifier 11 further includes a third NMOS transistor N33 and a fourth NMOS transistor N34, thereby forming a cascode structure, It is beneficial to increase the gain of the operational amplifier.
  • the gate and drain of the first PMOS transistor P31 are connected to the drain of the first NOMS transistor N31 through the third NMOS transistor N33, and the drain of the second PMOS transistor P32 is connected through the fourth NMOS transistor N33.
  • the transistor N34 is connected to the drain of the second NMOS transistor N32.
  • the gate and drain of the third NMOS transistor N33, the gate of the fourth NMOS transistor N34 are connected to the gate and drain of the first PMOS transistor P31, and the gate and drain of the third NMOS transistor N33
  • the source is connected to the drain of the first NMOS transistor N31
  • the drain of the fourth NMOS transistor N34 is connected to the drain of the second PMOS transistor P32
  • the source of the fourth NMOS transistor N34 is connected to the drain of the fourth NMOS transistor N34.
  • the drain of the second NMOS transistor N32 is connected.
  • both the third NMOS transistor N33 and the fourth NMOS transistor N34 of the telescopic operational amplifier 11 are biased by the power supply voltage VDD.
  • a bias circuit may also be set to provide bias voltages for the third NMOS transistor N33 and the fourth NMOS transistor N34.
  • the reference voltage source 100 further includes a first bias circuit 13 for providing a first bias voltage NBIAS, wherein the gate of the third NMOS transistor N33 is connected to the gate of the fourth NMOS transistor N34 and connected to the first bias circuit 13, the drain of the third NMOS transistor N33 is connected to the gate and drain of the first PMOS transistor P31, the source of the third NMOS transistor N33 is connected to the The drain of the first NMOS transistor N31 is connected, the drain of the fourth NMOS transistor N34 is connected to the drain of the second PMOS transistor P32, and the source of the fourth NMOS transistor N34 is connected to the second NMOS transistor N34.
  • the drain connection of tube N32 wherein the gate of the third NMOS transistor N33 is connected to the gate of the fourth NMOS transistor N34 and connected to the first bias circuit 13, the drain of the third NMOS transistor N33 is connected to the gate and drain of the first PMOS transistor P31, the source of the third NMOS transistor N33 is connected to the The drain of the
  • the first bias circuit 13 includes a fourth resistor R34, a fifth NMOS transistor N35 and a third pass element.
  • One end of the fourth resistor R34 is connected to the power supply voltage VDD, the other end of the fourth resistor R34 is connected to the gate and drain of the fifth NMOS transistor N35, and the drain of the fifth NMOS transistor N35
  • the pole is connected to the gate of the third NMOS transistor N33 and the gate of the fourth NMOS transistor N34, and the source of the third NMOS transistor N35 is grounded through the third pass element.
  • the third conduction element is a diode or a PNP bipolar transistor, taking a diode as an example, the third conduction element is a diode Q33.
  • the reference voltage source 100 further includes a second bias circuit 14 providing a second bias voltage PBIAS, and the second bias circuit 14 includes a sixth PMOS transistor P36 and the sixth resistor R36.
  • the telescopic operational amplifier 11 further includes a fourth PMOS transistor P34 and a fifth PMOS transistor P35, thereby forming a cascode structure, which is beneficial to increase the gain of the operational amplifier.
  • the drain of the third NMOS transistor N33 is connected to the drain of the first PMOS transistor P31 through the fourth PMOS transistor P34, and the drain of the fourth NMOS transistor N34 is connected to the drain of the fifth PMOS transistor P35.
  • the drain of the second PMOS transistor P32 is connected.
  • the gate of the fourth PMOS transistor P34 is connected to the gate of the fifth PMOS transistor P35 and connected to the gate of the sixth PMOS transistor P36, and the gate of the sixth PMOS transistor P36 connected to the drain and grounded through the sixth resistor R36, the source of the sixth PMOS transistor P36 is connected to the power supply voltage VDD, the drain of the fourth PMOS transistor P34 is connected to the third NMOS transistor N33 The drain is connected, the source of the fourth PMOS transistor P34 is connected to the drain of the first PMOS transistor P31, the source of the fifth PMOS transistor P35 is connected to the drain of the second PMOS transistor P32, The drain of the fifth PMOS transistor P35 is connected to the drain of the fourth NMOS transistor N34, and the output terminal OPOUT of the telescopic operational amplifier 11 is drawn out from the drain of the fifth PMOS transistor P35.

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Abstract

A reference voltage source (100), comprising a sleeve-type operational amplifier (11) and a reference voltage generation nuclear circuit (12). The sleeve-type operational amplifier (11) comprises a first PMOS transistor (P31), a second PMOS transistor (P32), a first NMOS transistor (N31), a second NMOS transistor (N32), and a current generation circuit. The reference voltage generation nuclear circuit (12) comprises a third PMOS transistor (P33), a first resistor (R31), a second resistor (R32), a third resistor (R33), a first conducting element and a second conducting element. An output end of the sleeve-type operational amplifier (11) is directly connected to the third PMOS transistor (P33) of the reference voltage generation nuclear circuit (12), while there are no current mirrors (P11, P12, P13) in the reference voltage generation nuclear circuit (12) that are used in the prior art for generating reference voltages. Therefore, the precision of the reference voltage source (100) will not be affected by a current mismatch of the current mirrors (P11, P12, P13), and the precision of the reference voltage source (100) can be improved.

Description

一种基准电压源A reference voltage source 技术领域technical field
本发明涉及电子技术领域，尤其涉及一种基准电压源。The invention relates to the field of electronic technology, in particular to a reference voltage source.
背景技术Background technique
基准电压源是模拟电路极为重要的组成部分，它为串联型稳压电路、A/D和D/A转化器等提供基准电压，也是大多数传感器的稳压供电电源或激励源参阅。图1，图1是目前常见的基准电压源电路，其包括运算放大器OP1和用于产生基准电压的电流镜，电流镜由PMOS管P11、P12、P13构成，运算放大器OP1主要用于钳位作用。如图2所示，现有的运算放大器OP的实现电路中，由两级运算放大器构成，其中PMOS管P21、P22和NMOS管N21、N22组成第一级放大器，NMOS管N23为第二级放大器。The reference voltage source is an extremely important part of the analog circuit. It provides a reference voltage for series voltage regulator circuits, A/D and D/A converters, etc. It is also a reference for most sensors' regulated power supply or excitation source. Figure 1, Figure 1 is a current common reference voltage source circuit, which includes an operational amplifier OP1 and a current mirror for generating a reference voltage. The current mirror is composed of PMOS transistors P11, P12, and P13. The operational amplifier OP1 is mainly used for clamping . As shown in Figure 2, the existing operational amplifier OP implementation circuit consists of two stages of operational amplifiers, in which PMOS transistors P21, P22 and NMOS transistors N21, N22 form the first stage amplifier, and NMOS transistor N23 is the second stage amplifier .
在上述结构的基准电压源电路中，运算放大器OP的输入失调电压和电流镜P11/P12/P13之间的失配会对基准电压源的精度造成较大的影响，降低基准电压源的精度，而运算放大器OP自身结构中的P21和P22的电压失配，N21和N22的失配以及N2和N3的失配，这三对器件的失配都会运算放大器OP的输入失调电压造成不良影响，从而影响基准电压源的精度。In the reference voltage source circuit with the above structure, the mismatch between the input offset voltage of the operational amplifier OP and the current mirror P11/P12/P13 will have a greater impact on the accuracy of the reference voltage source and reduce the accuracy of the reference voltage source. However, the voltage mismatch between P21 and P22 in the structure of the operational amplifier OP itself, the mismatch between N21 and N22, and the mismatch between N2 and N3, the mismatch of these three pairs of devices will cause adverse effects on the input offset voltage of the operational amplifier OP, thus Affects the accuracy of the voltage reference.
发明内容Contents of the invention
本发明实施例提供一种基准电压源，能够提高基准电压源的精度。An embodiment of the present invention provides a reference voltage source, which can improve the precision of the reference voltage source.
为了解决上述技术问题，本发明一方面提供一种基准电压源，包括套筒式运算放大器和基准电压产生核电路；In order to solve the above technical problems, the present invention provides a reference voltage source on the one hand, including a telescopic operational amplifier and a reference voltage generating core circuit;
所述套筒式运算放大器包括第一PMOS管P31、第二PMOS管P32、第一NMOS管N31、第二NMOS管N32以及电流产生电路；所述基准电压产生核电路包括第三PMOS管P33、第一电阻R31、第二电阻R32、第三电阻R33、第一导通元件和第二导通元件；The telescopic operational amplifier includes a first PMOS transistor P31, a second PMOS transistor P32, a first NMOS transistor N31, a second NMOS transistor N32, and a current generating circuit; the reference voltage generating core circuit includes a third PMOS transistor P33, a first resistor R31, a second resistor R32, a third resistor R33, a first conduction element and a second conduction element;
所述第一PMOS管P31的栅极和漏极、所述第二PMOS管P32的栅极与所述第一NMOS管N31的漏极连接，所述第一PMOS管P31的源极和所述第二PMOS管P32的源极与电源电压VDD连接，所述第二PMOS管P32的漏极为 所述套筒式运算放大器的输出端，并与所述第二NMOS管N32的漏极连接，所述第一NMOS管N31的源极与所述第二NMOS管N32的源极连接且通过所述电流产生电路接地，所述第一NMOS管N31的栅极和所述第二NMOS管N32的栅极分别为所述套筒式运算放大器的正输入端VP和负输入端VN；The gate and drain of the first PMOS transistor P31, the gate of the second PMOS transistor P32 are connected to the drain of the first NMOS transistor N31, the source of the first PMOS transistor P31 is connected to the The source of the second PMOS transistor P32 is connected to the power supply voltage VDD, the drain of the second PMOS transistor P32 is the output end of the telescopic operational amplifier, and is connected to the drain of the second NMOS transistor N32, so The source of the first NMOS transistor N31 is connected to the source of the second NMOS transistor N32 and grounded through the current generating circuit, the gate of the first NMOS transistor N31 and the gate of the second NMOS transistor N32 The poles are respectively the positive input terminal VP and the negative input terminal VN of the telescopic operational amplifier;
所述第三PMOS管P33的栅极与所述套筒式运算放大器的输出端连接，所述第三PMOS管P33的源极与所述电压电源VDD连接，所述第一电阻R31的一端和所述第二电阻R32的一端与所述第三PMOS管的漏极连接，所述第一电阻R31的另一端与所述负输入端VN连接，并通过所述第一导通元件接地，所述第二电阻R32的另一端与所述正输入端VP和所述第三电阻R33的一端连接，所述第三电阻R33的另一端通过所述第二导通元件接地，所述第三PMOS管的漏极为所述基准电压产生核电路的输出端，用于输出基准电压VREF。The gate of the third PMOS transistor P33 is connected to the output terminal of the telescopic operational amplifier, the source of the third PMOS transistor P33 is connected to the voltage power supply VDD, and one end of the first resistor R31 and One end of the second resistor R32 is connected to the drain of the third PMOS transistor, the other end of the first resistor R31 is connected to the negative input terminal VN, and grounded through the first conduction element, so The other end of the second resistor R32 is connected to the positive input terminal VP and one end of the third resistor R33, the other end of the third resistor R33 is grounded through the second conduction element, and the third PMOS The drain of the tube is the output terminal of the reference voltage generating core circuit for outputting the reference voltage VREF.
更进一步地，所述套筒式运算放大器还包括第三NMOS管N33和第四NMOS管N34，所述第一PMOS管P31的栅极和漏极通过所述第三NMOS管N33与所述第一NOMS管N31的漏极连接，所述第二PMOS管P32的漏极通过所述第四NMOS管N34与所述第二NMOS管N32的漏极连接；Further, the telescopic operational amplifier also includes a third NMOS transistor N33 and a fourth NMOS transistor N34, the gate and drain of the first PMOS transistor P31 are connected to the first PMOS transistor N33 through the third NMOS transistor N33. A drain of the NOMS transistor N31 is connected, and the drain of the second PMOS transistor P32 is connected to the drain of the second NMOS transistor N32 through the fourth NMOS transistor N34;
其中，所述第三NMOS管N33的栅极和漏极、所述第四NMOS管N34的栅极与所述第一PMOS管P31的栅极和漏极连接，所述第三NMO管N33的源极与所述第一NMOS管N31的漏极连接，所述第四NMOS管N34的漏极与所述第二PMOS管P32的漏极连接，所述第四NMOS管N34的源极与所述第二NMOS管N32的漏极连接。Wherein, the gate and drain of the third NMOS transistor N33, the gate of the fourth NMOS transistor N34 are connected to the gate and drain of the first PMOS transistor P31, and the gate and drain of the third NMOS transistor N33 The source is connected to the drain of the first NMOS transistor N31, the drain of the fourth NMOS transistor N34 is connected to the drain of the second PMOS transistor P32, and the source of the fourth NMOS transistor N34 is connected to the drain of the fourth NMOS transistor N34. The drain of the second NMOS transistor N32 is connected.
更进一步地，还包括用于提供第一偏置电压的第一偏置电路；所述套筒式运算放大器还包括第三NMOS管N33和第四NMOS管N34，所述第一PMOS管P31的栅极和漏极通过所述第三NMOS管N33与所述第一NOMS管N31的漏极连接，所述第二PMOS管P32的漏极通过所述第四NMOS管N34与所述第二NMOS管N32的漏极连接；Furthermore, it also includes a first bias circuit for providing a first bias voltage; the telescopic operational amplifier also includes a third NMOS transistor N33 and a fourth NMOS transistor N34, and the first PMOS transistor P31 The gate and drain are connected to the drain of the first NOMS transistor N31 through the third NMOS transistor N33, and the drain of the second PMOS transistor P32 is connected to the second NMOS transistor P34 through the fourth NMOS transistor N34. The drain connection of tube N32;
其中，所述第三NMOS管N33的栅极和所述第四NMOS管N34的栅极连接并连接至所述第一偏置电路，所述第三NMOS管N33的漏极与所述第一PMOS管P31的栅极和漏极连接，所述第三NMO管N33的源极与所述第一NMOS管N31的漏极连接，所述第四NMOS管N34的漏极与所述第二PMOS 管P32的漏极连接，所述第四NMOS管N34的源极与所述第二NMOS管N32的漏极连接。Wherein, the gate of the third NMOS transistor N33 is connected to the gate of the fourth NMOS transistor N34 and connected to the first bias circuit, and the drain of the third NMOS transistor N33 is connected to the first bias circuit. The gate of the PMOS transistor P31 is connected to the drain, the source of the third NMOS transistor N33 is connected to the drain of the first NMOS transistor N31, and the drain of the fourth NMOS transistor N34 is connected to the second PMOS transistor N31. The drain of the transistor P32 is connected, and the source of the fourth NMOS transistor N34 is connected to the drain of the second NMOS transistor N32.
更进一步地，还包括提供第二偏置电压的第二偏置电路，所述套筒式运算放大器还包括第四PMOS管P34和第五PMOS管P35，所述第三NMOS管N33的漏极通过所述第四PMOS管P34与所述第一PMOS管P31的漏极连接，所述第四NMOS管N34的漏极通过所述第五PMOS管P35与所述第二PMOS管P32的漏极连接；Furthermore, it also includes a second bias circuit that provides a second bias voltage, the telescopic operational amplifier also includes a fourth PMOS transistor P34 and a fifth PMOS transistor P35, and the drain of the third NMOS transistor N33 The fourth PMOS transistor P34 is connected to the drain of the first PMOS transistor P31, and the drain of the fourth NMOS transistor N34 is connected to the drain of the second PMOS transistor P32 through the fifth PMOS transistor P35. connect;
其中，所述第四PMOS管P34的栅极和所述第五PMOS管P35的栅极连接并连接至所述第二偏置电路，所述第四PMOS管P34的漏极与所述第三NMOS管N33的漏极连接，所述第四PMOS管P34的源极与所述第一PMOS管P31的漏极连接，所述第五PMOS管P35的源极与所述第二PMOS管P32的漏极连接，所述第五PMOS管P35的漏极与所述第四NMOS管N34的漏极连接，所述套筒式运算放大器的输出端从所述第五PMOS管P35的漏极引出。Wherein, the gate of the fourth PMOS transistor P34 is connected to the gate of the fifth PMOS transistor P35 and connected to the second bias circuit, and the drain of the fourth PMOS transistor P34 is connected to the third bias circuit. The drain of the NMOS transistor N33 is connected, the source of the fourth PMOS transistor P34 is connected to the drain of the first PMOS transistor P31, and the source of the fifth PMOS transistor P35 is connected to the second PMOS transistor P32. The drain is connected, the drain of the fifth PMOS transistor P35 is connected to the drain of the fourth NMOS transistor N34, and the output terminal of the telescopic operational amplifier is drawn from the drain of the fifth PMOS transistor P35.
更进一步地，所述第一偏置电路包括第四电阻R34、第五NMOS管N35以及第三导通元件；Furthermore, the first bias circuit includes a fourth resistor R34, a fifth NMOS transistor N35, and a third conduction element;
所述第四电阻R34的一端与所述电源电压VDD连接，所述第四电阻R34的另一端与所述第五NMOS管N35的栅极和漏极连接，所述第五NMOS管N35的漏极与所述第三NMOS管N33的栅极、所述第四NMOS管N34的栅极连接，所述第三NMOS管N35的源极通过所述第三导通元件接地。One end of the fourth resistor R34 is connected to the power supply voltage VDD, the other end of the fourth resistor R34 is connected to the gate and drain of the fifth NMOS transistor N35, and the drain of the fifth NMOS transistor N35 The pole is connected to the gate of the third NMOS transistor N33 and the gate of the fourth NMOS transistor N34, and the source of the third NMOS transistor N35 is grounded through the third conduction element.
更进一步地，所述第三导通元件为二极管或者PNP型双极型晶体管。Furthermore, the third conduction element is a diode or a PNP bipolar transistor.
更进一步地，所述第一导通元件为二极管或者PNP型双极型晶体管，所述第二导通元件为二极管或PNP型双极型晶体管。Furthermore, the first conduction element is a diode or a PNP bipolar transistor, and the second conduction element is a diode or a PNP bipolar transistor.
更进一步地，所述第一导通元件和所述第二导通元件的个数比为1：N，N为大于等于2的整数。Furthermore, the number ratio of the first conduction element to the second conduction element is 1:N, where N is an integer greater than or equal to 2.
更进一步地，所述电流产生电路包括第五电阻R35，所述第五电阻R35的一端与所述第一NMOS管N31和所述第二NMOS管N32的源极连接，所述第五电阻R35的另一端接地。Furthermore, the current generating circuit includes a fifth resistor R35, one end of the fifth resistor R35 is connected to the sources of the first NMOS transistor N31 and the second NMOS transistor N32, and the fifth resistor R35 The other end of the ground.
更进一步地，所述电流产生电路为电流源I1，所述电流源I1的输入端与所述第一NMOS管N31和所述第二NMOS管N32的源极连接，所述电流源I1 的输出端接地。Furthermore, the current generating circuit is a current source I1, the input terminal of the current source I1 is connected to the source electrodes of the first NMOS transistor N31 and the second NMOS transistor N32, and the output of the current source I1 end grounded.
有益效果：本发明的基准电压源中，包括套筒式运算放大器和基准电压产生核电路；所述套筒式运算放大器包括第一PMOS管P31、第二PMOS管P32、第一NMOS管N31、第二NMOS管N32以及电流产生电路；所述基准电压产生核电路包括第三PMOS管P33、第一电阻R31、第二电阻R32、第三电阻R33、第一导通元件和第二导通元件，所述第三PMOS管P33的栅极与所述套筒式运算放大器的输出端连接，所述第三PMOS管P33的源极与所述电压电源VDD连接，所述第一电阻R31的一端和所述第二电阻R32的一端与所述第三PMOS管的漏极连接，所述第一电阻R31的另一端与套筒式运算放大器的负输入端VN连接，并通过所述第一导通元件接地，所述第二电阻R32的另一端与套筒式运算放大器的正输入端VP和所述第三电阻R33的一端连接，所述第三电阻R33的另一端通过所述第二导通元件接地，所述第三PMOS管的漏极为所述基准电压产生核电路的输出端，用于输出基准电压VREF，因此，本方案中，套筒式运算放大器的输出端直接连接至基准电压产生核电路的第三PMOS管P33，基准电压产生核电路中没有电流镜P11/P12/P13，因此基准电压源的精度不会受到电流镜P11/P12/P13电流失配的影响，由此可以提高基准电压源的精度。Beneficial effects: the reference voltage source of the present invention includes a telescopic operational amplifier and a reference voltage generating core circuit; the telescopic operational amplifier includes a first PMOS transistor P31, a second PMOS transistor P32, a first NMOS transistor N31, The second NMOS transistor N32 and a current generating circuit; the reference voltage generating core circuit includes a third PMOS transistor P33, a first resistor R31, a second resistor R32, a third resistor R33, a first conduction element and a second conduction element , the gate of the third PMOS transistor P33 is connected to the output terminal of the telescopic operational amplifier, the source of the third PMOS transistor P33 is connected to the voltage power supply VDD, and one end of the first resistor R31 One end of the second resistor R32 is connected to the drain of the third PMOS transistor, the other end of the first resistor R31 is connected to the negative input terminal VN of the telescopic operational amplifier, and is connected through the first lead The through element is grounded, and the other end of the second resistor R32 is connected to the positive input terminal VP of the telescopic operational amplifier and one end of the third resistor R33, and the other end of the third resistor R33 is connected through the second lead The pass element is grounded, and the drain of the third PMOS transistor is the output terminal of the reference voltage generating nuclear circuit for outputting the reference voltage VREF. Therefore, in this solution, the output terminal of the telescopic operational amplifier is directly connected to the reference voltage Generate the third PMOS transistor P33 of the core circuit, there is no current mirror P11/P12/P13 in the reference voltage generation core circuit, so the accuracy of the reference voltage source will not be affected by the current mismatch of the current mirror P11/P12/P13, which can Improve the accuracy of the voltage reference.
附图说明Description of drawings
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其有益效果显而易见。The technical solution and beneficial effects of the present invention will be apparent through the detailed description of specific embodiments of the present invention in conjunction with the accompanying drawings.
图1是现有技术一种基准电压源的电路原理图；Fig. 1 is the circuit schematic diagram of a kind of reference voltage source of prior art;
图2是图1所示的运算放大器的结构示意图；Fig. 2 is a schematic structural diagram of the operational amplifier shown in Fig. 1;
图3是本发明实施例提供的基准电压源的一电路原理图；FIG. 3 is a schematic circuit diagram of a reference voltage source provided by an embodiment of the present invention;
图4是本发明实施例提供的基准电压源的另一电路原理图；Fig. 4 is another schematic circuit diagram of the reference voltage source provided by the embodiment of the present invention;
图5是本发明实施例提供的套筒式运算放大器的一结构示意图；5 is a schematic structural diagram of a telescopic operational amplifier provided by an embodiment of the present invention;
图6是本发明实施例提供的基准电压源的又一电路原理图；6 is another schematic circuit diagram of the reference voltage source provided by the embodiment of the present invention;
图7是本发明实施例提供的套筒式运算放大器的另一结构示意图，图中示意了第二偏置电路的电路图。FIG. 7 is another structural schematic diagram of the telescopic operational amplifier provided by the embodiment of the present invention, in which the circuit diagram of the second bias circuit is shown.
具体实施方式Detailed ways
请参照图式，其中相同的组件符号代表相同的组件，本发明的原理是以实施在一适当的运算环境中来举例说明。以下的说明是基于所例示的本发明具体实施例，其不应被视为限制本发明未在此详述的其它具体实施例。Referring to the drawings, wherein like reference numerals represent like components, the principles of the present invention are exemplified when implemented in a suitable computing environment. The following description is based on illustrated specific embodiments of the invention, which should not be construed as limiting other specific embodiments of the invention not described in detail herein.
参阅图3，本发明实施例提供的一种基准电压源100，包括套筒式运算放大器11和基准电压产生核电路12。Referring to FIG. 3 , a reference voltage source 100 provided by an embodiment of the present invention includes a telescopic operational amplifier 11 and a reference voltage generating core circuit 12 .
其中，所述套筒式运算放大器11包括第一PMOS管P31、第二PMOS管P32、第一NMOS管N31、第二NMOS管N32以及电流产生电路。所述基准电压产生核电路12包括第三PMOS管P33、第一电阻R31、第二电阻R32、第三电阻R33、第一导通元件和第二导通元件。Wherein, the telescopic operational amplifier 11 includes a first PMOS transistor P31 , a second PMOS transistor P32 , a first NMOS transistor N31 , a second NMOS transistor N32 and a current generating circuit. The reference voltage generating core circuit 12 includes a third PMOS transistor P33, a first resistor R31, a second resistor R32, a third resistor R33, a first conduction element and a second conduction element.
所述第一PMOS管P31的栅极和漏极、所述第二PMOS管P32的栅极与所述第一NMOS管N31的漏极连接，所述第一PMOS管P31的源极和所述第二PMOS管P32的源极与电源电压VDD连接，所述第二PMOS管P32的漏极为所述套筒式运算放大器11的输出端OPOUT，并与所述第二NMOS管N32的漏极连接，所述第一NMOS管N31的源极与所述第二NMOS管N32的源极连接且通过所述电流产生电路接地，所述第一NMOS管N31的栅极和所述第二NMOS管N32的栅极分别为所述套筒式运算放大器11的正输入端VP和负输入端VN。The gate and drain of the first PMOS transistor P31, the gate of the second PMOS transistor P32 are connected to the drain of the first NMOS transistor N31, the source of the first PMOS transistor P31 is connected to the The source of the second PMOS transistor P32 is connected to the power supply voltage VDD, the drain of the second PMOS transistor P32 is the output terminal OPOUT of the telescopic operational amplifier 11, and is connected to the drain of the second NMOS transistor N32 , the source of the first NMOS transistor N31 is connected to the source of the second NMOS transistor N32 and grounded through the current generating circuit, the gate of the first NMOS transistor N31 is connected to the second NMOS transistor N32 The gates of are respectively the positive input terminal VP and the negative input terminal VN of the telescopic operational amplifier 11 .
可选地，本发明实施例中，电流产生电路可以采用第五电阻R35实现，即电流产生电路包括第五电阻R35，所述第五电阻R35的一端与所述第一NMOS管N31和所述第二NMOS管N32的源极连接，所述第五电阻R35的另一端接地，从而通过第五电阻R35为套筒式运算放大器11提供工作所需的电流。当然，在其他实施方式中，电流产生电路也可以采用其他结构实现，例如，如图4所示，电流产生电路也可以采用一个电流源I1实现，其中，所述电流源I1的输入端与所述第一NMOS管N31和所述第二NMOS管N32的源极连接，所述电流源I1的输出端接地，通过电流源I1可以为套筒式运算放大器11提供工作所需的电流。Optionally, in the embodiment of the present invention, the current generating circuit can be realized by using the fifth resistor R35, that is, the current generating circuit includes the fifth resistor R35, and one end of the fifth resistor R35 is connected to the first NMOS transistor N31 and the The source of the second NMOS transistor N32 is connected, and the other end of the fifth resistor R35 is grounded, so as to provide the telescopic operational amplifier 11 with current required for operation through the fifth resistor R35 . Of course, in other implementation manners, the current generating circuit can also be implemented with other structures. For example, as shown in FIG. The sources of the first NMOS transistor N31 and the second NMOS transistor N32 are connected, the output end of the current source I1 is grounded, and the current source I1 can provide the telescopic operational amplifier 11 with the current required for operation.
继续参阅图3，所述第三PMOS管P33的栅极与所述套筒式运算放大器11的输出端OPOUT连接，所述第三PMOS管P33的源极与所述电压电源VDD 连接，所述第一电阻R31的一端和所述第二电阻R32的一端与所述第三PMOS管的漏极连接，所述第一电阻R31的另一端与所述负输入端VN连接，并通过所述第一导通元件接地，所述第二电阻R32的另一端与所述正输入端VP和所述第三电阻R33的一端连接，所述第三电阻R33的另一端通过所述第二导通元件接地，所述第三PMOS管的漏极为所述基准电压产生核电路12的输出端，用于输出基准电压VREF。所述套筒式运算放大器11用于电压钳位，即：根据理想运算放大器原理，其正负输入端的电压相等：VN＝VP。Continuing to refer to FIG. 3, the gate of the third PMOS transistor P33 is connected to the output terminal OPOUT of the telescopic operational amplifier 11, and the source of the third PMOS transistor P33 is connected to the voltage power supply VDD. One end of the first resistor R31 and one end of the second resistor R32 are connected to the drain of the third PMOS transistor, and the other end of the first resistor R31 is connected to the negative input terminal VN, and passes through the first A conduction element is grounded, the other end of the second resistor R32 is connected to the positive input terminal VP and one end of the third resistor R33, and the other end of the third resistor R33 passes through the second conduction element Grounded, the drain of the third PMOS transistor is the output terminal of the reference voltage generation core circuit 12 for outputting the reference voltage VREF. The telescopic operational amplifier 11 is used for voltage clamping, that is, according to the principle of an ideal operational amplifier, the voltages at its positive and negative input terminals are equal: VN=VP.
可选地，本发明实施例中，第一导通元件和第二导通元件均可采用二极管或者PNP型双极型晶体管实现，以二极管为例，第一导通元件为二极管Q31，第二导通元件为二极管Q32，其中第一导通元件和第二导通元件的个数比可以是1：N，N为大于等于2的整数，例如N可以是8，即当第一导通元件为1个时，第二导通元件有8个。更进一步地，多个第二导通元件与第四电阻R33并联，比如，作为第二导通元件的二极管Q32有N个，N个二极管Q32的正极与第三电阻R33并联，N个二极管Q32的负极接地。此外，当第一导通元件有多个时，即二极管Q31为多个时，多个二极管Q32为并联连接。Optionally, in this embodiment of the present invention, both the first conduction element and the second conduction element can be realized by using a diode or a PNP bipolar transistor. Taking a diode as an example, the first conduction element is a diode Q31, and the second conduction element is a diode Q31. The conduction element is a diode Q32, wherein the number ratio of the first conduction element to the second conduction element can be 1:N, N is an integer greater than or equal to 2, for example, N can be 8, that is, when the first conduction element When the number is one, there are eight second conduction elements. Furthermore, a plurality of second conduction elements are connected in parallel with the fourth resistor R33, for example, there are N diodes Q32 as the second conduction elements, the anodes of the N diodes Q32 are connected in parallel with the third resistor R33, and the N diodes Q32 The negative terminal is grounded. In addition, when there are multiple first conduction elements, that is, when there are multiple diodes Q31, the multiple diodes Q32 are connected in parallel.
其中，基准电压产生核电路12产生的基准电压的计算公式如下：Wherein, the calculation formula of the reference voltage generated by the reference voltage generating nuclear circuit 12 is as follows:
Figure PCTCN2022090596-appb-000001
Figure PCTCN2022090596-appb-000001
ΔV PN＝V Tln(N) ΔV PN =V T ln(N)
其中，V PN为二极管Q31、Q32或者所述PNP型双极型晶体管的正向导通压降，V T表示热电压，在温度为300K时，V T≈26mV，N为所述第二导通元件和所述第一导通元件的个数比，R31和R33分别表示第一电阻和第三电阻的阻值。 Wherein, V PN is the forward conduction voltage drop of the diodes Q31, Q32 or the PNP bipolar transistor, V T represents the thermal voltage, when the temperature is 300K, V T ≈ 26mV, N is the second conduction The number ratio of the element to the first conduction element, R31 and R33 represent the resistance values of the first resistor and the third resistor, respectively.
与现有技术相比，本发明实施例的基准电压源100，通过套筒式运算放大器11的输出端直接连接至基准电压产生核电路12的第三PMOS管P33，基准电压产生核电路12中没有电流镜P11/P12/P13，因此基准电压源100的精度不会受到电流镜P11/P12/P13电流失配的影响，由此可以提高基准电压源的精度。Compared with the prior art, the reference voltage source 100 of the embodiment of the present invention is directly connected to the third PMOS transistor P33 of the reference voltage generating core circuit 12 through the output end of the telescopic operational amplifier 11, and the reference voltage generating core circuit 12 There is no current mirror P11/P12/P13, so the accuracy of the reference voltage source 100 will not be affected by the current mismatch of the current mirror P11/P12/P13, thereby improving the accuracy of the reference voltage source.
此外，与现有的运算放大器相比，本发明实施例中的套筒式运算放大器11的输入失调电压的来源只有N31/N32电压失配、电流镜P31/P32失配，比常见的运算放大器失配源少一对，有利于减小输入失调电压，理论上可以将输入失 调电压减小1/3，从而进一步减小输入失调电压对基准电压源100的精度的影响。In addition, compared with the existing operational amplifiers, the source of the input offset voltage of the telescopic operational amplifier 11 in the embodiment of the present invention is only the N31/N32 voltage mismatch and the current mirror P31/P32 mismatch. The lack of one pair of mismatching sources is beneficial to reduce the input offset voltage. Theoretically, the input offset voltage can be reduced by 1/3, thereby further reducing the impact of the input offset voltage on the accuracy of the reference voltage source 100 .
本发明的基准电压源100，正常工作所需电源电压VDD为VDD≥VREF+V DSP＝1.2V+0.2V＝1.4V，实现了超低压工作的目标。其中，V DSP表示PMOS器件源漏两端的电压差，一般设计值为0.2V。 For the reference voltage source 100 of the present invention, the power supply voltage VDD required for normal operation is VDD≧VREF+V DSP =1.2V+0.2V=1.4V, achieving the goal of ultra-low voltage operation. Among them, V DSP represents the voltage difference between the source and drain of the PMOS device, and the general design value is 0.2V.
可选地，本发明的一些实施例中，如图5所示，所述套筒式运算放大器11还包括第三NMOS管N33和第四NMOS管N34，由此可构成共源共栅结构，有利于提高运算放大器的增益。所述第一PMOS管P31的栅极和漏极通过所述第三NMOS管N33与所述第一NOMS管N31的漏极连接，所述第二PMOS管P32的漏极通过所述第四NMOS管N34与所述第二NMOS管N32的漏极连接。Optionally, in some embodiments of the present invention, as shown in FIG. 5 , the telescopic operational amplifier 11 further includes a third NMOS transistor N33 and a fourth NMOS transistor N34, thereby forming a cascode structure, It is beneficial to increase the gain of the operational amplifier. The gate and drain of the first PMOS transistor P31 are connected to the drain of the first NOMS transistor N31 through the third NMOS transistor N33, and the drain of the second PMOS transistor P32 is connected through the fourth NMOS transistor N33. The transistor N34 is connected to the drain of the second NMOS transistor N32.
其中，所述第三NMOS管N33的栅极和漏极、所述第四NMOS管N34的栅极与所述第一PMOS管P31的栅极和漏极连接，所述第三NMO管N33的源极与所述第一NMOS管N31的漏极连接，所述第四NMOS管N34的漏极与所述第二PMOS管P32的漏极连接，所述第四NMOS管N34的源极与所述第二NMOS管N32的漏极连接。Wherein, the gate and drain of the third NMOS transistor N33, the gate of the fourth NMOS transistor N34 are connected to the gate and drain of the first PMOS transistor P31, and the gate and drain of the third NMOS transistor N33 The source is connected to the drain of the first NMOS transistor N31, the drain of the fourth NMOS transistor N34 is connected to the drain of the second PMOS transistor P32, and the source of the fourth NMOS transistor N34 is connected to the drain of the fourth NMOS transistor N34. The drain of the second NMOS transistor N32 is connected.
在图5所示的实施例中，套筒式运算放大器11的第三NMOS管N33和第四NMOS管N34均由电源电压VDD提供偏置电压，与图5所示实施例不同的是，参阅图6，在本发明的另一些实施例中，还可以设置一个偏置电路为第三NMOS管N33和第四NMOS管N34提供偏置电压。具体地，基准电压源100还包括用于提供第一偏置电压NBIAS的第一偏置电路13，其中，所述第三NMOS管N33的栅极和所述第四NMOS管N34的栅极连接并连接至所述第一偏置电路13，所述第三NMOS管N33的漏极与所述第一PMOS管P31的栅极和漏极连接，所述第三NMO管N33的源极与所述第一NMOS管N31的漏极连接，所述第四NMOS管N34的漏极与所述第二PMOS管P32的漏极连接，所述第四NMOS管N34的源极与所述第二NMOS管N32的漏极连接。In the embodiment shown in FIG. 5, both the third NMOS transistor N33 and the fourth NMOS transistor N34 of the telescopic operational amplifier 11 are biased by the power supply voltage VDD. The difference from the embodiment shown in FIG. FIG. 6 , in some other embodiments of the present invention, a bias circuit may also be set to provide bias voltages for the third NMOS transistor N33 and the fourth NMOS transistor N34. Specifically, the reference voltage source 100 further includes a first bias circuit 13 for providing a first bias voltage NBIAS, wherein the gate of the third NMOS transistor N33 is connected to the gate of the fourth NMOS transistor N34 and connected to the first bias circuit 13, the drain of the third NMOS transistor N33 is connected to the gate and drain of the first PMOS transistor P31, the source of the third NMOS transistor N33 is connected to the The drain of the first NMOS transistor N31 is connected, the drain of the fourth NMOS transistor N34 is connected to the drain of the second PMOS transistor P32, and the source of the fourth NMOS transistor N34 is connected to the second NMOS transistor N34. The drain connection of tube N32.
更进一步地，所述第一偏置电路13包括第四电阻R34、第五NMOS管N35以及第三导通元件。所述第四电阻R34的一端与所述电源电压VDD连接，所述第四电阻R34的另一端与所述第五NMOS管N35的栅极和漏极连接，所述第五NMOS管N35的漏极与所述第三NMOS管N33的栅极、所述第四NMOS 管N34的栅极连接，所述第三NMOS管N35的源极通过所述第三导通元件接地。Furthermore, the first bias circuit 13 includes a fourth resistor R34, a fifth NMOS transistor N35 and a third pass element. One end of the fourth resistor R34 is connected to the power supply voltage VDD, the other end of the fourth resistor R34 is connected to the gate and drain of the fifth NMOS transistor N35, and the drain of the fifth NMOS transistor N35 The pole is connected to the gate of the third NMOS transistor N33 and the gate of the fourth NMOS transistor N34, and the source of the third NMOS transistor N35 is grounded through the third pass element.
可选地，所述第三导通元件为二极管或者PNP型双极型晶体管，以二极管为例，所述第三导通元件为二极管Q33。Optionally, the third conduction element is a diode or a PNP bipolar transistor, taking a diode as an example, the third conduction element is a diode Q33.
参阅图7，进一步地，在本发明的一些实施例中，基准电压源100还包括提供第二偏置电压PBIAS的第二偏置电路14，所属第二偏置电路14包括第六PMOS管P36和第六电阻R36。所述套筒式运算放大器11进一步地还包括第四PMOS管P34和第五PMOS管P35，由此构成共源共栅结构，有利于提高运算放大器的增益。所述第三NMOS管N33的漏极通过所述第四PMOS管P34与所述第一PMOS管P31的漏极连接，所述第四NMOS管N34的漏极通过所述第五PMOS管P35与所述第二PMOS管P32的漏极连接。Referring to FIG. 7 , further, in some embodiments of the present invention, the reference voltage source 100 further includes a second bias circuit 14 providing a second bias voltage PBIAS, and the second bias circuit 14 includes a sixth PMOS transistor P36 and the sixth resistor R36. The telescopic operational amplifier 11 further includes a fourth PMOS transistor P34 and a fifth PMOS transistor P35, thereby forming a cascode structure, which is beneficial to increase the gain of the operational amplifier. The drain of the third NMOS transistor N33 is connected to the drain of the first PMOS transistor P31 through the fourth PMOS transistor P34, and the drain of the fourth NMOS transistor N34 is connected to the drain of the fifth PMOS transistor P35. The drain of the second PMOS transistor P32 is connected.
更具体地，所述第四PMOS管P34的栅极和所述第五PMOS管P35的栅极连接并连接至所述第六PMOS管P36的栅极，所述第六PMOS管P36的栅极和漏极连接并且通过所述第六电阻R36接地，所述第六PMOS管P36的源极连接所述电源电压VDD，所述第四PMOS管P34的漏极与所述第三NMOS管N33的漏极连接，所述第四PMOS管P34的源极与所述第一PMOS管P31的漏极连接，所述第五PMOS管P35的源极与所述第二PMOS管P32的漏极连接，所述第五PMOS管P35的漏极与所述第四NMOS管N34的漏极连接，所述套筒式运算放大器11的输出端OPOUT从所述第五PMOS管P35的漏极引出。More specifically, the gate of the fourth PMOS transistor P34 is connected to the gate of the fifth PMOS transistor P35 and connected to the gate of the sixth PMOS transistor P36, and the gate of the sixth PMOS transistor P36 connected to the drain and grounded through the sixth resistor R36, the source of the sixth PMOS transistor P36 is connected to the power supply voltage VDD, the drain of the fourth PMOS transistor P34 is connected to the third NMOS transistor N33 The drain is connected, the source of the fourth PMOS transistor P34 is connected to the drain of the first PMOS transistor P31, the source of the fifth PMOS transistor P35 is connected to the drain of the second PMOS transistor P32, The drain of the fifth PMOS transistor P35 is connected to the drain of the fourth NMOS transistor N34, and the output terminal OPOUT of the telescopic operational amplifier 11 is drawn out from the drain of the fifth PMOS transistor P35.
本文中应用了具体个例对本发明的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本发明的方法及其核心思想；同时，对于本领域的技术人员，依据本发明的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本发明的限制。In this paper, specific examples have been used to illustrate the principle and implementation of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; meanwhile, for those skilled in the art, according to the present invention Thoughts, specific implementation methods and scope of application all have changes. In summary, the contents of this specification should not be construed as limiting the present invention.

Claims (10)

  1. 一种基准电压源，其特征在于，包括套筒式运算放大器和基准电压产生核电路；A reference voltage source, characterized in that it includes a telescopic operational amplifier and a reference voltage generation core circuit;
    所述套筒式运算放大器包括第一PMOS管P31、第二PMOS管P32、第一NMOS管N31、第二NMOS管N32以及电流产生电路；所述基准电压产生核电路包括第三PMOS管P33、第一电阻R31、第二电阻R32、第三电阻R33、第一导通元件和第二导通元件；The telescopic operational amplifier includes a first PMOS transistor P31, a second PMOS transistor P32, a first NMOS transistor N31, a second NMOS transistor N32, and a current generating circuit; the reference voltage generating core circuit includes a third PMOS transistor P33, a first resistor R31, a second resistor R32, a third resistor R33, a first conduction element and a second conduction element;
    所述第一PMOS管P31的栅极和漏极、所述第二PMOS管P32的栅极与所述第一NMOS管N31的漏极连接，所述第一PMOS管P31的源极和所述第二PMOS管P32的源极与电源电压VDD连接，所述第二PMOS管P32的漏极为所述套筒式运算放大器的输出端，并与所述第二NMOS管N32的漏极连接，所述第一NMOS管N31的源极与所述第二NMOS管N32的源极连接且通过所述电流产生电路接地，所述第一NMOS管N31的栅极和所述第二NMOS管N32的栅极分别为所述套筒式运算放大器的正输入端VP和负输入端VN；The gate and drain of the first PMOS transistor P31, the gate of the second PMOS transistor P32 are connected to the drain of the first NMOS transistor N31, the source of the first PMOS transistor P31 is connected to the The source of the second PMOS transistor P32 is connected to the power supply voltage VDD, the drain of the second PMOS transistor P32 is the output end of the telescopic operational amplifier, and is connected to the drain of the second NMOS transistor N32, so The source of the first NMOS transistor N31 is connected to the source of the second NMOS transistor N32 and grounded through the current generating circuit, the gate of the first NMOS transistor N31 and the gate of the second NMOS transistor N32 The poles are respectively the positive input terminal VP and the negative input terminal VN of the telescopic operational amplifier;
    所述第三PMOS管P33的栅极与所述套筒式运算放大器的输出端连接，所述第三PMOS管P33的源极与所述电压电源VDD连接，所述第一电阻R31的一端和所述第二电阻R32的一端与所述第三PMOS管的漏极连接，所述第一电阻R31的另一端与所述负输入端VN连接，并通过所述第一导通元件接地，所述第二电阻R32的另一端与所述正输入端VP和所述第三电阻R33的一端连接，所述第三电阻R33的另一端通过所述第二导通元件接地，所述第三PMOS管的漏极为所述基准电压产生核电路的输出端，用于输出基准电压VREF。The gate of the third PMOS transistor P33 is connected to the output terminal of the telescopic operational amplifier, the source of the third PMOS transistor P33 is connected to the voltage power supply VDD, and one end of the first resistor R31 and One end of the second resistor R32 is connected to the drain of the third PMOS transistor, the other end of the first resistor R31 is connected to the negative input terminal VN, and grounded through the first conduction element, so The other end of the second resistor R32 is connected to the positive input terminal VP and one end of the third resistor R33, the other end of the third resistor R33 is grounded through the second conduction element, and the third PMOS The drain of the tube is the output terminal of the reference voltage generating core circuit for outputting the reference voltage VREF.
  2. 根据权利要求1所述的基准电压源，其特征在于，所述套筒式运算放大器还包括第三NMOS管N33和第四NMOS管N34，所述第一PMOS管P31的栅极和漏极通过所述第三NMOS管N33与所述第一NOMS管N31的漏极连接，所述第二PMOS管P32的漏极通过所述第四NMOS管N34与所述第二NMOS管N32的漏极连接；The reference voltage source according to claim 1, wherein the telescopic operational amplifier further comprises a third NMOS transistor N33 and a fourth NMOS transistor N34, and the gate and drain of the first PMOS transistor P31 pass through The third NMOS transistor N33 is connected to the drain of the first NOMS transistor N31, and the drain of the second PMOS transistor P32 is connected to the drain of the second NMOS transistor N32 through the fourth NMOS transistor N34 ;
    其中，所述第三NMOS管N33的栅极和漏极、所述第四NMOS管N34的栅极与所述第一PMOS管P31的栅极和漏极连接，所述第三NMO管N33的源极与所述第一NMOS管N31的漏极连接，所述第四NMOS管N34的漏极与所 述第二PMOS管P32的漏极连接，所述第四NMOS管N34的源极与所述第二NMOS管N32的漏极连接。Wherein, the gate and drain of the third NMOS transistor N33, the gate of the fourth NMOS transistor N34 are connected to the gate and drain of the first PMOS transistor P31, and the gate and drain of the third NMOS transistor N33 The source is connected to the drain of the first NMOS transistor N31, the drain of the fourth NMOS transistor N34 is connected to the drain of the second PMOS transistor P32, and the source of the fourth NMOS transistor N34 is connected to the drain of the fourth NMOS transistor N34. The drain of the second NMOS transistor N32 is connected.
  3. 根据权利要求1所述的基准电压源，其特征在于，还包括用于提供第一偏置电压的第一偏置电路；所述套筒式运算放大器还包括第三NMOS管N33和第四NMOS管N34，所述第一PMOS管P31的栅极和漏极通过所述第三NMOS管N33与所述第一NOMS管N31的漏极连接，所述第二PMOS管P32的漏极通过所述第四NMOS管N34与所述第二NMOS管N32的漏极连接；The reference voltage source according to claim 1, further comprising a first bias circuit for providing a first bias voltage; the telescopic operational amplifier further comprises a third NMOS transistor N33 and a fourth NMOS transistor N33 N34, the gate and drain of the first PMOS transistor P31 are connected to the drain of the first NOMS transistor N31 through the third NMOS transistor N33, and the drain of the second PMOS transistor P32 is connected through the third NMOS transistor N33 The fourth NMOS transistor N34 is connected to the drain of the second NMOS transistor N32;
    其中，所述第三NMOS管N33的栅极和所述第四NMOS管N34的栅极连接并连接至所述第一偏置电路，所述第三NMOS管N33的漏极与所述第一PMOS管P31的栅极和漏极连接，所述第三NMO管N33的源极与所述第一NMOS管N31的漏极连接，所述第四NMOS管N34的漏极与所述第二PMOS管P32的漏极连接，所述第四NMOS管N34的源极与所述第二NMOS管N32的漏极连接。Wherein, the gate of the third NMOS transistor N33 is connected to the gate of the fourth NMOS transistor N34 and connected to the first bias circuit, and the drain of the third NMOS transistor N33 is connected to the first bias circuit. The gate of the PMOS transistor P31 is connected to the drain, the source of the third NMOS transistor N33 is connected to the drain of the first NMOS transistor N31, and the drain of the fourth NMOS transistor N34 is connected to the second PMOS transistor N31. The drain of the transistor P32 is connected, and the source of the fourth NMOS transistor N34 is connected to the drain of the second NMOS transistor N32.
  4. 根据权利要求3所述的基准电压源，其特征在于，还包括提供第二偏置电压的第二偏置电路，所述套筒式运算放大器还包括第四PMOS管P34和第五PMOS管P35，所述第三NMOS管N33的漏极通过所述第四PMOS管P34与所述第一PMOS管P31的漏极连接，所述第四NMOS管N34的漏极通过所述第五PMOS管P35与所述第二PMOS管P32的漏极连接；The reference voltage source according to claim 3, further comprising a second bias circuit providing a second bias voltage, and the telescopic operational amplifier further comprising a fourth PMOS transistor P34 and a fifth PMOS transistor P35 , the drain of the third NMOS transistor N33 is connected to the drain of the first PMOS transistor P31 through the fourth PMOS transistor P34, and the drain of the fourth NMOS transistor N34 is connected through the fifth PMOS transistor P35 connected to the drain of the second PMOS transistor P32;
    其中，所述第四PMOS管P34的栅极和所述第五PMOS管P35的栅极连接并连接至所述第二偏置电路，所述第四PMOS管P34的漏极与所述第三NMOS管N33的漏极连接，所述第四PMOS管P34的源极与所述第一PMOS管P31的漏极连接，所述第五PMOS管P35的源极与所述第二PMOS管P32的漏极连接，所述第五PMOS管P35的漏极与所述第四NMOS管N34的漏极连接，所述套筒式运算放大器的输出端从所述第五PMOS管P35的漏极引出。Wherein, the gate of the fourth PMOS transistor P34 is connected to the gate of the fifth PMOS transistor P35 and connected to the second bias circuit, and the drain of the fourth PMOS transistor P34 is connected to the third bias circuit. The drain of the NMOS transistor N33 is connected, the source of the fourth PMOS transistor P34 is connected to the drain of the first PMOS transistor P31, and the source of the fifth PMOS transistor P35 is connected to the second PMOS transistor P32. The drain is connected, the drain of the fifth PMOS transistor P35 is connected to the drain of the fourth NMOS transistor N34, and the output terminal of the telescopic operational amplifier is drawn from the drain of the fifth PMOS transistor P35.
  5. 根据权利要求3所述的基准电压源，其特征在于，所述第一偏置电路包括第四电阻R34、第五NMOS管N35以及第三导通元件；The reference voltage source according to claim 3, wherein the first bias circuit comprises a fourth resistor R34, a fifth NMOS transistor N35 and a third conduction element;
    所述第四电阻R34的一端与所述电源电压VDD连接，所述第四电阻R34的另一端与所述第五NMOS管N35的栅极和漏极连接，所述第五NMOS管N35的漏极与所述第三NMOS管N33的栅极、所述第四NMOS管N34的栅极连接， 所述第三NMOS管N35的源极通过所述第三导通元件接地。One end of the fourth resistor R34 is connected to the power supply voltage VDD, the other end of the fourth resistor R34 is connected to the gate and drain of the fifth NMOS transistor N35, and the drain of the fifth NMOS transistor N35 The pole is connected to the gate of the third NMOS transistor N33 and the gate of the fourth NMOS transistor N34, and the source of the third NMOS transistor N35 is grounded through the third conduction element.
  6. 根据权利要求5所述的基准电压源，其特征在于，所述第三导通元件为二极管或者PNP型双极型晶体管。The reference voltage source according to claim 5, wherein the third conduction element is a diode or a PNP bipolar transistor.
  7. 根据权利要求1所述的基准电压源，其特征在于，所述第一导通元件为二极管或者PNP型双极型晶体管，所述第二导通元件为二极管或PNP型双极型晶体管。The reference voltage source according to claim 1, wherein the first conduction element is a diode or a PNP bipolar transistor, and the second conduction element is a diode or a PNP bipolar transistor.
  8. 根据权利要求7所述的基准电压源，其特征在于，所述第一导通元件和所述第二导通元件的个数比为1：N，N为大于等于2的整数。The reference voltage source according to claim 7, wherein the number ratio of the first conduction element to the second conduction element is 1:N, and N is an integer greater than or equal to 2.
  9. 根据权利要求1所述的基准电压源，其特征在于，所述电流产生电路包括第五电阻R35，所述第五电阻R35的一端与所述第一NMOS管N31和所述第二NMOS管N32的源极连接，所述第五电阻R35的另一端接地。The reference voltage source according to claim 1, wherein the current generating circuit comprises a fifth resistor R35, one end of the fifth resistor R35 is connected to the first NMOS transistor N31 and the second NMOS transistor N32 The source of the fifth resistor R35 is connected to the ground.
  10. 根据权利要求1所述的基准电压源，其特征在于，所述电流产生电路为电流源I1，所述电流源I1的输入端与所述第一NMOS管N31和所述第二NMOS管N32的源极连接，所述电流源I1的输出端接地。The reference voltage source according to claim 1, wherein the current generating circuit is a current source I1, the input terminal of the current source I1 is connected to the first NMOS transistor N31 and the second NMOS transistor N32 The source is connected, and the output terminal of the current source I1 is grounded.
PCT/CN2022/090596 2021-12-15 2022-04-29 Reference voltage source WO2023108990A1 (en)

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Publication number Priority date Publication date Assignee Title
CN114265461A (en) * 2021-12-15 2022-04-01 深圳飞骧科技股份有限公司 Reference voltage source

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060055383A1 (en) * 2004-09-14 2006-03-16 Dialog Semiconductor Gmbh Adaptive biasing concept for current mode voltage regulators
CN102622038A (en) * 2012-03-29 2012-08-01 北京经纬恒润科技有限公司 Band-gap reference voltage source circuit and band-gap reference voltage source
CN104503528A (en) * 2014-12-24 2015-04-08 电子科技大学 Low-noise band-gap reference circuit reducing detuning influence
US20160274617A1 (en) * 2015-03-17 2016-09-22 Sanjay Kumar Wadhwa Bandgap circuit
CN110928353A (en) * 2019-11-25 2020-03-27 上海申矽凌微电子科技有限公司 PTAT current source circuit
CN111045470A (en) * 2020-01-15 2020-04-21 西安电子科技大学 Band-gap reference circuit with low offset voltage and high power supply rejection ratio
CN113126689A (en) * 2019-12-31 2021-07-16 圣邦微电子（北京）股份有限公司 Direct current trimming module and band gap reference circuit adopting direct current trimming
CN114265461A (en) * 2021-12-15 2022-04-01 深圳飞骧科技股份有限公司 Reference voltage source

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6407623B1 (en) * 2001-01-31 2002-06-18 Qualcomm Incorporated Bias circuit for maintaining a constant value of transconductance divided by load capacitance
JP2003063062A (en) * 2001-08-23 2003-03-05 Oki Data Corp Control voltage generating circuit, and printhead and printer using the same
CN101443997A (en) * 2006-11-30 2009-05-27 松下电器产业株式会社 Operational amplifier
US7605654B2 (en) * 2008-03-13 2009-10-20 Mediatek Inc. Telescopic operational amplifier and reference buffer utilizing the same
CN201936216U (en) * 2011-01-31 2011-08-17 成都瑞芯电子有限公司 Reference voltage source with wide input voltage and high power supply rejection ratio
CN104767496B (en) * 2014-08-27 2018-12-11 北京中电华大电子设计有限责任公司 A kind of frequency compensated circuit improving operational amplifier power supply rejection ratio
CN104503527A (en) * 2014-11-25 2015-04-08 上海华力微电子有限公司 Reference current generating circuit
CN104616690B (en) * 2014-12-24 2018-06-19 中国科学院上海微系统与信息技术研究所 Phase transition storage reading circuit and reading method based on diode selection
CN104503530B (en) * 2015-01-09 2016-11-16 中国科学技术大学 A kind of low voltage CMOS reference voltage source of high-performance high-reliability
CN106094955A (en) * 2016-07-20 2016-11-09 成都启英泰伦科技有限公司 A kind of low-dropout linear voltage-regulating circuit of low-power consumption
US10429878B2 (en) * 2018-01-10 2019-10-01 Ememory Technology Inc. Test device
CN108900168A (en) * 2018-06-27 2018-11-27 重庆湃芯入微科技有限公司 The collapsible difference that output end can increase output voltage swing turns single-ended amplifier
CN113760031B (en) * 2021-09-13 2023-09-01 苏州大学 Low quiescent current NMOS type full-integrated LDO circuit

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060055383A1 (en) * 2004-09-14 2006-03-16 Dialog Semiconductor Gmbh Adaptive biasing concept for current mode voltage regulators
CN102622038A (en) * 2012-03-29 2012-08-01 北京经纬恒润科技有限公司 Band-gap reference voltage source circuit and band-gap reference voltage source
CN104503528A (en) * 2014-12-24 2015-04-08 电子科技大学 Low-noise band-gap reference circuit reducing detuning influence
US20160274617A1 (en) * 2015-03-17 2016-09-22 Sanjay Kumar Wadhwa Bandgap circuit
CN110928353A (en) * 2019-11-25 2020-03-27 上海申矽凌微电子科技有限公司 PTAT current source circuit
CN113126689A (en) * 2019-12-31 2021-07-16 圣邦微电子（北京）股份有限公司 Direct current trimming module and band gap reference circuit adopting direct current trimming
CN111045470A (en) * 2020-01-15 2020-04-21 西安电子科技大学 Band-gap reference circuit with low offset voltage and high power supply rejection ratio
CN114265461A (en) * 2021-12-15 2022-04-01 深圳飞骧科技股份有限公司 Reference voltage source

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