WO2023103358A1 - 编程装置、方法及新型存储器 - Google Patents

编程装置、方法及新型存储器 Download PDF

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Publication number
WO2023103358A1
WO2023103358A1 PCT/CN2022/102419 CN2022102419W WO2023103358A1 WO 2023103358 A1 WO2023103358 A1 WO 2023103358A1 CN 2022102419 W CN2022102419 W CN 2022102419W WO 2023103358 A1 WO2023103358 A1 WO 2023103358A1
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Prior art keywords
programming
switch
clock
flip
control
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PCT/CN2022/102419
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English (en)
French (fr)
Inventor
沈灵
温建新
蒋宇
严慧婕
Original Assignee
上海集成电路装备材料产业创新中心有限公司
上海集成电路研发中心有限公司
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Priority claimed from CN202111494342.XA external-priority patent/CN114242141A/zh
Priority claimed from CN202111496692.XA external-priority patent/CN114242142A/zh
Application filed by 上海集成电路装备材料产业创新中心有限公司, 上海集成电路研发中心有限公司 filed Critical 上海集成电路装备材料产业创新中心有限公司
Publication of WO2023103358A1 publication Critical patent/WO2023103358A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/12—Programming voltage switching circuits

Definitions

  • the present application relates to the field of integrated circuit design, in particular to a programming device, method and new memory.
  • Memory is a collection of storage units arranged in order of unit number. Each unit consists of several binary bits to represent the value stored in the storage unit.
  • Traditional memories such as flash memory Flash and Dynamic Random Access Memory (DRAM), change the electrical characteristics of the cell by injecting charge into the cell to store data "0" and data "1".
  • DRAM Dynamic Random Access Memory
  • a new type of memory such as Resistive Random Access Memory (RRAM) is a non-volatile memory based on the reversible conversion between the high-resistance state and the low-resistance state under the action of the resistance of the non-conductive material. The memory is used as the judgment condition of the storage signal according to the size of its own resistance value.
  • FIG. 1 is a schematic diagram of a programming structure of a traditional flash memory array.
  • this method is not suitable for new types of memory.
  • the programming current of a single resistive variable unit in a new type of memory is very high, and programming at the same time will result in excessive current, and there is a risk that the chip will be burned due to heat.
  • FIG. 2 it is a schematic diagram of a programming structure of a resistive memory array provided by the present application, but there is a problem of how to control the selection of some resistive memory cells in the programming method.
  • the programming device, method and new memory provided by the present application provide a A structure that can not only solve the partial selection of cells but also realize cell traversal.
  • the application provides a programming device, a method and a new type of memory, which are used to solve the programming problem of the new type of memory.
  • the application provides a programming device, including: a programming control unit and a programming unit;
  • the programming control unit is used to respond to the control clock, and sequentially use each valid storage unit in the row to be programmed as the first unit, and perform processing until all valid storage units are programmed: select the first unit and subsequent valid storage units according to a predetermined number
  • the storage unit is configured as a programming state, and the unselected effective storage cells after the first unit are configured as a non-programming state;
  • the programming unit is configured to program valid storage cells currently configured in a programming state according to a predetermined cycle until all valid storage cells are programmed.
  • the present application provides a programming method, which is applied to a programming device, and the programming device includes a programming control unit and a programming unit; the method includes: the programming control unit responds to the control clock, sequentially takes each effective storage unit in the row to be programmed as the first unit, Perform the following processing until all valid memory cells are programmed: according to the predetermined number, select the first cell and the valid memory cells after it, configure it as a programming state, and configure the unselected valid memory cells after the first cell as non-programming state: the programming unit executes programming the valid storage cells currently configured as the programming state according to a predetermined cycle until all valid storage cells are programmed.
  • the present application provides a hardware code product, including hardware code, and when the hardware code is executed by a processor, the method in the second aspect is implemented.
  • the present application provides a readable storage medium, wherein hardware codes are stored in the readable storage medium, and the hardware codes are used to implement the method in the second aspect when executed.
  • the present application provides an electronic device, including: a processor, and a memory communicated with the processor; the memory stores hardware codes; and the processor executes the hardware codes stored in the memory, so as to implement the method according to the second aspect.
  • the present application provides a new type of memory, including a plurality of resistance memory cells, and the programming device according to the first aspect; the programming device is used for programming the resistance memory cells.
  • the present application configures a predetermined number of effective memory cells in a programming state at any time period through the excitation clock control, realizes programming only some cells in a row, effectively controls the total programming current, and avoids the simultaneous programming of all cells in the entire row.
  • the incoming high current will cause the risk of chip heat damage; and it can move in sequence in a row, replace the programmed cells with unprogrammed cells, and realize the traversal of the entire row of cells to be programmed, without setting an external control device, reducing resources consume.
  • FIG. 1 is a schematic diagram of a programming structure of a traditional flash memory array
  • FIG. 2 is a schematic diagram of a resistive memory array programming structure provided by the present application.
  • FIG. 3 is a schematic structural diagram of a programming device provided in Embodiment 1 of the present application.
  • FIG. 4 is a schematic diagram of the working process of a programming device provided in Embodiment 1 of the present application.
  • FIG. 5 is a circuit diagram of a programming control unit provided in Embodiment 1 of the present application.
  • FIG. 6 is a waveform diagram of an external link signal provided in Embodiment 1 of the present application.
  • FIG. 7 is a schematic structural diagram of another programming device provided in Embodiment 1 of the present application.
  • FIG. 8 is a schematic structural diagram of another programming device provided in Embodiment 1 of the present application.
  • FIG. 9 is a circuit diagram of another programming control unit provided in Embodiment 1 of the present application.
  • FIG. 10 is a schematic structural diagram of another programming device provided in Embodiment 1 of the present application.
  • FIG. 11 is a circuit diagram of another programming control unit provided in Embodiment 1 of the present application.
  • FIG. 12 is a signal timing diagram of the programming control unit provided in Embodiment 1 of the present application.
  • FIG. 13 is a schematic structural diagram of a programming device provided in Embodiment 3 of the present application.
  • FIG. 14 is a schematic diagram of the working process of a programming device provided in Embodiment 3 of the present application.
  • FIG. 15 is a circuit diagram of a programming control unit provided in Embodiment 3 of the present application.
  • FIG. 16 is a waveform diagram of an external link signal provided in Embodiment 3 of the present application.
  • FIG. 17 is a schematic structural diagram of a clock generating unit provided in Embodiment 3 of the present application.
  • FIG. 18 is a schematic structural diagram of another clock generating unit provided in Embodiment 3 of the present application.
  • FIG. 19 is a circuit diagram of a clock generating unit provided in Embodiment 3 of the present application.
  • FIG. 20 is a schematic structural diagram of an error reporting unit provided in Embodiment 3 of the present application.
  • FIG. 21 is a circuit diagram of an error reporting unit provided in Embodiment 3 of the present application.
  • FIG. 22 is a schematic structural diagram of a quantity setting unit provided in Embodiment 3 of the present application.
  • FIG. 23 is a circuit diagram of a quantity setting unit provided in Embodiment 3 of the present application.
  • FIG. 24 is a schematic structural diagram of a clock control module provided in Embodiment 3 of the present application.
  • FIG. 25 is a schematic circuit diagram of a second detection module provided in Embodiment 3 of the present application.
  • FIG. 26 is a schematic circuit diagram of a logical computing module provided in Embodiment 3 of the present application.
  • FIG. 27 is a waveform diagram for increasing the number provided by Embodiment 3 of the present application.
  • FIG. 28 is a waveform diagram for reducing the number provided by Embodiment 3 of the present application.
  • FIG. 3 is a schematic structural diagram of a programming device provided in Embodiment 1 of the present application.
  • the programming device includes: a programming control unit 10 and a programming unit 20 .
  • the programming control unit 10 is used for controlling the selection of memory cells to be programmed
  • the programming unit 20 is used for programming the selected memory cells.
  • the programming control unit 10 in response to the control clock, sequentially takes each valid storage unit in the row to be programmed as the first unit, and performs processing until all valid storage units are programmed: select the first unit and subsequent valid storage units according to a predetermined number.
  • the memory cell is configured in a programmed state, and the unselected effective memory cells after the first cell are configured in a non-programmed state.
  • the programming unit 20 executes programming the valid storage cells currently configured as the programming state according to a predetermined cycle until all valid storage cells are programmed.
  • FIG. 4 is a schematic diagram of a working process of a programming device provided in Embodiment 1 of the present application.
  • a row needs to be written to the memory array, a value is written to the page latch.
  • 1 represents a cell that needs to be programmed
  • 0 represents a cell that does not need to be programmed.
  • the cells marked with 1 are memory cells that need to be programmed. Select the units that need to be programmed, and arrange these units in order to form an effective programming unit chain.
  • N memory units are selected to be in the programming state within a single time. During any programming time, only the adjacent N cells are in the programmed state. Exemplarily, as shown in FIG. 4 , four valid memory cells are selected in a single time to be configured as a programmed state, and other valid memory cells are configured as a non-programmed state.
  • the programming unit 20 sequentially programs the first unit among the four selected effective storage units.
  • the operation of configuring a selected number N of memory cells in a programming state within a single time is performed in an initialization stage before programming.
  • the clock signal control quantity N is input to the effective programming unit chain through an external link, and will be described in detail later in conjunction with the circuit structure of the programming control unit 10.
  • the Active cells box is configured as a storage unit in the programming state, when the programming of the first storage unit in the box is completed, the Active cells move in turn, Add another unprogrammed storage unit and continue programming the first storage unit in the current Active cells box. This operation is repeated until the programming of the last cell is completed.
  • the traversal of the entire row of memory cells to be programmed is realized.
  • FIG. 5 is a circuit diagram of a programming control unit provided in Embodiment 1 of the present application.
  • the programming control unit 10 includes: a programming unit chain composed of a plurality of flip-flops connected in series; wherein, the plurality of flip-flops are in one-to-one correspondence with the page latches corresponding to the memory cells in the row to be programmed.
  • each D flip-flop corresponds to a page latch P.L. (abbreviation for Page Latch), and each page latch P.L. corresponds to a storage unit Cell .
  • the input terminal of the D flip-flop is the "D" terminal; the output terminal is the "Q” terminal; the clock port is the "CLK” terminal.
  • each flip-flop is connected to the excitation clock through the first switch A
  • the output end of each flip-flop is connected to the input end of the next flip-flop through the second switch B
  • the input end of each flip-flop is connected to the input end of the next flip-flop through the second switch B.
  • Three switches E are connected to the input of the next flip-flop.
  • Figure 5 shows the first switch A i+1 , the second switch B i+1 and the third switch E i+ 1 corresponding to the i+1th flip-flop, the output value is C i+1 , and its subscript represents Corresponding flip-flops, and so on, the i+2th flip-flop corresponds to the first switch A i+2 , the second switch B i+2 and the third switch E i+2 (not shown in FIG. 5 ), output The value is C i+2 .
  • the page latch corresponding to each storage unit is used to control the switching states of the first switch A, the second switch B, and the third switch E of the corresponding flip-flop based on its own storage data, so as to establish an effective programming unit chain; wherein,
  • the storage unit corresponding to the flip-flop in the valid programming unit chain is a valid storage unit; wherein, the flip-flop corresponding to the valid storage unit in the programming state is configured as the first logic, and the flip-flop corresponding to the valid storage unit in the non-programming state is configured as second logic.
  • the first logic is 1 and the second logic is 0 as an example for illustration.
  • the programming control unit 10 further includes: a plurality of inverters; the plurality of inverters correspond to a plurality of flip-flops one by one, the input terminals of the inverters are connected to the corresponding page latches, and the inverters The output terminal is connected with the control terminal of the third switch E corresponding to the flip-flop.
  • the method for establishing an effective programming cell chain based on the page memory's own storage data is as follows: when the data stored in the page latch is 1, the first switch A and the second switch B are in a closed state; the third switch E is Disconnected state.
  • the clock port of the D flip-flop can receive a clock signal through the first switch A, and the output end of the current D flip-flop is connected to the input end of the next D flip-flop through the second switch B. At this point, the current D flip-flop is connected in the chain.
  • the first switch A and the second switch B are in an open state; the third switch E is in a closed state.
  • the clock port of the D flip-flop cannot receive the clock signal, and the output end of the current D flip-flop is disconnected from the input end of the next D flip-flop.
  • the next D flip-flop can receive the signal output by the previous D flip-flop through the closed third switch E. At this point, the current D flip-flop is skipped and not connected in the chain.
  • N In a practical application process, the number N needs to be obtained through experiments or calculations. If N is too large, the programming current will be too large, and if N is too small, the programming efficiency will be affected.
  • FIG. 6 is a waveform diagram of an external link signal provided by Embodiment 1 of the present application. Combining with the circuit structure shown in FIG. 5 , a method for configuring N effective memory cells in a programming state is introduced.
  • the programming enable signal Prog_en is used to control the programming mode of the array.
  • Prog_en is always at logic 0, which keeps the array out of programming mode and can be initialized via an external link before programming.
  • the link input signal Chain_In inputs a signal to the input terminal D of the D flip-flop, and the link clock signal CLK_O provides a trigger rising edge excitation signal for the D flip-flop.
  • the D flip-flop includes an input terminal, a clock port, and an output terminal, and the clock port is used for receiving a clock signal.
  • the edge-triggered D flip-flop As an example, its function result is: when the input terminal is logic 1, after receiving the trigger of the rising edge excitation signal, the output terminal outputs 1; when the input terminal is logic 0, the rising edge signal is received After the trigger of the edge excitation signal, the output terminal outputs 0.
  • the first step of initialization write all 1 data to the page latch, so that all D flip-flops are in the link.
  • the second step of initialization through external link clock control, write all D flip-flops to save the state of logic 0.
  • the Chain_In signal is always set to logic 0, and the periodic link clock signal CLK_O is continuously input until all D flip-flops are written to save the state of logic 0.
  • the third step of initialization storing the data to be written in the page latch, so that only the D flip-flops corresponding to the cells to be programmed are in the link, and a valid programming cell chain is established.
  • the Chain_In signal input terminal is set to logic 1
  • the CLK_O signal provides N clock cycles, N is any integer, which can be customized.
  • the Chain_In signal input terminal is set to logic 0.
  • the CLK_O signal provides 2 clock cycles, that is, the CLK_O signal has 2 rising edge signals.
  • D i+1 flip-flops from left to right are D i+1 flip-flops, D i+2 flip-flops, D i+3 flip-flops, and D i+4 flip-flops.
  • the Chain_In signal input is set to logic 1, and the input C i signal of the D i+1 flip-flop is logic 1.
  • D i+1 flip-flop receives the first rising edge signal of the CLK_O signal
  • D i+1 The output of the flip-flop transitions to logic 1, that is, C i+1 transitions to logic 1.
  • the output of the D i+2 flip-flop still maintains logic 0 at this moment.
  • the output C i+2 of the D i+ 2 flip-flop jumps to logic 1.
  • the CLK_O signal provides 2 clock cycles, which can set the first 2 D flip-flops of the effective programming unit chain to 1.
  • the CLK_O signal provides 3 clock cycles, the first 3 D flip-flops of the effective programming unit chain can be set to 1.
  • the programming enable signal Prog_en jumps to logic 1, so that the array is in the programming mode.
  • the clock signal of the programming control unit 10 is based on the internal clock.
  • FIG. 7 is a schematic structural diagram of another programming device provided in Embodiment 1 of the present application.
  • the programming device also includes a clock generating unit 30 for providing an excitation clock to the programming control unit 10, that is, there is an internal self-built clock.
  • Self-built clocks do not require additional clock generation circuits to generate initial clocks.
  • FIG. 8 is a schematic structural diagram of another programming device provided in Embodiment 1 of the present application.
  • the clock generation unit 30 includes: a first detection module 31 and a generation module 32; the first detection module 31 is used to sequentially detect the Whether the programming of the first effective storage unit is completed, and output the detection result; the generation module 32 is used to control the excitation clock to generate the excitation signal if the detection result indicates that the programming is completed; otherwise, control the excitation clock to not generate the excitation signal.
  • FIG. 9 is a circuit diagram of another programming control unit provided in Embodiment 1 of the present application.
  • the first detection module 31 includes: a plurality of fourth switches S and a first comparator; a plurality of fourth switches correspond to the memory cells in the row to be programmed; the first of the fourth switches S terminal is connected to the corresponding storage unit, the second terminal of the fourth switch is connected to the non-inverting input terminal of the first comparator; the inverting input terminal of the first comparator is connected to the first reference voltage Vref1.
  • the fourth switch S is used to select the effective storage unit currently detected by the first detection module 31, and the state of the fourth switch depends on the input data and output data of the corresponding flip-flop; the output data of the first comparator represents the currently selected Valid memory cells are programmed.
  • the fourth switch S i+1 depends on the corresponding flip-flop input data C i and output data C i+1 .
  • the storage value C of all flip-flops is logic 0 except for the adjacent N consecutive flip-flops which are logic 1. Therefore, there is only one type of the previous flip-flop in the entire chain.
  • the storage value C logic is 0, and the storage value C logic of this memory is 1, that is, the first cell configured as a valid storage cell in the programmed state.
  • the output data of the corresponding flip-flop must be logic 1, that is, C i+1 is 1.
  • its input data C i is the output data of the previous flip-flop, which must be logic 0.
  • the first detection module 31 detects the first effective memory cell currently in a programming state.
  • the function process of the first comparator is: when the voltage received by the first input end is higher than the reference voltage Vref1, the output detection result C O is at high level; otherwise, it is at low level.
  • CO when the programming of the detected unit is completed, CO is logic 1 high level; when programming is not completed, CO is logic 0.
  • the first detection module 31 also includes: a first enabling switch F1; the first enabling switch F1 is arranged between the fourth switch and the first comparator; after the programming unit 20 starts programming, the first enabling switch F1 is in a closed state; before the programming unit 20 is programmed, the first enabling switch F1 is in an open state.
  • the first enabling switch F1 is controlled by an external link signal, which is the Prog_en signal shown in FIG. 6 . After Prog_en jumps to logic 1, the array is in the programming state.
  • the generation module 32 includes: a first AND gate, a first OR gate, a first delayer and a first inverter.
  • the first input end of the first AND gate is connected with the output end of the first detection module 31, and receives the detection result CO output by the first detection module 31.
  • the output end of the first AND gate is connected with the first input end of the first OR gate; the output end of the first OR gate is connected with the input end of the first delayer; the output end of the first delayer is connected with the first inversion
  • the input end of the device is connected; the output end of the first inverter is connected with the second input end of the first AND gate; wherein, the second input end of the first OR gate is input with the first control signal Turn-off; according to the first The control signal and the output signal of the output terminal of the first AND gate, the output terminal of the first OR gate outputs the initial excitation clock CLK_Internal.
  • the output CO of the comparator can be used as a judgment flag for link self-mobile clock jumps.
  • CO does not directly control the clock CLK_Internal, but performs logic operations with its own delay logic and then outputs the clock.
  • Delay is 1, the first AND gate outputs 1, and the first OR gate outputs 1, that is, CLK_Intrenal jumps to 1.
  • CO continues to be 1 Delay is 0, the first AND gate outputs 0, and the first OR gate outputs 0, that is, CLK_Intrenal jumps to 0.
  • the interval between the up and down jumps of CLK_Intrenal is controlled to avoid the risk of circuit logic caused by the interval being too short.
  • the CO generates its own delayed signal through the first AND gate, the first OR gate, the first delayer, and the first inverter, and outputs it after the logic operation of the first AND gate.
  • Delay effects include self-built clock generation during initialization and prevention of clock lock-up in special cases during cell programming.
  • the clock generating unit 30 also includes: a delay module 33; the delay module 33 includes a second delayer for delaying the initial excitation clock CLK_Internal to generate the excitation clock CLK_dff as the clock of the D flip-flop chain .
  • the clock generation unit 30 also includes: a second enable switch F2; the second enable switch F2 is connected between the output terminal of the second delayer and the programming control unit; after the programming unit 20 starts programming, the second enable switch F2 The enabling switch is in the closed state; before the programming unit 20 is programmed, the second enabling switch is in the off state.
  • the second enable switch F2 is controlled by an external link signal, which is the Prog_en signal shown in FIG. 6 .
  • FIG. 10 is a schematic structural diagram of another programming device provided in Embodiment 1 of the present application.
  • the programming device also includes: an error reporting unit 40; the error reporting unit 40 is used to control the excitation clock CLK_dff output by the clock generation unit 30 to generate an excitation signal if the currently detected effective storage unit has not completed programming after a preset period of time.
  • the excitation clock output by the clock generating unit 30 will be at a continuous low level.
  • the error reporting unit 40 is also used to output an error reporting signal err, which is provided to an external circuit as a judgment flag of unit abnormality.
  • FIG. 11 is a circuit diagram of another programming control unit provided in Embodiment 1 of the present application.
  • the error reporting unit 40 includes: a second inverter, a fifth switch G1, a sixth switch G2, a first capacitor, and a second comparator; the non-inverting input terminal of the second comparator is connected to the first terminal of the first capacitor and the sixth switch One end of G2 is connected; the first end of the first capacitor is connected to the power supply signal Lin through the fifth switch G1; the inverting input end of the second comparator is connected to the second reference voltage Vref2; the second end of the first capacitor is grounded; the sixth The other end of the switch G2 is grounded; the input end of the second inverter is connected to the initial excitation clock CLK_Internal, the output end of the second inverter is connected to the control end of the fifth switch G1; the control end of the sixth switch G2 is connected to the initial excitation clock CLK_Internal; the second comparator is connected to the second input end of the first OR gate
  • the initial excitation clock CLK_Internal is at a low level for a long time, correspondingly, the fifth switch G1 is turned on, the sixth switch G2 is turned off, and the Lin signal shown in Figure 11 is continuously Charging the first capacitor causes the voltage of the non-inverting input terminal of the second comparator to continuously increase.
  • the first control signal Turn-off output by the second comparator is set to 1, and the first The OR gate outputs 1, that is, the initial excitation clock CLK_Internal generates a rising edge, skips the faulty unit, and continues subsequent programming.
  • the first control signal Turn-off can be used as an error signal err, which is used as a judgment flag of unit abnormality.
  • FIG. 12 is a signal timing diagram of the programming control unit provided in Embodiment 1 of the present application.
  • S i represents the state of the ith fourth switch.
  • the fourth switch S i is turned on in response to a high level and turned off at a low level.
  • the initial excitation clock CLK_internal is delayed, and the excitation clock CLK_dff is output. In one cycle of the excitation clock CLK_dff, three cases are included.
  • Case 1 the currently detected storage unit is the i+1th storage unit, and the i+1th storage unit is programmed within this cycle.
  • the internal delay part of the generation module generates the falling edge of CLK_internal.
  • CLK_internal provides clock CLK_dff as D flip-flop chain after another delay. The two delays in the circuit are reasonably designed so that the rising edge of CLK_dff is slightly delayed and the falling edge of CLK_internal is slightly delayed to prevent the circuit logic risk caused by the short interval between the up and down jumps of CLK_internal caused by the down jump of CO when the unit is not programmed. .
  • Case 2 the currently detected memory cell is the i+1th memory cell, and the i+2th memory cell has been programmed before the cycle.
  • the switch S i+ 2 of the i+2th unit is turned on, making the i+2th unit the unit to be compared.
  • any cell in the array several cycles before judging whether it has been programmed, because it is already in the programming state, there is a certain probability that when the cell is detected, the cell has been programmed.
  • CO will be at logic 1 during detection, and CLK_internal is set to regenerate a rising edge after two delays to generate the next rising edge of CLK_dff to end the cycle.
  • Situation 3 the currently detected storage unit is the i+3th storage unit, and the i+3th storage unit is in an abnormal state and programming cannot be completed, then the programming is forcibly terminated through the error reporting unit 40 .
  • the switch S i+ 3 of the i+3th unit is turned on, making the i+3th unit the unit to be compared.
  • the fifth switch G1 in the error reporting unit 40 is turned off under the control of the negative signal of CLK_internal, and the sixth switch is turned on under the control of CLK_internal.
  • the first end of the first capacitor is grounded, and then it will be discharged quickly, so that the Turn-off becomes logic 0 again, waiting for the next abnormal judgment.
  • the Turn-off signal can also be used as an error signal to output the err signal, which is provided to the external circuit as a judgment mark of the abnormality of the unit.
  • the programming device includes a programming control unit 10 and a programming unit 20;
  • the effective storage unit is used as the first unit, and the following processing is performed until all effective storage units are programmed: according to the predetermined number, the first unit and the effective storage units after it are selected, configured as a programming state, and the unselected ones after the first unit are
  • the valid storage cells are configured in a non-programmed state; the programming unit 20 performs programming on the valid storage cells currently configured in a programmed state according to a predetermined cycle until all valid storage cells are programmed.
  • the programming method further includes: the programming control unit 10 configures each flip-flop in the programming unit chain as a second logic; the programming control unit 10 responds to a predetermined number of external excitation signals based on the input first logic, and will effectively The first predetermined number of flip-flops in the chain of programming cells are configured as the first logic.
  • the flip-flops stored as the first logic in the page latches one-to-one corresponding to each flip-flop in the programming unit chain constitute an effective programming unit chain.
  • the implementation manner of establishing an effective programming unit chain is introduced in detail in combination with the circuit structure, and details are not repeated here.
  • the programming control unit 10 initializes the effective programming unit chain to select a number N of valid memory cells and configure them in a programming state. In the initialization phase, it is necessary to write part of the data to the effective programming unit chain externally, as shown in Figure 6.
  • the input signal includes a link input signal Chain_in and a link clock signal CLK_O, the main function of which is to determine the number N of memory cells in the programming state at the same time.
  • the programming control unit 10 responds to the control clock, sequentially takes each effective memory cell in the row to be programmed as the first cell, and performs processing, including:
  • the programming control unit 10 responds to the control clock based on the input second logic, and configures the next flip-flop that is currently the first flip-flop and the last flip-flop of the first logic in the effective programming unit chain as the second logic and the last flip-flop respectively.
  • First logic
  • the total programming current is equal to the sum of the currents of the resistive variable units being programmed at the same time. If the programming current of a single unit is known in advance, the number N of some resistive variable units selected at the same time can be calculated according to the safety range set for the total programming current. The value of N can be set by an external link signal before programming.
  • Embodiment 3 provides a programming structure capable of adjusting the number N of memory cells to be programmed simultaneously according to the real-time total programming current.
  • FIG. 13 is a schematic structural diagram of a programming device provided in Embodiment 3 of the present application.
  • the programming device includes: a quantity setting unit 50 , a programming control unit 10 and a programming unit 20 .
  • the number setting unit 50 is used to generate a control clock according to the total programming current of the valid memory cells configured as the programming state in the current cycle of the excitation clock, so as to determine the number of valid memory cells configured as the programming state in the next cycle .
  • the period in the quantity setting unit 50 starts when the first excitation signal of the excitation clock is received, and ends when the second excitation signal of the excitation clock is received.
  • the number setting unit 50 generates a control clock in response to the excitation signal and according to the magnitude of the total programming current, and the control clock can realize the adjustment of the number of effective memory cells configured in the programming state.
  • the programming control unit 10 sequentially selects a corresponding number of valid storage cells and configures them in a programming state.
  • an initial quantity value needs to be set through an external link signal. That is to say, the number of effective memory cells configured as the programming state in the first cycle is preset in advance; the number in each cycle after that is the total programming current according to the total programming current of the previous cycle through the number setting unit 50 Adjusted quantity.
  • the number setting unit 50 detects that the total programming current is too small and is lower than the set low current threshold, then in the next cycle, an additional effective programming unit is added, that is, N becomes N+1; if the number setting The setting unit 50 detects that the total programming current is too large and is higher than the set high current threshold, so in the next cycle, one effective programming unit is reduced, that is, N becomes N-1; if the number setting unit 50 monitors the total programming current Within the set range, then in the next cycle, no change in the number of effective programming units will be made.
  • the number setting unit 50 When the number of effective memory cells to be configured in the programming state in the next cycle is the same as that in the current cycle, the positions of the effective memory cells configured in the programming state in the next cycle are moved backward by one bit relative to the current cycle.
  • the number setting unit 50 generates control clocks containing different excitation signals, which are respectively used to control the last valid storage unit among the multiple valid storage units sequentially configured as the programming state in the current cycle, and the next one of the last unit.
  • Valid storage cells and other non-last valid storage cells that are configured to be in the programming state in the current cycle so as to increase or decrease the number of valid storage cells in the programming state in one cycle.
  • the cycle of the programming unit 20 and the cycle of the quantity setting unit 50 are not the same cycle, unless otherwise specified, the cycle mentioned in the following refers to the introduction of the cycle of the quantity setting unit 50 .
  • the programming unit is used to program valid memory cells configured in a programmed state.
  • FIG. 14 is a schematic diagram of a working process of a programming device provided in Embodiment 3 of the present application. When a row in the memory array is programmed, a value is written to the page latch.
  • the Active cells box is a memory cell configured as a programming state.
  • 4 valid memory cells are selected in a single time to be configured as a programmed state, and other valid memory cells are configured as a non-programmed state.
  • the programming unit 20 sequentially programs the first unit among the four selected effective storage units.
  • the Active cells frame moves backward by 0, 1 or 2 effective memory cells, and continues to program the first memory cell in the current Active cells frame.
  • FIG. 15 is a circuit diagram of a programming control unit provided in Embodiment 3 of the present application.
  • the number of effective memory cells in the programming state in each cycle is determined by the number setting unit.
  • the quantity setting unit cannot increase the quantity in the next cycle. The following describes the mid-term process of new memory programming (the number of effective memory cells that have not completed programming is sufficient to adjust the number of setting cells).
  • Fig. 16 is a waveform diagram of an external link signal provided by the third embodiment of the present application.
  • the method for configuring the number N of effective memory cells in the programming state provided by the third embodiment of the present application is the same as that of the present application Embodiment 1 will not be repeated here.
  • FIG. 17 is a schematic structural diagram of a clock generating unit provided in Embodiment 3 of the present application.
  • the programming device also includes a quantity setting unit 50 arranged between the clock generating unit 30 and the programming control unit 10.
  • the clock generating unit 30 provides an excitation clock to the quantity setting unit 50, that is, there is an internal self-built clock. .
  • FIG. 18 is a schematic structural diagram of another clock generation unit provided in Embodiment 3 of the present application.
  • the clock generation unit 30 includes: a first detection module 31 and a generation module 32; the first detection module 31 uses To sequentially detect whether the first effective memory cell currently configured as the programming state has completed programming, and output the detection result; the generating module 32 is used to control the excitation clock to generate an excitation signal if the detection result indicates that the programming is completed; otherwise, control the excitation clock No excitation signal is generated.
  • FIG. 19 is a circuit diagram of a clock generating unit provided in Embodiment 3 of the present application, wherein the first detection module 31 is the same as in Embodiment 1 of the present application, and details are not repeated here.
  • FIG. 20 is a schematic structural diagram of an error reporting unit 40 provided in Embodiment 3 of the present application
  • FIG. 21 is a circuit diagram of an error reporting unit 40 provided in Embodiment 3 of the present application. Wherein, the error reporting unit 40 is the same as the first embodiment of the present application, and will not be repeated here.
  • FIG. 22 is a schematic structural diagram of a quantity setting unit 50 provided in Embodiment 3 of the present application.
  • FIG. 23 is a circuit diagram of a quantity setting unit 50 provided in Embodiment 3 of the present application.
  • the quantity setting unit 50 includes a clock control module 51 and a clock selection module 52 .
  • the clock control module 51 is configured to output the first control clock CLK_dff_D, the second control clock CLK_dff_N and the third control clock CLK_dff_O based on the relationship between the total programming current of the effective memory cells in the current cycle and the predetermined range.
  • the CLK_CTRL module shown in FIG. 23 receives the excitation clock CLK_dff, and outputs the first control clock CLK_dff_D, the second control clock CLK_dff_N and the third control clock CLK_dff_O.
  • Case 1 When the total programming current of the current cycle is lower than the predetermined range, the number of excitation signals of the first control clock CLK_dff_D is increased compared with that of the excitation clock, and the second control clock CLK_dff_N and the third control clock CLK_dff_O are consistent with the excitation clock.
  • Case 3 When the total programming current of the current cycle is within a predetermined range, the first control clock CLK_dff_D, the second control clock CLK_dff_N, and the third control clock CLK_dff_O are consistent with the excitation clock. Even if the number of the previous cycle is used, the total programming current may not be within the predetermined range due to the programming difference of individual resistive variable cells. Refer to Case 1 and Case 2 to adjust the number of effective memory cells in the programming state.
  • the clock selection module 52 includes a plurality of seventh switches H1 , a plurality of eighth switches H2 and a plurality of ninth switches H3 .
  • the seventh switch H1 i+1 , the eighth switch H2 i+1 , and the ninth switch H3 i+1 corresponding to the trigger on the left are exemplarily marked, and their subscripts indicate that they correspond to the i+1th trigger device.
  • the plurality of seventh switches H1 , the plurality of eighth switches H2 and the plurality of ninth switches H3 are in one-to-one correspondence with the plurality of flip-flops, respectively.
  • one terminal of the seventh switch H1, the eighth switch H2 and the ninth switch H3 is connected to the clock port of the corresponding flip-flop through the first switch.
  • the other end of the seventh switch H1 is connected to the first control clock CLK_dff_D; the other end of the eighth switch H3 is connected to the second control clock CLK_dff_N; the other end of the ninth switch H3 is connected to the third control clock CLK_dff_O.
  • the three switches corresponding to each flip-flop only one switch is turned on at the same time. That is, each flip-flop receives only one stimulus clock.
  • the eighth switch H2 corresponding to the last flip-flop corresponding to the valid memory cell in the programming state is turned on, and the seventh switch H1 and the ninth switch H3 corresponding to the flip-flop are turned off;
  • the seventh switch H1 corresponding to the next flip-flop corresponding to the last flip-flop in the memory cell is turned on, and the eighth switch H2 and the ninth switch H3 corresponding to the flip-flop are turned off;
  • the ninth switch H3 corresponding to other flip-flops except the last flip-flop is turned on, and the seventh switch H1 and the eighth switch H2 corresponding to the other flip-flop are turned off.
  • Each cycle contains N effective memory cells in the programming state. At any time, only one of the eighth switch H2 and the seventh switch H1 is turned on, corresponding to the last effective memory cell and the The first valid storage unit adjacent to the N valid storage units.
  • FIG. 24 is a schematic structural diagram of a clock control module 51 provided in Embodiment 3 of the present application.
  • the clock control module 51 includes a second detection module 53 and a logic calculation module 54; the second detection module 53 is used to output the second control signal, the third control signal and the fourth control signal; the second control signal, the third control signal, and the fourth control signal represent the relationship between the total programming current of the current cycle and the predetermined range; the logic calculation module 54 is connected to the second detection module 53, Used to output the first control clock CLK_dff_D, the second control clock CLK_dff_N and the third control clock CLK_dff_O under the control of the second control signal, the third control signal and the fourth control signal.
  • the second control signal indicates that the total programming current of the effective memory cells in the current cycle is lower than the low parameter value in the predetermined range;
  • the third control signal represents that the total programming current of the effective memory cells in the current cycle is higher than the high value in the predetermined range.
  • the fourth control signal indicates that the total programming current of the valid memory cells in the current cycle is within a predetermined range.
  • control signal (including the second control signal, the third control signal and the fourth control signal) is controlled to generate the realization of the control clock (including the first control clock CLK_dff_D, the second control clock CLK_dff_N and the third control clock CLK_dff_O) way to explain.
  • FIG. 25 is a schematic circuit diagram of a second detection module 53 provided in Embodiment 3 of the present application.
  • the second detection module 53 includes a plurality of tenth switches T, a third comparator, a fourth comparator, a first flip-flop, a second flip-flop and a third inverter.
  • a plurality of tenth switches T correspond to the memory cells in the row to be programmed; the first end of the tenth switch T is connected to the corresponding memory cell, and the second end of the tenth switch T is connected to the second end of the tenth switch T respectively.
  • the inverting input of the three comparators and the non-inverting input of the fourth comparator are connected; the non-inverting input of the third comparator is connected to the low parameter value in the predetermined range; the inverting input of the fourth comparator is connected to the low parameter value in the predetermined range High parameter value.
  • the state of the tenth switch T depends on the output data of the corresponding flip-flop and the storage data of the corresponding page latch, so as to control the conduction of the tenth switch T corresponding to the effective memory cell configured as the programming state, and other non-programming states
  • the tenth switch T corresponding to the effective storage unit is turned off.
  • the state of the tenth switch T is determined by AND logic of the output data of the corresponding flip-flop and the storage data of the corresponding page latch.
  • the output data that is, its storage value
  • the storage data of its corresponding page latch must be logic 1
  • the output data of its corresponding flip-flop must also be 1
  • its corresponding tenth Switch T is conductive. That is, the tenth switches T i+1 corresponding to all valid memory cells configured in the programming state in each cycle are turned on, so as to obtain the total programming current.
  • the input terminal of the comparator is a voltage value
  • the current value of each selected column needs to be summed by a reasonable circuit and then linearly converted into a voltage value.
  • the obtained total programming current is converted into a total programming voltage value, which is input into the third comparator and the fourth comparator for comparison, and the comparison results CO L , CO H are respectively output.
  • the third comparator its non-inverting input terminal is the low voltage value Vref_L, and its inverting input terminal inputs the total programming voltage value.
  • the CO L signal is 1; when the total programming voltage is higher than Vref_L, the CO L signal is 0.
  • the fourth comparator its inverting input terminal is the low voltage value Vref_H, and the non-inverting input terminal inputs the total programming voltage value.
  • the CO H signal is 1; when the total programming voltage is higher than Vref_H, the CO L signal is 0.
  • the output end of the third comparator is connected with the input end of the first flip-flop; the first output end of the first flip-flop outputs the first parameter OL; the second output end of the first flip-flop outputs the non-logic parameter of the first parameter
  • the fourth comparator is connected to the output end of the input end of the second flip-flop; the first output end of the second flip-flop outputs the second parameter OH; the second output end of the second flip-flop outputs the non-logic parameter of the second parameter
  • the combination of the first parameter OL and the second parameter OH forms a second control signal, a third control signal and a fourth control signal.
  • the first flip-flop input signal CO L and the second flip-flop input signal CO H are the same as that of CO L.
  • the second flip-flop outputs the first parameter OH with the same logical value as CO H.
  • the clock ports of the first flip-flop and the second flip-flop are both connected to the output end of the third inverter, and the input end of the third inverter is connected to the fourth control clock CLK_ds. That is, the first flip-flop and the second flip-flop are controlled by the inverted signal of the fourth control clock CLK_ds.
  • FIG. 26 is a schematic circuit diagram of a logic calculation module 54 provided in Embodiment 3 of the present application. With reference to FIG. 26 , the process of controlling the output of the first control clock CLK_dff_D, the second control clock CLK_dff_N, and the third control clock CLK_dff_O by the three control signals, and the generation process of the fourth control clock CLK_ds are described.
  • the logic calculation module 54 includes: a third delayer, a first XOR gate, an eleventh switch M1 , a twelfth switch M2 , a thirteenth switch M3 , and a fourteenth switch M4 .
  • the control end of the eleventh switch M1 is connected to the first parameter OL; the control end of the twelfth switch M2 is connected to the non-logic parameter OL of the first parameter; the control end of the thirteenth switch M3 is connected to the second parameter OH; the fourteenth The control end of the switch M4 is connected to the non-logic parameter of the second parameter
  • the input end of the third delayer is connected to the excitation clock CLK_dff; the output end of the third delayer outputs the fourth control clock CLK_ds.
  • the above settings are used to control the response timing of each device.
  • the first flip-flop and the second flip-flop function again after a certain time interval. T.
  • the third comparator and the fourth comparator function in response to the excitation clock CLK_dff.
  • the first input end of the first exclusive OR gate is connected to the output end of the third delayer; the second input end of the first exclusive OR gate is connected to the excitation clock CLK_dff; the output end of the first exclusive OR gate is connected to the eleventh switch M1 The first terminal; the second terminal of the eleventh switch M1 is connected to the output terminal of the first control clock CLK_dff_D.
  • the excitation clock CLK_dff performs an exclusive OR logic operation with its own delay signal, which will generate one more rising edge than the excitation clock CLK_dff.
  • the eleventh switch M1 is turned on, and the twelfth switch M2 is turned off.
  • the outputted first control clock CLK_dff_D has one more rising edge than the excitation clock CLK_dff, which can be used to add an additional valid memory cell to be configured as a programming state.
  • the first end of the twelfth switch M2 is connected to the excitation clock CLK_dff; the second end of the twelfth switch M2 is connected to the output end of the first control clock CLK_dff_D.
  • the first end of the thirteenth switch M3 is connected to the excitation clock CLK_dff; the first end of the fourteenth switch M4 is grounded; the second end of the thirteenth switch M3 and the second end of the fourteenth switch M4 are both connected to the second control clock Output of CLK_dff_N.
  • the output second control clock CLK_dff_N coincides with the excitation clock CLK_dff.
  • the output second control clock CLK_dff_N is grounded and does not generate a rising edge, so that it can be used to reduce one effective memory cell to be configured as a programming state.
  • the output end of the third control clock CLK_dff_0 is connected to the excitation clock CLK_dff.
  • This setting is under three kinds of control signals, CLK_dff_O is consistent with the excitation clock CLK_dff all the time.
  • FIG. 27 is a waveform diagram for increasing the number provided by Embodiment 3 of the present application, and illustrates the process of adding an additional valid memory cell to be configured as a programming state.
  • the excitation signal CLK_dff includes two rising edges, and each rising edge represents the beginning of a cycle.
  • the initial excitation clock CLK_Internal generates the excitation signal CLK_dff through the second delayer.
  • the excitation signal CLK_dff generates the fourth control clock CLK_ds through the third delayer.
  • the rising edge of the inverted signal of the fourth control clock CLK_ds corresponds to the falling edge of the fourth control clock CLK_ds.
  • Delay shown in FIG. 27 is an inverted delay signal of the signal CO output by the first inverter of the generating module 32 .
  • the output signal CO L 1 of the third comparator.
  • the output signal OL jumps to 1
  • the eleventh switch M1 is turned on
  • the twelfth switch M2 is turned off.
  • the output first control clock CLK_dff_D has one more rising edge than the excitation clock CLK_dff, such as the third rising edge of CLK_dff_D in FIG. 27 .
  • the eighth switch H2 is turned on and connected to the second control clock CLK_dff_N.
  • the i-th flip-flop transitions to 1. At this time, the output of the i+1th flip-flop is still 0. At the third rising edge of CLK_dff_D in Figure 27, the output of the i+1th flip-flop is 1. Since the third rising edge of CLK_dff_D in Figure 27 is between the second rising edge and the second falling edge of CLK_dff, the output C i+1 of the i+1th flip-flop will be on the third rising edge of CLK_dff_D Jump to 1 at the upper jump edge.
  • the output C of the flip-flop corresponding to the valid memory cell is 1, it is configured as a programming state.
  • the output C i+1 of the i+1th flip-flop is 1, it is configured as a programming state.
  • the i+1th flip-flop becomes the last flip-flop in this cycle, and the number of effective memory cells in the programming state in this cycle is equal to the number in the previous cycle plus one. If the number is not increased, the i-th flip-flop is used as the last flip-flop in this cycle, and the number of effective memory cells in the programming state in this cycle is equal to the number in the previous cycle.
  • FIG. 28 is a waveform diagram for reducing the number provided by Embodiment 3 of the present application. In conjunction with FIG. 28 , the process of reducing one effective memory cell to be configured as a programmed state is described.
  • the CLK_Internal, Delay, CLK_dff, and CLK_ds shown in FIG. 28 are the same as those shown in FIG. 27 and will not be repeated here.
  • the output signal CO H 0 of the fourth comparator.
  • the second flip-flop is excited by the first falling edge of the fourth control clock CLK_ds, the output signal OH jumps to 0, the thirteenth switch M3 is turned off, and the fourteenth switch M4 is turned on.
  • the output second control clock CLK_dff_N is grounded without generating a rising edge, as shown in FIG. 28 , CLK_dff_N has no second rising edge compared with CLK_dff.
  • the output first control clock CLK_dff_D coincides with the excitation clock CLK_dff.
  • the i th flip-flop receives the second control clock CLK_dff_N
  • the i+1 th flip-flop receives the first control clock CLK_dff_D.
  • the last effective memory cell corresponds to turning on the eighth switch H2, and is connected to the second control clock CLK_dff_N
  • the first effective storage unit after the N effective storage units corresponds to turning on the seventh switch H1, and is connected to the first control clock CLK_dff_D. What remains unchanged is the connections between the output ports of the three excitation clocks and the corresponding flip-flops, and what changes is the excitation signals of the three excitation clocks.
  • the excitation signals of the first control clock CLK_dff_D and the excitation clock CLK_dff are consistent; the second control clock CLK_dff_N is grounded and does not generate a rising edge, which reduces the excitation compared to the excitation clock CLK_dff Signal.
  • the i-1th flip-flop becomes the last flip-flop in this cycle, and the number of effective memory cells in the programming state in this cycle is equal to the number in the previous cycle minus one. If the number is not reduced, the i-th flip-flop is used as the last flip-flop in this cycle, and the number of valid memory cells in the programming state in this cycle is equal to the number in the previous cycle.
  • the programming device includes a programming control unit 10, a programming unit 20, and a quantity setting unit 50; The total programming current of the valid memory cells configured in the programmed state, and a control clock is generated to determine the number of valid memory cells configured in the programmed state in the next cycle.
  • the present application also provides a hardware code product, including hardware codes, and when the hardware codes are executed by a processor, the methods provided in the foregoing embodiments are implemented.
  • the present application also provides a readable storage medium, in which hardware codes are stored, and when executed, the hardware codes are used to implement the methods provided in the foregoing embodiments.
  • the present application also provides an electronic device, including: a processor, and a memory communicatively connected to the processor; the memory stores hardware codes; and the processor executes the hardware codes stored in the memory, so as to implement the methods provided in the foregoing embodiments.
  • the present application also provides a new type of memory, including a plurality of resistive memory cells, and a programming device as provided in the foregoing embodiments; the programming device is used to program the resistive memory cells.
  • the new memory can be a resistive change memory, a phase change memory, or a magnetic change memory.

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Abstract

本申请提供一种编程装置、方法及新型存储器。包括：编程控制单元和编程单元；编程控制单元，用于响应控制时钟，依次将待编程行中的每个有效存储单元作为首单元，执行处理，直至所有有效存储单元被编程：根据预定数量，选中该首单元及其之后的有效存储单元，配置为编程状态，将该首单元之后的未被选中的有效存储单元配置为非编程状态；编程单元，用于按照预定周期，执行对当前被配置为编程状态的有效存储单元进行编程，直至所有有效存储单元被编程。本申请实现了任意时间段选中相同数量的部分单元，同时在一行中能够按照顺序移动，将编程完成的单元用未编程的单元替换，实现整一行待编程单元的遍历。

Description

编程装置、方法及新型存储器
交叉引用
本申请要求2021年12月8日提交的申请号为202111496692.X及202111494342.X的中国专利申请的优先权。上述申请的内容以引用方式被包含于此。
技术领域
本申请涉及集成电路设计领域，尤其涉及一种编程装置、方法及新型存储器。
技术背景
存储器是许多存储单元的集合，按单元号顺序排列。每个单元由若干二进制位构成，以表示存储单元中存放的数值。传统存储器，如闪存存储器Flash以及动态随机存储器(Dynamic Random Access Memory，DRAM)，其通过对单元注入电荷改变单元的阈值电压等电学特性，以存储数据“0”和数据“1”。新型存储器，如阻变式存储器(Resistive Random Access Memory，RRAM)是以非导性材料的电阻在外加电场作用下，在高阻态和低阻态之间实现可逆转换为基础的非易失性存储器，根据自身电阻值的大小来作为存储信号的判决条件。
以闪存存储器为例，普遍采用整片擦除后，再对每一行进行编程。由于每一个闪存存储单元消耗的功耗较低，可以对一整行同时进行编程。如图1所示为传统闪存阵列编程结构示意图。然而,该方法并不适用于新型存储器，新型存储器中单个阻变单元的编程电流很高，同时进行编程导致电流过大，存在芯片因发热而烧毁的风险。
如图2所示为本申请提供的一种阻变式存储器阵列编程结构的示意图，但编程方式存在如何控制选择部分阻变单元的问题，本申请提供的编程装 置、方法及新型存储器，提供一种既可以解决单元部分选中又可以实现单元遍历的结构。
发明概要
本申请提供一种编程装置、方法及新型存储器，用以解决新型存储器的编程问题。
本申请提供一种编程装置，包括：编程控制单元和编程单元；
编程控制单元，用于响应控制时钟，依次将待编程行中的每个有效存储单元作为首单元，执行处理，直至所有有效存储单元被编程：根据预定数量，选中该首单元及其之后的有效存储单元，配置为编程状态，将该首单元之后的未被选中的有效存储单元配置为非编程状态；
编程单元，用于按照预定周期，执行对当前被配置为编程状态的有效存储单元进行编程，直至所有有效存储单元被编程。
本申请提供一种编程方法，应用于编程装置，编程装置包括编程控制单元和编程单元；方法包括：编程控制单元响应于控制时钟，依次将待编程行中的每个有效存储单元作为首单元，执行以下处理，直至所有有效存储单元被编程：根据预定数量，选中该首单元及其之后的有效存储单元，配置为编程状态，将该首单元之后的未被选中的有效存储单元配置为非编程状态；编程单元按照预定周期，执行对当前被配置为编程状态的有效存储单元进行编程，直至所有有效存储单元被编程。
本申请提供一种硬件代码产品，包括硬件代码，硬件代码被处理器执行时实现如第二方面的方法。
本申请提供一种可读存储介质，可读存储介质中存储有硬件代码，硬件 代码被执行时用于实现如第二方面的方法。
本申请提供一种电子设备，包括：处理器，以及与处理器通信连接的存储器；存储器存储硬件代码；处理器执行存储器存储的硬件代码，以实现如第二方面的方法。
本申请提供一种新型存储器，包括多个电阻型存储单元，以及如第一方面的编程装置；编程装置用以对电阻型存储单元进行编程。
本申请通过激励时钟控制在任意时间段将预定数量的部分有效存储单元配置为编程状态，实现只对一行中的部分单元进行编程，有效控制编程总电流，避免对整行所有单元同时编程所带来的高电流导致芯片发热损坏的风险；并且在一行中能够按照顺序移动，将编程完成的单元用未编程的单元替换，实现整一行待编程单元的遍历，无需设置外部控制装置，减少了资源消耗。
附图说明
图1为传统闪存阵列编程结构示意图；
图2为本申请提供的一种阻变式存储器阵列编程结构的示意图；
图3为本申请实施例一提供的一种编程装置的结构示意图；
图4为本申请实施例一提供的一种编程装置的工作过程示意图；
图5为本申请实施例一提供的一种编程控制单元的电路图；
图6为本申请实施例一提供的一种外部链路信号波形图；
图7为本申请实施例一提供的另一种编程装置的结构示意图；
图8为本申请实施例一提供的又一种编程装置的结构示意图；
图9为本申请实施例一提供的另一种编程控制单元的电路图；
图10为本申请实施例一提供的再一种编程装置的结构示意图；
图11为本申请实施例一提供的再一种编程控制单元的电路图；
图12为本申请实施例一提供的编程控制单元的信号时序图；
图13为本申请实施例三提供的一种编程装置的结构示意图；
图14为本申请实施例三提供的一种编程装置的工作过程示意图；
图15为本申请实施例三提供的一种编程控制单元的电路图；
图16为本申请实施例三提供的一种外部链路信号波形图；
图17为本申请实施例三提供的一种时钟生成单元的结构示意图；
图18为本申请实施例三提供的另一种时钟生成单元的结构示意图；
图19为本申请实施例三提供的一种时钟生成单元的电路图；
图20为本申请实施例三提供的一种报错单元的结构示意图；
图21为本申请实施例三提供的一种报错单元的电路图；
图22为本申请实施例三提供的一种数量设定单元的结构示意图；
图23为本申请实施例三提供的一种数量设定单元的电路图；
图24为本申请实施例三提供的一种时钟控制模块的结构示意图；
图25为本申请实施例三提供的一种第二检测模块的电路示意图；
图26为本申请实施例三提供的一种逻辑计算模块的电路示意图；
图27为本申请实施例三提供的一种用于增加数量的波形图；
图28为本申请实施例三提供的一种用于减少数量的波形图。
发明内容
为使本发明实施例的目的、技术方案和优点更加清楚，下面将对本发明 实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。
实施例一
图3为本申请实施例一提供的一种编程装置的结构示意图，编程装置包括：编程控制单元10和编程单元20。其中，编程控制单元10用于控制选择待编程的存储单元，编程单元20用于对被选中的存储单元进行编程。
编程控制单元10，响应于控制时钟，依次将待编程行中的每个有效存储单元作为首单元，执行处理，直至所有有效存储单元被编程：根据预定数量，选中该首单元及其之后的有效存储单元，配置为编程状态，将该首单元之后的未被选中的有效存储单元配置为非编程状态。编程单元20，按照预定周期，执行对当前被配置为编程状态的有效存储单元进行编程，直至所有有效存储单元被编程。
具体的，图4为本申请实施例一提供的一种编程装置的工作过程示意图。当需要向存储阵列写入某一行时，页锁存器上会写入数值。其中，1表征需要编程的单元，0表征不需要编程的单元。如图4所示，第一行cell中，上标有1的cell为需要编程的存储单元。选出需要编程的单元，并将这些单元也按照顺序排列，组成有效编程单元链。
在实际编程中，所有编程操作只对选出的有效编程单元链起作用。需要说明的是，对页锁存器写入数值是由另外的程序或电路控制的，并不是本申请中编程控制单元10和编程单元20执行的。
在上述有效编程单元链中，单一时间内选定N个存储单元配置为编程状态。任意编程时间内只有相邻的N个单元处于被编程状态。示例性的，如图4所示，单一时间内选定了四个有效存储单元被配置为编程状态，其他有效存储单元配置为非编程状态。编程单元20依次对选中的四个有效存储单元中的首单元进行编程。
需要说明的是，单一时间内选定数量N的存储单元配置为编程状态的操作在编程前的初始化阶段进行。例如，通过外部链路向有效编程单元链输入 时钟信号控制数量N，后续结合编程控制单元10的电路结构进行详细阐述。
开始编程后，参照图4，自第二行至第四行，Active cells框内为被配置为编程状态的存储单元，当对框内的第一个存储单元完成编程后，Active cells依次移动，加入另一个未编程存储单元，继续对当前Active cells框内的第一个存储单元进行编程。一直循环该操作，直到最后一个单元完成编程，通过流水线的编程控制过程，实现了对整行待编程存储单元的遍历。
下面结合电路图，对编程装置的结构和作用过程进行介绍。
图5为本申请实施例一提供的一种编程控制单元的电路图。编程控制单元10包括：由依次串联的多个触发器构成的编程单元链；其中，多个触发器与待编程行中各存储单元对应的页锁存器一一对应。
如图5所示，包括四个D触发器构成的编程单元链，每个D触发器对应有一个页锁存器P.L.(Page Latch的缩写)，每个页锁存器P.L.对应一个存储单元Cell。D触发器的输入端为“D”端；输出端为“Q”端；时钟端口为“CLK”端。
其中，每个触发器的时钟端口通过第一开关A连接至激励时钟，每个触发器的输出端通过第二开关B连接至下一触发器的输入端，每个触发器的输入端通过第三开关E连接至下一触发器的输入端。
图5示出了第i+1个触发器对应的第一开关A i+1、第二开关B i+1和第三开关E i+1，输出值为C i+1，其下标表征对应的触发器，依次类推，第i+2个触发器对应的第一开关A i+2、第二开关B i+2和第三开关E i+2(图5中未示出)，输出值为C i+2。
各存储单元对应的页锁存器，用于基于自身的存储数据，控制对应触发器的第一开关A、第二开关B以及第三开关E的开关状态，以建立有效编程单元链；其中，处于有效编程单元链的触发器对应的存储单元为有效存储单元；其中，编程状态的有效存储单元对应的触发器被配置为第一逻辑，非编程状态的有效存储单元对应的触发器被配置为第二逻辑。后文中以第一逻辑为1，第二逻辑为0为例进行阐述。
在一个示例中，编程控制单元10还包括：多个反相器；多个反相器与多个触发器一一对应，反相器的输入端与对应页锁存器连接，反相器的输出端与对应触发器的第三开关E的控制端连接。
参照图5，页存储器基于自身的存储数据建立有效编程单元链的方法为：当页锁存器内存储数据为1，则第一开关A和第二开关B为闭合状态；第三开关E为断开状态。D触发器的时钟端口可通过第一开关A接收时钟信号，当前D触发器的输出端通过第二开关B与下一个D触发器的输入端是连接的。此时，当前D触发器是连接在链路中的。
当页锁存器内存储数据为0，则第一开关A和第二开关B为断开状态；第三开关E为闭合状态。D触发器的时钟端口不能接收时钟信号，当前D触发器的输出端与下一个D触发器的输入端是断开的。下一个D触发器可以通过闭合的第三开关E，接收前面D触发器输出的信号。此时，当前D触发器被跳过，没有连接在链路中。
在进行编程之前，需要通过外部链路向有效编程单元链写入部分数据，选中数量N个有效存储单元并配置为编程状态，即进行初始化。运行编程后，任何时间段同时处于编程状态的有效存储单元的数量均为N，一经外部链路设定，则在编程过程中不会改变。其中，在对整个新型存储器编程即将完成时，当剩余的未完成编程的有效存储单元数量少于N时，后续的周期内处于编程状态的有效存储单元的数量会依次递减，直到完成对所有有效存储单元的编程。下文介绍的是新型存储器编程的中期过程(每个周期内数量固定为N)，非特别说明，不考虑新型存储器编程末期这种特殊情况。
在实际应用过程中，该数量N需要经过实验或计算获得，N过大则会造成编程电流过大，N过小影响编程效率。
图6为本申请实施例一提供的一种外部链路信号波形图，结合图5所示的电路结构，对将数量N个有效存储单元配置为编程状态的方法进行介绍。
如图6所示，编程使能信号Prog_en用于控制阵列的编程模式。Prog_en始终处于逻辑0，使阵列不处于编程模式，可以在编程前通过外部链路进行 初始化。链路输入信号Chain_In向D触发器的输入端D端输入信号，链路时钟信号CLK_O为D触发器提供触发上升沿激励信号。
D触发器是一个具有记忆功能的、两个稳定状态的信息存储器件，是构成多种时序电路的最基本逻辑单元，其触发方式有电平触发和边沿触发两种，前者在时钟脉冲＝1时即可触发，后者多在时钟脉冲的前沿(正跳变0→1)时触发。D触发器包括输入端、时钟端口、输出端，时钟端口用于接收时钟信号。
以边沿触发式的D触发器为例，其作用结果是：当输入端为逻辑1时，接收到上升沿激励信号的触发后，输出端输出1；当输入端为逻辑0时，接收到上升沿激励信号的触发后，输出端输出0。
初始化第一步：对页锁存器写入全1数据，使得所有的D触发器都在链路中。
初始化第二步：通过外部链路时钟控制，将所有的D触发器都写成保存逻辑0的状态。具体过程：Chain_In信号一直置为逻辑0，不间断地输入周期性链路时钟信号CLK_O，直到所有的D触发器都写成保存逻辑0的状态。
初始化第三步：在页锁存器中存入需要写入的数据，使得只有需要编程的单元对应的D触发器处于链路中，建立有效编程单元链。
初始化第四步：Chain_In信号输入端置为逻辑1，CLK_O信号提供N次时钟周期，N为任意整数，可自定义，N次周期完成后，Chain_In信号输入端置为逻辑0。使有效编程单元链中的前N位D触发器处于逻辑1，而其他D触发器为逻辑0。
举例说明，以图5中四个D触发器为例，假设其对应的页存储器均为1，即该四个D触发器均处于链路中。同时，假设N＝2，CLK_O信号提供2次时钟周期，即CLK_O信号具有2个上升沿信号。图5中，自左向右分别是D i+1触发器、D i+2触发器、D i+3触发器、D i+4触发器。
Chain_In信号输入端置为逻辑1，D i+1触发器的输入端输入C i信号为逻辑1，当D i+1触发器接收到CLK_O信号的第一个上升沿信号时，D i+1触发器的 输出跳变至逻辑1，即C i+1跳变至逻辑1。CLK_O信号的第一个上升沿时刻下，D i+2触发器的输出在此时刻下仍然保持逻辑0，当接收到CLK_O信号的第二个上升沿信号时，由于C i+1为逻辑1，所以D i+2触发器的输出C i+2跳变至逻辑1。而CLK_O信号的第二个上升沿时刻下，C i信号依然为逻辑1，因此D i+1触发器输出C i+1保持为逻辑1。当CLK_O信号的两个时钟周期完成后，Chain_In信号输入端置为逻辑0。有效编程单元链中D触发器的状态不会再变化。
即CLK_O信号提供2次时钟周期，可以使有效编程单元链前2个D触发器置为1。以此类推，当CLK_O信号提供3次时钟周期，可以使有效编程单元链前3个D触发器置为1。
只有D触发器和页锁存器同时为逻辑1对应的存储单元列，才会配置成编程状态的电学条件，使对应的存储单元进入编程状态。初始化时，只有前N个需要编程的单元可以在阵列进入编程模式时进入编程状态，确保了任意时间处于编程状态的存储单元的数量不会多于N个。
当通过外部链路来实现设定同一时间被配置为编程状态的存储单元的数量N后，编程使能信号Prog_en信号跳变为逻辑1，使阵列处于编程模式。处于编程模式下，编程控制单元10的时钟信号则以内部时钟为基准。
示例性的，图7为本申请实施例一提供的另一种编程装置的结构示意图。编程装置还包括时钟生成单元30，用于向编程控制单元10提供激励时钟，即存在内部自建时钟。自建时钟不需要额外的时钟产生电路来生成初始的时钟。
图8为本申请实施例一提供的又一种编程装置的结构示意图，时钟生成单元30包括：第一检测模块31和生成模块32；第一检测模块31，用于依次检测当前处于编程状态的首个有效存储单元是否完成编程，并输出检测结果；生成模块32，用于若检测结果表征完成编程，则控制激励时钟产生激励信号，否则，控制激励时钟不产生激励信号。
图9为本申请实施例一提供的另一种编程控制单元的电路图。如图9所示，第一检测模块31包括：多个第四开关S、以及第一比较器；多个第四开 关与待编程行中的存储单元一一对应；第四开关S的第一端与对应的存储单元连接，第四开关的第二端与第一比较器的同相输入端连接；第一比较器的反相输入端连接第一参考电压Vref1。其中，第四开关S用于选择第一检测模块31当前检测的有效存储单元，第四开关的状态取决于对应触发器的输入数据和输出数据；第一比较器的输出数据表征当前被选择的有效存储单元是否完成编程。
具体的，第四开关S i+1取决于对应的触发器输入数据C i和输出数据C i+1。在有效编程单元链中，所有的触发器的存储值C，除了相邻连续的N个触发器为逻辑1外，其余都是逻辑0，因此，整个链中只存在一种前一个触发器的存储值C逻辑为0，本存储器的存储值C逻辑为1的情况，即被配置为编程状态的有效存储单元的首个单元。其对应的触发器的输出数据一定为逻辑1，即C i+1为1。而其输入数据C i为前一个触发器的输出数据，一定为逻辑0。第一检测模块31检测当前处于编程状态的首个有效存储单元。
为了正确的判断存储值为C 1的触发器对应的有效存储单元的编程状态，在D触发器链的最前端，存在一个额外的不与阵列中的列对应D触发器，用于存储C 0值，容易理解的，其逻辑值为0。
第一比较器的作用过程为：当其第一输入端接收的电压高于参考电压Vref1时，则输出的检测结果C O为高电平；否则为低电平。本实施例中，当被检测单元编程完成时，C O为逻辑1高电平；当没有完成编程时，C O为逻辑0。
参照图9，第一检测模块31还包括：第一使能开关F1；第一使能开关F1设置在第四开关与第一比较器之间；编程单元20开始编程后，第一使能开关F1为闭合状态；编程单元20编程前，第一使能开关F1为断开状态。第一使能开关F1由外部链路信号控制，外部链路信号如图6所示的Prog_en信号。Prog_en跳变为逻辑1后，阵列进行编程状态。
参照图9，生成模块32包括：第一与门、第一或门、第一延时器以及第一反相器。第一与门的第一输入端，与第一检测模块31的输出端连接，接 收第一检测模块31输出的检测结果CO。第一与门的输出端与第一或门的第一输入端连接；第一或门的输出端与第一延时器的输入端连接；第一延时器的输出端与第一反相器的输入端连接；第一反相器的输出端与第一与门的第二输入端连接；其中，第一或门的第二输入端输入有第一控制信号Turn-off；根据第一控制信号以及第一与门的输出端的输出信号，第一或门的输出端输出初始激励时钟CLK_Internal。
具体的，比较器的输出CO可以作为链路自移动时钟跳变的判决标志。CO并不是直接控制时钟CLK_Internal，而是与自身的延迟逻辑进行逻辑运算后再输出时钟。控制过程为：CO＝0时，Delay为1，第一与门输出0，第一或门输出0，CLK_Intrenal为0。CO跳变为1时，Delay为1，第一与门输出1，第一或门输出1，即CLK_Intrenal跳变为1。CO持续为1时，Delay为0，第一与门输出0，第一或门输出0，即CLK_Intrenal跳变为0。通过控制第一延时器，来控制CLK_Intrenal的上下跳沿间隔，避免因间隔太短产生的电路逻辑风险。CO经过第一与门、第一或门、第一延时器、第一反相器生成自身的延迟信号，经过第一与门的逻辑运算后输出。延迟作用包括作为初始化时的自建时钟产生，以及防止单元编程过程中特殊情形时存在的时钟锁定现象。
进一步地，时钟生成单元30还包括：延时模块33；延时模块33包括第二延时器，用于对初始激励时钟CLK_Internal进行延时处理，生成激励时钟CLK_dff，作为D触发器链的时钟。
进一步地，时钟生成单元30还包括：第二使能开关F2；第二使能开关F2连接在第二延时器的输出端与编程控制单元之间；编程单元20开始编程后，第二使能开关为闭合状态；编程单元20编程前，第二使能开关为断开状态。第二使能开关F2由外部链路信号控制，外部链路信号如图6所示的Prog_en信号。
图10为本申请实施例一提供的再一种编程装置的结构示意图。编程装置还包括：报错单元40；报错单元40，用于若当前检测的有效存储单元经 过预设时长后仍未完成编程，则控制时钟生成单元30输出的激励时钟CLK_dff产生激励信号。在有效存储单元出现故障而无法进行编程时，则时钟生成单元30输出的激励时钟会是持续的低电平。为了继续完成后续有效存储单元的编程，则通过报错单元强制生成模块输出的激励时钟中产生一个上升沿，跳过该故障单元，继续进行后续的编程。进一步地，报错单元40还用于输出报错信号err，提供给外部电路，作为单元异常的判决标志。
图11为本申请实施例一提供的再一种编程控制单元的电路图。报错单元40包括：第二反相器、第五开关G1、第六开关G2、第一电容、第二比较器；第二比较器的同相输入端与第一电容的第一端和第六开关G2的一端连接；第一电容的第一端通过第五开关G1与电源信号Lin连接；第二比较器的反相输入端连接第二参考电压Vref2；第一电容的第二端接地；第六开关G2的另一端接地；第二反相器的输入端连接初始激励时钟CLK_Internal，第二反相器的输出端与第五开关G1的控制端连接；第六开关G2的控制端连接初始激励时钟CLK_Internal；第二比较器与第一或门的第二输入端连接，用于输出第一控制信号Turn-off。具体的，第一控制信号Turn-off用于控制生成模块32输出的初始激励时钟CLK_Internal产生一个上升沿，进而延时模块33输出的激励时钟CLK_dff产生一个上升沿。
具体的，当编程出现异常，长时间无法完成时，初始激励时钟CLK_Internal长时间为低电平，相应地，第五开关G1导通，第六开关G2断开，图11所示的Lin信号不断对第一电容充电，导致第二比较器的同相输入端的电压不断升高，当大于第二参考电压Vref2时，则第二比较器输出的第一控制信号Turn-off置为1，则第一或门输出1，即初始激励时钟CLK_Internal产生一个上升沿，跳过故障单元，继续进行后续的编程。同时，该第一控制信号Turn-off置可以作为错误信号err，作为单元异常的判决标志。
阵列进行编程状态后，以内部时钟CLK_internal为基准，每一次时钟周期，可以同时进行至多N个单元的编程，但是只会对其中第一个顺位的单 元进行是否编程完成的判决。具体操作方式为，阵列中的编程电路将采集每一列的D触发器和页锁存器的存储数据，只有全部为逻辑1的列会配置成编程的电学条件，该列所在的单元可以处于编程状态。当判决完成后，CLK_internal会自动生成下一个上升沿，进行下一个单元的判决。
图12为本申请实施例一提供的编程控制单元的信号时序图。其中，S i表示第i个第四开关的状态。在一个示例中，第四开关S i响应于高电平导通，低电平断开。结合图12中示例，初始激励时钟CLK_internal经过延迟，输出激励时钟CLK_dff。在激励时钟CLK_dff的一个周期中，包括三种情况。
情况1：当前检测的存储单元为第i+1个存储单元，第i+1个存储单元在该周期内完成编程。如case1，CLK_dff周期开始时，假设第i+1个单元还没有编程完成。实际应用中，生成模块内部的延迟部分产生CLK_internal的下降沿。CLK_internal在经过另一个延迟后，提供作为D触发器链的时钟CLK_dff。电路内的两个延迟经过合理设计，使得CLK_dff的上升沿略微延后与CLK_internal的下降沿，防止单元未完成编程时，由于CO的下跳导致的CLK_internal上下跳沿间隔太短产生的电路逻辑风险。
当CLK_dff产生第一个上升沿时，第i+1个单元的开关S i+1打开，使第i+1个单元成为待比较的单元。当CLK_dff产生上升沿时，第i+1个单元没有完成编程，所以CO将跳变为逻辑0，一直到该单元编程完成后，CO重新跳变为逻辑1，从而使得CLK_internal再次产生上升沿，本编程周期结束，进入下一个单元的编程周期。
情况2：当前检测的存储单元为第i+1个存储单元，第i+2个存储单元在周期前已经完成编程。如case2，当CLK_dff产生第二个上升沿时，第i+2个单元的开关S i+2打开，使第i+2个单元成为待比较的单元。实际应用中，阵列中任一个单元，在判决其是否已经编程完成的之前若干个周期，因已经处在编程状态，存在一定概率，当检测该单元时，该单元已经完成编程。相应的，检测时CO会处于逻辑1，设定CLK_internal在经过两个延迟后重新产生上升沿，以生成CLK_dff的下一个上升沿，结束该周期。
情况3：当前检测的存储单元为第i+3个存储单元，第i+3个存储单元处于异常情况，无法完成编程，则通过报错单元40强制结束编程。如case3，当CLK_dff产生第三个上升沿时，第i+3个单元的开关S i+3打开，使第i+3个单元成为待比较的单元。
如果第i+3个存储单元异常，迟迟未完成编程，CO会一直输出低电平，相应的，CLK_internal则长期处于逻辑0。对此，报错单元40中的第五开关G1在CLK_internal的反信号控制下导通，第六开关G2在CLK_internal控制下断开。第一电容的第一端连接至电源信号，开始充电，相应的，第二比较器同相输入端的电压值上升，当其超过Vref2，第二比较器输出的Turn-off跳变为逻辑1，控制CLK_internal产生上升沿，结束该周期。
CLK_internal产生上升沿后，报错单元40中的第五开关G1在CLK_internal的反信号控制下断开，第六开关在CLK_internal控制下导通。第一电容的第一端接地，随后会较快的放电，使得Turn-off重新变为逻辑0，等待下一次异常判决。Turn-off信号同时也可以作为错误信号输出err信号，提供给外部电路，作为单元异常的判决标志。
综上，整个电路结构会按该方式递进，直到最后一个单元编程完成为止。
实施例二
本申请提供一种编程方法，应用于实施例一的编程装置，编程装置包括编程控制单元10和编程单元20；方法包括：编程控制单元10响应于控制时钟，依次将待编程行中的每个有效存储单元作为首单元，执行以下处理，直至所有有效存储单元被编程：根据预定数量，选中该首单元及其之后的有效存储单元，配置为编程状态，将该首单元之后的未被选中的有效存储单元配置为非编程状态；编程单元20按照预定周期，执行对当前配置为编程状态的有效存储单元进行编程，直至所有有效存储单元被编程。
在一个示例中，编程方法还包括：编程控制单元10将编程单元链中各触发器配置为第二逻辑；编程控制单元10基于输入的第一逻辑，响应于预 定数量的外部激励信号，将有效编程单元链中的前预定数量个触发器配置为第一逻辑。
其中，与编程单元连中各所述触发器一一对应的页锁存器内存储为第一逻辑的触发器构成有效编程单元链。在本申请实施例一中，结合电路结构详细介绍了建立有效编程单元链的实现方式，在此不做赘述。
在编程单元20进行编程之前，由编程控制单元10对有效编程单元链进行初始化，以选中数量N个有效存储单元并配置为编程状态。在初始化阶段，需要通过外部向有效编程单元链写入部分数据，由图6所示。输入信号包括链路输入信号Chain_in和链路时钟信号CLK_O，主要功能为确定同一时间处于编程状态的存储单元的数量N。
在一个示例中，编程控制单元10响应于控制时钟，依次将待编程行中的每个有效存储单元作为首单元，执行处理，包括：
编程控制单元10基于输入的第二逻辑，响应于控制时钟，将有效编程单元链中当前为第一逻辑的首个触发器和最后一个触发器的下一触发器，分别配置为第二逻辑和第一逻辑。
具体的，参照图11和图12，当首个触发器编程完成后，CO输出一个上升沿，从而使得CLK_internal再次产生上升沿，CLK_dff产生上升沿；首个触发器接收到CLK_dff中的上升沿激励信号，基于输入的逻辑0，输出逻辑0。最后一个触发器的下一触发器，接收到CLK_dff中的上升沿激励信号，基于最后一个触发器输出的逻辑1，输出逻辑1，即最后一个触发器的下一触发器及其对应的页存储器均为逻辑1，符合被配置成编程状态的电学条件。也就是说N个编程状态的有效存储单元自动移动了一位。
实施例三
已知编程总电流等于同时被编程的各阻变单元的电流的总和。若预先知道单个单元的编程电流，根据对编程总电流设定的安全范围，可计算出同一时间内所选定的部分阻变单元的数量N。N的数值可以在编程前通过外部链 路信号进行设置。
实施例三提供一种能根据实时的编程总电流大小调整同时进行编程的存储单元的数量N的编程结构。
图13为本申请实施例三提供的一种编程装置的结构示意图，编程装置包括：数量设定单元50、编程控制单元10和编程单元20。
数量设定单元50，用于根据激励时钟的当前周期内被配置为编程状态的有效存储单元的总编程电流，生成控制时钟，以确定下一周期内被配置为编程状态的有效存储单元的数量。
具体的，数量设定单元50中的周期在接收到激励时钟的第一个激励信号时开始，在接收到激励时钟的第二个激励信号时结束。数量设定单元50响应于该激励信号，并根据总编程电流的大小，生成控制时钟，该控制时钟可以实现对配置为编程状态的有效存储单元的数量的调整。编程控制单元10响应于该控制时钟，依次选中对应数量的有效存储单元，将其配置为编程状态。
在对一个存储器进行编程前，需要通过外部链路信号设定一个初始数量值。也就是说第一个周期内被配置为编程状态的有效存储单元的数量是事先预设的；之后的每个周期内的数量，则是通过数量设定单元50根据前一个周期的总编程电流调整后的数量。
示例性的，如果数量设定单元50监测到总编程电流偏小，低于设定的低电流阈值，那么在下一个周期，额外加入一个有效编程单元，即N变为N+1；如果数量设定单元50监测到总编程电流偏大，高于设定的高电流阈值，那么在下一个周期，减少一个有效编程单元，即N变为N-1；如果数量设定单元50监测到总编程电流在设定范围内，那么在下一个周期，不做有效编程单元数量的变化。
在下一周期拟被配置为编程状态的有效存储单元的数量与当前周期一样时，则下个周期内被配置为编程状态的有效存储单元的位置相对于当前周期向后移动一位。数量设定单元50生成包含不同的激励信号的控制时钟， 分别用于控制当前周期内被顺次配置为编程状态的多个有效存储单元中的最末尾有效存储单元、该最末尾单元的下一个有效存储单元以及当前周期内被配置为编程状态的其他非最末尾有效存储单元，以实现一个周期内处于编程状态的有效存储单元的数量的增加还是减少。
另外，编程单元20的周期与数量设定单元50的周期并不是同一个周期，非特殊说明，后文中提到的周期均是指数量设定单元50的周期的介绍。编程单元用于对配置为编程状态的有效存储单元进行编程。
图14为本申请实施例三提供的一种编程装置的工作过程示意图。当向存储阵列中某一行进行编程时，页锁存器上会写入数值。
如图14所示，Active cells框内为被配置为编程状态的存储单元。第一个周期内单一时间内选定了4个有效存储单元被配置为编程状态，其他有效存储单元配置为非编程状态。编程单元20依次对选中的4个有效存储单元中的首单元进行编程。当对框内的第一个存储单元完成编程后，Active cells框向后移动0个、1个或者2个有效存储单元，继续对当前Active cells框内的第一个存储单元进行编程。
如图14，第一周期N＝4，该4个有效存储单元的总编程电流低于预设范围，则在第二个周期增加一，N＝5；当第二周期内总编程电流高于预设范围，则第三个周期减一，N＝4；当第三个周期内总编程电流在预设范围内，则第四个周期内数量不变，N＝4；当第四个周期内总编程电流高于预设范围，则第五个周期减一，N＝3。
图15为本申请实施例三提供的一种编程控制单元的电路图。
在进行编程之前，需要通过外部链路向有效编程单元链写入部分数据，选中数量N个有效存储单元并配置为编程状态，即进行初始化，为第一周期的编程提供一个初始的数量N。第一周期的初始数量需要经过实验或计算获得。
第一周期之后，每个周期内处于编程状态的有效存储单元的数量由数量设定单元进行确定。另外，在对整个新型存储器编程即将完成时，当剩余的 未完成编程的有效存储单元数量较少使总编程电流低于预设范围时，数量设定单元无法增加下一个周期内的数量。下文介绍的是新型存储器编程的中期过程(未完成编程的有效存储单元数量足够数量设定单元来调节)。
图16为本申请实施例三提供的一种外部链路信号波形图，结合图15所示的电路结构，本申请实施例三提供的数量N个有效存储单元配置为编程状态的方法同本申请实施例一，在此不再赘述。
示例性的，图17为本申请实施例三提供的一种时钟生成单元的结构示意图。编程装置还包括设于时钟生成单元30及编程控制单元10之间的数量设定单元50，时钟生成单元30向数量设定单元50提供激励时钟，即存在内部自建时钟。。
在上述示例的基础上，图18为本申请实施例三提供的另一种时钟生成单元的结构示意图，时钟生成单元30包括：第一检测模块31和生成模块32；第一检测模块31，用于依次检测当前被配置为编程状态的首个有效存储单元是否完成编程，并输出检测结果；生成模块32，用于若检测结果表征完成编程，则控制激励时钟产生激励信号，否则，控制激励时钟不产生激励信号。
示例性的，图19为本申请实施例三提供的一种时钟生成单元的电路图，其中，第一检测模块31同本申请实施例一，在此不再赘述。
图20为本申请实施例三提供的一种报错单元40的结构示意图；图21为本申请实施例三提供的一种报错单元40的电路图。其中，报错单元40同本申请实施例一，在此不再赘述。
图22为本申请实施例三提供的一种数量设定单元50的结构示意图。图23为本申请实施例三提供的一种数量设定单元50的电路图。数量设定单元50包括时钟控制模块51和时钟选择模块52。时钟控制模块51，用于基于当前周期内有效存储单元的总编程电流与预定范围的关系，输出第一控制时钟CLK_dff_D、第二控制时钟CLK_dff_N和第三控制时钟CLK_dff_O。
具体的，如图23所示的CLK_CTRL模块，接收激励时钟CLK_dff，输出第一控制时钟CLK_dff_D、第二控制时钟CLK_dff_N和第三控制时钟 CLK_dff_O。
情况1：当前周期的总编程电流低于预定范围时，第一控制时钟CLK_dff_D的激励信号的数量相比激励时钟的激励信号增加，第二控制时钟CLK_dff_N和第三控制时钟CLK_dff_O与激励时钟一致。
情况2：当前周期的总编程电流高于预定范围时，第二控制时钟CLK_dff_N的激励信号的数量相比激励时钟的激励信号减少，第一控制时钟CLK_dff_D和第三控制时钟CLK_dff_O与激励时钟一致。
情况3：当前周期的总编程电流在预定范围时，第一控制时钟CLK_dff_D、第二控制时钟CLK_dff_N和第三控制时钟CLK_dff_O与激励时钟一致。即使沿用上个周期的数量，因个别阻变单元的编程差异，总编程电流可能不在预定范围，参照情况1和情况2对处于编程状态的有效存储单元的数量进行调整。
如图23所示，时钟选择模块52包括多个第七开关H1、多个第八开关H2和多个第九开关H3。在图23中示例性的标注了左侧触发器对应的第七开关H1 i+1、第八开关H2 i+1、第九开关H3 i+1，其下标表征对应第i+1个触发器。多个第七开关H1、多个第八开关H2和多个第九开关H3分别与多个触发器一一对应。
进一步地，第七开关H1、第八开关H2和第九开关H3的一端通过第一开关与对应触发器的时钟端口连接。第七开关H1的另一端连接第一控制时钟CLK_dff_D；第八开关H3的另一端连接第二控制时钟CLK_dff_N；第九开关H3的另一端连接第三控制时钟CLK_dff_O。每个触发器所对应的三个开关，在同一时刻仅有一个开关是导通的。即每个触发器仅接收一个激励时钟。
每个周期内，处于编程状态的有效存储单元中对应的最后一个触发器对应的第八开关H2导通，该触发器对应的第七开关H1和第九开关H3断开；处于编程状态的有效存储单元中对应的最后一个触发器的下一个触发器对应的第七开关H1导通，该触发器对应的第八开关H2和第九开关H3断开；处于编程状态的有效存储单元中对应的除最后一个触发器之外的其他触发 器对应的第九开关H3导通，该其他触发器对应的第七开关H1和第八开关H2断开。
参照图23，体现在电路的逻辑控制上，只有当所对应的触发器输出逻辑0，所对应的触发器的前一个触发器输出逻辑1时，第七开关H1导通；只有所对应的触发器输出逻辑1，所对应的触发器的后一个触发器输出逻辑为0时，第八开关H2开关导通；第九开关H3在第七开关H1和第八开关H2均不导通时导通。这样每个触发器所对应的三个开关在用同一时刻均只有一个开关导通。
每个周期内包含数量N个处于编程状态的有效存储单元，在任意时刻，第八开关H2和第七开关H1均只有一个导通，分别对应这N个有效存储单元中最后一个有效存储单元和这N个有效存储单元后相邻的第一个有效存储单元。
图24为本申请实施例三提供的一种时钟控制模块51的结构示意图。时钟控制模块51包括第二检测模块53和逻辑计算模块54；第二检测模块53，用于基于当前周期内有效存储单元的总编程电流与预定范围的关系，输出第二控制信号、第三控制信号和第四控制信号；第二控制信号、第三控制信号、和第四控制信号表征当前周期的总编程电流与预定范围之间的关系；逻辑计算模块54，连接至第二检测模块53，用于在第二控制信号、第三控制信号和第四控制信号的控制下，输出第一控制时钟CLK_dff_D、第二控制时钟CLK_dff_N和第三控制时钟CLK_dff_O。
具体的，第二控制信号表征当前周期内有效存储单元的总编程电流低于预定范围中的低参数值；第三控制信号表征当前周期内有效存储单元的总编程电流高于预定范围中的高参数值；第四控制信号表征当前周期内有效存储单元的总编程电流在预定范围中。
下面结合电路图，对控制信号(包括第二控制信号、第三控制信号和第四控制信号)控制生成控制时钟(包括第一控制时钟CLK_dff_D、第二控制时钟CLK_dff_N和第三控制时钟CLK_dff_O)的实现方式进行阐述。
图25为本申请实施例三提供的一种第二检测模块53的电路示意图。第二检测模块53包括多个第十开关T、第三比较器、第四比较器、第一触发器、第二触发器和第三反相器。如图25所示，多个第十开关T与待编程行中的存储单元一一对应；第十开关T的第一端与对应的存储单元连接，第十开关T的第二端分别与第三比较器的反相输入端、第四比较器的同相输入端连接；第三比较器的同相输入端连接预定范围中的低参数值；第四比较器的反相输入端连接预定范围中的高参数值。
其中，第十开关T的状态取决于对应触发器的输出数据和对应页锁存器的存储数据，以控制被配置为编程状态的有效存储单元对应的第十开关T导通，其它非编程状态的有效存储单元对应的第十开关T断开。
具体的，第十开关T的状态由对应触发器的输出数据和对应页锁存器的存储数据的与逻辑决定。示例性的，当第十开关T i+1对应的触发器的输出数据(即其存储值)C i+1和对应的页锁存器的存储数据P i+1均为逻辑1，则二者与逻辑为1，则第十开关T i+1导通。对于每个周期内被配置为编程状态的有效存储单元而言，其对应的页锁存器的存储数据必然为逻辑1，其对应的触发器的输出数据也必然为1，其对应的第十开关T是导通的。即每个周期内被配置为编程状态的所有有效存储单元对应的第十开关T i+1均导通，以获取总编程电流。
由于比较器输入端是电压值，需要将选通的每一列的电流值通过合理的电路加和后线性转换成电压值。
将所获取的总编程电流转换为总编程电压值，输入第三比较器和第四比较器进行比较，并分别输出比较结果CO L、CO H。对于第三比较器，其同相输入端为低电压值Vref_L，反相输入端输入总编程电压值。当总编程电压值低于Vref_L时，则CO L信号为1；当总编程电压值高于Vref_L时，则CO L信号为0。对于第四比较器，其反相输入端为低电压值Vref_H，同相输入端输入总编程电压值。当总编程电压值低于Vref_H时，则CO H信号为1；当总编程电压值高于Vref_H时，则CO L信号为0。
第三比较器的输出端与第一触发器的输入端连接；第一触发器的第一输出端输出第一参数OL；第一触发器的第二输出端输出第一参数的非逻辑参数
Figure PCTCN2022102419-appb-000001
第四比较器与第二触发器的输入端的输出端连接；第二触发器的第一输出端输出第二参数OH；第二触发器的第二输出端输出第二参数的非逻辑参数
Figure PCTCN2022102419-appb-000002
第一参数OL和第二参数OH的组合形成第二控制信号、第三控制信号和第四控制信号。
第一触发器输入信号CO L、第二触发器输入信号CO H。第一触发器输出第一参数OL与CO L逻辑值相同。第二触发器输出第一参数OH与CO H逻辑值相同。综合第三比较器和第四比较器的比较结果，第一参数和第二参数对应有三种组合结果：
(1)当总编程电压值低于预定范围时，总编程电压值低于Vref_L，必然也低于Vref_H，则CO L＝1、CO H＝1，相应的OL＝1、OH＝1，即为第二控制信号。
(2)当总编程电压值高于预定范围时，总编程电压值高于Vref_H，必然也高于Vref_L，则CO L＝0、CO H＝0，相应的OL＝0、OH＝0，即为第三控制信号。
(3)当总编程电压值在预定范围内时，总编程电压值高于Vref_L，低于Vref_H，则CO L＝0、CO H＝1，相应的OL＝0、OH＝1，即为第四控制信号。
另外，第一触发器与第二触发器的时钟端口均连接第三反相器的输出端，第三反相器的输入端连接第四控制时钟CLK_ds。即第一触发器与第二触发器由第四控制时钟CLK_ds的反相信号控制。
图26为本申请实施例三提供的一种逻辑计算模块54的电路示意图。结合图26，对三种控制信号控制输出第一控制时钟CLK_dff_D、第二控制时钟CLK_dff_N和第三控制时钟CLK_dff_O的过程，以及第四控制时钟CLK_ds的生成过程进行阐述。
如图26所示，逻辑计算模块54包括：第三延时器、第一异或门、第十一开关M1、第十二开关M2、第十三开关M3、第十四开关M4。第十一开关M1的控制端连接第一参数OL；第十二开关M2的控制端连接第一参数的非逻辑参数O L；第十三开关M3的控制端连接第二参数OH；第十四开关M4的控制 端连接第二参数的非逻辑参数
Figure PCTCN2022102419-appb-000003
第三延时器的输入端连接激励时钟CLK_dff；第三延时器的输出端输出第四控制时钟CLK_ds。
上述设置用于控制各器件的响应时序，第一触发器和第二触发器延迟一定时间间隔再起作用，这段时间间隔用于编程控制模块20内的触发器、第四开关S、第十开关T、第三比较器和第四比较器的响应于激励时钟CLK_dff而起作用。
第一异或门的第一输入端连接第三延时器的输出端；第一异或门的第二输入端连接激励时钟CLK_dff；第一异或门的输出端连接第十一开关M1的第一端；第十一开关M1的第二端连接第一控制时钟CLK_dff_D的输出端。
上述设置，激励时钟CLK_dff与自身的延时信号进行异或逻辑运算，会相较于激励时钟CLK_dff多产生一个上跳沿。在第二控制信号(OL＝1、OH＝1)下，第十一开关M1导通，第十二开关M2断开。输出的第一控制时钟CLK_dff_D相较于激励时钟CLK_dff多一个上跳沿，进而可用于额外增加一个有效存储单元被配置为编程状态。
第十二开关M2的第一端连接激励时钟CLK_dff；第十二开关M2的第二端连接第一控制时钟CLK_dff_D的输出端。
上述设置，在第三控制信号(OL＝0、OH＝0)和第四控制信号(OL＝0、OH＝1)下，第十一开关M1闭合，第十二开关M2断开。输出的第一控制时钟CLK_dff_D与激励时钟CLK_dff一致。
第十三开关M3的第一端连接激励时钟CLK_dff；第十四开关M4的第一端接地；第十三开关M3的第二端和第十四开关M4的第二端均连接第二控制时钟CLK_dff_N的输出端。
上述设置，在第二控制信号(OL＝1、OH＝1)和第四控制信号(OL＝0、OH＝1)下，第十三开关M3导通，第十四开关M4断开。输出的第二控制时钟CLK_dff_N与激励时钟CLK_dff一致。在第三控制信号(OL＝0、OH＝0)下，第十三开关M3断开，第十四开关M4导通。输出的第二控制时钟CLK_dff_N接地，不产 生上跳沿，进而可用于减少一个有效存储单元被配置为编程状态。
第三控制时钟CLK_dff_O的输出端，连接激励时钟CLK_dff。该设置在三种控制信号下，CLK_dff_O一直与激励时钟CLK_dff一致。
图27为本申请实施例三提供的一种用于增加数量的波形图，对额外增加一个有效存储单元被配置为编程状态的过程进行阐述。激励信号CLK_dff包括两个上跳沿，每个上跳沿表征一个周期的开始。
初始激励时钟CLK_Internal经过第二延时器生成激励信号CLK_dff。激励信号CLK_dff经过第三延时器生成第四控制时钟CLK_ds。第四控制时钟CLK_ds的反相信号的上跳沿对应的时第四控制时钟CLK_ds的下降沿。其中，图27所示的Delay为生成模块32的第一反相器输出的对信号CO的反相延时信号。
当检测到总编程电流低于预设范围时，第三比较器的输出信号CO L＝1。第一触发器在第四控制时钟CLK_ds的第一个下降沿的激励下，输出信号OL跳变为1，第十一开关M1导通，第十二开关M2断开。输出的第一控制时钟CLK_dff_D相较于激励时钟CLK_dff多一个上跳沿，如图27中CLK_dff_D的第三个上升沿。
当总编程电流低于预设范围时，第四比较器的输出信号CO H＝1，第二触发器输出信号OH＝1，第十三开关M3导通，第十四开关M4断开，第二控制时钟CLK_dff_N与激励时钟CLK_dff一致。
当所对应的触发器输出逻辑0，所对应的触发器的前一个触发器输出逻辑1时，第七开关H1导通，连接的是第一控制时钟CLK_dff_D。图27中，在CLK_dff的第二个上跳沿处，对于第i+1个触发器，其输出C i+1＝0，第i个触发器的输出C i＝1，所以第i+1个触发器接收第一控制时钟CLK_dff_D。
当所对应的触发器输出逻辑1，所对应的触发器的后一个触发器输出逻辑为0时，第八开关H2开关导通，连接的是第二控制时钟CLK_dff_N。图27中，对于第i个触发器，其输出C i＝1，第i+1个触发器的输出C i+1＝0，所以第i个触发器接收第二控制时钟CLK_dff_N。
在图27中CLK_dff_D的第二个上跳沿处，第i个触发器跳变为1。此时第i+1个触发器依然输出为0。在图27中CLK_dff_D的第三个上跳沿处，第i+1个触发器输出为1。由于图27中CLK_dff_D的第三个上跳沿在CLK_dff的第二个上跳沿和第二个下降沿之间，所以第i+1个触发器的输出C i+1会在CLK_dff_D的第三个上跳沿处跳变为1。
当有效存储单元对应的触发器的输出C为1，则被配置为编程状态。当第i+1个触发器的输出C i+1为1，则其被配置为编程状态。基于上述的调整过程，增加了数量，则第i+1个触发器成为该周期下的最后一个触发器，该周期下的处于编程状态的有效存储单元的数量等于上一个周期的数量加一。若不增加数量，则第i个触发器作为该周期下的最后一个触发器，该周期下的处于编程状态的有效存储单元的数量等于上一个周期的数量。
若不额外增加数量，图27中CLK_dff_D则没有第三个上升沿，则第i+1个触发器一直输出为0。这种情况，对应的是总编程电流在预设范围内的情况：第三比较器的输出信号CO L＝0，第四比较器的输出信号CO H＝1，对应图26中，第十一开关M1断开，第十二开关M2导通，第十三开关M3导通，第十四开关M4断开，则第二控制时钟CLK_dff_D、第三控制时钟CLK_dff_N均与激励时钟CLK_dff一致。该周期下处于编程状态的有效存储单元的数量与上一个周期的数量一致。
另外，可观察到图27中CO L在CLK_dff的第一个上升沿之前的周期内已感知到总编程电流低于预设范围而输出为1，而在CLK_dff的第一个上升沿处开始的周期内并没有对数量进行调整。这是极端情况，CO L在CLK_dff的第一个上升沿之前的周期内已感知到总编程电流低于预设范围而输出为1，但是OL的输出是由CLK_ds的下降沿决定的，可能存在延后一个周期再调整的情况，即在CLK_dff的第二个上升沿处开始的周期才开始调整。此时，有可能在CLK_dff的第一个上升沿处开始的周期内的总编程电流已经在预设范围内，也会被调整。
图28为本申请实施例三提供的一种用于减少数量的波形图。结合图28， 对减少一个有效存储单元被配置为编程状态的过程进行阐述。其中图28所示的CLK_Internal、Delay、CLK_dff、CLK_ds与图27所示的相同，不再赘述。
当检测到总编程电流高于预设范围时，第四比较器的输出信号CO H＝0。第二触发器在第四控制时钟CLK_ds的第一个下降沿的激励下，输出信号OH跳变为0，第十三开关M3断开，第十四开关M4导通。输出的第二控制时钟CLK_dff_N接地，而不产生上跳沿，如图28中CLK_dff_N相较于CLK_dff没有第二个上升沿。
当检测到总编程电流高于预设范围时，第三比较器的输出信号CO L＝0，输出信号OL＝0，第十一开关M1断开，第十二开关M2导通。输出的第一控制时钟CLK_dff_D与激励时钟CLK_dff一致。
通过对图27的分析，得知第i个触发器接收第二控制时钟CLK_dff_N，第i+1个触发器接收第一控制时钟CLK_dff_D。在图28中，从结构上看，每个周期中，被配置为编程状态的N个有效存储单元中，最后一个有效存储单元对应导通第八开关H2，连接的是第二控制时钟CLK_dff_N；这N个有效存储单元之后的第一个有效存储单元对应导通第七开关H1，连接的是第一控制时钟CLK_dff_D。不变的是这三个激励时钟的输出端口与对应触发器的连接，变化的是这三个激励时钟的激励信号。
在总编程电流高于预设范围的情况下，第一控制时钟CLK_dff_D与激励时钟CLK_dff的激励信号是一致的；第二控制时钟CLK_dff_N接地，没有产生上跳沿，相比较激励时钟CLK_dff减少了激励信号。
在CLK_dff的第二个上跳沿，CLK_dff_N没有上跳沿，所以第i个触发器的输出C i＝0。由于C i＝0，第i+1个触发器在第一控制时钟CLK_dff_D的上跳沿(参考图28所示的CLK_dff)的激励下，其输出C i+1＝0。
基于上述的调整过程，减少了数量，则第i-1个触发器成为该周期下的最后一个触发器，该周期下的处于编程状态的有效存储单元的数量等于上一个周期的数量减一。若不减少数量，则第i个触发器作为该周期下的最后一 个触发器，该周期下的处于编程状态的有效存储单元的数量等于上一个周期的数量。
同图27中CO L在CLK_dff的第一个上升沿之前的周期内已感知到总编程电流低于预设范围而输出为1，图28中CO H在CLK_dff的第一个上升沿之前的周期内已感知到总编程电流高于预设范围而输出为0，而在CLK_dff的第一个上升沿处开始的周期内并没有对数量进行调整。
实施例四
本申请提供一种编程方法，应用于实施例三的编程装置，编程装置包括编程控制单元10、编程单元20和数量设定单元50；方法包括：数量设定单元50根据激励时钟的当前周期内被配置为编程状态的有效存储单元的总编程电流，生成控制时钟，以确定下一周期内被配置为编程状态的有效存储单元的数量。
本申请还提供一种硬件代码产品，包括硬件代码，硬件代码被处理器执行时实现上述实施例提供的方法。
本申请还提供一种可读存储介质，可读存储介质中存储有硬件代码，硬件代码被执行时用于实现上述实施例提供的方法。
本申请还提供一种电子设备，包括：处理器，以及与处理器通信连接的存储器；存储器存储硬件代码；处理器执行存储器存储的硬件代码，以实现上述实施例提供的方法。
本申请还提供一种新型存储器，包括多个电阻型存储单元，以及如前述实施例提供的编程装置；编程装置用以对电阻型存储单元进行编程。其中，新型存储器可以是阻变式存储器，可以是相变式存储器，也可以是磁变式存储器。
应当理解的是，本申请并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本申请的范围仅由所附的权利要求书来限制。

Claims (20)

  1. 一种编程装置，其特征在于，包括：编程控制单元和编程单元；
    所述编程控制单元，用于响应控制时钟，依次将待编程行中的每个有效存储单元作为首单元，执行处理，直至所有所述有效存储单元被编程：根据预定数量，选中该首单元及其之后的所述有效存储单元，配置为编程状态，将该首单元之后的未被选中的所述有效存储单元配置为非编程状态；
    所述编程单元，用于按照预定周期，执行对当前被配置为编程状态的所述有效存储单元进行编程，直至所有所述有效存储单元被编程。
  2. 根据权利要求1所述的装置，其特征在于，所述编程控制单元包括：由依次串联的多个触发器构成的编程单元链；其中，所述多个触发器与所述待编程行中各存储单元对应的页锁存器一一对应；其中，
    每个所述触发器的时钟端口通过第一开关连接至所述激励时钟，每个所述触发器的输出端通过第二开关连接至下一个所述触发器的输入端，每个所述触发器的输入端通过第三开关连接至下一个所述触发器的输入端；
    所述各存储单元对应的所述页锁存器，用于基于自身的存储数据，控制对应的所述触发器的所述第一开关、所述第二开关以及所述第三开关的开关状态，以建立有效编程单元链；其中，处于所述有效编程单元链的所述触发器对应的所述存储单元为所述有效存储单元；
    其中，被配置为编程状态的所述有效存储单元对应的所述触发器被配置为第一逻辑，被配置为非编程状态的所述有效存储单元对应的所述触发器被配置为第二逻辑。
  3. 根据权利要求2所述的装置，其特征在于，所述编程控制单元还包括：多个反相器；
    所述多个反相器与所述多个触发器一一对应，所述反相器的输入端与对应的所述页锁存器连接，所述反相器的输出端与对应的所述触发器的第三开关的控制端连接。
  4. 根据权利要求1所述的装置，其特征在于，所述编程控制单元还包括：
    数量设定单元，用于根据激励时钟的当前周期内被配置为编程状态的有效存储单元的总编程电流，生成所述控制时钟，以确定下一周期内被配置为编程状态的所述有效存储单元的数量；和/或，
    时钟生成单元，用于向所述数量设定单元提供所述激励时钟，或，用于向所述编程控制单元提供所述控制时钟。
  5. 根据权利要求4所述的装置，其特征在于，所述时钟生成单元包括：第一检测模块和生成模块；
    所述第一检测模块，用于依次检测当前被配置为编程状态的首个所述有效存储单元是否完成编程，并输出检测结果；
    所述生成模块，用于若所述检测结果表征完成编程，则控制所述激励时钟产生激励信号，否则，控制所述激励时钟不产生所述激励信号。
  6. 根据权利要求5所述的装置，其特征在于，所述第一检测模块包括：多个第四开关、以及第一比较器；
    所述多个第四开关与所述待编程行中的所述存储单元一一对应；所述第四开关的第一端与对应的所述存储单元连接，所述第四开关的第二端与所述 第一比较器的同相输入端连接；所述第一比较器的反相输入端连接第一参考电压；
    其中，所述第四开关用于选择所述第一检测模块当前要检测的所述有效存储单元，所述第四开关的状态取决于对应的所述触发器的输入数据和输出数据；所述第一比较器的输出数据表征当前被选择的所述有效存储单元是否完成编程。
  7. 根据权利要求6所述的装置，其特征在于，所述第一检测模块还包括：第一使能开关；
    所述第一使能开关设置在所述第四开关与所述第一比较器之间；
    所述编程单元开始编程后，所述第一使能开关为闭合状态；所述编程单元编程前，所述第一使能开关为断开状态。
  8. 根据权利要求7所述的装置，其特征在于，所述生成模块包括：第一与门、第一或门、第一延时器以及第一反相器；
    所述第一与门的第一输入端，与所述第一检测模块的输出端连接，接收所述第一检测模块输出的所述检测结果；
    所述第一与门的输出端与所述第一或门的第一输入端连接；所述第一或门的输出端与所述第一延时器的输入端连接；所述第一延时器的输出端与所述第一反相器的输入端连接；所述第一反相器的输出端与所述第一与门的第二输入端连接；
    其中，所述第一或门的第二输入端输入第一控制信号；根据所述第一控制信号以及所述第一与门的输出端的输出信号，所述第一或门的输出端输出初始激励时钟。
  9. 根据权利要求8所述的装置，其特征在于，所述时钟生成单元还包括：延时模块；
    所述延时模块包括第二延时器，用于对所述初始激励时钟进行延时处理，生成所述激励时钟。
  10. 根据权利要求9所述的装置，其特征在于，所述时钟生成单元还包括：第二使能开关；所述第二使能开关连接在所述第二延时器的输出端与所述编程控制单元之间；所述编程单元开始编程后，所述第二使能开关为闭合状态；所述编程单元编程前，所述第二使能开关为断开状态；或，
    所述装置还包括：报错单元，用于若当前检测的有效存储单元经过预设时长后仍未完成编程，则控制所述时钟生成单元输出的所述激励时钟产生所述激励信号。
  11. 根据权利要求10所述的装置，其特征在于，所述报错单元包括：第二反相器、第五开关、第六开关、第一电容、第二比较器；
    所述第二比较器的同相输入端与所述第一电容的第一端和所述第六开关的一端连接；所述第一电容的第一端通过所述第五开关与电源信号连接；所述第二比较器的反相输入端连接第二参考电压；所述第一电容的第二端接地；所述第六开关的另一端接地；
    所述第二比较器与第一或门的第二输入端连接，用于输出所述第一控制信号；
    所述第二反相器的输入端连接所述初始激励时钟，所述第二反相器的输出端与所述第五开关的控制端连接；所述第六开关的控制端连接所述初始激励时钟。
  12. 根据权利要求4所述的装置，其特征在于，所述数量设定单元包括：时钟控制模块和时钟选择模块；
    所述时钟控制模块，用于基于当前周期内所述总编程电流与预定范围的关系，输出第一控制时钟、第二控制时钟和第三控制时钟；
    其中，当所述总编程电流低于所述预定范围时，所述第一控制时钟的激励信号的数量相比所述激励时钟的激励信号增加，所述第二控制时钟和所述第三控制时钟与所述激励时钟一致；当所述总编程电流高于所述预定范围时，所述第二控制时钟的激励信号的数量相比所述激励时钟的激励信号减少，所述第一控制时钟和所述第三控制时钟与所述激励时钟一致；当所述总编程电流在所述预定范围时，所述第一控制时钟、所述第二控制时钟和所述第三控制时钟与所述激励时钟一致；
    所述时钟选择模块包括多个第七开关、多个第八开关和多个第九开关；
    所述多个第七开关、所述多个第八开关和所述多个第九开关分别与所述多个触发器一一对应，所述第七开关、所述第八开关和所述第九开关的一端通过所述第一开关与对应的所述触发器的时钟端口连接；所述第七开关的另一端连接所述第一控制时钟；所述第八开关的另一端连接所述第二控制时钟；所述第九开关的另一端连接所述第三控制时钟；
    每个周期内，被配置为编程状态的所述有效存储单元中对应的最后一个所述触发器对应的所述第八开关导通，该触发器对应的所述第七开关和所述第九开关断开；被配置为编程状态的所述有效存储单元中对应的最后一个所述触发器的下一个所述触发器对应的所述第七开关导通，该触发器对应的所述第八开关和所述第九开关断开；被配置为编程状态的所述有效存储单元中 对应的除最后一个所述触发器之外的其他所述触发器对应的所述第九开关导通，该其他所述触发器对应的所述第七开关和所述第八开关断开。
  13. 根据权利要求12所述的装置，其特征在于，所述时钟控制模块包括第二检测模块和逻辑计算模块；
    所述第二检测模块，用于基于当前周期内所述总编程电流与预定范围的关系，输出第二控制信号、第三控制信号和第四控制信号；所述第二控制信号、所述第三控制信号、和所述第四控制信号表征当前周期内所述总编程电流与所述预定范围之间的关系；
    所述逻辑计算模块，连接至所述第二检测模块，用于在所述第二控制信号、所述第三控制信号和所述第四控制信号的控制下，输出所述第一控制时钟、所述第二控制时钟和所述第三控制时钟。
  14. 根据权利要求13所述的装置，其特征在于，所述第二检测模块包括多个第十开关、第三比较器、第四比较器、第一触发器、第二触发器和第三反相器；
    所述多个第十开关与所述待编程行中的所述存储单元一一对应；所述第十开关的第一端与对应的所述存储单元连接，所述第十开关的第二端分别与所述第三比较器的反相输入端、所述第四比较器的同相输入端连接；所述第三比较器的同相输入端连接所述预定范围中的低参数值；所述第四比较器的反相输入端连接所述预定范围中的高参数值；
    其中，所述第十开关的状态取决于对应的所述触发器的输出数据和对应的所述页锁存器的存储数据，以控制被配置为编程状态的所述有效存储单元对应的所述第十开关导通，其他的所述有效存储单元对应的第十开关断开；
    所述第三比较器的输出端与所述第一触发器的输入端连接；所述第一触发器的第一输出端输出第一参数；所述第一触发器的第二输出端输出所述第一参数的非逻辑参数；所述第四比较器与所述第二触发器的输入端的输出端连接；所述第二触发器的第一输出端输出第二参数；所述第二触发器的第二输出端输出所述第二参数的非逻辑参数；所述第一参数和所述第二参数的组合形成所述第二控制信号、所述第三控制信号和所述第四控制信号；
    所述第一触发器与所述第二触发器的时钟端口均连接所述第三反相器的输出端，所述第三反相器的输入端连接第四控制时钟。
  15. 根据权利要求14所述的装置，其特征在于，所述逻辑计算模块包括：第三延时器、第一异或门、第十一开关、第十二开关、第十三开关、第十四开关；
    所述第十一开关的控制端连接所述第一参数；所述第十二开关的控制端连接所述第一参数的非逻辑参数；所述第十三开关的控制端连接所述第二参数；所述第十四开关的控制端连接所述第二参数的非逻辑参数；
    所述第三延时器的输入端连接所述激励时钟；所述第三延时器的输出端输出所述第四控制时钟；
    所述第一异或门的第一输入端连接所述第三延时器的输出端；所述第一异或门的第二输入端连接所述激励时钟；所述第一异或门的输出端连接所述第十一开关的第一端；所述第十一开关的第二端连接所述第一控制时钟的输出端；
    所述第十二开关的第一端连接所述激励时钟；所述第十二开关的第二端连接所述第一控制时钟的输出端；
    所述第十三开关的第一端连接所述激励时钟；所述第十四开关的第一端接地；所述第十三开关的第二端和所述第十四开关的第二端均连接所述第二控制时钟的输出端；
    所述第三控制时钟的输出端连接所述激励时钟。
  16. 一种编程方法，其特征在于，应用于编程装置，所述编程装置包括编程控制单元和编程单元；所述方法包括：
    所述编程控制单元响应于控制时钟，依次将待编程行中的每个有效存储单元作为首单元，执行以下处理，直至所有有效存储单元被编程：根据预定数量，选中该首单元及其之后的所述有效存储单元配置为编程状态，将该首单元之后的未被选中的所述有效存储单元配置为非编程状态；
    所述编程单元按照预定周期，执行对当前被配置为编程状态的所述有效存储单元进行编程，直至所有所述有效存储单元被编程。
  17. 根据权利要求16所述的方法，其特征在于，所述编程装置还包括数量设定单元，所述数量设定单元根据激励时钟的当前周期内被配置为编程状态的有效存储单元的总编程电流，生成控制时钟，以确定下一周期内被配置为编程状态的所述有效存储单元的数量。
  18. 根据权利要求16所述的方法，其特征在于，所述方法还包括：
    所述编程控制单元将编程单元链中各触发器配置为第二逻辑；
    所述编程控制单元基于输入的第一逻辑，响应于所述预定数量的外部激励信号，将有效编程单元链中的前预定数量的所述触发器配置为所述第一逻辑；
    其中，与所述编程单元连中各所述触发器一一对应的页锁存器内存储为 所述第一逻辑的所述触发器构成所述有效编程单元链。
  19. 根据权利要求18所述的方法，其特征在于，所述编程控制单元响应于控制时钟，依次将待编程行中的每个有效存储单元作为首单元，执行处理，包括：
    所述编程控制单元基于输入的所述第二逻辑，响应于所述控制时钟，将所述有效编程单元链中当前为所述第一逻辑的首个触发器和最后一个触发器的下一触发器，分别配置为所述第二逻辑和所述第一逻辑。
  20. 一种新型存储器，其特征在于，包括多个电阻型存储单元，以及如权利要求1-15中任一项所述的编程装置；所述编程装置用以对所述电阻型存储单元进行编程。
PCT/CN2022/102419 2021-12-08 2022-06-29 编程装置、方法及新型存储器 WO2023103358A1 (zh)

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