WO2023103007A1 - 显示面板的制造方法以及显示面板 - Google Patents

显示面板的制造方法以及显示面板 Download PDF

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Publication number
WO2023103007A1
WO2023103007A1 PCT/CN2021/138810 CN2021138810W WO2023103007A1 WO 2023103007 A1 WO2023103007 A1 WO 2023103007A1 CN 2021138810 W CN2021138810 W CN 2021138810W WO 2023103007 A1 WO2023103007 A1 WO 2023103007A1
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Prior art keywords
substrate
transistor
display panel
storage capacitor
base substrate
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PCT/CN2021/138810
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English (en)
French (fr)
Inventor
卢马才
姚江波
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Tcl华星光电技术有限公司
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Application filed by Tcl华星光电技术有限公司 filed Critical Tcl华星光电技术有限公司
Priority to JP2021577835A priority Critical patent/JP2024503946A/ja
Priority to US17/622,801 priority patent/US20240038784A1/en
Publication of WO2023103007A1 publication Critical patent/WO2023103007A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0095—Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Definitions

  • the present application relates to the technical field of display panels, in particular to a method for manufacturing a display panel and a display panel.
  • organic light emitting diode Organic Light Emitting Diode
  • TFT Thi Film Transistor
  • Micro LED micro light emitting diode
  • SCLED submillimeter light emitting diode
  • OLEDs, Micro LEDs, and Mini LEDs in the prior art are designed with 3T1C external supplementary pixel circuits.
  • One pixel requires three thin film transistors and one storage capacitor, and in the display panel, the three thin film transistors are arranged along parallel lines. They are arranged side by side in the direction of the display panel, so that the pixel size cannot be reduced. If the display panel requires better electronic characteristics, more than four thin film transistors are required in one pixel, resulting in a further increase in pixel size, a decrease in pixel density, and a decrease in the resolution of display panel products.
  • the main purpose of the present application is to provide a method for manufacturing a display panel and a display panel, so as to solve the problem that the pixel in the display panel of the prior art adopts a pixel circuit including a plurality of TFTs and capacitors arranged along the horizontal direction parallel to the display panel. Design, resulting in a decrease in the pixel density of the display panel, resulting in a technical problem of a decrease in the resolution of the display panel product.
  • an embodiment of the present application provides a method for manufacturing a display panel, including:
  • first insulating layer on the first semiconductor element and the buffer layer, forming a first metal wiring layer on the first insulating layer, patterning the first metal wiring layer to form a second gate and a first plate of a storage capacitor, wherein the second gate is located above the first semiconductor element;
  • first interlayer dielectric layer on the buffer layer, the first semiconductor element, and the first metal wiring layer, forming a second metal wiring layer on the first interlayer dielectric layer, and patterning the second metal wiring layer to form a second source and a second drain, wherein the first semiconductor element, the second gate, the second source and the second drain constitute drive transistor;
  • the third metal circuit layer is used to form the first gate, the first source, the first drain, the third gate, the third source, and the third drain, the first gate, the first source,
  • the first drain constitutes a switch transistor
  • the third gate, third source, and third drain constitute a sensing transistor.
  • the method further includes:
  • the orthogonal projection of the switching transistor on the substrate at least partially overlaps the orthogonal projection of the driving transistor on the substrate, or at least partially overlaps the storage capacitor on the substrate.
  • the orthogonal projection of the sensing transistor on the base substrate at least partially overlaps the orthogonal projection of the driving transistor on the substrate substrate, or at least partially overlaps the storage capacitor The orthographic projection of the substrate on the substrate.
  • the storage capacitor and the driving transistor are arranged along a direction parallel to the substrate, and are electrically connected to the driving transistor;
  • the switching transistor and the driving transistor are arranged along a direction perpendicular to the base substrate;
  • the sensing transistor and the driving transistor are arranged along the direction parallel to the base substrate, and are arranged with the storage capacitor along the direction perpendicular to the base substrate.
  • the embodiment of the present application also provides a display panel, including:
  • At least one pixel circuit is arranged on the base substrate, and includes:
  • a storage capacitor disposed on the base substrate and electrically connected to the drive transistor
  • a switch transistor arranged on the base substrate
  • a light emitting diode disposed on the base substrate, and electrically connected to the driving transistor and the sensing transistor;
  • the orthogonal projection of the switching transistor on the substrate at least partially overlaps the orthogonal projection of the driving transistor on the substrate, or at least partially overlaps the storage capacitor on the substrate. Orthographic projection of the substrate.
  • the orthogonal projection of the sensing transistor on the substrate is at least partially overlapped with the orthogonal projection of the driving transistor on the substrate, or is at least partially Overlaid on the orthogonal projection of the storage capacitor on the base substrate.
  • the storage capacitor and the driving transistor are arranged along a direction parallel to the substrate;
  • the switching transistor and the driving transistor are arranged along a direction perpendicular to the base substrate;
  • the sensing transistor and the driving transistor are arranged along the direction parallel to the base substrate, and are arranged with the storage capacitor along the direction perpendicular to the base substrate.
  • the storage capacitor includes a first plate and a second plate, and the first plate is set on the same layer as the second source or the second drain of the driving transistor, so The second electrode plate is arranged on the same layer as the electrode layer connected to the light emitting diode.
  • the first plate and the second plate of the storage capacitor are arranged with the sensing transistor along a direction perpendicular to the substrate, and the sensing A transistor is interposed between the first plate and the second plate.
  • One end of the storage capacitor is grounded
  • first source or the first drain of the switching transistor is electrically connected to the second gate of the driving transistor and the other end of the storage capacitor
  • sensing source or sensing drain of the sensing transistor is grounded.
  • the driving transistor is disposed between the switching transistor and the substrate, and the storage capacitor is disposed between the sensing transistor and the substrate.
  • the embodiment of the present application also provides a display panel, including:
  • At least one pixel circuit is arranged on the base substrate, and includes:
  • a storage capacitor disposed on the base substrate and electrically connected to the driving transistor
  • a switch transistor arranged on the base substrate
  • a light emitting diode disposed on the base substrate, and electrically connected to the driving transistor and the sensing transistor;
  • the orthogonal projection of the switching transistor on the substrate at least partially overlaps the orthogonal projection of the driving transistor on the substrate, or at least partially overlaps the storage capacitor on the substrate.
  • the orthogonal projection of the sensing transistor on the base substrate at least partially overlaps the orthogonal projection of the driving transistor on the substrate substrate, or at least partially overlaps the storage capacitor said orthogonal projection on said substrate substrate;
  • the storage capacitor and the driving transistor are arranged along a direction parallel to the base substrate;
  • the switching transistor and the driving transistor are arranged along a direction perpendicular to the base substrate.
  • the sensing transistor and the driving transistor are arranged along the direction parallel to the base substrate.
  • the sensing transistor and the storage capacitor are arranged along the direction perpendicular to the base substrate.
  • the storage capacitor includes a first plate and a second plate, and the first plate is set on the same layer as the second source or the second drain of the driving transistor, so The second electrode plate is arranged on the same layer as the electrode layer connected to the light emitting diode.
  • the first plate and the second plate of the storage capacitor are arranged with the sensing transistor along a direction perpendicular to the substrate.
  • the sensing transistor is interposed between the first plate and the second plate.
  • the driving transistor is disposed between the switching transistor and the substrate, and the storage capacitor is disposed between the sensing transistor and the substrate.
  • the second source or the second drain of the driving transistor is grounded
  • One end of the storage capacitor is grounded.
  • the first source or the first drain of the switching transistor is electrically connected to the second gate of the driving transistor and the other end of the storage capacitor.
  • the sensing source or the sensing drain of the sensing transistor is grounded.
  • the driving transistor, storage capacitor, switching transistor, and sensing transistor in the 3T1C pixel circuit are arranged to at least partially overlap each other in the orthogonal projection of the base substrate to achieve driving
  • the vertical stacking of transistors, storage capacitors, switching transistors, and sensing transistors reduces the area of pixels in the horizontal direction, and solves the problem that pixels in display panels in the prior art include multiple TFTs and capacitors along the lines parallel to the display panel.
  • the pixel circuit design arranged in the horizontal direction causes a decrease in the pixel density of the display panel, resulting in a technical problem of a decrease in the resolution of the display panel product, and achieves an increase in pixel density and an increase in the resolution of the display panel.
  • Fig. 1 is the thin film transistor (Thin Film Transistor) of the display panel of the embodiment of the present application Film Transistor, TFT) cross-sectional view of the substrate;
  • FIG. 2 is a pixel circuit diagram of a display panel according to an embodiment of the present application.
  • FIG. 3 is a flow chart of steps of a method for manufacturing a display panel according to an embodiment of the present application
  • FIG. 4 is a cross-sectional view of a semi-finished display panel corresponding to step S01 of the manufacturing method according to an embodiment of the present application;
  • FIG. 5 is a cross-sectional view of a semi-finished display panel corresponding to step S02 of the manufacturing method provided in the embodiment of the present application;
  • FIG. 6 is a cross-sectional view of a semi-finished display panel corresponding to step S03 of the manufacturing method provided in the embodiment of the present application;
  • FIG. 7 is a cross-sectional view of a semi-finished display panel corresponding to step S04 of the manufacturing method provided in the embodiment of the present application;
  • step S04 and step S05 of the manufacturing method provided by the embodiment of the present application are a cross-sectional views of a semi-finished display panel corresponding to step S04 and step S05 of the manufacturing method provided by the embodiment of the present application;
  • FIG. 9 is a cross-sectional view of a semi-finished display panel corresponding to step S05 of the manufacturing method provided by the embodiment of the present application.
  • FIG. 10 is a cross-sectional view of a semi-finished display panel corresponding to step S06 of the manufacturing method provided in the embodiment of the present application;
  • Fig. 11 is a cross-sectional view of another semi-finished display panel corresponding to step S06 of the manufacturing method provided by the embodiment of the present application;
  • Fig. 12 is a cross-sectional view of a semi-finished display panel corresponding to step S07 of the manufacturing method provided by the embodiment of the present application;
  • Fig. 13 is a cross-sectional view of another semi-finished display panel corresponding to step S07 of the manufacturing method provided by the embodiment of the present application;
  • Fig. 14 is a cross-sectional view of a semi-finished display panel corresponding to step S08 of the manufacturing method provided by the embodiment of the present application;
  • FIG. 15 is a cross-sectional view of a finished display panel corresponding to step S08 of the manufacturing method provided by the embodiment of the present application.
  • the main purpose of the present application is to provide a method for manufacturing a display panel and a display panel to solve the problem of using a pixel circuit design that includes multiple TFTs and capacitors arranged in a direction parallel to the display panel in the prior art.
  • the decrease in the pixel density of the display panel leads to a technical problem in which the resolution of the display panel product decreases.
  • an embodiment of the present application provides a method for manufacturing a display panel, which is used to manufacture a display panel including a 3T1C pixel circuit as shown in FIG. 1 and FIG. 2 .
  • the manufacturing method can also be used to manufacture a display panel including 4T1C pixel circuits or a display panel including more TFTs according to the same principle.
  • the above-mentioned display panel manufacturing method includes:
  • Step S01 forming a light-shielding layer on the base substrate.
  • a light shielding layer LS is formed on the base substrate 10 .
  • the light-shielding layer LS is not an essential structure of the display panel, so the step S01 can also be omitted.
  • the light-shielding layer LS is used to avoid unnecessary light leakage from the display panel, and it can be a metal layer.
  • Step S02 forming a buffer layer on the base substrate, and forming a first semiconductor element on the buffer layer.
  • the buffer layer B is formed on the base substrate 10 and the light shielding layer LS, and the first semiconductor element SC1 is formed on the buffer layer B.
  • the first semiconductor element SC1 is used to form a subsequent driving transistor, which will be further described later.
  • Step S03 forming a first insulating layer on the first semiconductor element and the buffer layer, forming a first metal wiring layer on the first insulating layer, and patterning the first metal wiring layer to form a second A gate and a first plate of the storage capacitor, wherein the second gate is located above the first semiconductor element.
  • the first semiconductor element SC1 can be further used to form a driving transistor, which will be further described in detail below.
  • the first insulating layer GI1 is formed on the first semiconductor element SC1 and the buffer layer B, and the first metal wiring layer 20 is formed on the first insulating layer.
  • the first metal circuit layer 20 is patterned to form a second gate GE1 and a first plate C01 of the storage capacitor Cst, wherein the second gate GE1 is located above the first semiconductor element SC1 .
  • Step S04 forming a first interlayer dielectric layer to the buffer layer, the first semiconductor element, and the first metal wiring layer, and forming a second metal wiring layer to the first interlayer dielectric layer , and pattern the second metal wiring layer to form a second source and a second drain, wherein the first semiconductor element, the second gate, the second source and the second The drain constitutes the drive transistor.
  • the first interlayer dielectric layer ILD1 is formed on the buffer layer B, the first semiconductor element SC1, and the first metal wiring layer 20,
  • the second metal wiring layer 30 is formed on the first interlayer dielectric layer ILD1, and the second metal wiring layer 30 is patterned to form S1 and a second drain corresponding to the second gate GE1.
  • pole D1 wherein the first semiconductor element SC1, the second gate GE1, the S1 and the second drain D1 form a driving transistor T2.
  • the driving transistor T2 can be further used to form a 3T1C pixel circuit.
  • Step S05 forming a second interlayer dielectric layer on the second metal circuit layer, forming a second semiconductor element and a third semiconductor element on the second interlayer dielectric layer.
  • the second interlayer dielectric layer ILD2 is formed on the second metal wiring layer 30, the second semiconductor element SC2 and the third semiconductor element SC3 formed on the second interlayer dielectric layer ILD2.
  • the second interlayer dielectric layer ILD2 is used for insulation between the metal circuit layer and the semiconductor element.
  • Step S06 forming a second insulating layer on the second interlayer dielectric layer, the second semiconductor element, and the third semiconductor element, forming a third metal wiring layer on the second insulating layer, patterning the third metal wiring layer to form a first gate, a first source, a first drain, a third gate, a third source, and a third drain, the first gate, the first The source and the first drain form a switching transistor, and the third gate, the third source and the third drain form a sensing transistor.
  • the second insulating layer GI2 is formed on the second interlayer dielectric layer ILD2, the second semiconductor element SC2, and the third semiconductor element SC3.
  • the third metal wiring layer 40 is formed on the second insulating layer GI2, and the third metal wiring layer 40 is patterned to form the first gate GE2, the first source S2, and the first drain D2 , the third gate GE3, the third source S3, and the third drain D3, the first gate GE2, the first source S2, and the first drain D2 form a switching transistor T1, and the third gate GE3 , the third source S3 and the third drain D3 form a sensing transistor T3.
  • the switching transistor T1 , the sensing transistor T3 , and the above-mentioned driving transistor T2 can jointly form a 3T1C pixel circuit.
  • Step S07 forming a passivation layer covering the third metal circuit layer, and forming a planarization layer on the passivation layer.
  • the passivation layer covers the third metal wiring layer 40 , and the planarization layer PLN is formed on the passivation layer PV.
  • Step S08 forming an electrode layer on the planarization layer, and arranging light-emitting diodes on the electrode layer, thereby completing the manufacture of the finished display panel.
  • the electrode layer PE is formed on the planarization layer PLN, and the light emitting diode 50 is disposed on the electrode layer PE, thereby completing the finished product of the display panel 1. manufacture.
  • the electrode layer PE is disposed on the same layer as the second plate C02 of the storage capacitor Cst.
  • the orthogonal projection of the switching transistor T1 on the substrate 10 at least partially overlaps the orthogonal projection of the driving transistor T2 on the substrate 10, or at least partially overlaps the storage capacitor Cst on the substrate 10.
  • the orthogonal projection of the switching transistor T1 is at least partially overlapped with the orthogonal projection of the driving transistor T2 or the orthogonal projection of the storage capacitor Cst, so that the switching transistor T1 and the driving
  • the transistor T2 is stacked in the vertical direction of the base substrate 10, which reduces the pixel circuit composed of the driving transistor T2, the switching transistor T1, and the sensing transistor T3 along the direction parallel to the display panel.
  • the orthogonal projection of the sensing transistor T3 on the substrate 10 at least partially overlaps the orthogonal projection of the driving transistor T2 on the substrate 10, Or at least partially overlap with the orthogonal projection of the storage capacitor Cst on the base substrate 10 .
  • the orthogonal projection of the sensing transistor T3 at least partially overlaps with the orthogonal projection of the driving transistor T2 or the orthogonal projection of the storage capacitor Cst, so that the switching transistor T1 and the
  • the driving transistor T2 is stacked in the vertical direction of the base substrate 10, which reduces the pixel circuit formed by the driving transistor T2, the switching transistor T1, and the sensing transistor T3 along the direction parallel to the display.
  • the area in the direction of the panel 1 further increases the pixel density.
  • the storage capacitor Cst and the driving transistor T2 are arranged along a direction X parallel to the substrate 10, and are electrically connected to the driving transistor T2; the switching transistor T1 is connected to the driving transistor T2.
  • the driving transistor T2 is arranged along a direction Y perpendicular to the base substrate 10; and the sensing transistor T3 and the driving transistor T2 are arranged along the direction X parallel to the base substrate 10, and and the storage capacitor Cst are arranged along the direction Y perpendicular to the base substrate 10 .
  • the light emitting diode 50 is electrically connected to the driving transistor T2, the switching transistor T1, and the sensing transistor T3 through the electrode layer PE.
  • the first source S2 or the first drain D2 is electrically connected to the second gate GE1 through a first via hole penetrating through the second interlayer dielectric layer ILD2, and the The electrode layer PE is electrically connected to the switching transistor and the sensing transistor T3 through a second via hole penetrating through the passivation layer and the planarization layer PLN.
  • the embodiment of the present application provides a display panel 1 , including: a base substrate 10 and at least one pixel circuit.
  • the pixel circuit is disposed on the base substrate 10 and includes: a driving transistor T2 , a storage capacitor Cst, a switching transistor T1 , a sensing transistor T3 , and a light emitting diode 50 .
  • the driving transistor T2 is disposed above the base substrate 10 .
  • the storage capacitor Cst is disposed above the base substrate 10 and electrically connected to the driving transistor T2.
  • the storage capacitor Cst includes a first plate C01 and a second plate C02 , as shown in FIG. 1 .
  • the switch transistor T1 is disposed above the base substrate 10 .
  • the sensing transistor T3 is disposed above the base substrate 10 .
  • the light emitting diode 50 is disposed above the base substrate 10 and is electrically connected to the driving transistor T2 and the sensing transistor T3.
  • the orthogonal projection of the switching transistor T1 on the substrate 10 at least partially overlaps the orthogonal projection of the driving transistor T2 on the substrate 10, or at least partially overlaps the storage capacitor Cst on the substrate 10.
  • the orthogonal projection of the switching transistor T1 is at least partially overlapped with the orthogonal projection of the driving transistor T2 or the orthogonal projection of the storage capacitor Cst, so that the switching transistor T1 and the driving
  • the transistor T2 is stacked in the vertical direction of the base substrate 10, which reduces the pixel circuit composed of the driving transistor T2, the switching transistor T1, and the sensing transistor T3 along the direction parallel to the display panel.
  • the area in the direction of 1 increases the pixel density.
  • the orthogonal projection of the sensing transistor T3 on the substrate 10 at least partially overlaps the orthogonal projection of the driving transistor T2 on the substrate 10, or at least partially overlaps the orthogonal projection of the driving transistor T2 on the substrate 10.
  • the orthogonal projection of the storage capacitor Cst on the base substrate 10 The orthogonal projection of the sensing transistor T3 at least partially overlaps with the orthogonal projection of the driving transistor T2 or the orthogonal projection of the storage capacitor Cst, so that the switching transistor T1 and the
  • the driving transistor T2 is stacked in the vertical direction of the base substrate 10, which reduces the pixel circuit formed by the driving transistor T2, the switching transistor T1, and the sensing transistor T3 along the direction parallel to the display.
  • the area in the direction of the panel 1 further increases the pixel density.
  • the storage capacitor Cst and the driving transistor T2 are arranged along a direction X parallel to the base substrate 10; the switching transistor T1 and the driving transistor T2 are arranged along a direction perpendicular to the The direction Y of the base substrate 10 is arranged; and the sensing transistor T3 and the driving transistor T2 are arranged along the direction X parallel to the base substrate 10, and are arranged with the storage capacitor Cst along the direction X The direction Y perpendicular to the base substrate 10 is arranged.
  • the storage capacitor Cst includes a first plate C01 and a second plate C02, the first plate C01 is connected to the second source S1 or the second drain of the driving transistor T1
  • the electrode D1 is arranged on the same layer, and the second electrode plate C02 is arranged on the same layer as the electrode layer PE of the light emitting diode 50 .
  • the first plate C01 and the second plate C02 of the storage capacitor Cst are arranged with the sensing transistor along a direction perpendicular to the base substrate 10 , and The sensing transistor is interposed between the first plate C01 and the second plate C02.
  • S1 or the second drain D1 of the driving transistor T2 is grounded;
  • the first source S2 or the first drain D2 of the switching transistor T1 is electrically connected to the second gate GE1 of the driving transistor T2 and the other end of the storage capacitor Cst one end; and the third source S3 or the third drain D3 of the sensing transistor T3 is grounded.
  • the driving transistor T2 is interposed between the switching transistor T1 and the substrate 10
  • the storage capacitor Cst is interposed between the sensing transistor T3 and the substrate. Between 10.
  • the display panel 1 further includes a light-shielding layer LS, a buffer layer B, a first semiconductor element SC1, a first insulating layer GI1, a first Metal wiring layer 20, first interlayer dielectric layer ILD1, second metal wiring layer 30, second interlayer dielectric layer ILD2, second insulating layer GI2, third metal wiring layer 40, passivation layer, planar layer, and an electrode layer PE;
  • the second gate GE1 of the driving transistor T2 is formed by patterning the first metal circuit layer 20;
  • the S1 and the second drain D1 of the driving transistor T2 are formed by The second metal circuit layer 30 is patterned;
  • the first source S2, the first drain D2, and the first gate GE2 of the switch transistor T1 are patterned by the third metal circuit layer 40
  • the third source S3, the third drain D3, and the third gate GE3 of the sensing transistor T3 are formed by patterning the third metal circuit layer 40; and the light emitting diode 50 It is arranged on the electrode layer PE.
  • the drive transistor T2, the storage capacitor Cst, the switching transistor T1, and the sensing transistor T3 in the 3T1C pixel circuit are arranged as orthogonal projections of each other on the base substrate 10 At least partial overlap achieves the way that the driving transistor T2, the storage capacitor Cst, the switching transistor T1, and the sensing transistor T3 are vertically stacked on each other, which reduces the area of the pixel in the horizontal direction, and solves the problem that the pixel in the display panel 1 of the prior art adopts the following methods:
  • the pixel circuit design in which multiple TFTs and capacitors are arranged along the horizontal direction parallel to the display panel 1 causes a decrease in the pixel density of the display panel 1, resulting in a technical problem of a decrease in the resolution of the display panel product, and achieves an improved display panel with pixel density resolution improvement.

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Abstract

一种显示面板制造方法以及一种显示面板，显示面板包括了上下堆叠的驱动晶体管（T2）、储存电容（Cst）、开关晶体管（T1）、以及感测晶体管（T3），其中至少两个晶体管上下相互堆叠，以解决现有技术的显示面板中的像素采用包括多个晶体管及电容沿着平行于显示面板的方向排列的像素电路设计，造成显示面板像素密度下降，导致显示面板产品的解析度下降的技术问题。

Description

显示面板的制造方法以及显示面板 技术领域
本申请涉及显示面板技术领域，具体涉及一种显示面板制造方法以及一种显示面板。
 背景技术
随着显示技术的发展，有机发光二极管(Organic Light Emitting Diode, OLED) 显示面板的薄膜晶体管(Thin Film Transistor, TFT)基板、微型发光二极管(Micro LED) 显示面板、次毫米发光二极管(Mini LED) 显示面板等主动发光显示面板具有高对比度、高色域、轻薄等优点。
现有技术的大尺寸OLED、Micro LED、Mini LED采用3T1C外补像素电路设计，一个像素需要三个薄膜晶体管和一个存储电容，且在所述显示面板中，所述三个薄膜晶体管沿着平行于所述显示面板的方向并排设置，导致像素的尺寸无法缩小。若显示面板需要更佳的电子特性，一个像素内需要四个以上的薄膜晶体管，造成像素尺寸进一步增大，造成像素密度下降，导致显示面板产品的解析度下降的问题。
 技术问题
本申请主要目的在于提供一种显示面板的制造方法以及一种显示面板，以解决现有技术的显示面板中的像素采用包括多个TFT及电容沿着平行于显示面板的水平方向排列的像素电路设计，造成显示面板像素密度下降，导致显示面板产品的解析度下降的技术问题。
 技术解决方案
在一方面，本申请实施例提供一种显示面板制造方法，包括：
形成缓冲层到衬底基板上，并形成第一半导体元件到所述缓冲层上；
形成第一绝缘层到所述第一半导体元件以及所述缓冲层上，形成第一金属线路层到所述第一绝缘层上，图形化所述第一金属线路层以形成第二栅极以及储存电容的第一极板，其中所述第二栅极位于所述第一半导体元件上方；
形成第一层间介电层到所述缓冲层、所述第一半导体元件、以及所述第一金属线路层上，形成第二金属线路层到所述第一层间介电层上，且图形化所述第二金属线路层以形成第二源极及第二漏极，其中所述第一半导体元件、所述第二栅极、所述第二源极以及所述第二漏极构成驱动晶体管；
形成一第二层间介电层到所述第二金属线路层上，形成一第二半导体元件以及第三半导体元件到所述第二层间介电层上；以及
形成第二绝缘层到所述第二层间介电层、所述第二半导体元件、以及所述第三半导体元件上，形成第三金属线路层到所述第二绝缘层上，图形化所述第三金属线路层以形成第一栅极、第一源极、第一漏极、第三栅极、第三源极、第三漏极，所述第一栅极、第一源极、第一漏极构成开关晶体管，所述第三栅极、第三源极、第三漏极构成感测晶体管。
在本申请一些实施例中，所述方法进一步包括：
形成覆盖所述第三金属线路层的钝化层，形成平坦化层到所述钝化层上；以及
形成电极层到所述平坦化层上，设置发光二极管到所述电极层上；
其中，所述开关晶体管在所述衬底基板的正交投影至少部分重叠于所述驱动晶体管在所述衬底基板的正交投影，或是至少部分重叠于所述储存电容在所述衬底基板的正交投影；
其中，所述感测晶体管在所述衬底基板的所述正交投影至少部分重叠于所述驱动晶体管在所述衬底基板的所述正交投影，或是至少部分重叠于所述储存电容在所述衬底基板的所述正交投影。
在本申请一些实施例中，所述储存电容与所述驱动晶体管沿着平行于所述衬底基板的方向排列，且电连接所述驱动晶体管；
所述开关晶体管与所述驱动晶体管沿着垂直于所述衬底基板的方向排列；以及
所述感测晶体管与所述驱动晶体管沿着所述平行于所述衬底基板的方向排列，且与所述储存电容沿着所述垂直于所述衬底基板的方向排列。
在另一方面，本申请实施例还提供一种显示面板，包括：
衬底基板；
至少一像素电路，设置在所述衬底基板上，且包括：
驱动晶体管，设置在所述衬底基板上；
储存电容，设置在所述衬底基板上，且电连接所述驱动晶体管；
开关晶体管，设置在所述衬底基板上；
感测晶体管，设置在所述衬底基板上；以及
发光二极管，设置在所述衬底基板上，且电连接所述驱动晶体管以及所述感测晶体管；
其中，所述开关晶体管在所述衬底基板的正交投影至少部分重叠于所述驱动晶体管在所述衬底基板的正交投影，或是至少部分重叠于所述储存电容在所述衬底基板的正交投影。
在本申请一些实施例中，所述感测晶体管在所述衬底基板的所述正交投影至少部分重叠于所述驱动晶体管在所述衬底基板的所述正交投影，或是至少部分重叠于所述储存电容在所述衬底基板的所述正交投影。
在本申请一些实施例中，所述储存电容与所述驱动晶体管沿着平行于所述衬底基板的方向排列；
所述开关晶体管与所述驱动晶体管沿着垂直于所述衬底基板的方向排列；以及
所述感测晶体管与所述驱动晶体管沿着所述平行于所述衬底基板的方向排列，且与所述储存电容沿着所述垂直于所述衬底基板的方向排列。
在本申请一些实施例中，所述储存电容包括第一极板以及一第二极板，所述第一极板与所述驱动晶体管的第二源极或第二漏极同层设置，所述第二极板与所述发光二极管连接的电极层同层设置。
在本申请一些实施例中，所述储存电容的所述第一极板以及所述第二极板与所述感测晶体管沿着垂直于所述衬底基板的方向排列，且所述感测晶体管介于所述第一极板与所述第二极板之间。
在本申请一些实施例中，其中所述驱动晶体管的第二源极或第二漏极接地；
其中所述储存电容的一端接地；
其中所述开关晶体管的第一源极或第一漏极电连接到所述驱动晶体管的所述第二栅极以及所述储存电容的另一端；以及
其中所述感测晶体管的感测源极或感测漏极接地。
在本申请一些实施例中，所述驱动晶体管设置在所述开关晶体管与所述衬底基板之间，且所述储存电容设置在所述感测晶体管与所述衬底基板之间。
在另一方面，本申请实施例还提供一种显示面板，包括：
衬底基板；
至少一像素电路，设置在所述衬底基板上，且包括：
驱动晶体管，设置在所述衬底基板上；
储存电容，设置在所述衬底基板上，且电连接所述驱动晶体管；
开关晶体管，设置在所述衬底基板上；
感测晶体管，设置在所述衬底基板上；以及
发光二极管，设置在所述衬底基板上，且电连接所述驱动晶体管以及所述感测晶体管；
其中，所述开关晶体管在所述衬底基板的正交投影至少部分重叠于所述驱动晶体管在所述衬底基板的正交投影，或是至少部分重叠于所述储存电容在所述衬底基板的正交投影；
其中，所述感测晶体管在所述衬底基板的所述正交投影至少部分重叠于所述驱动晶体管在所述衬底基板的所述正交投影，或是至少部分重叠于所述储存电容在所述衬底基板的所述正交投影；
其中，所述储存电容与所述驱动晶体管沿着平行于所述衬底基板的方向排列；以及
其中，所述开关晶体管与所述驱动晶体管沿着垂直于所述衬底基板的方向排列。
在本申请一些实施例中，所述感测晶体管与所述驱动晶体管沿着所述平行于所述衬底基板的方向排列。
在本申请一些实施例中，所述感测晶体管与所述储存电容沿着所述垂直于所述衬底基板的方向排列。
在本申请一些实施例中，所述储存电容包括第一极板以及一第二极板，所述第一极板与所述驱动晶体管的第二源极或第二漏极同层设置，所述第二极板与所述发光二极管连接的电极层同层设置。
在本申请一些实施例中，所述储存电容的所述第一极板以及所述第二极板与所述感测晶体管沿着垂直于所述衬底基板的方向排列。
在本申请一些实施例中，所述感测晶体管介于所述第一极板与所述第二极板之间。
在本申请一些实施例中，所述驱动晶体管设置在所述开关晶体管与所述衬底基板之间，且所述储存电容设置在所述感测晶体管与所述衬底基板之间。
在本申请一些实施例中，所述驱动晶体管的第二源极或第二漏极接地；以及
所述储存电容的一端接地。
在本申请一些实施例中，所述开关晶体管的第一源极或第一漏极电连接到所述驱动晶体管的所述第二栅极以及所述储存电容的另一端。
在本申请一些实施例中，所述感测晶体管的感测源极或感测漏极接地。
 有益效果
本申请具有至少下列优点：
本申请实施例提供的显示面板制造方法及显示面板，将3T1C像素电路中的驱动晶体管、储存电容、开关晶体管、以及感测晶体管配置为彼此在衬底基板的正交投影至少部分重叠达成了驱动晶体管、储存电容、开关晶体管、以及感测晶体管相互垂直堆叠的方式，减少了像素在水平方向的面积，解决现有技术的显示面板中的像素采用包括多个TFT及电容沿着平行于显示面板的水平方向排列的像素电路设计，造成显示面板像素密度下降，导致显示面板产品的解析度下降的技术问题，达成了像素密度的提升级显示面板的解析度提升。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例的显示面板的薄膜晶体管(Thin Film Transistor, TFT)基板的剖视图；
图2是本申请实施例的显示面板的像素电路图；
图3是本申请实施例的显示面板制造方法的步骤流程图；
图4是本申请实施例的对应所述制造方法的步骤S01的显示面板半成品剖视图；
图5是本申请实施例提供的对应所述制造方法的步骤S02的显示面板半成品剖视图；
图6是本申请实施例提供的对应所述制造方法的步骤S03的显示面板半成品剖视图；
图7是本申请实施例提供的对应所述制造方法的步骤S04的显示面板半成品剖视图；
图8是本申请实施例提供的对应所述制造方法的步骤S04以及步骤S05的显示面板半成品剖视图；
图9是本申请实施例提供的对应所述制造方法的步骤S05的显示面板半成品剖视图；
图10是本申请实施例提供的对应所述制造方法的步骤S06的显示面板半成品剖视图；
图11是本申请实施例提供的对应所述制造方法的步骤S06的另一显示面板半成品剖视图；
图12是本申请实施例提供的对应所述制造方法的步骤S07的显示面板半成品剖视图；
图13是本申请实施例提供的对应所述制造方法的步骤S07的另一显示面板半成品剖视图；
图14是本申请实施例提供的对应所述制造方法的步骤S08的显示面板半成品剖视图；
图15是本申请实施例提供的对应所述制造方法的步骤S08的显示面板成品剖视图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属本申请保护的范围。此外，应当理解的是，此处所描述的具体实施方式仅用于说明和解释本申请，并不用于限制本申请。
本申请主要目的在于提供一种显示面板的制造方法以及一种显示面板，以解决现有技术的显示面板像素采用包括多个TFT及电容沿着平行于显示面板的方向排列的像素电路设计，造成显示面板像素密度下降，导致显示面板产品的解析度下降的技术问题。
请参照图1至图3，本申请实施例提供一种显示面板的制造方法，用于制造如图1及图2所示的包括3T1C像素电路的显示面板。所述制造方法也可依据相同原则用于制造包括4T1C像素电路的显示面板或是包过更多TFT的显示面板。
请参照图3，上述显示面板制造方法包括：
步骤S01，在衬底基板上形成遮光层。
请参照图4，于上述步骤中，遮光层LS形成在所述衬底基板10上。遮光层LS并非显示面面板的必要结构，因此也可以省略所述步骤S01。所述遮光层LS用于避免显示面板产生不必要的漏光问题，且其可为金属层。
步骤S02，形成缓冲层到衬底基板上，并形成第一半导体元件到所述缓冲层上。
请参照图5，于上述步骤中，所述缓冲层B形成在所述衬底基板10以及所述遮光层LS上，并且所述第一半导体元件SC1形成在所述缓冲层B上。所述第一半导体元件SC1用于构成后续的驱动晶体管，将于后文中进一步叙述。
步骤S03，形成第一绝缘层到所述第一半导体元件以及所述缓冲层上，形成第一金属线路层到所述第一绝缘层上，图形化所述第一金属线路层以形成第二栅极以及储存电容的第一极板，其中所述第二栅极位于所述第一半导体元件上方。所述第一半导体元件SC1可进一步用于构成驱动晶体管，将进一步详述如下。
请参照图6，于上述步骤中，所述第一绝缘层GI1形成在所述第一半导体元件SC1以及所述缓冲层B上，所述第一金属线路层20形成在所述第一绝缘层GI1上，所述第一金属线路层20进行图形化以形成第二栅极GE1以及储存电容Cst的第一极板C01，其中所述第二栅极GE1位于所述第一半导体元件SC1上方。
步骤S04，形成第一层间介电层到所述缓冲层、所述第一半导体元件、以及所述第一金属线路层上，形成第二金属线路层到所述第一层间介电层上，且图形化所述第二金属线路层以形成第二源极及第二漏极，其中所述第一半导体元件、所述第二栅极、所述第二源极以及所述第二漏极构成驱动晶体管。
请参照图7及图8，于上述步骤中，所述第一层间介电层ILD1形成在所述缓冲层B、所述第一半导体元件SC1、以及所述第一金属线路层20上，所述第二金属线路层30形成在所述第一层间介电层ILD1上，且所述第二金属线路层30进行图形化以形成对应所述第二栅极GE1的S1及第二漏极D1，其中所述第一半导体元件SC1、所述第二栅极GE1、所述S1以及所述第二漏极D1构成驱动晶体管T2。所述驱动晶体管T2可进一步用于构成3T1C像素电路。步骤S05，形成一第二层间介电层到所述第二金属线路层上，形成第二半导体元件以及第三半导体元件到所述第二层间介电层上。
请参照图8及图9，于上述步骤中，所述第二层间介电层ILD2形成在所述第二金属线路层30上，所述第二半导体元件SC2以及所述第三半导体元件SC3形成在所述第二层间介电层ILD2上。所述第二层间介电层ILD2用于金属线路层和半导体元件之间的绝缘。
步骤S06，形成第二绝缘层到所述第二层间介电层、所述第二半导体元件、以及所述第三半导体元件上，形成第三金属线路层到所述第二绝缘层上，图形化所述第三金属线路层以形成第一栅极、第一源极、第一漏极、第三栅极、第三源极、第三漏极，所述第一栅极、第一源极、第一漏极构成开关晶体管，所述第三栅极、第三源极、第三漏极构成感测晶体管。
请参照图10及图11，于上述步骤中，所述第二绝缘层GI2形成在所述第二层间介电层ILD2、所述第二半导体元件SC2、以及所述第三半导体元件SC3上，所述第三金属线路层40形成在所述第二绝缘层GI2上，所述第三金属线路层40进行图形化以形成第一栅极GE2、第一源极S2、第一漏极D2、第三栅极GE3、第三源极S3、第三漏极D3，所述第一栅极GE2、第一源极S2、第一漏极D2构成开关晶体管T1，所述第三栅极GE3、第三源极S3、第三漏极D3构成感测晶体管T3。所述开关晶体管T1、感测晶体管T3、以及上述的驱动晶体管T2可共同构成3T1C像素电路。
步骤S07，形成覆盖所述第三金属线路层的钝化层，形成平坦化层到所述钝化层上。
请参照图12及图13，于上述步骤中，所述钝化层覆盖所述第三金属线路层40的，所述平坦化层PLN形成在所述钝化层PV上。
步骤S08，形成电极层到所述平坦化层上，设置发光二极管到所述电极层上，藉此完成显示面板成品的制造。
请参照图14及图15，于上述步骤中，所述电极层PE形成在所述平坦化层PLN上，所述发光二极管50设置在所述电极层PE上，藉此完成显示面板1成品的制造。此外，所述电极层PE与所述储存电容Cst的第二极板C02同层设置。
所述开关晶体管T1在所述衬底基板10的正交投影至少部分重叠于所述驱动晶体管T2在所述衬底基板10的正交投影，或是至少部分重叠于所述储存电容Cst在所述衬底基板10的正交投影。通过所述开关晶体管T1的所述正交投影至少部分重叠于所述驱动晶体管T2的所述正交投影或所述储存电容Cst的所述正交投影，使得所述开关晶体管T1以及所述驱动晶体管T2在所述衬底基板10的垂直方向上堆叠，减少了由所述驱动晶体管T2、所述开关晶体管T1、所述感测晶体管T3所构成的像素电路在沿着平行于所述显示面板1的方向的面积，进而提升了像素密度，从而提升显示面板的解析度。
在本申请一些实施例中，所述感测晶体管T3在所述衬底基板10的所述正交投影至少部分重叠于所述驱动晶体管T2在所述衬底基板10的所述正交投影，或是至少部分重叠于所述储存电容Cst在所述衬底基板10的所述正交投影。通过所述感测晶体管T3的所述正交投影至少部分重叠于所述驱动晶体管T2的所述正交投影或所述储存电容Cst的所述正交投影，使得所述开关晶体管T1以及所述驱动晶体管T2在所述衬底基板10的垂直方向上堆叠，减少了由所述驱动晶体管T2、所述开关晶体管T1、所述感测晶体管T3所构成的像素电路在沿着平行于所述显示面板1的方向的面积，进而提升了像素密度。
在本申请一些实施例中，所述储存电容Cst与所述驱动晶体管T2沿着平行于所述衬底基板10的方向X排列，且电连接所述驱动晶体管T2；所述开关晶体管T1与所述驱动晶体管T2沿着垂直于所述衬底基板10的方向Y排列；以及所述感测晶体管T3与所述驱动晶体管T2沿着所述平行于所述衬底基板10的方向X排列，且与所述储存电容Cst沿着所述垂直于所述衬底基板10的方向Y排列。在本申请一些实施例中，其中所述发光二极管50通过所述电极层PE电连接所述驱动晶体管T2、所述开关晶体管T1、以及所述感测晶体管T3。
在本申请一些实施例中，所述第一源极S2或第一漏极D2通过贯穿所述第二层间介电层ILD2的第一过孔电连接所述第二栅极GE1，且所述电极层PE通过贯穿所述钝化层以及所述平坦化层PLN的第二过孔电连接所述开关晶体管以及所述感测晶体管T3。
请复参照图1及图2，在另一方面，本申请实施例提供一种显示面板1，包括：衬底基板10以及至少一像素电路。
所述像素电路设置在所述衬底基板10上，且包括：驱动晶体管T2、储存电容Cst、开关晶体管T1、感测晶体管T3、以及发光二极管50。
所述驱动晶体管T2，设置在所述衬底基板10上方。
所述储存电容Cst，设置在所述衬底基板10上方，且电连接所述驱动晶体管T2。此外，所述储存电容Cst包括第一极板C01以及第二极板C02，如图1所示。
所述开关晶体管T1，设置在所述衬底基板10上方。
所述感测晶体管T3，设置在所述衬底基板10上方。
所述发光二极管50，设置在所述衬底基板10上方，且电连接所述驱动晶体管T2以及所述感测晶体管T3。
所述开关晶体管T1在所述衬底基板10的正交投影至少部分重叠于所述驱动晶体管T2在所述衬底基板10的正交投影，或是至少部分重叠于所述储存电容Cst在所述衬底基板10的正交投影。通过所述开关晶体管T1的所述正交投影至少部分重叠于所述驱动晶体管T2的所述正交投影或所述储存电容Cst的所述正交投影，使得所述开关晶体管T1以及所述驱动晶体管T2在所述衬底基板10的垂直方向上堆叠，减少了由所述驱动晶体管T2、所述开关晶体管T1、所述感测晶体管T3所构成的像素电路在沿着平行于所述显示面板1的方向的面积，进而提升了像素密度。
所述感测晶体管T3在所述衬底基板10的所述正交投影至少部分重叠于所述驱动晶体管T2在所述衬底基板10的所述正交投影，或是至少部分重叠于所述储存电容Cst在所述衬底基板10的所述正交投影。通过所述感测晶体管T3的所述正交投影至少部分重叠于所述驱动晶体管T2的所述正交投影或所述储存电容Cst的所述正交投影，使得所述开关晶体管T1以及所述驱动晶体管T2在所述衬底基板10的垂直方向上堆叠，减少了由所述驱动晶体管T2、所述开关晶体管T1、所述感测晶体管T3所构成的像素电路在沿着平行于所述显示面板1的方向的面积，进而提升了像素密度。
在本申请一些实施例中，所述储存电容Cst与所述驱动晶体管T2沿着平行于所述衬底基板10的方向X排列；所述开关晶体管T1与所述驱动晶体管T2沿着垂直于所述衬底基板10的方向Y排列；以及所述感测晶体管T3与所述驱动晶体管T2沿着所述平行于所述衬底基板10的方向X排列，且与所述储存电容Cst沿着所述垂直于所述衬底基板10的方向Y排列。
在本申请一些实施例中，所述储存电容Cst包括第一极板C01以及一第二极板C02，所述第一极板C01与所述驱动晶体管T1的第二源极S1或第二漏极D1同层设置，所述第二极板C02与所述发光二极管50的电极层PE同层设置。
在本申请一些实施例中，所述储存电容Cst的所述第一极板C01以及所述第二极板C02与所述感测晶体管沿着垂直于所述衬底基板10的方向排列，且所述感测晶体管介于所述第一极板C01与所述第二极板C02之间。
在本申请一些实施例中，所述驱动晶体管T2的S1或第二漏极D1接地；
所述储存电容Cst的一端接地；所述开关晶体管T1的第一源极S2或第一漏极D2电连接到所述驱动晶体管T2的所述第二栅极GE1以及所述储存电容Cst的另一端；以及所述感测晶体管T3的第三源极S3或第三漏极D3接地。
在本申请一些实施例中，所述驱动晶体管T2介于所述开关晶体管T1与所述衬底基板10之间，且所述储存电容Cst介于所述感测晶体管T3与所述衬底基板10之间。
在本申请一些实施例中，所述显示面板1进一步包括依序叠设在所述衬底基板10上的遮光层LS、缓冲层B、第一半导体元件SC1、第一绝缘层GI1、第一金属线路层20、第一层间介电层ILD1、第二金属线路层30、第二层间介电层ILD2、第二绝缘层GI2、第三金属线路层40、钝化层、平坦层、以及电极层PE；所述驱动晶体管T2的所述第二栅极GE1由所述第一金属线路层20图形化而形成；所述驱动晶体管T2的所述S1及所述第二漏极D1由第二金属线路层30图形化而成；所述开关晶体管T1的所述第一源极S2、所述第一漏极D2、以及第一栅极GE2由第三金属线路层40图形化而成；所述感测晶体管T3的所述第三源极S3、所述第三漏极D3、以及第三栅极GE3由所述第三金属线路层40图形化而成；以及所述发光二极管50设置在所述电极层PE上。此外，所述储存电容Cst的所述第二极板C02形成在所述电极层PE上并且与所述第一极板C01垂直相对。
本申请具有至少下列优点：
本申请实施例提供的显示面板制造方法及显示面板1，将3T1C像素电路中的驱动晶体管T2、储存电容Cst、开关晶体管T1、以及感测晶体管T3配置为彼此在衬底基板10的正交投影至少部分重叠达成了驱动晶体管T2、储存电容Cst、开关晶体管T1、以及感测晶体管T3相互垂直堆叠的方式，减少了像素在水平方向的面积，解决现有技术的显示面板1中的像素采用包括多个TFT及电容沿着平行于显示面板1的水平方向排列的像素电路设计，造成显示面板1像素密度下降，导致显示面板产品的解析度下降的技术问题，达成了像素密度的提升级显示面板的解析度提升。
以上对本申请实施例所提供的显示面板制造方法及显示面板1进行了详细介绍。
本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种显示面板制造方法，包括：
    形成缓冲层到衬底基板上，并形成第一半导体元件到所述缓冲层上；
    形成第一绝缘层到所述第一半导体元件以及所述缓冲层上，形成第一金属线路层到所述第一绝缘层上，图形化所述第一金属线路层以形成第二栅极以及储存电容的第一极板，其中所述第二栅极位于所述第一半导体元件上方；
    形成第一层间介电层到所述缓冲层、所述第一半导体元件、以及所述第一金属线路层上，形成第二金属线路层到所述第一层间介电层上，且图形化所述第二金属线路层以形成第二源极及第二漏极，其中所述第一半导体元件、所述第二栅极、所述第二源极以及所述第二漏极构成驱动晶体管；
    形成一第二层间介电层到所述第二金属线路层上，形成一第二半导体元件以及第三半导体元件到所述第二层间介电层上；以及
    形成第二绝缘层到所述第二层间介电层、所述第二半导体元件、以及所述第三半导体元件上，形成第三金属线路层到所述第二绝缘层上，图形化所述第三金属线路层以形成第一栅极、第一源极、第一漏极、第三栅极、第三源极、第三漏极，所述第一栅极、第一源极、第一漏极构成开关晶体管，所述第三栅极、第三源极、第三漏极构成感测晶体管。
  2. 根据权利要求1所述的显示面板制造方法，其中，所述方法进一步包括：
    形成覆盖所述第三金属线路层的钝化层，形成平坦化层到所述钝化层上；以及
    形成电极层到所述平坦化层上，设置发光二极管到所述电极层上；
    其中，所述开关晶体管在所述衬底基板的正交投影至少部分重叠于所述驱动晶体管在所述衬底基板的正交投影，或是至少部分重叠于所述储存电容在所述衬底基板的正交投影；
    其中，所述感测晶体管在所述衬底基板的所述正交投影至少部分重叠于所述驱动晶体管在所述衬底基板的所述正交投影，或是至少部分重叠于所述储存电容在所述衬底基板的所述正交投影。
  3. 根据权利要求1所述的显示面板制造方法，其中，
    所述储存电容与所述驱动晶体管沿着平行于所述衬底基板的方向排列，且电连接所述驱动晶体管；
    所述开关晶体管与所述驱动晶体管沿着垂直于所述衬底基板的方向排列；以及
    所述感测晶体管与所述驱动晶体管沿着所述平行于所述衬底基板的方向排列，且与所述储存电容沿着所述垂直于所述衬底基板的方向排列。
  4. 一种显示面板，包括：
    衬底基板；
    至少一像素电路，设置在所述衬底基板上，且包括：
    驱动晶体管，设置在所述衬底基板上；
    储存电容，设置在所述衬底基板上，且电连接所述驱动晶体管；
    开关晶体管，设置在所述衬底基板上；
    感测晶体管，设置在所述衬底基板上；以及
    发光二极管，设置在所述衬底基板上，且电连接所述驱动晶体管以及所述感测晶体管；
    其中，所述开关晶体管在所述衬底基板的正交投影至少部分重叠于所述驱动晶体管在所述衬底基板的正交投影，或是至少部分重叠于所述储存电容在所述衬底基板的正交投影。
  5. 根据权利要求4所述的显示面板，其中，所述感测晶体管在所述衬底基板的所述正交投影至少部分重叠于所述驱动晶体管在所述衬底基板的所述正交投影，或是至少部分重叠于所述储存电容在所述衬底基板的所述正交投影。
  6. 根据权利要求4所述的显示面板，其中，
    所述储存电容与所述驱动晶体管沿着平行于所述衬底基板的方向排列；
    所述开关晶体管与所述驱动晶体管沿着垂直于所述衬底基板的方向排列；以及
    所述感测晶体管与所述驱动晶体管沿着所述平行于所述衬底基板的方向排列，且与所述储存电容沿着所述垂直于所述衬底基板的方向排列。
  7. 根据权利要求4所述的显示面板，其中：
    所述储存电容包括第一极板以及一第二极板，所述第一极板与所述驱动晶体管的第二源极或第二漏极同层设置，所述第二极板与所述发光二极管连接的电极层同层设置。
  8. 根据权利要求7所述的显示面板，其中：所述储存电容的所述第一极板以及所述第二极板与所述感测晶体管沿着垂直于所述衬底基板的方向排列，且所述感测晶体管介于所述第一极板与所述第二极板之间。
  9. 根据权利要求4所述的显示面板，其中：
    所述驱动晶体管的第二源极或第二漏极接地；
    所述储存电容的一端接地；
    所述开关晶体管的第一源极或第一漏极电连接到所述驱动晶体管的所述第二栅极以及所述储存电容的另一端；以及
    所述感测晶体管的感测源极或感测漏极接地。
  10. 根据权利要求4所述的显示面板，其中，所述驱动晶体管设置在所述开关晶体管与所述衬底基板之间，且所述储存电容设置在所述感测晶体管与所述衬底基板之间。
  11. 一种显示面板，包括：
    衬底基板；
    至少一像素电路，设置在所述衬底基板上，且包括：
    驱动晶体管，设置在所述衬底基板上；
    储存电容，设置在所述衬底基板上，且电连接所述驱动晶体管；
    开关晶体管，设置在所述衬底基板上；
    感测晶体管，设置在所述衬底基板上；以及
    发光二极管，设置在所述衬底基板上，且电连接所述驱动晶体管以及所述感测晶体管；
    其中，所述开关晶体管在所述衬底基板的正交投影至少部分重叠于所述驱动晶体管在所述衬底基板的正交投影，或是至少部分重叠于所述储存电容在所述衬底基板的正交投影；
    其中，所述感测晶体管在所述衬底基板的所述正交投影至少部分重叠于所述驱动晶体管在所述衬底基板的所述正交投影，或是至少部分重叠于所述储存电容在所述衬底基板的所述正交投影；
    其中，所述储存电容与所述驱动晶体管沿着平行于所述衬底基板的方向排列；以及
    其中，所述开关晶体管与所述驱动晶体管沿着垂直于所述衬底基板的方向排列。
  12. 根据权利要求11所述的显示面板，其中，所述感测晶体管与所述驱动晶体管沿着所述平行于所述衬底基板的方向排列。
  13. 根据权利要求12所述的显示面板，其中，所述感测晶体管与所述储存电容沿着所述垂直于所述衬底基板的方向排列。
  14. 根据权利要求11所述的显示面板，其中，所述储存电容包括第一极板以及一第二极板，所述第一极板与所述驱动晶体管的第二源极或第二漏极同层设置，所述第二极板与所述发光二极管连接的电极层同层设置。
  15. 根据权利要求12所述的显示面板，其中，所述储存电容的所述第一极板以及所述第二极板与所述感测晶体管沿着垂直于所述衬底基板的方向排列。
  16. 根据权利要求11所述的显示面板，其中，所述感测晶体管介于所述第一极板与所述第二极板之间。
  17. 根据权利要求11所述的显示面板，其中，所述驱动晶体管设置在所述开关晶体管与所述衬底基板之间，且所述储存电容设置在所述感测晶体管与所述衬底基板之间。
  18. 根据权利要求11所述的显示面板，其中：
    所述驱动晶体管的第二源极或第二漏极接地；以及
    所述储存电容的一端接地。
  19. 根据权利要求18所述的显示面板，其中，所述开关晶体管的第一源极或第一漏极电连接到所述驱动晶体管的所述第二栅极以及所述储存电容的另一端。
  20. 根据权利要求18述的显示面板，其中，所述感测晶体管的感测源极或感测漏极接地。
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