WO2023100365A1 - Dispositif d'affichage - Google Patents

Dispositif d'affichage Download PDF

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Publication number
WO2023100365A1
WO2023100365A1 PCT/JP2021/044517 JP2021044517W WO2023100365A1 WO 2023100365 A1 WO2023100365 A1 WO 2023100365A1 JP 2021044517 W JP2021044517 W JP 2021044517W WO 2023100365 A1 WO2023100365 A1 WO 2023100365A1
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Prior art keywords
metal layer
display device
layer
terminal
wiring
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PCT/JP2021/044517
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English (en)
Japanese (ja)
Inventor
浩英 見村
正悟 村重
一篤 伊東
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シャープディスプレイテクノロジー株式会社
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Priority to PCT/JP2021/044517 priority Critical patent/WO2023100365A1/fr
Publication of WO2023100365A1 publication Critical patent/WO2023100365A1/fr

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements

Definitions

  • the present invention relates to display devices.
  • EL display devices using organic electroluminescence (hereinafter also referred to as "EL") elements have attracted attention as display devices that can replace liquid crystal display devices.
  • a plurality of thin film transistors (hereinafter also referred to as "TFTs") are provided for each sub-pixel, which is the minimum unit of an image.
  • TFTs thin film transistors
  • a semiconductor layer constituting a TFT for example, a semiconductor layer made of polysilicon with high mobility, a semiconductor layer made of an oxide semiconductor such as In--Ga--Zn--O with small leakage current, and the like are well known. ing.
  • Patent Document 1 discloses a display device having a hybrid structure in which a first TFT using a polysilicon semiconductor and a second TFT using an oxide semiconductor are formed on a substrate.
  • the organic EL display device includes a base substrate, a TFT layer provided on the base substrate, for example, a first metal layer, an inorganic insulating film and a second metal layer laminated in order, and a TFT layer provided on the TFT layer. It includes a light emitting element layer and a sealing film provided on the light emitting element layer.
  • a plurality of terminals are arranged in the terminal portion, and a lower metal layer formed on the same layer with the same material as the first metal layer and an upper metal layer formed on the same layer with the same material as the second metal layer.
  • Each terminal may be configured by stacking layers. In this case, the lack of adhesion between the lower metal layer and the upper metal layer may cause the upper metal layer to separate from the lower metal layer at each terminal, so there is room for improvement.
  • the present invention has been made in view of this point, and its object is to suppress peeling of the upper layer metal layer from the lower layer metal layer in each terminal pad of the terminal portion.
  • a display device comprises a base substrate and a thin film transistor layer provided on the base substrate and having a first metal layer, a first inorganic insulating film, and a second metal layer laminated in this order.
  • a light-emitting element layer provided on the thin-film transistor layer and having a plurality of light-emitting elements arranged corresponding to a plurality of sub-pixels forming a display region;
  • a frame region is provided around the display region, and a terminal portion is provided at an end portion of the frame region so as to extend in one direction.
  • each terminal pad comprises a lower metal layer made of the same material as the first metal layer and formed in the same layer, and an upper metal layer made of the same material as the second metal layer and formed in the same layer.
  • a metal layer, the lower metal layer is formed with a through-hole penetrating the lower metal layer, and the upper metal layer is provided so as to fill the through-hole.
  • peeling of the upper metal layer from the lower metal layer can be suppressed in each terminal pad of the terminal portion.
  • FIG. 1 is a plan view showing a schematic configuration of an organic EL display device according to a first embodiment of the invention.
  • FIG. 2 is a plan view of the display area of the organic EL display device according to the first embodiment of the invention.
  • FIG. 3 is a cross-sectional view of the display area of the organic EL display device according to the first embodiment of the invention.
  • FIG. 4 is an equivalent circuit diagram of a thin film transistor layer that constitutes the organic EL display device according to the first embodiment of the present invention.
  • FIG. 5 is a cross-sectional view showing an organic EL layer that constitutes the organic EL display device according to the first embodiment of the present invention.
  • FIG. 6 is a plan view of the terminal portion of the frame region of the organic EL display device according to the first embodiment of the present invention.
  • FIG. 7 is a cross-sectional view of the terminal portion of the organic EL display device along line VI-VI in FIG.
  • FIG. 8 is a cross-sectional view of the terminal portion of the organic EL display device taken along line VIII--VIII in FIG.
  • FIG. 9 is a cross-sectional view of the terminal portion of the organic EL display device along line IX-IX in FIG.
  • FIG. 10 is a plan view showing a first modification of the lower metal layer provided in the terminal portion of the organic EL display device according to the first embodiment of the present invention.
  • FIG. 11 is a plan view showing a second modification of the lower metal layer provided in the terminal portion of the organic EL display device according to the first embodiment of the present invention.
  • FIG. 10 is a plan view showing a first modification of the lower metal layer provided in the terminal portion of the organic EL display device according to the first embodiment of the present invention.
  • FIG. 11 is a plan view showing a second modification of the lower metal layer provided in the terminal portion of the organic
  • FIG. 12 is a plan view showing a third modification of the lower metal layer provided in the terminal portion of the organic EL display device according to the first embodiment of the present invention.
  • FIG. 13 is a plan view of a chip mounting portion and its periphery in the frame area of the organic EL display device according to the first embodiment of the present invention.
  • FIG. 1 is a plan view showing a schematic configuration of the organic EL display device 50 of this embodiment.
  • 2 and 3 are a plan view and a cross-sectional view of the display area D of the organic EL display device 50.
  • FIG. 4 is an equivalent circuit diagram of the thin film transistor layer 30 that constitutes the organic EL display device 50.
  • FIG. 5 is a cross-sectional view showing the organic EL layer 33 forming the organic EL display device 50.
  • FIG. 1 is a plan view showing a schematic configuration of the organic EL display device 50 of this embodiment.
  • 2 and 3 are a plan view and a cross-sectional view of the display area D of the organic EL display device 50.
  • FIG. 4 is an equivalent circuit diagram of the thin film transistor layer 30 that constitutes the organic EL display device 50.
  • FIG. 5 is a cross-sectional view showing the organic EL layer 33 forming the organic EL display device 50.
  • FIG. 6 is a plan view of the terminal portion T of the frame area F of the organic EL display device 50.
  • FIG. 7, 8 and 9 are sectional views of the terminal portion T of the organic EL display device 50 taken along lines VI-VI, VIII-VIII and IX-IX in FIG. 10, 11, and 12 show lower metal layers 19ta, 19tb, and 19tc of first, second, and third modifications of the lower metal layer 19t provided in the terminal portion T of the organic EL display device 50.
  • FIG. It is a plan view showing the.
  • FIG. 13 is a plan view of the chip mounting portion M of the frame area F of the organic EL display device 50 and its surroundings.
  • the organic EL display device 50 includes, for example, a rectangular display area D for displaying an image, and a frame area F provided around the display area D in a frame shape.
  • the rectangular display area D is exemplified, but the rectangular shape includes, for example, a shape with arc-shaped sides, a shape with arc-shaped corners, and a shape with arc-shaped corners.
  • a substantially rectangular shape such as a shape with a notch is also included.
  • a plurality of sub-pixels P are arranged in a matrix.
  • sub-pixels P having a red light-emitting region Er for displaying red sub-pixels P having a green light-emitting region Eg for displaying green
  • a sub-pixel P having a blue light-emitting region Eb for displaying blue is provided so as to be adjacent to each other.
  • one pixel is configured by three adjacent sub-pixels P each having a red light emitting region Er, a green light emitting region Eg and a blue light emitting region Eb.
  • a terminal part T for mounting a flexible printed wiring board, for example, is provided so as to extend in one direction (the X direction in the figure) at the lower end part of the frame area F in FIG.
  • a chip mounting portion M for mounting an integrated circuit chip is provided between the display region D and the terminal portion T in one direction (the X direction in the drawing). It is provided to extend to
  • the organic EL display device 50 includes a resin substrate 10 provided as a base substrate, a TFT layer 30 provided on the resin substrate 10, and a light emitting element layer provided on the TFT layer 30. and a sealing film 45 provided to cover the organic EL element layer 40 .
  • the resin substrate 10 is made of, for example, polyimide resin.
  • the TFT layer 30 includes a base coat film 11 provided on the resin substrate 10, an initialization TFT 9a (see FIG. 4) provided for each sub-pixel P on the base coat film 11, and a compensation TFT 9b. (see FIG. 4), a writing TFT 9c (see FIG. 4), a driving TFT 9d, a power supply TFT 9e (see FIG. 4), a light emission control TFT 9f, an anode discharge TFT 9g, a capacitor 9h, and the respective TFTs 9a to 9g and capacitors. and a planarizing film 22a provided on 9h.
  • a planarizing film 22a provided on 9h.
  • the TFT layer 30 is provided with a plurality of gate lines 14g extending parallel to each other in the X direction in the drawing. Further, as shown in FIG. 2, the TFT layer 30 is provided with a plurality of light emission control lines 14e extending parallel to each other in the X direction in the figure. Further, as shown in FIG. 2, the TFT layer 30 is provided with a plurality of second initialization power supply lines 19i as first metal layers so as to extend parallel to each other in the X direction in the figure. As shown in FIG. 2, each light emission control line 14e is provided adjacent to each gate line 14g and each second initialization power supply line 19i. In the TFT layer 30, as shown in FIG.
  • a plurality of source lines 21h are provided as a second metal layer so as to extend parallel to each other in the Y direction in the figure.
  • the TFT layer 30 is provided with a plurality of power supply lines 21i as a second metal layer so as to extend parallel to each other in the Y direction in the figure.
  • Each power supply line 21i is provided adjacent to each source line 21h, as shown in FIG.
  • the writing TFT 9c, the driving TFT 9d, the power supply TFT 9e, and the light emission control TFT 9f are provided as first TFTs having a first semiconductor layer made of polysilicon such as LTPS (low temperature polysilicon), and have gate electrodes. , a first terminal electrode and a second terminal electrode.
  • the initialization TFT 9a, the compensation TFT 9b, and the anode discharge TFT 9g are provided as second TFTs having a second semiconductor layer formed of an oxide semiconductor such as an In--Ga--Zn--O-based semiconductor.
  • a third terminal electrode and a fourth terminal electrode are provided.
  • the In—Ga—Zn—O-based oxide semiconductor is a ternary oxide of In (indium), Ga (gallium), and Zn (zinc), and the ratio (composition) of In, Ga, and Zn is ratio) is not particularly limited.
  • In--Ga--Zn--O based semiconductors may be amorphous or crystalline.
  • As the crystalline In--Ga--Zn--O-based semiconductor a crystalline In--Ga--Zn--O-based semiconductor in which the c-axis is oriented substantially perpendicular to the layer surface is preferable.
  • another oxide semiconductor may be included instead of the In--Ga--Zn--O-based semiconductor.
  • oxide semiconductors may include, for example, In—Sn—Zn—O-based semiconductors (eg, In 2 O 3 —SnO 2 —ZnO; InSnZnO).
  • the In—Sn—Zn—O-based semiconductor is a ternary oxide of In (indium), Sn (tin), and Zn (zinc).
  • oxide semiconductors include In--Al--Zn--O based semiconductors, In--Al--Sn--Zn--O based semiconductors, Zn--O based semiconductors, In--Zn--O based semiconductors, Zn--Ti-- O-based semiconductor, Cd--Ge--O-based semiconductor, Cd--Pb--O-based semiconductor, CdO (cadmium oxide), Mg--Zn--O-based semiconductor, In--Ga--Sn--O-based semiconductor, In--Ga--O-based semiconductor Semiconductors, Zr-In-Zn-O-based semiconductors, Hf-In-Zn-O-based semiconductors, Al-Ga-Zn-O-based semiconductors, Ga-Zn-O-based semiconductors, In-Ga-Zn-Sn-O-based semiconductors Semiconductors such as InGaO 3 (ZnO) 5 , magnesium zinc oxide (Mg
  • the initialization TFT 9a has its gate electrode electrically connected to the preceding (n-1) gate line 14g (n-1) and its third terminal electrode. is electrically connected to the lower conductive layer 16c of the capacitor 9h and the gate electrode of the driving TFT 9d, which will be described later, and its fourth terminal electrode is electrically connected to the power supply line 21i.
  • the first terminal electrodes and the second terminal electrodes of the first TFTs are indicated by circled numerals 1 and 2.
  • the third terminal electrode and the fourth terminal electrode of the second TFT are indicated by circled numerals 3 and 4.
  • the equivalent circuit diagram of FIG. 4 shows the pixel circuit of the n-th row and m-th column sub-pixel P, it also includes part of the pixel circuit of the (n ⁇ 1)-th row and m-th column sub-pixel P.
  • the power supply line 21i for supplying the high power supply voltage ELVDD also serves as the first initialization power supply line, but the power supply line 21i and the first initialization power supply line are provided separately.
  • the present invention is not limited to this, and a voltage different from the low power supply voltage ELVSS can be applied to turn off the organic EL element 35. can be entered.
  • the compensation TFT 9b has its gate electrode electrically connected to the gate line 14g(n) of its own stage (n stage) in each sub-pixel P, and its third terminal electrode is used for driving. It is electrically connected to the gate electrode of the TFT 9d, and its fourth terminal electrode is electrically connected to the first terminal electrode of the driving TFT 9d.
  • the write TFT 9c has its gate electrode electrically connected to the gate line 14g(n) of its own stage (n stage), and its first terminal electrode corresponds to the gate line 14g(n).
  • the second terminal electrode of the source line 21h is electrically connected to the second terminal electrode of the driving TFT 9d.
  • the driving TFT 9d has its gate electrode 14b (see FIG. 3) electrically connected to the third terminal electrodes of the initialization TFT 9a and the compensation TFT 9b.
  • the first terminal electrode 21e (see FIG. 3) is electrically connected to the fourth terminal electrode of the compensating TFT 9b and the second terminal electrode of the power supply TFT 9e, and the second terminal electrode 21g (see FIG. 3) is the write terminal electrode. It is electrically connected to the second terminal electrode of the embedding TFT 9c and the first terminal electrode of the light emission controlling TFT 9f.
  • the driving TFT 9 d is configured to control the current of the organic EL element 35 . Further, as shown in FIG.
  • the driving TFT 9d the first semiconductor layer 12b provided on the base coat film 11, the first gate insulating film 13 provided on the first semiconductor layer 12b, and the first gate insulating film
  • a gate electrode 14b provided on the film 13, a first interlayer insulating film 15 and a second interlayer insulating film 20 provided to cover the gate electrode 14b, and a second interlayer insulating film 20 spaced apart from each other.
  • a first terminal electrode 21e and a second terminal electrode 21g are provided.
  • the first semiconductor layer 12b includes a first conductor region and a second conductor region provided so as to be spaced apart from each other, and a channel region defined between the first conductor region and the second conductor region.
  • the first terminal electrode 21e and the second terminal electrode 21g are formed on the laminated film of the first gate insulating film 13, the first interlayer insulating film 15 and the second interlayer insulating film 20. It is electrically connected to the first conductor region and the second conductor region of the first semiconductor layer 12b through one contact hole.
  • the power supply TFT 9e has its gate electrode electrically connected to the light emission control line 14e of its own stage (n stage), and its first terminal electrode connected to the power supply line 21i. and its second terminal electrode is electrically connected to the first terminal electrode of the driving TFT 9d.
  • the light emission control TFT 9f has its gate electrode 14a (see FIG. 3) electrically connected to the light emission control line 14e of its own stage (n stage).
  • the terminal electrode 21a (see FIG. 3) is electrically connected to the second terminal electrode of the driving TFT 9d, and the second terminal electrode 21c (see FIG. 3) is electrically connected to the first electrode 31 of the organic EL element 35 to be described later. It is connected to the.
  • the light emission control TFT 9f includes a first semiconductor layer 12a provided on the base coat film 11, a first gate insulating film 13 provided on the first semiconductor layer 12a, and a first gate insulating film 13 provided on the first semiconductor layer 12a.
  • a first terminal electrode 21a and a second terminal electrode 21b (21c) are provided as follows.
  • the first semiconductor layer 12a includes a first conductor region and a second conductor region provided so as to be spaced apart from each other, and a channel region defined between the first conductor region and the second conductor region. there is 3, the first terminal electrode 21a and the second terminal electrode 21b are formed on the laminated film of the first gate insulating film 13, the first interlayer insulating film 15 and the second interlayer insulating film 20.
  • the second terminal electrode 21c is formed in the contact hole formed in the laminated film of the first gate insulating film 13 and the first interlayer insulating film 15, the relay electrode 16a, and the second interlayer insulating film 20. It is electrically connected to the second conductor region of the first semiconductor layer 12a through the formed contact hole.
  • the anode discharge TFT 9g has its gate electrode 19a (see FIG. 3) electrically connected to the gate line 14g(n) of its own stage (n stage).
  • the third terminal electrode 21c (see FIG. 3) is electrically connected to the first electrode 31 of the organic EL element 35, and the fourth terminal electrode 21d (see FIG. 3) is electrically connected to the second initialization power line 19i. It is connected.
  • the third terminal electrode 21c of the anode discharge TFT 9g is shared with the second terminal electrode 21c of the light emission control TFT 9f. Further, as shown in FIG.
  • the anode discharge TFT 9g includes a second semiconductor layer 17a provided on the first interlayer insulating film 15 and a second semiconductor layer 17a provided on the second semiconductor layer 17a as a second inorganic insulating film.
  • a third terminal electrode 21c and a fourth terminal electrode 21d are provided on the insulating film 20 so as to be spaced apart from each other.
  • the second semiconductor layer 17a is provided between the third conductor region and the fourth conductor region provided so as to be spaced apart from each other and between the third conductor region and the fourth conductor region. and a channel region.
  • the third terminal electrode 21c is electrically connected to the third conductor region of the second semiconductor layer 17a through the contact hole formed in the second interlayer insulating film 20 and the relay electrode 16a.
  • the fourth terminal electrode 21d is electrically connected to the fourth conductor region of the second semiconductor layer 17a through the contact hole formed in the second interlayer insulating film 20 and the relay electrode 16b.
  • the writing TFT 9c, the driving TFT 9d, the power supply TFT 9e, and the light emission control TFT 9f are provided as the first TFTs having the first semiconductor layer made of polysilicon, and are made of an oxide semiconductor.
  • the pixel circuit provided with the initialization TFT 9a, the compensation TFT 9b, and the anode discharge TFT 9g is exemplified as the second TFT having the second semiconductor layer, all the TFTs of the pixel circuit, that is, the initialization TFT 9a and the compensation TFT 9g, are provided.
  • the TFT 9b, the writing TFT 9c, the driving TFT 9d, the power supply TFT 9e, the light emission control TFT 9f, and the anode discharge TFT 9g may be composed of TFTs having a semiconductor layer formed of an oxide semiconductor.
  • the capacitor 9h has a lower conductive layer 16c (see FIG. 3) connected to the gate electrode 14b (see FIG. 3) of the driving TFT 9d, the initializing TFT 9a and the compensating TFT 9b.
  • the upper conductive layer 19b (see FIG. 3) is electrically connected to each third terminal electrode, the third terminal electrode of the anode discharge TFT 9g, the second terminal electrode of the light emission control TFT 9f, and the first terminal electrode of the organic EL element 35. It is electrically connected to the electrode 31 . Also, as shown in FIG.
  • the capacitor 9h is composed of a lower conductive layer 16c formed in the same layer with the same material as the third metal layer such as the relay electrodes 16a and 16b, and a second inorganic insulating layer on the lower conductive layer 16c. a second gate insulating film 18b provided as a film; and an upper conductive layer 19b provided on the second gate insulating film 18b and made of the same material and in the same layer as the first metal layer such as the gate electrode 19a. ing.
  • the upper conductive layer 19b is electrically connected to the source conductive layer 21f through a contact hole formed in the second interlayer insulating film 20, as shown in FIG.
  • the source conductive layer 21f is made of the same material as the second metal layer such as the source line 21h and formed in the same layer. 35 is electrically connected to the first electrode 31 .
  • the planarizing film 22a has a flat surface in the display region D, and is made of an organic insulating film such as an organic resin material such as polyimide resin or acrylic resin, or a polysiloxane-based SOG (spin on glass) material. It is
  • the organic EL element layer 40 includes a plurality of organic EL elements 35 (see FIG. 4) provided as a plurality of light emitting elements arranged in a matrix corresponding to the plurality of sub-pixels P. and an edge cover 32 which is provided in a grid pattern in common to all the sub-pixels P so as to cover the peripheral edge of the first electrode 31 of each organic EL element 35 .
  • the organic EL element 35 includes a first electrode 31 provided on the planarizing film 22a of the TFT layer 30 and an organic EL layer 31 provided on the first electrode 31. 33 and a second electrode 34 provided on the organic EL layer 33 .
  • the first electrode 31 is electrically connected to the second terminal electrode 21c of the light emission control TFT 9f of each sub-pixel P through a contact hole formed in the planarizing film 22a. .
  • the first electrode 31 also has a function of injecting holes into the organic EL layer 33 .
  • the first electrode 31 is more preferably made of a material having a large work function in order to improve the efficiency of injecting holes into the organic EL layer 33 .
  • examples of materials forming the first electrode 31 include silver (Ag), aluminum (Al), vanadium (V), cobalt (Co), nickel (Ni), tungsten (W), and gold (Au).
  • the material forming the first electrode 31 may be an alloy such as astatine (At)/astatine oxide (AtO 2 ). Further, the material forming the first electrode 31 is, for example, conductive oxides such as tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), and indium zinc oxide (IZO). There may be. Also, the first electrode 31 may be formed by stacking a plurality of layers made of the above materials. Compound materials having a large work function include, for example, indium tin oxide (ITO) and indium zinc oxide (IZO).
  • the edge cover 32 is made of, for example, an organic resin material such as polyimide resin or acrylic resin, or a polysiloxane-based SOG material.
  • the organic EL layer 33 is provided as a light-emitting functional layer, and as shown in FIG. and an electron injection layer 5 .
  • the hole injection layer 1 is also called an anode buffer layer, and has the function of bringing the energy levels of the first electrode 31 and the organic EL layer 33 close to each other and improving the efficiency of hole injection from the first electrode 31 to the organic EL layer 33 .
  • materials constituting the hole injection layer 1 include triazole derivatives, oxadiazole derivatives, imidazole derivatives, polyarylalkane derivatives, pyrazoline derivatives, phenylenediamine derivatives, oxazole derivatives, styrylanthracene derivatives, fluorenone derivatives, hydrazone derivatives, stilbene derivatives and the like.
  • the hole transport layer 2 has the function of improving the transport efficiency of holes from the first electrode 31 to the organic EL layer 33 .
  • Examples of materials constituting the hole transport layer 2 include porphyrin derivatives, aromatic tertiary amine compounds, styrylamine derivatives, polyvinylcarbazole, poly-p-phenylene vinylene, polysilane, triazole derivatives, and oxadiazole.
  • the light-emitting layer 3 In the light-emitting layer 3, holes and electrons are injected from the first electrode 31 and the second electrode 34 when a voltage is applied by the first electrode 31 and the second electrode 34, and the holes and electrons recombine. area.
  • the light-emitting layer 3 is made of a material with high light-emitting efficiency. Examples of materials constituting the light-emitting layer 3 include metal oxinoid compounds [8-hydroxyquinoline metal complex], naphthalene derivatives, anthracene derivatives, diphenylethylene derivatives, vinylacetone derivatives, triphenylamine derivatives, butadiene derivatives, and coumarin derivatives.
  • the electron transport layer 4 has a function of efficiently transferring electrons to the light emitting layer 3 .
  • the materials constituting the electron transport layer 4 include, for example, organic compounds such as oxadiazole derivatives, triazole derivatives, benzoquinone derivatives, naphthoquinone derivatives, anthraquinone derivatives, tetracyanoanthraquinodimethane derivatives, diphenoquinone derivatives, and fluorenone derivatives. , silole derivatives, and metal oxinoid compounds.
  • the electron injection layer 5 has a function of bringing the energy levels of the second electrode 34 and the organic EL layer 33 close to each other and improving the efficiency of electron injection from the second electrode 34 to the organic EL layer 33. With this function, The driving voltage of the organic EL element 35 can be lowered.
  • the electron injection layer 5 is also called a cathode buffer layer.
  • examples of materials constituting the electron injection layer 5 include lithium fluoride (LiF), magnesium fluoride (MgF 2 ), calcium fluoride (CaF 2 ), strontium fluoride (SrF 2 ), and barium fluoride.
  • inorganic alkali compounds such as (BaF 2 ), aluminum oxide (Al 2 O 3 ), strontium oxide (SrO), and the like.
  • the second electrode 34 is provided in common to all the sub-pixels P so as to cover each organic EL layer 33 and the edge cover 32, as shown in FIG.
  • the second electrode 34 also has a function of injecting electrons into the organic EL layer 33 .
  • the second electrode 34 is more preferably made of a material with a small work function in order to improve the efficiency of injecting electrons into the organic EL layer 33 .
  • materials constituting the second electrode 34 include silver (Ag), aluminum (Al), vanadium (V), calcium (Ca), titanium (Ti), yttrium (Y), and sodium (Na).
  • the second electrode 34 is composed of, for example, magnesium (Mg)/copper (Cu), magnesium (Mg)/silver (Ag), sodium (Na)/potassium (K), astatine (At)/astatine oxide (AtO 2 ), lithium (Li)/aluminum (Al), lithium (Li)/calcium (Ca)/aluminum (Al), lithium fluoride (LiF)/calcium (Ca)/aluminum (Al), etc.
  • the second electrode 34 may be formed of conductive oxides such as tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), and indium zinc oxide (IZO). . Also, the second electrode 34 may be formed by laminating a plurality of layers made of the above materials.
  • Examples of materials with a small work function include magnesium (Mg), lithium (Li), lithium fluoride (LiF), magnesium (Mg)/copper (Cu), magnesium (Mg)/silver (Ag), sodium (Na)/potassium (K), lithium (Li)/aluminum (Al), lithium (Li)/calcium (Ca)/aluminum (Al), lithium fluoride (LiF)/calcium (Ca)/aluminum (Al) etc.
  • the sealing film 45 is provided so as to cover the second electrode 34 , and the first inorganic sealing film 41 , the organic sealing film 42 and the second sealing film 42 are laminated on the second electrode 34 in this order. It has an inorganic sealing film 43 and has a function of protecting the organic EL layer 33 of the organic EL element 35 from moisture, oxygen, and the like.
  • the first inorganic sealing film 41 and the second inorganic sealing film 43 are composed of an inorganic insulating film such as a silicon nitride film, a silicon oxide film, or a silicon oxynitride film.
  • the organic sealing film 42 is made of an organic resin material such as acrylic resin, epoxy resin, silicone resin, polyurea resin, parylene resin, polyimide resin, or polyamide resin.
  • a first damming wall for suppressing the spread of the ink forming the organic sealing film 42 is provided in a frame shape so as to surround the display area D.
  • a second damming wall is provided in a frame shape so as to surround the first damming wall.
  • the organic EL display device 50 has a plurality of terminals arranged in a line in the terminal portion T of the frame region F in the direction in which the terminal portion T extends (the X direction in the drawing). It has a pad Up and a plurality of terminal wirings Uw provided so as to extend parallel to each other in the Y direction in the figure corresponding to the plurality of terminal pads Up.
  • the plurality of terminal wirings Uw are electrically connected to the plurality of terminal pads Up.
  • the terminal pad Up includes a lower metal layer 19t provided on the second gate insulating film 18c and an upper metal layer 21t provided on the lower metal layer 19t.
  • the display area D side (right side in the drawing) of the terminal pad Up is covered with a wiring covering layer 22b formed in the same layer and made of the same material as the flattening film 22a.
  • the lower metal layer 19t is formed in the same layer with the same material as the first metal layer such as the gate electrode 19a.
  • the lower metal layer 19t is formed with a plurality of through holes Sa penetrating through the lower metal layer 19t.
  • the plurality of through holes Sa are formed in the shape of a plurality of slits extending parallel to each other in the Y direction in the drawing.
  • the configuration in which a plurality of through holes Sa are formed in the lower metal layer 19t is exemplified, but one through hole Sa may be formed in the lower metal layer 19t.
  • the upper metal layer 21t is formed in the same layer with the same material as the second metal layer such as the source line 21h. Moreover, as shown in FIG. 8, the upper metal layer 21t is provided so as to fill the plurality of through holes Sa formed in the lower metal layer 19t.
  • the first metal layer and the second metal layer are formed by sequentially stacking a titanium-based metal film, an aluminum-based metal film, and a titanium-based metal film, as described later. Then, when patterning the silicon oxide film formed on the lower metal layer 19t in order to form the second interlayer insulating film 20, one portion of the titanium-based metal film on the upper metal layer 21t side of the lower metal layer 19t is removed. Some parts may be missing due to etching. As a result, in the lower metal layer 19t, the aluminum-based metal film exposed from the missing portion of the titanium-based metal film is oxidized, and there is a concern that the adhesion with the upper metal layer 21t is lowered.
  • the lower metal layer 19t and the upper metal layer 21t have a large area (as in the case without the through holes Sa). Since there is no contact and the adhesion between the upper metal layer 21t and the second gate insulating film 18c under the lower metal layer 19t is high, the adhesion between the lower metal layer 19t and the upper metal layer 21t is ensured.
  • the terminal wiring Uw is arranged on the second gate insulating film 18c so as to be spaced apart from the first terminal wiring 19tw provided on the second gate insulating film 18c. and a third terminal wiring 16t provided on the first interlayer insulating film 15 and arranged between the first terminal wiring 19tw and the second terminal wiring 19u.
  • an upper metal layer 21t extends over the first terminal wiring 19tw and the second terminal wiring 19u with the second interlayer insulating film 20 interposed therebetween, as shown in FIG.
  • the first terminal wiring 19tw is formed in the same layer with the same material as the first metal layer such as the gate electrode 19a. 6 and 7, the first terminal wiring 19tw is provided integrally with the lower metal layer 19t of the terminal pad Up. Further, as shown in FIGS. 6 and 9, the first terminal wiring 19tw is formed with a plurality of wiring through holes Sb penetrating through the first terminal wiring 19tw.
  • the plurality of wiring through holes Sb are formed in the shape of a plurality of slits extending parallel to each other in the Y direction in the drawing.
  • the configuration in which a plurality of wiring through-holes Sb are formed in the first terminal wiring 19tw is illustrated, but one wiring through-hole Sb may be formed in the first terminal wiring 19tw. .
  • the second terminal wiring 19u is formed in the same layer with the same material as the first metal layer such as the gate electrode 19a.
  • the second terminal wiring 19u is electrically connected to, for example, a fifth terminal wiring 19mw of an input-side chip wiring Nw arranged in the chip mounting portion M and described later.
  • the third terminal wiring 16t is formed in the same layer with the same material as the third metal layer such as the relay electrode 16a. 6 and 7, the third terminal wiring 16t is connected to the first terminal wiring 19tw and the second terminal wiring 19tw through the first contact hole Ha and the second contact hole Hb formed in the second gate insulating film 18c. It is electrically connected to the second terminal wiring 19u.
  • the third terminal wiring 16t formed in the same layer with the same material as the third metal layer is exemplified. It may be formed in one layer.
  • the lower metal layer 19t (including the first terminal wiring 19tw) in which the through holes Sa and the wiring through holes Sb are formed is illustrated, but the lower metal layer 19ta as shown in FIG. and a lower metal layer 19tc as shown in FIG. 12 .
  • a plurality of through holes Sc are formed by integrating a part of a plurality of through holes Sa (see FIG. 6) and a plurality of wiring through holes Sb (see FIG. 6). formed.
  • a plurality of through holes Sda and a plurality of wiring through holes Sdb are formed in dots.
  • some of the plurality of through holes Sa are integrated with the plurality of wiring through holes Sb (see FIG. 6), and the plurality of through holes Sa are integrated. (See FIG. 6) is formed to reach one end of the lower metal layer 19tc, and the lower metal layer 19tc is provided in a comb shape.
  • the organic EL display device 50 includes, in the chip mounting portion M of the frame area F, a chip under-chip circuit portion C provided in a rectangular shape extending in the X direction in the drawing, and a chip under-chip A plurality of output-side chip wirings 19md are provided so as to extend parallel to each other on the display area D side (upper side in the drawing) of the circuit section C.
  • FIG. 13 shows that the organic EL display device 50 includes, in the chip mounting portion M of the frame area F, a chip under-chip circuit portion C provided in a rectangular shape extending in the X direction in the drawing, and a chip under-chip A plurality of output-side chip wirings 19md are provided so as to extend parallel to each other on the display area D side (upper side in the drawing) of the circuit section C.
  • the output-side chip wiring 19md is made of the same material as the first metal layer such as the gate electrode 19a and is formed in the same layer.
  • Output-side chip terminals 21md are provided on the output-side chip wiring 19md, as shown in FIG.
  • the output-side chip wiring 19md is formed wide at the portion overlapping with the output-side chip terminal 21md.
  • (a plurality of) through-holes may be formed through the output-side chip wiring 19md in the same manner as the lower metal layer 19t.
  • the output-side chip terminals 21md are formed in the same layer with the same material as the second metal layer such as the source line 21h.
  • the plurality of output-side chip terminals 21md respectively provided on the plurality of output-side chip wirings 19md are arranged in a staggered manner along the X direction in the drawing.
  • the output-side chip wiring 19md is cut off at the upper and lower portions of the output-side chip terminal 21md in FIG. Electrical connection may be made through a pair of contact holes formed in the second gate insulating film 18c and wiring formed in the same layer of the same material as the three metal layers.
  • the chip mounting portion M extends on the terminal portion T side (lower side in the drawing) of the chip lower circuit portion C in the chip mounting portion M in the frame area F.
  • a plurality of input-side chip wirings Nw are provided as follows.
  • the plurality of input-side chip wirings Nw are electrically connected to the plurality of input-side chip terminals Np, respectively.
  • the input-side chip terminal Np is composed of a chip lower metal layer 19mt provided on the second gate insulating film 18c and a chip upper metal layer 21mt provided on the chip lower metal layer 19mt. I have.
  • the chip lower metal layer 19mt is formed in the same layer with the same material as the first metal layer such as the gate electrode 19a.
  • the chip lower metal layer 19mt is formed with a plurality of through holes Sf penetrating through the chip lower metal layer 19mt.
  • the plurality of through holes Sf are formed in the shape of a plurality of slits extending parallel to each other in the Y direction in the drawing. In this embodiment, the configuration in which a plurality of through holes Sf are formed in the chip lower metal layer 19mt is illustrated, but one through hole Sf may be formed in the chip lower metal layer 19mt.
  • the chip upper metal layer 21mt is made of the same material as the second metal layer such as the source line 21h and is formed in the same layer. Also, the chip upper metal layer 21mt is provided so as to fill the plurality of through holes Sf formed in the chip lower metal layer 19mt.
  • the input-side chip wiring Nw is separated from the fourth terminal wiring 19mv provided on the second gate insulating film 18c and the fourth terminal wiring 19mv on the second gate insulating film 18c. and a sixth terminal wiring 16m provided on the first interlayer insulating film 15 and arranged between the fourth terminal wiring 19mv and the fifth terminal wiring 19mw.
  • the fourth terminal wiring 19mv is formed in the same layer with the same material as the first metal layer such as the gate electrode 19a. Further, as shown in FIG. 13, the fourth terminal wiring 19mv is provided integrally with the chip lower metal layer 19mt of the input-side chip terminals Np. Further, as shown in FIG. 13, the fourth terminal wiring 19mv is formed with a plurality of wiring through-holes Sg penetrating through the fourth terminal wiring 19mv.
  • the plurality of wiring through holes Sg are formed in the shape of a plurality of slits extending parallel to each other in the Y direction in the drawing.
  • the fourth terminal wiring 19mv has a plurality of wiring through-holes Sg, but the fourth terminal wiring 19mv may have a single wiring through-hole Sg. .
  • the fifth terminal wiring 19mw is formed in the same layer with the same material as the first metal layer such as the gate electrode 19a.
  • the fifth terminal wiring 19mw is electrically connected to the second terminal wiring 19u of the terminal wiring Uw arranged in the terminal portion T, for example.
  • the sixth terminal wiring 16m is formed in the same layer with the same material as the third metal layer such as the relay electrode 16a. Also, as shown in FIG. 13, the sixth terminal wiring 16m is connected to the fourth terminal wiring 19mv and the fifth terminal via the third contact hole Hc and the fourth contact hole Hd formed in the second gate insulating film 18c. It is electrically connected to the wiring 19mw.
  • the sixth terminal wiring 16m formed in the same layer with the same material as the third metal layer is exemplified. It may be formed in one layer.
  • the organic EL display device 50 configured as described above, in each sub-pixel P, first, when the light emission control line 14e is selected and rendered inactive, the organic EL element 35 becomes non-light emitting. In the non-light-emitting state, the preceding gate line 14g(n-1) is selected, and a gate signal is input to the initialization TFT 9a via the gate line 14g(n-1), whereby the initialization TFT 9a is turned on, the high power supply voltage ELVDD of the power supply line 21i is applied to the capacitor 9h, and the driving TFT 9d is turned on. As a result, the charge in the capacitor 9h is discharged, and the voltage applied to the gate electrode of the driving TFT 9d is initialized.
  • the compensation TFT 9b and the writing TFT 9c are turned on, and the source signal is transmitted through the corresponding source line 21h. is written to the capacitor 9h via the diode-connected driving TFT 9d, the anode discharge TFT 9g is turned on, and the initialization signal is applied to the organic EL element via the second initialization power supply line 19i. The charge accumulated in the first electrode 31 applied to the first electrode 31 of 35 is reset.
  • the light emission control line 14e is selected, the power supply TFT 9e and the light emission control TFT 9f are turned on, and the driving current corresponding to the voltage applied to the gate electrode of the driving TFT 9d is supplied from the power line 21i to the organic EL element 35. be done.
  • the organic EL display device 50 in each sub-pixel P, the organic EL element 35 emits light with luminance corresponding to the drive current, and image display is performed.
  • the manufacturing method of the organic EL display device 50 of this embodiment includes a TFT layer forming process, an organic EL element layer forming process, a sealing film forming process, and a through hole forming process.
  • ⁇ TFT layer forming process> First, for example, on a resin substrate 10 formed on a glass substrate, a silicon oxide film (about 250 nm thick) and a silicon nitride film (about 100 nm thick) are sequentially formed by plasma CVD (Chemical Vapor Deposition). A base coat film 11 is formed by film forming.
  • an amorphous silicon film (about 50 nm thick) is formed by plasma CVD on the surface of the substrate on which the base coat film 11 is formed, and the amorphous silicon film is crystallized by laser annealing or the like to form a polysilicon film. are formed, the polysilicon film is patterned to form the first semiconductor layers 12a and 12b.
  • a silicon oxide film (thickness of about 100 nm) is formed on the substrate surface on which the first semiconductor layer 12a is formed by, for example, a plasma CVD method to form the first gate insulating film 13, and then, for example, sputtering is performed.
  • a metal film such as a molybdenum film (thickness of about 200 nm) by a method, the metal film is patterned to form gate electrodes 14a and 14b.
  • a silicon oxide film (thickness of about 150 nm) is formed, or a silicon nitride film (thickness of 150 nm) and a silicon oxide film (thickness of After forming the first interlayer insulating film 15 by forming a film of a molybdenum film (about 200 nm thick) in order, for example, by sputtering, the metal film is patterned. Then, a third metal layer such as the relay electrodes 16a and 16b and the lower conductive layer 16c is formed.
  • a semiconductor film such as InGaZnO 4 (about 30 nm thick) is formed by, for example, a sputtering method, is annealed, and then the semiconductor film is patterned. to form the second semiconductor layer 17a.
  • the inorganic insulating film such as a silicon oxide film (thickness of about 100 nm) on the substrate surface on which the second semiconductor layer 17a is formed, for example, by plasma CVD, the inorganic insulating film is patterned. , the second gate insulating film 18c of the terminal portion T and the chip mounting portion M are formed.
  • a titanium film (about 50 nm thick), an aluminum film (about 300 nm thick), and a titanium film (about 50 nm thick) are formed on the substrate surface on which the second gate insulating film 18c and the like are formed, by, for example, a sputtering method. and the like to form a metal laminated film, and then patterning the metal laminated film and the underlying silicon oxide film to form the first metal layer such as the gate electrode 19a and the upper conductive layer 19b, and the display area.
  • D second gate insulating films 12a and 12b are formed.
  • a silicon oxide film (about 400 nm thick) is formed, or a silicon oxide film (thickness: 300 nm) and a silicon nitride film are formed on the substrate surface on which the first metal layer and the like are formed, for example, by plasma CVD. (thickness of about 200 nm) are sequentially formed to form the second interlayer insulating film 20 .
  • a titanium film (thickness of about 50 nm) and an aluminum film (thickness of about 50 nm) are formed by sputtering, for example. 600 nm in thickness), a titanium film (about 50 nm in thickness) and the like are sequentially formed to form a metal laminated film.
  • the coating film is pre-baked, By performing exposure, development and post-baking, the planarizing film 22a and the wiring covering layer 22b are formed.
  • the TFT layer 30 can be formed as described above.
  • Organic EL element layer forming process A first electrode 31, an edge cover 32, an organic EL layer 33 (hole injection layer 1, hole transport The layer 2, the light emitting layer 3, the electron transport layer 4, the electron injection layer 5) and the second electrode 34 are formed to form the organic EL element layer 40.
  • FIG. 1 An edge cover 32, an organic EL layer 33 (hole injection layer 1, hole transport The layer 2, the light emitting layer 3, the electron transport layer 4, the electron injection layer 5) and the second electrode 34 are formed to form the organic EL element layer 40.
  • a sealing film 45 (first inorganic sealing film 41, organic sealing film 42, second inorganic sealing film 42) is formed on the organic EL element layer 40 formed in the organic EL element layer forming step using a known method.
  • a membrane 43) is formed.
  • the glass substrate is peeled off from the lower surface of the resin substrate 10 by irradiating laser light from the glass substrate side of the resin substrate 10 .
  • a protective sheet (not shown) is attached to the lower surface of the resin substrate 10 from which the glass substrate has been removed.
  • the organic EL display device 50 of this embodiment can be manufactured.
  • each terminal pad Up provided in the terminal portion T of the frame region F includes the lower metal layer 19t and the upper metal layer 21t.
  • the metal layer 21t is provided so as to fill the plurality of through holes Sa formed in the lower metal layer 19t.
  • the plurality of through holes Sa are not formed in the lower metal layer 19t, the lower metal layer 19t and the upper metal layer 21t are in contact with each other through one surface having a relatively large area.
  • the upper metal layer 21t is easily separated from 19t.
  • the plurality of through holes Sa are formed in the lower metal layer 19t.
  • the contact area is small, it becomes difficult for the upper metal layer 21t to separate from the lower metal layer 19t. Further, the upper metal layer 21t is exposed from each through-hole Sa formed in the lower metal layer 19t, and contacts the second gate insulating film 18c having higher adhesion than the lower metal layer 19t. As a result, the adhesion between the lower metal layer 19t and the upper metal layer 21t is ensured, so that peeling of the upper metal layer 21t from the lower metal layer 19t can be suppressed in each terminal pad Up of the terminal portion T. .
  • each terminal wiring Uw provided in the terminal portion T of the frame region F includes the first terminal wiring 19tw provided integrally with the lower metal layer 19t, and the first terminal wiring 19tw provided integrally with the lower metal layer 19t.
  • the first terminal wiring 19tw and the second terminal wiring 19tw are connected to the first terminal wiring 19tw through the second terminal wiring 19u provided so as to be separated from the first terminal wiring 19tw, and the first contact hole Ha and the second contact hole Hb formed in the second gate insulating film 18c. and a third terminal wiring 16t electrically connected to the terminal wiring 19u.
  • a plurality of wiring through holes Sb are formed in the first terminal wiring 19tw of each terminal wiring Uw provided in the terminal portion T of the frame region F.
  • the second interlayer insulating film 20 contacts the second gate insulating film 18c exposed from each wiring through-hole Sb formed in the first terminal wiring 19tw.
  • the second interlayer insulating film 20 comes into contact with the second gate insulating film 18c having higher adhesion than the first terminal wiring 19tw, and the adhesion between the first terminal wiring 19tw and the second interlayer insulating film 20 is ensured. Therefore, peeling of the second interlayer insulating film 20 from the first terminal wiring 19tw can be suppressed.
  • each chip terminal Np provided in the chip mounting portion M of the frame area F includes the chip lower metal layer 19mt and the chip upper metal layer 21mt.
  • the upper metal layer 21mt is provided so as to fill the plurality of through holes Sf formed in the chip lower metal layer 19mt.
  • the chip lower metal layer 19mt and the chip upper metal layer 21mt are in contact with each other on one surface having a relatively large area.
  • the chip upper metal layer 21mt is easily separated from the chip lower metal layer 19mt.
  • the chip lower layer metal layer 19mt and the chip upper layer metal layer 21mt are separated by the plurality of through holes Sf. Since the contact area is relatively small, it is difficult for the chip upper metal layer 21mt to separate from the chip lower metal layer 19mt. Further, the chip upper metal layer 21mt is exposed from each through-hole Sf formed in the chip lower metal layer 19mt, and contacts the second gate insulating film 18c having higher adhesion than the chip lower metal layer 19mt.
  • the chip upper metal layer 21mt is separated from the chip lower metal layer 19mt at each chip terminal Np of the chip mounting portion M. can be suppressed.
  • each input-side chip wiring Nw provided in the chip mounting portion M of the frame area F is connected to the fourth terminal provided integrally with the chip lower metal layer 19mt.
  • a plurality of wiring through-holes Sg are formed in the fourth terminal wiring 19mv of each input-side chip wiring Nw provided in the chip mounting portion M of the frame area F. Therefore, the second interlayer insulating film 20 contacts the second gate insulating film 18c exposed from each wiring through-hole Sg formed in the fourth terminal wiring 19mv. As a result, the second interlayer insulating film 20 comes into contact with the second gate insulating film 18c having higher adhesion than the fourth terminal wiring 19mv, and the adhesion between the fourth terminal wiring 19mv and the second interlayer insulating film 20 is ensured. Therefore, peeling of the second interlayer insulating film 20 from the fourth terminal wiring 19mv can be suppressed.
  • an organic EL layer having a five-layer structure of a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer was exemplified. It may have a three-layered structure of a combined hole-transport layer, a light-emitting layer, and an electron-transport layer and electron-injection layer.
  • the organic EL display device in which the first electrode is the anode and the second electrode is the cathode is exemplified.
  • an organic EL display device in which the second electrode is an anode is exemplified.
  • an organic EL display device was described as an example of a display device.
  • a display device equipped with a QLED (Quantum-dot light emitting diode), which is a light emitting element using a quantum dot-containing layer was described as an example of a display device.
  • the present invention is useful for flexible display devices.

Abstract

Dans la présente invention, une partie de borne (T) d'une partie de base dans une région de cadre comporte une pluralité de plots de connexion (Up) qui sont alignés dans une rangée dans une direction dans laquelle la partie de borne (T) s'étend, et elle comporte également une pluralité de fils de borne (Uw) disposés de façon à correspondre à la pluralité de plots de connexion (Up). Chaque plot de connexion (Up) comprend une couche métallique inférieure (19t) qui est formée dans la même couche et à partir du même matériau qu'une première couche métallique, et une couche métallique supérieure (21t) qui est formée dans la même couche et à partir du même matériau qu'une seconde couche métallique. Dans la couche métallique inférieure (19t), des trous traversants (Sa) qui pénètrent dans la couche métallique inférieure (19t) sont formés, et la couche métallique supérieure (21t) est disposée de manière à remplir ces trous traversants (Sa).
PCT/JP2021/044517 2021-12-03 2021-12-03 Dispositif d'affichage WO2023100365A1 (fr)

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Publication number Priority date Publication date Assignee Title
US20010031510A1 (en) * 1997-12-18 2001-10-18 Ahn Byung Chul Liquid crystal display and method of manufacturing the same
JP2010050194A (ja) * 2008-08-20 2010-03-04 Mitsubishi Electric Corp 素子基板、及びその製造方法、並びに電子機器
WO2013076940A1 (fr) * 2011-11-22 2013-05-30 シャープ株式会社 Substrat de matrice active et dispositif d'affichage à cristaux liquides
JP2014021472A (ja) * 2012-07-24 2014-02-03 Mitsubishi Electric Corp 表示パネルおよび表示装置
WO2015031037A1 (fr) * 2013-08-26 2015-03-05 Apple Inc. Affichages dotés de transistors à film mince de silicium et d'oxyde semi-conducteur
WO2019167279A1 (fr) * 2018-03-02 2019-09-06 シャープ株式会社 Dispositif d'affichage
WO2020170433A1 (fr) * 2019-02-22 2020-08-27 シャープ株式会社 Dispositif d'affichage et son procédé de fabrication
US20200357345A1 (en) * 2019-05-07 2020-11-12 Samsung Display Co., Ltd. Display device
WO2021240584A1 (fr) * 2020-05-25 2021-12-02 シャープ株式会社 Dispositif d'affichage et procédé de production de dispositif d'affichage

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010031510A1 (en) * 1997-12-18 2001-10-18 Ahn Byung Chul Liquid crystal display and method of manufacturing the same
JP2010050194A (ja) * 2008-08-20 2010-03-04 Mitsubishi Electric Corp 素子基板、及びその製造方法、並びに電子機器
WO2013076940A1 (fr) * 2011-11-22 2013-05-30 シャープ株式会社 Substrat de matrice active et dispositif d'affichage à cristaux liquides
JP2014021472A (ja) * 2012-07-24 2014-02-03 Mitsubishi Electric Corp 表示パネルおよび表示装置
WO2015031037A1 (fr) * 2013-08-26 2015-03-05 Apple Inc. Affichages dotés de transistors à film mince de silicium et d'oxyde semi-conducteur
WO2019167279A1 (fr) * 2018-03-02 2019-09-06 シャープ株式会社 Dispositif d'affichage
WO2020170433A1 (fr) * 2019-02-22 2020-08-27 シャープ株式会社 Dispositif d'affichage et son procédé de fabrication
US20200357345A1 (en) * 2019-05-07 2020-11-12 Samsung Display Co., Ltd. Display device
WO2021240584A1 (fr) * 2020-05-25 2021-12-02 シャープ株式会社 Dispositif d'affichage et procédé de production de dispositif d'affichage

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