WO2023097425A1 - 阵列基板、手写板、板擦、手写板系统及图案擦除方法 - Google Patents

阵列基板、手写板、板擦、手写板系统及图案擦除方法 Download PDF

Info

Publication number
WO2023097425A1
WO2023097425A1 PCT/CN2021/134290 CN2021134290W WO2023097425A1 WO 2023097425 A1 WO2023097425 A1 WO 2023097425A1 CN 2021134290 W CN2021134290 W CN 2021134290W WO 2023097425 A1 WO2023097425 A1 WO 2023097425A1
Authority
WO
WIPO (PCT)
Prior art keywords
erasing
layer
nfc
eraser
array substrate
Prior art date
Application number
PCT/CN2021/134290
Other languages
English (en)
French (fr)
Inventor
武晓娟
王修亮
王家星
赵宇
王建
毕谣
段金帅
葛杨
段智龙
于志强
陈翠玉
柳峰
韩天洋
Original Assignee
京东方科技集团股份有限公司
北京京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 北京京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202180003669.4A priority Critical patent/CN116529660A/zh
Priority to PCT/CN2021/134290 priority patent/WO2023097425A1/zh
Publication of WO2023097425A1 publication Critical patent/WO2023097425A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/137—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells characterised by the electro-optical or magneto-optical effect, e.g. field-induced phase transition, orientation effect, guest-host interaction or dynamic scattering
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/042—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by opto-electronic means
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals

Definitions

  • the present disclosure relates to the field of display technology, in particular, to an array substrate, a tablet, an eraser, a tablet system, and a pattern erasing method.
  • the LCD handwriting tablet can be used with the board eraser to realize the partial erasing function.
  • a light source is arranged on the eraser to irradiate the part of the handwriting board to be erased; under the irradiation of the light source, the pattern of the irradiated part will be erased.
  • the timing of turning on and off the light source of the current board eraser is inaccurate, which leads to inaccurate erasing range and is easy to mistakenly illuminate the human eye.
  • the purpose of the present disclosure is to overcome the shortcomings of the above-mentioned prior art, provide an array substrate, a tablet, an eraser, a tablet system and a pattern erasing method, improve erasing accuracy and protect human eyes.
  • an array substrate having a handwriting area and a peripheral area surrounding the handwriting area;
  • the array substrate includes erasing electrodes arranged in an array and a driving circuit for driving the erasing electrodes;
  • the driving circuit is configured to apply an erasing voltage to the erasing electrode under the irradiation of preset light;
  • the array substrate is also provided with an NFC coil for sending NFC (Near Field Communication) signals, and the induction range of the NFC coil covers the handwriting area.
  • NFC Near Field Communication
  • the sensing distance of the NFC coil is not greater than 10 cm.
  • the array substrate includes a base substrate and a driving layer stacked; the erasing electrodes and driving circuits are disposed on the driving layer.
  • the driving layer is provided with gate lines extending along the row direction and power supply lines extending along the column direction;
  • the driving circuit includes a thin film transistor; the source of the thin film transistor is electrically connected to the power line, the gate of the thin film transistor is electrically connected to the gate line, and the drain of the thin film transistor is connected to the corresponding
  • the erase electrodes are electrically connected.
  • the NFC coil is arranged on the driving layer, and the NFC coil is composed of a plurality of sub-electrodes; the orthographic projection of the sub-electrodes on the substrate is located on the wiper Between the orthographic projections of the electrodes on the substrate substrate.
  • the driving layer includes a gate layer provided with the gate line and a source-drain metal layer provided with the power line;
  • Some of the sub-electrodes are disposed on the gate layer and/or some of the sub-electrodes are disposed on the source-drain metal layer.
  • the sub-electrodes include row sub-electrodes extending along the row direction and column sub-electrodes extending along the column direction;
  • the row sub-electrode is located on the gate layer; the column sub-electrode is located on the source-drain metal layer.
  • the array substrate further includes a sensing layer, the NFC coil is located in the sensing layer; the sensing layer is located on a side of the driving layer close to the base substrate .
  • the array substrate further includes a base color layer and an anti-reflection layer
  • the anti-reflection layer is located on the side of the sensing layer close to the driving layer;
  • the base color layer is located on a side of the sensing layer away from the driving layer.
  • the wiring of the NFC coil at least partially overlaps with the erasing electrode.
  • a handwriting tablet comprising a cover plate, a liquid crystal layer, and the above-mentioned array substrate sequentially stacked.
  • the cover plate is provided with a common electrode layer.
  • an eraser which is provided with at least one erasing unit; the erasing unit includes a light source and an NFC chip;
  • the erasing unit is configured to: when the NFC chip senses an NFC signal, the light source emits preset light; when the NFC chip does not sense an NFC signal, the light source does not emit light.
  • the erasing unit further includes a control circuit, the control circuit is electrically connected to the NFC chip and the light source;
  • the control circuit is configured to: drive the light source to emit light after receiving the start signal generated by the NFC chip in response to the NFC signal; not drive the light source to emit light when the start signal is not received.
  • the NFC chip in the erasing unit is arranged overlapping with the light source, or arranged adjacent to each other.
  • the eraser includes a front side and a back side oppositely arranged, and includes a plurality of sides between the front side and the back side;
  • At least one erasing unit is provided on the front side of the eraser.
  • At least one of the erasing units is provided on at least one of the side surfaces.
  • the eraser is provided with a chamfer between the front surface and the side surface; at least one of the erasing units is provided at the chamfer.
  • a tablet system including the above-mentioned tablet and the above-mentioned eraser.
  • a pattern erasing method is provided, which is applied to the above-mentioned tablet system; the pattern erasing method includes:
  • the NFC coil of the tablet sends an NFC signal
  • the light source of the eraser When the NFC chip of the eraser senses the NFC signal, the light source of the eraser emits preset light; when the NFC chip of the eraser does not sense the NFC signal, the light source of the eraser does not emit light ;
  • an erasing voltage is applied to the erasing electrodes of the tablet.
  • FIG. 1 is a schematic diagram of the principle of a tablet system in an embodiment of the present disclosure.
  • Fig. 2 is a schematic structural diagram of a tablet in an embodiment of the present disclosure.
  • FIG. 3 is a schematic structural diagram of a tablet in an embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of an array substrate in an embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of an array substrate in an embodiment of the present disclosure.
  • Fig. 6 is a schematic diagram of writing a pattern on a handwriting board in an embodiment of the present disclosure.
  • Fig. 7 is a schematic diagram of erasing a partial pattern on a tablet in an implementation manner of the present disclosure.
  • FIG. 8 is a schematic diagram of the distribution of NFC coils in an embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram of the distribution of NFC coils in an embodiment of the present disclosure.
  • Fig. 10 is a schematic diagram of the distribution of NFC coils in an embodiment of the present disclosure.
  • FIG. 11 is a schematic diagram of the distribution of NFC coils in an embodiment of the present disclosure.
  • Fig. 12 is a schematic diagram of the distribution of NFC coils in an embodiment of the present disclosure.
  • FIG. 13 is a schematic diagram of the distribution of NFC coils in an embodiment of the present disclosure.
  • Fig. 14 is a schematic structural diagram of an eraser in an embodiment of the present disclosure.
  • Fig. 15 is a schematic structural view of an eraser in an embodiment of the present disclosure.
  • Fig. 16 is a schematic structural view of an eraser in an embodiment of the present disclosure.
  • FIG. 17 is a schematic structural diagram of an erasing unit in an embodiment of the present disclosure.
  • FIG. 18 is a schematic structural diagram of an erasing unit in an embodiment of the present disclosure.
  • FIG. 19 is a schematic structural diagram of an erasing unit in an embodiment of the present disclosure.
  • FIG. 20 is a schematic flowchart of a pattern erasing method in an embodiment of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.
  • the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.
  • the disclosure provides a tablet system and a pattern erasing method.
  • the tablet system includes a tablet and an eraser.
  • the handwriting board has a handwriting area, and an NFC coil D1 for transmitting NFC signals, an array of erasing electrodes P2 and a drive circuit PDC for driving the erasing electrodes are arranged in the handwriting area.
  • the driving circuit is configured to apply an erasing voltage to the erasing electrode under the irradiation of preset light. When the erasing electrode is loaded with an erasing voltage, the pattern at the position of the erasing electrode will be erased.
  • the eraser is provided with at least one erasing unit UU, and each erasing unit includes an NFC chip US and a light source UL.
  • the erasing unit is configured to: when the NFC chip senses an NFC signal, the light source emits preset light; when the NFC chip does not sense an NFC signal, the light source does not emit light.
  • the handwriting tablet system can apply the pattern erasing method shown in steps S110 to S130 to erase the pattern of the partial area of the handwriting panel.
  • Step S110 the NFC coil of the tablet sends an NFC signal
  • Step S120 when the NFC chip of the eraser detects the NFC signal, the light source of the eraser emits preset light; when the NFC chip of the eraser does not sense the NFC signal, the The light source does not emit light;
  • Step S130 when the driving circuit of the tablet is irradiated by the predetermined light, apply an erasing voltage to the erasing electrode of the tablet.
  • the NFC chip in the blackboard eraser can sense the NFC signal, and then make the light source emit light to erase the pattern on the tablet.
  • the NFC chip in the eraser cannot sense the NFC signal, and the light source does not emit light. In this way, the light source of the eraser can be turned off in time.
  • the power consumption of the eraser can be reduced, and on the other hand, it can prevent the light source from being irradiated to the user's eyes if the light source is not turned off in time.
  • the goals of reducing power consumption and improving safety can be achieved.
  • the eraser emits light when it is close to the tablet and turns off the power in time when it is away from the tablet, it can prevent the pattern on the tablet from being erased by mistake when the eraser is far away from the tablet. precision.
  • the tablet of the present disclosure may include a tablet panel PNL and a control module CTR for controlling the tablet panel PNL.
  • the tablet panel PNL may include an array substrate AR, a liquid crystal layer LC, and a cover CF that are sequentially stacked.
  • the liquid crystals in the liquid crystal layer LC may be liquid crystals with bistable properties, especially bistable cholesteric liquid crystals.
  • the cholesteric liquid crystal In the non-writing state, the cholesteric liquid crystal exhibits a focal conic texture and weakly scatters ambient light, making the tablet present a base color (for example, a dark color).
  • the pressure causes the cholesteric liquid crystal to change from a focal conic texture to a planar texture, which selectively reflects visible light and presents a specific color (such as yellow-green), thereby displaying the corresponding written content.
  • an erasing electrode P2 and a driving circuit for driving the erasing electrode P2 may be disposed on the array substrate AR.
  • the cover plate CF is provided with a common electrode layer (not shown in the figure); the liquid crystal layer LC is interposed between the erasing electrode P2 and the common electrode layer.
  • the electric field between the erasing electrode P2 and the common electrode layer can make the liquid crystal recover to the focal conic texture, achieving the effect of erasing written content.
  • the cover plate CF may include a flexible substrate, and the common electrode layer is disposed on a side of the flexible substrate close to the liquid crystal layer LC. In this way, when the cover plate CF is pressed, the cover plate CF can be deformed to squeeze the liquid crystal, and then the liquid crystal is transformed into a planar texture, so as to achieve the purpose of writing on the tablet.
  • the cover plate CF may also have an alignment layer located on the side (inside) of the common electrode layer away from the flexible substrate.
  • the tablet panel PNL may further include a support PS located between the array substrate AR and the cover CF, so as to maintain the thickness of the liquid crystal cell.
  • the support PS can be a silicon ball, a plastic ball, a resin ball, etc., or it can be a support PS such as a resin column or a resin boss preformed on the array substrate AR or the cover plate CF.
  • the tablet panel PNL may also include a sealant E2 located between the array substrate AR and the cover CF, and the sealant E2 may be arranged around the handwriting area AA of the tablet panel PNL to seal the liquid crystal layer LC and connect the array substrate AR to the cover plate CF.
  • the array substrate AR has a handwriting area AA and a peripheral area surrounding the handwriting area AA.
  • a writing pattern can be formed by pressing (for example, by a finger or a pen).
  • the array substrate may also be provided with an NFC coil for sending out NFC signals, and the NFC coil covers the handwriting area AA. In this way, in the handwriting area AA of the handwriting tablet of the present disclosure, each position is covered with NFC signals.
  • the NFC chip When the eraser is close to the handwriting board and the NFC chip enters the sensing range of the NFC coil, the NFC chip can receive the NFC signal, and the light source can emit light at this time to illuminate the handwriting area, and then the driving circuit of the handwriting area loads the erasing voltage to the erasing electrode , to realize the erasing of the pattern in the handwriting area.
  • the NFC chip When the eraser is far away from the tablet, the NFC chip cannot receive the NFC signal, and the light source cannot emit light at this time.
  • the eraser when it is necessary to erase the written content in a specific area A1, the eraser can be brought close to the specific area A1; when the distance between the eraser and the specific area A1 is close enough so that the NFC chip can receive the NFC signal, the eraser can be The light source above emits light and then illuminates the specific area A1, so that the driving circuit in the specific area A1 applies an erasing voltage to the erasing electrodes therein.
  • the electric field between the erasing electrode and the common electrode makes the liquid crystal in the specific area A1 transform into a focal conic texture, and then changes from a reflective state to a scattering state, so that the specific area A1 has a base color.
  • the written content in the area A1 is erased.
  • the eraser can be removed; at this time, the NFC chip in the eraser is out of the sensing range of the NFC coil, the NFC chip cannot receive the NFC signal, and the light source is turned off in time.
  • the light source can be prevented from being turned on too early, and the light source can also be prevented from being turned off too late, thereby preventing the light from the light source from erroneously irradiating other areas and preventing patterns in other areas from being erased by mistake, thereby improving the accuracy of erasing.
  • the number of NFC coils may be one or multiple, subject to being able to cover the handwriting area.
  • the number of NFC coil D1 is one, and the distribution range of NFC coils covers the handwriting area AA, so that each position of the handwriting area has an NFC signal.
  • a plurality of NFC coils D1 are arranged in the handwriting area AA.
  • the sensing range of the NFC signal sent by each NFC coil D1 covers the entire handwriting area AA.
  • the array substrate AR may include a base substrate F100 , a base color layer F200 and a driving layer F300 stacked up, wherein the base color layer F200 is disposed on a side of the driving layer F300 close to the base substrate F100 .
  • the base color layer F200 may be disposed between the driving layer F300 and the base substrate F100.
  • the base color layer F200 can be disposed on the side of the base substrate F100 away from the driving layer F300, for example, a base color film as the base color layer F200 can be attached to the back side of the base substrate F100 (away from the driving layer F300). side of the driving layer F300).
  • the base substrate F100 may be a base substrate F100 of inorganic material, or may be a base substrate F100 of organic material.
  • the material of the base substrate F100 may be glass materials such as soda-lime glass, quartz glass, sapphire glass, or may be stainless steel, aluminum, nickel, etc. metallic material.
  • the material of the substrate F100 may be polymethyl methacrylate (Polymethyl methacrylate, PMMA), polyvinyl phenol (Polyvinyl phenol, PVP), polyether sulfone (Polyether sulfone, PES), polyimide, polyamide, polyacetal, polycarbonate (Polycarbonate, PC), polyethylene terephthalate (Polyethylene terephthalate, PET), polyethylene naphthalate (Polyethylene naphthalate , PEN) or a combination thereof.
  • the base substrate F100 may also be a flexible base substrate F100, for example, the material of the base substrate F100 may be polyimide (PI).
  • the base substrate F100 can also be a composite of multi-layer materials.
  • the base substrate F100 can include a bottom film layer (Bottom Film), a pressure-sensitive adhesive layer, A first polyimide layer and a second polyimide layer.
  • the base color layer F200 can be a film layer with high absorption rate to reduce the reflection of light, so that the base color layer F200 has a dark color, such as black or dark blue. In this way, the base color of the tablet can be dark.
  • the base color layer F200 may be a black resin layer or a black plastic layer.
  • the erasing electrode P2 and the driving circuit PDC may be disposed in the driving layer.
  • the driving circuit may include a photosensitive switching element, and one end of the photosensitive switching element is electrically connected to the erasing electrode. Under illumination, the switching element can be turned on to apply an erasing voltage to the erasing electrode.
  • the switching element may be a thin film transistor, and the drains of each thin film transistor are electrically connected to each erasing electrode in a one-to-one correspondence. When the gate of the thin film transistor is loaded with a cut-off voltage, the thin film transistor is in a cut-off state.
  • the thin film transistor If no predetermined light (eg, light in a predetermined wavelength range) is irradiated to the channel region of the thin film transistor, the thin film transistor has a small leakage current in the off state. When the preset light irradiates the channel region of the thin film transistor, the leakage current of the thin film transistor will increase significantly to turn on the thin film transistor.
  • a predetermined light eg, light in a predetermined wavelength range
  • the driving layer may also be provided with gate lines GL extending along the row direction and power supply lines DL extending along the column direction.
  • the gate of the thin film transistor TFT is connected to the gate line GL
  • the drain of the thin film transistor TFT is connected to the erasing electrode P2
  • the source of the thin film transistor TFT is connected to the power line DL.
  • the tablet can also detect whether the eraser is far away from the handwriting area AA.
  • the reset voltage can be applied to the erasing electrode P2 by controlling the drive circuit PDC, and then the erasing voltage that may be loaded on the erasing electrode can be eliminated, so that the tablet is at the erasing electrode. The status can be written again.
  • the reset voltage loaded on the erasing electrode may not affect the shape of the liquid crystal.
  • the reset voltage can be consistent with the common voltage on the common electrode.
  • the NFC coil on the tablet can be used to detect whether the eraser is removed. When the eraser with the NFC chip leaves the sensing range of the NFC coil, the signal on the NFC coil will change; according to the signal change on the NFC coil, it can be determined whether the NFC coil has left.
  • the tablet can have two different working modes: display mode and reset mode.
  • the gate line can apply a cut-off voltage to the gate of the thin film transistor
  • the power line can apply a preset voltage signal to the source of the thin film transistor, such as applying a stable erasing voltage, or alternately applying an erasing voltage and reset voltage.
  • the eraser irradiates light to the handwriting area in response to the NFC signal
  • the leakage current of the irradiated thin film transistor increases, and then the preset voltage signal on the power line is loaded to the erasing electrode driven by the thin film transistor.
  • the pattern of the region on the erasing electrode can be erased.
  • the preset voltage signal is a stable erasing voltage
  • the voltage on the erasing electrode driven by the irradiated thin film transistor is the erasing voltage after the light is eliminated;
  • the preset voltage signal is When the erasing voltage and the reset voltage are applied alternately, after the light is eliminated, the voltage on the erasing electrode driven by the irradiated thin film transistor is the erasing voltage or the reset voltage.
  • the tablet When the tablet detects that the eraser is far away, for example, when it detects that the light disappears or the signal of the NFC coil changes, the tablet can enter the reset mode with a preset duration, and enter the display mode again after the reset mode.
  • the gate line In the reset mode, the gate line can load a turn-on voltage to the gate of the thin film transistor, and the power line can load a reset voltage to the source of the thin film transistor.
  • the reset voltage can be applied to the erasing electrode in the reset mode, and the reset voltage can be maintained to enter the display mode.
  • the handwriting tablet enters the display mode again, patterns can be written everywhere in the handwriting area.
  • each erasing electrode can be reset at the same time, or each erasing electrode can be reset row by row in a row-by-row scanning manner, which is not limited in the present disclosure.
  • the driving circuit as an example of a thin film transistor, the structure of the driving layer is exemplarily introduced and illustrated. It can be understood that this example is only one possible manner of the driving layer of the present disclosure, and the driving layer of the present disclosure may also adopt other feasible manners to control the erasing electrodes.
  • the driving layer may include a transistor layer and an erasing electrode layer stacked; wherein the transistor layer is located between the erasing electrode layer and the base substrate.
  • the erasing electrodes are arranged on the erasing electrode layer, and the transistor layer has thin film transistors electrically connected to each erasing electrode in one-to-one correspondence.
  • the thin film transistor can be selected from a top gate thin film transistor, a bottom gate thin film transistor or a double gate thin film transistor; the material of the active layer of the thin film transistor can be amorphous silicon semiconductor material, low temperature polysilicon semiconductor material, metal oxide semiconductor material, Organic semiconductor materials or other types of semiconductor materials; the thin film transistors may be N-type thin film transistors or P-type thin film transistors.
  • a transistor can have a source, a drain and a gate. It can be understood that the source and the drain of the transistor are two opposite concepts that can be interchanged; when the working state of the transistor changes, for example, the direction of the current changes, the source and the drain of the transistor can be interchanged.
  • the transistor layer may include a gate layer F301, a gate insulating layer F302, a semiconductor layer F303, and a source-drain metal layer stacked between the ground color layer F200 and the erasing electrode layer F306. F304 etc.
  • the positional relationship of each film layer can be determined according to the film layer structure of the thin film transistor.
  • the active layer of the thin film transistor may be formed on the semiconductor layer F303.
  • the gate layer wiring such as the gate line GL and the gate of the thin film transistor can be formed on the gate layer F301 .
  • the source-drain metal layer traces such as the power line DL can be formed on the source-drain metal layer F304.
  • the driving layer F300 may further include a passivation layer F305, and the passivation layer F305 may be disposed on the surface of the source-drain metal layer F304 away from the substrate F100 to protect the source-drain metal layer F304.
  • the structural layer A is located on the side of the structural layer B away from the base substrate. It can be understood that the structural layer A is formed on the side of the structural layer B away from the base substrate.
  • part of the structure of the structural layer A may also be located at the same physical height of the structural layer B or lower than the physical height of the structural layer B, wherein the base substrate is the height reference.
  • the driving layer F300 may further include a planarization layer located between the source-drain metal layer F304 and the erasing electrode layer F306, and the planarization layer may provide a planarized surface for the erasing electrode P2.
  • the material of the planarization layer may be an organic material.
  • the driving layer F300 may further include an interlayer dielectric layer, the interlayer dielectric layer is located on the side of the semiconductor layer, the gate layer and other film layers away from the substrate, and the source-drain metal layer F304 is located The side of the inter-dielectric layer away from the base substrate.
  • the driving layer F300 may include a gate layer F301, a gate insulating layer 302, a semiconductor layer F303, a source-drain metal layer F304, a passivation layer F305 and an eraser layer. Electrode layer F306.
  • the thin film transistor thus formed is a bottom gate thin film transistor.
  • the material of the erasing electrode layer F306 may be a light-transmitting material, that is, the erasing electrode P2 may be a transparent electrode. In this way, the reflection of the erasing electrode can be reduced, which is beneficial to the clear display of patterns.
  • the material of the erasing electrode layer may be a metal oxide, such as ITO (indium tin oxide).
  • the NFC coil can be integrated in the driving layer, or a sensing layer with the NFC coil can be provided on the side of the driving layer close to the base substrate.
  • a sensing layer F400 with an NFC coil is provided on a side of the base substrate F100 away from the driving layer F300, or a sensing layer with an NFC coil is provided between the base substrate and the driving layer.
  • an anti-reflection layer F500 may also be disposed on the side of the sensing layer F400 away from the ground color layer F200 , to reduce the reflection of the NFC coil and improve the display effect of the tablet.
  • the NFC coil D1 may be disposed in the driving layer F300.
  • the NFC coil D1 and the driving layer F300 can share a metal layer, especially can be produced in a common process.
  • the driving layer F300 is provided with an erasing electrode P2 and a thin film transistor TFT (as a driving circuit) for driving the erasing electrode P2; wherein, the driving layer F300 has a gate layer F301 and the source-drain metal layer F304.
  • the gate line GL connected to the thin film transistor TFT may be provided on the gate layer F301 and extend in the row direction, and the power line DL connected to the thin film transistor TFT may be provided in the SD and extend in the column direction.
  • the NFC coil D1 may be composed of a plurality of sub-electrodes P1, some of the sub-electrodes are disposed on the gate layer F301 and/or some of the electrodes are disposed on the source-drain metal layer F304. In one example, part of the sub-electrodes (such as P11 in FIG. 4 ) are disposed on the gate layer F301 , and part of the electrodes (such as P12 in FIG. 4 ) are disposed on the source-drain metal layer F304 . In this way, the NFC coil D1 can be connected between the gate layer F301 and the source-drain metal layer F304, and the wiring can be performed without affecting the gate line GL and the power line DL.
  • the NFC coil D1 may not overlap the erasing electrodes P2 , that is, it may be arranged in a gap between the erasing electrodes P2 , so as to avoid signal shielding of the NFC coil by the erasing electrodes. That is, the sub-electrodes P1 may be disposed between the erasing electrodes P2; the orthographic projection of the sub-electrodes P1 on the base substrate is located between the orthographic projections of the erasing electrodes P2 on the base substrate.
  • structure A and structure B overlap, it means that structure A and structure B are located in different film layers, and the orthographic projection of structure A on the substrate is the same as that of structure B on the substrate.
  • the orthographic projections are at least partially coincident.
  • the sub-electrodes P1 include a row sub-electrode P11 extending along the row direction and a column sub-electrode P12 extending along the column direction; wherein the row sub-electrode P11 is located in the gate layer F301, and the column sub-electrode P12 is located in the source-drain metal layer .
  • the row sub-electrodes P11 and the column sub-electrodes P12 are connected through via holes.
  • the array substrate AR may further include a sensing layer F400 for setting the NFC coil D1 .
  • the sensing layer F400 is provided with one conductive layer or multiple conductive layers, and the wiring of the NFC coil D1 can be formed through these conductive layers.
  • the sensing layer F400 can be disposed on the side of the base substrate F100 away from the base color layer F200, or between the base substrate F100 and the base color layer F200, or between the driving layer F300 and the base color layer F200.
  • an anti-reflection layer F500 may also be provided on the side of the sensing layer F400 close to the driving layer F300 to reduce the reflectivity of the NFC coil D1 in the sensing layer F400, thereby improving the display effect. .
  • an anti-reflection layer F500 anti-reflection film
  • a sensing layer F400 NFC patch
  • the sensing layer F400 Can be a film with NFC coil D1.
  • the NFC coil D1 can use either hollow-out wiring or non-hollow-out wiring.
  • the wiring of the NFC coil D1 is a non-hollow wiring.
  • the width of the wiring in the NFC coil D1 may be greater than the gap between the erasing electrodes P2 .
  • the wiring of the NFC coil D1 may at least partially overlap with the erasing electrode P2. Since the NFC coil D1 is located below the drive layer F300 (near the side of the base substrate F100), the routing of the NFC coil D1 has a larger area, overlaps with the erasing electrode P2, etc., and will not affect the erasing electrode. P2 interferes.
  • the width of the NFC coil D1 is greater than the size of the erasing electrode P2 .
  • the width of the wiring of the NFC coil D1 is greater than the width of the gap of the erasing electrode P2 and not greater than the width of the erasing electrode P2 .
  • the orthographic projections of the wiring of the NFC coil on the base substrate overlap each other; the overlapping position of the orthographic projection of the wiring of the NFC coil is located at In addition to the orthographic projection of the electrode on the base substrate; the overlapping position of the orthographic projection of the wiring of the NFC coil is bridged through the driving layer.
  • the NFC coil D1 includes at least one turn of wiring.
  • the overlapping position of the wiring of the NFC coil D1 overlaps with the erasing electrode P2; at the overlapping position of the wiring of the NFC coil D1, the wiring of the NFC coil D1 is bridged through the driving layer F300.
  • the sensing layer F400 may also include multiple conductive layers, and the wiring of the NFC coil D1 is bridged between the multiple conductive layers of the sensing layer F400.
  • the patterns of the respective NFC coils D1 may not be exactly the same, for example, the number of turns, width, and wire length of the NFC coils D1 may be different.
  • the sensing distance of each NFC coil D1 can be made the same or substantially the same by adjusting the pattern of the NFC coil D1.
  • the sensing distance of the NFC coil D1 is not more than 10 cm, for example not more than 5 cm, especially between 0 and 3 cm to ensure the safety of the eraser.
  • the control module CTR may include a circuit distribution structure C1 and a control unit C2.
  • the circuit distribution structure C1 is electrically connected to the driving circuit and the NFC chip, and is electrically connected to the control unit, so that the control unit C2 interacts with the driving circuit and the NFC chip.
  • the circuit distribution structure may include a circuit board or a flexible circuit board, or may be a flexible film provided with traces.
  • the control unit can control the NFC coil D1 to send the NFC signal or detect the change of the NFC signal, and can also be used to control the working state of the driving circuit.
  • control unit can also perform other functions according to the functional requirements of the tablet, such as one-key clearing, screen saving, etc., which is not specifically limited in the present disclosure.
  • the control unit may include a printed circuit board, a chip, a single-chip microcomputer, a microprocessor or other circuits capable of realizing control functions connected to the circuit distribution structure.
  • the eraser provided by the present disclosure is provided with at least one erasing unit UU; the erasing unit UU includes a light source UL and an NFC chip US.
  • the light source UL emits light, it can emit preset light with a preset wavelength and intensity, and the spectral range and intensity of the preset light can be determined according to the characteristics of the driving circuit.
  • the erasing unit UU further includes a control circuit UC; the control circuit UC is electrically connected to the NFC chip US and the light source UL.
  • the control circuit is configured to control the light source UL to emit light when the NFC chip US senses an NFC signal; and to control the light source UL not to emit light when the NFC chip US does not sense an NFC signal.
  • the NFC chip US is configured to output a continuous activation signal to the control circuit UC when an NFC signal is sensed until no NFC signal is sensed.
  • the control circuit UC is configured to apply a power supply voltage to the light source UL to make the light source emit light when the NFC chip US outputs a start signal; and not apply a power supply voltage to the light source UL so that the light source UL does not emit light when the NFC chip US does not output a start signal.
  • the NFC chip US is configured to output a pulse-type start signal to the control circuit UC when the NFC signal is sensed; When detected, a pulse-shaped closing signal is output to the control circuit.
  • a pulse-shaped closing signal is output to the control circuit.
  • the control circuit is configured to continuously load the power supply voltage to the light source UL after receiving the start signal to make the power supply emit light until the shutdown signal is received.
  • the eraser includes a plurality of erasing areas, and each erasing area is provided with an erasing unit UU.
  • the NFC chip US of the erasing unit UU senses the NFC signal
  • the light source UL of the erasing unit UU emits light;
  • the light source UL emits light.
  • NFC chips US can be arranged overlapping each other, or can be arranged adjacent to each other, so as to ensure the timely and accurate light emission of the light source UL.
  • One or more NFC chips US can be set in the erasing unit UU, and one or more light sources UL can also be set. It can be understood that the light emitted by the light source UL can be directly irradiated to the tablet, or can be irradiated to the tablet through a light guide plate, a light guide strip, or the like.
  • the light source UL may be an LED (Light Emitting Diode).
  • the erasing unit UU includes a plurality of LEDs as light sources UL, and each LED is uniformly distributed in the erasing area.
  • the light source UL of the erasing unit UU includes an LED disposed at a local position of the erasing area, and the LED emits light uniformly from the erasing area through the light guide plate.
  • the eraser has at least one erasing surface, and one or more erasing units UU can be arranged on the erasing surface.
  • the erasing unit UU on the erasing surface can emit light in response to the NFC signal, so as to realize the erasing of a local area of the handwriting pad.
  • the blackboard eraser can be strip-shaped as a whole, and it includes a front side 201 for erasing patterns on the handwriting board toward the handwriting board, a back side opposite to the front side 201, and a Four sides 202 between 201 and the back.
  • the front side 201 of the eraser can be provided with an erasing unit UU, and when the erasing unit UU emits light, it can have a larger light-emitting area, for example, the light-emitting range covers the entire front side 201 . In this way, the front side 201 of the eraser can be used for efficiently erasing large-area patterns and improving erasing efficiency.
  • At least one side 202 of the eraser is provided with an erasing unit UU, the erasing unit UU has a small light-emitting area, so it is particularly suitable for erasing patterns in small areas , such as erasing specific text or characters.
  • each side 202 of the eraser is respectively provided with an erasing unit UU, so as to further improve the convenience of use.
  • any side 202 there may be one or more erasing units UU.
  • at least one side of the eraser is provided with a plurality of erasing units UU, so that each erasing unit UU has a smaller luminous range, improving the accuracy of erasing.
  • a chamfer 203 is provided between the front 201 and the side 202 of the eraser, and an erasing unit UU may be provided on the chamfer 203 .
  • the eraser can perform pattern erasing in an inclined state, so that the usage habits and effects of the eraser are closer to those of the chalk eraser, and the use experience and erasing efficiency are improved.
  • the eraser includes a body 101 and a handle 102 .
  • the surface of the main body 101 away from the grip portion 102 can be used as the front surface 201 of the eraser; the erasing unit UU can be disposed on the main body 101 .
  • the eraser further includes a power supply module UE to provide power to the erasing unit UU.
  • the power module UE is a rechargeable battery and is provided with a charging port.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Theoretical Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Optics & Photonics (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Human Computer Interaction (AREA)
  • Drawing Aids And Blackboards (AREA)
  • Position Input By Displaying (AREA)

Abstract

本公开提供一种阵列基板、手写板、板擦、手写板系统及图案擦除方法，属于显示技术领域。该阵列基板(AR)具有手写区(AA)和围绕所述手写区(AA)的外围区；所述阵列基板(AR)包括阵列设置的擦除电极(P2)和驱动所述擦除电极(P2)的驱动电路(PDC)；所述驱动电路(PDC)被配置为，在预设光的照射下向所述擦除电极(P2)加载擦除电压；所述阵列基板(AR)还设置有用于发出NFC信号的NFC线圈(D1)，所述NFC线圈(D1)的感应范围覆盖所述手写区(AA)。该阵列基板能够提高板擦的擦除精度并保护人眼。

Description

阵列基板、手写板、板擦、手写板系统及图案擦除方法 技术领域
本公开涉及显示技术领域，具体而言，涉及一种阵列基板、手写板、板擦、手写板系统及图案擦除方法。
背景技术
液晶手写板可以配合板擦使用，以实现局部擦除功能。板擦上设置有光源，以照射手写板待擦除的部位；在光源的照射下，被照射部分的图案将被擦除。然而，当前板擦的光源开启和关闭的时机不精准，这导致擦除范围不精准，而且容易误照人眼。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
公开内容
本公开的目的在于克服上述现有技术的不足，提供一种阵列基板、手写板、板擦、手写板系统及图案擦除方法，提高擦除精度并保护人眼。
根据本公开的第一个方面，提供一种阵列基板，具有手写区和围绕所述手写区的外围区；所述阵列基板包括阵列设置的擦除电极和驱动所述擦除电极的驱动电路；所述驱动电路被配置为，在预设光的照射下向所述擦除电极加载擦除电压；
所述阵列基板还设置有用于发出NFC(近场通信)信号的NFC线圈，所述NFC线圈的感应范围覆盖所述手写区。
根据本公开的一种实施方式，所述NFC线圈的感应距离不大于10cm。
根据本公开的一种实施方式，所述阵列基板包括层叠设置的衬底基板和驱动层；所述擦除电极和驱动电路设置于所述驱动层。
根据本公开的一种实施方式，所述驱动层设置有沿行方向延伸的栅极线和沿列方向延伸的电源线；
所述驱动电路包括薄膜晶体管；所述薄膜晶体管的源极与所述电源线 电连接，所述薄膜晶体管的栅极与所述栅极线电连接，所述薄膜晶体管的漏极与对应的所述擦除电极电连接。
根据本公开的一种实施方式，所述NFC线圈设置于所述驱动层，且所述NFC线圈由多个子电极组成；所述子电极在所述衬底基板上的正投影，位于所述擦除电极在所述衬底基板上的正投影之间。
根据本公开的一种实施方式，所述驱动层包括设置有所述栅极线的栅极层和设置有所述电源线的源漏金属层；
部分所述子电极设置于所述栅极层和/或部分所述子电极设置于所述源漏金属层。
根据本公开的一种实施方式，所述子电极包括沿所述行方向延伸的行子电极和沿所述列方向延伸的列子电极；
所述行子电极位于所述栅极层；所述列子电极位于所述源漏金属层。
根据本公开的一种实施方式，所述阵列基板还包括感测层，所述NFC线圈位于所述感测层内；所述感测层位于所述驱动层靠近所述衬底基板的一侧。
根据本公开的一种实施方式，所述阵列基板还包括底色层和抗反射层；
所述抗反射层位于所述感测层靠近所述驱动层的一侧；
所述底色层位于所述感测层远离所述驱动层的一侧。
根据本公开的一种实施方式，所述NFC线圈的走线与所述擦除电极至少部分交叠。
根据本公开的第二个方面，提供一种手写板，包括依次层叠设置的盖板、液晶层和上述的阵列基板。
根据本公开的一种实施方式，所述盖板设置有公共电极层。
根据本公开的第三个方面，提供一种板擦，设置有至少一个擦除单元；所述擦除单元包括光源和NFC芯片；
所述擦除单元被配置为：在所述NFC芯片感测到NFC信号时，所述光源发出预设光；在所述NFC芯片感测不到NFC信号时，所述光源不发光。
根据本公开的一种实施方式，所述擦除单元还包括控制电路，所述控制电路与所述NFC芯片和所述光源电连接；
所述控制电路被配置为：在接收到所述NFC芯片响应所述NFC信号而产生的启动信号后，驱动所述光源发光；在接收不到所述启动信号时，不驱动所述光源发光。
根据本公开的一种实施方式，所述擦除单元中的NFC芯片与所述光源交叠设置，或者相邻设置。
根据本公开的一种实施方式，所述板擦包括相对设置的正面和背面，以及包括正面和背面之间的多个侧面；
所述板擦的正面设置有至少一个所述擦除单元。
根据本公开的一种实施方式，至少一个所述侧面设置有至少一个所述擦除单元。
根据本公开的一种实施方式，所述板擦在所述正面和所述侧面之间设置有倒角；所述倒角处设置有至少一个所述擦除单元。
根据本公开的第四个方面，提供一种手写板系统，包括上述的手写板和上述的板擦。
根据本公开的第五个方面，提供一种图案擦除方法，应用于上述的手写板系统；所述图案擦除方法包括：
所述手写板的NFC线圈发出NFC信号；
当所述板擦的NFC芯片感测到所述NFC信号时，所述板擦的光源发出预设光；当所述板擦的NFC芯片感测不到所述NFC信号时，所述板擦的光源不发光；
当所述手写板的驱动电路被所述预设光照射时，向所述手写板的擦除电极加载擦除电压。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他 的附图。
图1为本公开一种实施方式中手写板系统的原理示意图。
图2为本公开一种实施方式中手写板的结构示意图。
图3为本公开一种实施方式中手写板的结构示意图。
图4为本公开一种实施方式中阵列基板的结构示意图。
图5为本公开一种实施方式中阵列基板的结构示意图。
图6为本公开一种实施方式中，在手写板上书写图案的示意图。
图7为本公开一种实施方式中，在手写板上擦除局部图案的示意图。
图8为本公开一种实施方式中，NFC线圈的分布示意图。
图9为本公开一种实施方式中，NFC线圈的分布示意图。
图10为本公开一种实施方式中，NFC线圈的分布示意图。
图11为本公开一种实施方式中，NFC线圈的分布示意图。
图12为本公开一种实施方式中，NFC线圈的分布示意图。
图13为本公开一种实施方式中，NFC线圈的分布示意图。
图14为本公开一种实施方式中，板擦的结构示意图。
图15为本公开一种实施方式中，板擦的结构示意图。
图16为本公开一种实施方式中，板擦的结构示意图。
图17为本公开一种实施方式中，擦除单元的结构示意图。
图18为本公开一种实施方式中，擦除单元的结构示意图。
图19为本公开一种实施方式中，擦除单元的结构示意图。
图20为本公开一种实施方式中，图案擦除方法的流程示意图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“该”、“所述”和“至少一个”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”、“第二”和“第三”等仅作为标记使用，不是对其对象的数量限制。
本公开提供一种手写板系统及图案擦除方法。参见图1，该手写板系统包括手写板和板擦。手写板具有手写区，手写区内设置有用于发射NFC信号的NFC线圈D1，以及设置有阵列分布的擦除电极P2和驱动擦除电极的驱动电路PDC。驱动电路被配置为，在预设光的照射下向所述擦除电极加载擦除电压。当擦除电极加载有擦除电压时，该擦除电极位置处的图案将被擦除。板擦设置有至少一个擦除单元UU，每个擦除单元包括NFC芯片US和光源UL。所述擦除单元被配置为：在所述NFC芯片感测到NFC信号时，所述光源发出预设光；在所述NFC芯片感测不到NFC信号时，所述光源不发光。
该手写板系统可以应用步骤S110～S130所示的图案擦除方法来擦除手写板局部区域的图案。
步骤S110，所述手写板的NFC线圈发出NFC信号；
步骤S120，当所述板擦的NFC芯片感测到所述NFC信号时，所述板擦的光源发出预设光；当所述板擦的NFC芯片感测不到所述NFC信号时，所述板擦的光源不发光；
步骤S130，当所述手写板的驱动电路被所述预设光照射时，向所述手写板的擦除电极加载擦除电压。
这样，当板擦靠近手写板而进入NFC线圈的感应范围时，该板擦中 的NFC芯片可以感测到NFC信号，进而使得光源发光以擦除手写板上的图案。当板擦远离手写板而脱离NFC线圈的感应范围时，该板擦中的NFC芯片不可以感测到NFC信号，进而使得光源不发光。这样，可以使得板擦的光源及时关闭，一方面可以降低板擦的功耗，另一方面可以避免光源关闭不及时而照射用户的眼睛，同时达成降低功耗和提高安全性的目的。不仅如此，由于板擦在靠近手写板时发光且在远离手写板后及时关闭电源，因此可以避免板擦在距离手写板较远时发光而导致手写板上的图案被误擦除，提高图案擦除的精准性。
参见图2和图3，本公开的手写板可以包括手写板面板PNL和用于控制手写板面板PNL的控制模块CTR。手写板面板PNL可以包括依次层叠设置的阵列基板AR、液晶层LC和盖板CF。
在一些实施方式中，液晶层LC中的液晶可以为具有双稳态特性的液晶，尤其是可以为双稳态胆甾相液晶。在非书写状态下，胆甾相液晶呈现焦锥织构，对环境光弱散射，使得手写板呈现基底色(例如深色)。当使用书写笔或铅笔等书写时，压力使胆甾相液晶由焦锥织构转变为平面织构，选择性反射可见光，呈现特定的颜色(例如黄绿色)，从而显示对应的书写内容。
参见图4和图5，阵列基板AR上可以设置有擦除电极P2和驱动擦除电极P2的驱动电路。盖板CF设置有公共电极层(图中未示出)；液晶层LC夹设于擦除电极P2与公共电极层之间。当在擦除电极P2和公共电极层之间加载擦除电压时，擦除电极P2和公共电极层之间的电场可以使得液晶恢复至焦锥织构，达成擦除书写内容的效果。
在一些实施方式中，盖板CF可以包括柔性基底，公共电极层设置于柔性基底靠近液晶层LC的一侧。如此，当按压盖板CF时，盖板CF可以形变以挤压液晶，进而使得液晶转变为平面织构，达成在手写板上书写的目的。
在一些实施方式中，盖板CF还可以具有位于公共电极层远离柔性基底一侧(内侧)的取向层。
在一些实施方式中，手写板面板PNL还可以包括位于阵列基板AR和盖板CF之间的支撑物PS，以利于维持液晶盒厚度。该支撑物PS可以 为硅球、塑料球、树脂球等，也可以为预先形成于阵列基板AR或者盖板CF上的树脂柱、树脂凸台等支撑物PS。
参见图2和图3，手写板面板PNL还可以包括位于阵列基板AR和盖板CF之间的封框胶E2，该封框胶E2可以围绕手写板面板PNL的手写区AA设置，以封闭液晶层LC并使得阵列基板AR与盖板CF连接。
参见图8和图9，阵列基板AR具有手写区AA和围绕手写区AA的外围区，在手写区AA内，可以通过按压(例如通过手指或者笔等)形成书写图案。阵列基板还可以设置有用于发出NFC信号的NFC线圈，所述NFC线圈覆盖所述手写区AA。这样，在本公开的手写板的手写区AA，各个位置处均覆盖有NFC信号。当板擦靠近手写板而使得NFC芯片进入NFC线圈的感应范围时，NFC芯片可以接收到NFC信号，光源此时可以发光以照射手写区，进而使得手写区的驱动电路向擦除电极加载擦除电压，实现对手写区中图案的擦除。当板擦远离手写板时，NFC芯片无法接收NFC信号，光源此时无法发光。
参见图6，当用户需要在手写板上书写内容时，可以通过手指、书写笔等按压手写板；手写板被按压的区域中液晶转变为平面织构，进而反射特定的颜色，形成书写笔记，进而呈现书写内容PA。
参见图6和图7，当需要擦除特定区域A1的书写内容时，可以将板擦靠近该特定区域A1；当板擦与特定区域A1的距离足够近以使得NFC芯片可以接收到NFC信号时，板擦上的光源发光进而照射特定区域A1，使得特定区域A1中的驱动电路向其中的擦除电极加载擦除电压。特定区域A1中，擦除电极与公共电极之间的电场使得特定区域A1中的液晶转变为焦锥织构，进而使得由反射状态变为散射状态，使得该特定区域A1呈基底色，该特定区域A1中的书写内容被擦除。当擦除完待擦除的图案后，可以拿开板擦；此时板擦中的NFC芯片脱离NFC线圈的感应范围，NFC芯片无法接受NFC信号，进而使得光源及时关闭。这样，可以避免光源过早打开，也可以避免光源过晚关闭，进而可以避免光源的光线误照射至其他区域，避免其他区域的图案被误擦除，进而提高擦除的准确性。
在本公开中，NFC线圈的数量可以为一个，也可以为多个，以能够覆盖手写区为准。
举例而言，在本公开的一种实施方式中，参见图8，NFC线圈D1的数量为一个，NFC线圈的分布范围覆盖手写区AA，以使得手写区的各个位置均具有NFC信号。
再举例而言，在本公开的另一种实施方式中，参见图9，手写区AA内设置有多个NFC线圈D1。各个NFC线圈D1所发送的NFC信号的感应范围覆盖整个手写区AA。
参见图4和图5，阵列基板AR可以包括层叠设置的衬底基板F100、底色层F200和驱动层F300，其中，底色层F200设置于驱动层F300靠近衬底基板F100的一侧。在一些实施方式中，底色层F200可以设置于驱动层F300和衬底基板F100之间。在另外一些实施方式中，底色层F200可以设置于衬底基板F100远离驱动层F300的一侧，例如可以将一作为底色层F200的底色膜贴附于衬底基板F100的背面(远离驱动层F300的一侧)。
衬底基板F100可以为无机材料的衬底基板F100，也可以为有机材料的衬底基板F100。举例而言，在本公开的一种实施方式中，衬底基板F100的材料可以为钠钙玻璃(soda-lime glass)、石英玻璃、蓝宝石玻璃等玻璃材料，或者可以为不锈钢、铝、镍等金属材料。在本公开的另一种实施方式中，衬底基板F100的材料可以为聚甲基丙烯酸甲酯(Polymethyl methacrylate，PMMA)、聚乙烯基苯酚(Polyvinyl phenol，PVP)、聚醚砜(Polyether sulfone，PES)、聚酰亚胺、聚酰胺、聚缩醛、聚碳酸酯(Poly carbonate，PC)、聚对苯二甲酸乙二酯(Polyethylene terephthalate，PET)、聚萘二甲酸乙二酯(Polyethylene naphthalate，PEN)或其组合。在本公开的另一种实施方式中，衬底基板F100也可以为柔性衬底基板F100，例如衬底基板F100的材料可以为聚酰亚胺(polyimide，PI)。衬底基板F100还可以为多层材料的复合，举例而言，在本公开的一种实施方式中，衬底基板F100可以包括依次层叠设置的底膜层(Bottom Film)、压敏胶层、第一聚酰亚胺层和第二聚酰亚胺层。
在一些实施方式中，底色层F200可以为具有高吸收率的膜层，以降低对光线的反射，进而使得底色层F200呈深色，例如呈黑色或者深蓝色。这样，手写板的基底色可以为深色。示例性地，底色层F200可以为黑色树脂层或者黑色塑料层。
在本公开中，擦除电极P2和驱动电路PDC可以设置于驱动层中。本公开的一些实施方式中，驱动电路可以包括光敏的开关元件，光敏的开关元件的一端与擦除电极电连接。在光照下，开关元件可以导通以向擦除电极加载擦除电压。在本公开的一种实施方式中，开关元件可以为薄膜晶体管，各个薄膜晶体管的漏极与各个擦除电极一一对应的电连接。当薄膜晶体管的栅极加载截止电压时，薄膜晶体管呈截止状态。如果没有预设光(例如预设波长范围的光线)照射至薄膜晶体管的沟道区，则该薄膜晶体管在截止状态下具有较小的漏电流。当预设光照射至薄膜晶体管的沟道区时，薄膜晶体管的漏电流将显著增大至薄膜晶体管导通。
参见图4和图5、图10，驱动层还可以设置有沿行方向延伸的栅极线GL和沿列方向延伸的电源线DL。薄膜晶体管TFT的栅极与栅极线GL连接，薄膜晶体管TFT的漏极与擦除电极P2连接，薄膜晶体管TFT的源极与电源线DL连接。当薄膜晶体管处于截止状态时，如果薄膜晶体管的沟道区没有受到光照(预设光)，则其具有较小的漏电流，这使得擦除电极上的电压可以较好的维持，擦除电压不能够加载至擦除电极上。当光照射至薄膜晶体管的沟道区时，薄膜晶体管的漏电流急剧增大，这使得擦除电压可以通过薄膜晶体管加载至擦除电极上。
在本公开的一些实施方式中，手写板还可以检测板擦是否远离手写区AA。当手写板检测到板擦远离手写区时，可以通过控制驱动电路PDC向擦除电极P2加载复位电压，进而将擦除电极上可能加载的擦除电压消除，使得手写板在该擦除电极处处于可再次书写状态。其中，擦除电极上加载的复位电压，可以不对液晶的形态产生影响。作为一种示例，该复位电压可以与公共电极上的公共电压保持一致。在本公开的一种实施方式中，手写板上的NFC线圈可以用于检测板擦是否离开。当具有NFC芯片的板擦离开NFC线圈的感应范围时，NFC线圈上的信号会发生变化；根据NFC线圈上的信号变化，可以确定NFC线圈是否离开。
举例而言，在本公开的一种实施方式中，手写板可以具有显示模式和复位模式两种不同的工作模式。在显示模式下，栅极线可以向薄膜晶体管的栅极加载截止电压，电源线可以向薄膜晶体管的源极加载预设的电压信号，例如加载稳定的擦除电压，亦或交替加载擦除电压和复位电压。当板 擦响应NFC信号而向手写区照射光线时，被照射的薄膜晶体管的漏电流增大，进而使得电源线上的预设的电压信号加载至该薄膜晶体管所驱动的擦除电极。在向擦除电极加载电压的过程中，只要擦除电压曾经被加载至擦除电极，则就可以使得该擦除电极上的区域的图案被消除。可以理解的是，当预设的电压信号为稳定的擦除电压时，在光照消除后，被照射的薄膜晶体管所驱动的擦除电极上的电压为擦除电压；当预设的电压信号为交替加载的擦除电压和复位电压时，在光照消除后，被照射的薄膜晶体管所驱动的擦除电极上的电压为擦除电压或者复位电压。当手写板检测到板擦远离时，例如检测到光照消失或者NFC线圈的信号变化时，手写板可以进入预设时长的复位模式，并在复位模式后再次进入显示模式。在复位模式下，栅极线可以向薄膜晶体管的栅极加载导通电压，电源线可以向薄膜晶体管的源极加载复位电压。这样，可以使得擦除电极在复位模式下加载复位电压，并保持复位电压以进入显示模式。这样，当手写板再次进入显示模式时，手写区的各处可以再次书写图案。可以理解的是，在复位模式下，可以使得各个擦除电极同时复位，也可以通过逐行扫描的方式使得各个擦除电极逐行复位，本公开对此不做限定。
如下，以驱动电路为薄膜晶体管为例，对驱动层的结构做示例性地介绍和说明。可以理解的是，该示例仅仅为本公开的驱动层的一种可行方式，本公开的驱动层也可以采用其他可行方式实现对擦除电极的控制。
在该示例中，驱动层可以包括层叠设置的晶体管层和擦除电极层；其中，晶体管层位于擦除电极层和衬底基板之间。擦除电极设置于擦除电极层，且晶体管层具有与各个擦除电极一一对应电连接的薄膜晶体管。薄膜晶体管可以选自顶栅型薄膜晶体管、底栅型薄膜晶体管或者双栅型薄膜晶体管；薄膜晶体管的有源层的材料可以为非晶硅半导体材料、低温多晶硅半导体材料、金属氧化物半导体材料、有机半导体材料或者其他类型的半导体材料；薄膜晶体管可以为N型薄膜晶体管或者P型薄膜晶体管。晶体管可以具有源极、漏极和栅极。可以理解的是，晶体管的源极和漏极为两个相对且可以相互转换的概念；当晶体管的工作状态改变时，例如电流方向改变时，晶体管的源极和漏极可以互换。
在该示例中，参见图4和图5，晶体管层可以包括层叠于底色层F200 和擦除电极层F306之间的栅极层F301、栅极绝缘层F302、半导体层F303和源漏金属层F304等。各个膜层的位置关系可以根据薄膜晶体管的膜层结构确定。进一步地，薄膜晶体管的有源层可以形成于半导体层F303。栅极线GL等栅极层走线和薄膜晶体管的栅极可以形成于栅极层F301。电源线DL等源漏金属层走线可以形成于源漏金属层F304。
在本公开的一种实施方式中，驱动层F300还可以包括有钝化层F305，钝化层F305可以设于源漏金属层F304远离衬底基板F100的表面，以便保护源漏金属层F304。
在本公开中，结构层A位于结构层B远离衬底基板的一侧，可以理解为，结构层A在结构层B背离衬底基板的一侧形成。当结构层B为图案化结构时，结构层A的部分结构也可以位于结构层B的同一物理高度或低于结构层B的物理高度，其中，衬底基板为高度基准。
在本公开的一种实施方式中，驱动层F300还可以包括位于源漏金属层F304和擦除电极层F306之间的平坦化层，平坦化层可以为擦除电极P2提供平坦化表面。可选地，平坦化层的材料可以为有机材料。
在本公开的一种实施方式中，驱动层F300还可以包括层间电介质层，层间电介质层位于半导体层、栅极层等膜层远离衬底基板的一侧，源漏金属层F304位于层间电介质层远离衬底基板的一侧。
举例而言，在一种示例中，参见图4和图5，驱动层F300可以包括栅极层F301、栅极绝缘层302、半导体层F303、源漏金属层F304、钝化层F305和擦除电极层F306。如此所形成的薄膜晶体管为底栅型薄膜晶体管。
在本公开的一种实施方式中，擦除电极层F306的材料可以为透光材料，即擦除电极P2可以为透明电极。这样，可以减小擦除电极的反光，利于图案的清晰显示。在本公开的一些实施方式中，擦除电极层的材料可以为金属氧化物，例如可以为ITO(氧化铟锡)。
在本公开提供的阵列基板中，NFC线圈可以集成于驱动层中，也可以在驱动层靠近衬底基板的一侧设置具有NFC线圈的感测层。例如在衬底基板F100远离驱动层F300的一侧设置具有NFC线圈的感测层F400，或者在衬底基板与驱动层之间设置具有NFC线圈的感测层。在本公开的一 种实施方式中，当感测层F400设置于底色层F200靠近驱动层F300的一侧时，还可以在感测层F400远离底色层F200的一侧设置抗反射层F500，以降低NFC线圈的反射，提高手写板的显示效果。
在本公开的一些实施方式中，NFC线圈D1可以设置于驱动层F300中。换言之，NFC线圈D1可以与驱动层F300共用金属层，尤其是可以在共同工序中进行制备。
在本公开的一种实施方式中，参见图4，驱动层F300中设置有擦除电极P2和驱动擦除电极P2的薄膜晶体管TFT(作为驱动电路)；其中，驱动层F300具有栅极层F301和源漏金属层F304。与薄膜晶体管TFT连接的栅极线GL可以设置于栅极层F301且沿行方向延伸，与薄膜晶体管TFT连接的电源线DL可以设置于SD且沿列方向延伸。其中，NFC线圈D1可以由多个子电极P1组成，部分子电极设置于栅极层F301和/或部分电极设置于源漏金属层F304。在一种示例中，部分子电极(例如图4中的P11)设置于栅极层F301，且部分电极(例如图4中的P12)设置于源漏金属层F304。如此，NFC线圈D1可以在栅极层F301和源漏金属层F304之间跨接，在不影响栅极线GL和电源线DL的情况下进行走线。
进一步地，参见图11，NFC线圈D1还可以不与擦除电极P2交叠，即设置于擦除电极P2之间的间隙中，以避免擦除电极对NFC线圈的信号屏蔽。即，子电极P1可以设置于擦除电极P2之间；子电极P1在衬底基板上的正投影，位于擦除电极P2在衬底基板上的正投影之间。在本公开中，当描述结构A和结构B交叠时，指的是结构A和结构B位于不同的膜层，且结构A在衬底基板上的正投影与结构B在衬底基板上的正投影至少部分重合。
示例性地，参见图11，子电极P1包括沿行方向延伸的行子电极P11和沿列方向延伸的列子电极P12；其中行子电极P11位于栅极层F301，列子电极P12位于源漏金属层。行子电极P11和列子电极P12之间通过过孔连接。
在本公开的另外一些实施方式中，参见图5，阵列基板AR还可以包括用于设置NFC线圈D1的感测层F400。感测层F400中设置有一层导电层或者多层导电层，NFC线圈D1的走线可以通过这些导电层形成。
感测层F400可以设置于衬底基板F100远离底色层F200的一侧，或者设置于衬底基板F100与底色层F200之间，或者设置于驱动层F300与底色层F200之间。在一些实施方式中，参见图5，在感测层F400靠近驱动层F300的一侧还可以设置有抗反射层F500，以降低感测层F400中的NFC线圈D1的反射率，进而提高显示效果。
在本公开的一种实施方式中，可以在衬底基板F100远离驱动层F300的一侧依次贴附抗反射层F500(抗反射膜)和感测层F400(NFC贴片)，感测层F400可以为具有NFC线圈D1的薄膜。
在这些实施方式中，NFC线圈D1既可以采用镂空走线，也可以采用非镂空走线。在一种示例中，NFC线圈D1的走线为非镂空的走线。
进一步地，参见图10，NFC线圈D1中走线的宽度可以大于擦除电极P2之间的间隙。换言之，NFC线圈D1的走线可以与擦除电极P2至少部分交叠。由于NFC线圈D1位于驱动层F300以下(靠近衬底基板F100的一侧)，因此NFC线圈D1的走线具有较大的面积、与擦除电极P2交叠等情况，均不会对擦除电极P2产生干扰。
示例性地，参见图12，在平行于衬底基板所在平面内，NFC线圈D1的宽度，大于擦除电极P2的尺寸。
再示例性地，参见图13，在平行于衬底基板所在平面内，NFC线圈D1的走线的宽度，大于擦除电极P2的间隙的宽度，且不大于擦除电极P2的宽度。
在本公开的一种实施方式中，参见图10，NFC线圈的走线在衬底基板上的正投影存在相互交叠的位置；NFC线圈的走线的正投影的交叠的位置，位于擦除电极在衬底基板上的正投影内；NFC线圈的走线的其正投影的交叠的位置，通过驱动层跨接。换言之，NFC线圈D1包括至少一圈走线。NFC线圈D1的走线的交叠位置与擦除电极P2交叠；在NFC线圈的走线的交叠位置，NFC线圈D1的走线通过驱动层F300进行跨接。当然的，在本公开的其他实施方式中，感测层F400也可以包括多层导电层，NFC线圈D1的走线在感测层F400的多层导电层之间跨接。
在本公开中，当设置多个NFC线圈时，各个NFC线圈D1的图案可以不完全相同，例如NFC线圈D1的圈数、宽度、走线长度等等可以存在 差异。在一些实施方式中，可以通过对NFC线圈D1的图案的调整，使得各个NFC线圈D1的感应距离相同或者基本相同。在本公开的一种实施方式中，NFC线圈D1的感应距离不超过10cm，例如不超过5cm，尤其是可以在0～3cm之间以保证板擦的安全性。
在本公开的一些实施方式中，控制模块CTR可以包括电路分布结构C1和控制单元C2。电路分布结构C1与驱动电路、NFC芯片电连接，且与控制单元电连接，以使得控制单元C2与驱动电路、NFC芯片之间交互。可选地，电路分布结构可以包括电路板或者柔性电路板，亦或可以为设置有走线的柔性薄膜。控制单元可以控制NFC线圈D1发送NFC信号或者检测NFC信号的变化，还可以用于控制驱动电路的工作状态。当然的，控制单元还可以根据手写板的功能要求实现发挥其他作用，例如一键清除、画面保存等，本公开对此不做特殊的限定。控制单元可以包括与电路分布结构连接的印刷电路板、芯片、单片机、微处理器亦或者其他能够实现控制功能的电路。
参见图14，本公开提供的板擦设置有至少一个擦除单元UU；所述擦除单元UU包括光源UL和NFC芯片US。光源UL在发光时，可以发出预设波长和强度的预设光，该预设光的波谱范围和强度可以根据驱动电路的特性确定。
在本公开的一些实施方式中，擦除单元UU还包括控制电路UC；所述控制电路UC与所述NFC芯片US和所述光源UL电连接。所述控制电路被配置为，当NFC芯片US感测到NFC信号时，控制光源UL发光；当NFC芯片US感测不到NFC信号时，控制光源UL不发光。
举例而言，在本公开的一种实施方式中，NFC芯片US被配置为，当感测到NFC信号时向控制电路UC输出持续的启动信号，直至感测不到NFC信号。控制电路UC配置为，在NFC芯片US输出启动信号时，向光源UL加载电源电压以使得光源发光；在NFC芯片US不输出启动信号时，不向光源UL加载电源电压以使得光源UL不发光。
再举例而言，在本公开的另一种实施方式中，NFC芯片US被配置为，当开始感测到NFC信号时向控制电路UC输出一个脉冲型的启动信号；当NFC信号不再被感测到时，向控制电路输出一个脉冲型的关闭信号。 换言之，当NFC芯片在能够感测到NFC信号和不能够感测到NFC信号两种状态之间变化时，输出启动信号或者关闭信号。控制电路被配置为，在收到启动信号后持续向光源UL加载电源电压以使得电源发光，直至收到关闭信号。
在本公开的一种实施方式中，板擦包括多个擦除区域，每个擦除区域中设置有一个擦除单元UU。当擦除单元UU的NFC芯片US感测到NFC信号时，该擦除单元UU的光源UL发光；当擦除单元UU的NFC芯片US感测不到NFC信号时，该擦除单元UU的不光源UL发光。如此，通过调整板擦上不同擦除区域的位置和大小，可以使得板擦在不同的使用姿态下实现擦除，且使得各个擦除区域的光源UL各自独立工作。
参见图17～图19，在同一擦除单元UU内，NFC芯片US可以相互交叠设置，也可以相邻设置，以保证光源UL发光的及时和准确性。擦除单元UU中可以设置一个或者过个NFC芯片US，也可以设置一个或者多个光源UL。可以理解的是，光源UL发出的光既可以直接照射向手写板，也可以通过导光板、导光条等照射向手写板。在本公开的一种实施方式中，光源UL可以为LED(发光二极管)。
作为一种示例，擦除单元UU包括多个作为光源UL的LED，各个LED均匀分布于擦除区域内。
作为另一种示例，擦除单元UU的光源UL包括在擦除区域的局部位置设置的LED，LED通过导光板将光线从擦除区域均匀射出。
在本公开的一些实施方式中，板擦具有至少一个擦除面，该擦除面中可以设置一个或者多个擦除单元UU。当擦除面靠近手写区时，该擦除面上的擦除单元UU可以响应NFC信号而发光，实现对手写板的局部区域的擦除。
举例而言，参见图15和图16，板擦可以在整体上呈条形，其包括用于朝向手写板以擦除手写板上图案的正面201、与正面201相对设置的背面，以及包括位于正面201和背面之间的四个侧面202。在板擦的正面201，可以设置有一个或者多个擦除单元UU。
在本公开的一种实施方式中，板擦的正面201可以设置有一个擦除单元UU，该擦除单元UU在发光时，可以具有较大的发光面积，例如发光 范围覆盖整个正面201。这样，板擦的正面201能够用于高效的擦除大面积的图案，提高擦除效率。
在本公开的一种实施方式中，参见图15，板擦的至少一个侧面202上设置有擦除单元UU，该擦除单元UU的发光面积较小，因此特别适用于擦除较小区域的图案，例如擦除特定的文字或者字符。
作为一种示例，板擦的各个侧面202上均分别设置有擦除单元UU，以进一步提高使用的便利性。
在任意一个侧面202上，擦除单元UU的数量可以为一个或者可以为多个。擦除单元UU的数量越多，则板擦所能够达成的擦除精度越高。作为一种示意，板擦的至少一个侧面上设置有多个擦除单元UU，以使得每个擦除单元UU具有较小的发光范围，提高擦除的精度。
在本公开的另一种实施方式中，参见图16，在板擦的正面201和侧面202之间设置有倒角203，在倒角203出可以设置有擦除单元UU。这样，该板擦可以以倾斜的状态进行图案擦除，使得板擦的使用习惯和使用效果与粉笔板擦更接近，提高使用体验和擦除效率。
在本公开的一种实施方式中，板擦包括本体101和握持部102。其中，本体101远离握持部102的表面可以作为板擦的正面201；擦除单元UU可以设置于本体101上。
在本公开的一种实施方式中，参见图14，板擦还包括电源模块UE，以便为擦除单元UU提供电力。作为一种示例，电源模块UE为充电电池，且设置有充电端口。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (20)

  1. 一种阵列基板，具有手写区和围绕所述手写区的外围区；所述阵列基板包括阵列设置的擦除电极和驱动所述擦除电极的驱动电路；所述驱动电路被配置为，在预设光的照射下向所述擦除电极加载擦除电压；
    所述阵列基板还设置有用于发出NFC信号的NFC线圈，所述NFC线圈的感应范围覆盖所述手写区。
  2. 根据权利要求1所述的阵列基板，其中，所述NFC线圈的感应距离不大于10cm。
  3. 根据权利要1所述的阵列基板，其中，所述阵列基板包括层叠设置的衬底基板和驱动层；所述擦除电极和驱动电路设置于所述驱动层。
  4. 根据权利要3所述的阵列基板，其中，所述驱动层设置有沿行方向延伸的栅极线和沿列方向延伸的电源线；
    所述驱动电路包括薄膜晶体管；所述薄膜晶体管的源极与所述电源线电连接，所述薄膜晶体管的栅极与所述栅极线电连接，所述薄膜晶体管的漏极与对应的所述擦除电极电连接。
  5. 根据权利要3所述的阵列基板，其中，所述NFC线圈设置于所述驱动层，且所述NFC线圈由多个子电极组成；所述子电极在所述衬底基板上的正投影，位于所述擦除电极在所述衬底基板上的正投影之间。
  6. 根据权利要5所述的阵列基板，其中，所述驱动层包括设置有所述栅极线的栅极层和设置有所述电源线的源漏金属层；
    部分所述子电极设置于所述栅极层和/或部分所述子电极设置于所述源漏金属层。
  7. 根据权利要6所述的阵列基板，其中，所述子电极包括沿所述行方向延伸的行子电极和沿所述列方向延伸的列子电极；
    所述行子电极位于所述栅极层；所述列子电极位于所述源漏金属层。
  8. 根据权利要3所述的阵列基板，其中，所述阵列基板还包括感测层，所述NFC线圈位于所述感测层内；所述感测层位于所述驱动层靠近所述衬底基板的一侧。
  9. 根据权利要8所述的阵列基板，其中，所述阵列基板还包括底色层和抗反射层；
    所述抗反射层位于所述感测层靠近所述驱动层的一侧；
    所述底色层位于所述感测层远离所述驱动层的一侧。
  10. 根据权利要8所述的阵列基板，其中，所述NFC线圈的走线与所述擦除电极至少部分交叠。
  11. 一种手写板，包括依次层叠设置的盖板、液晶层和如权利要求1～10任意一项所述的阵列基板。
  12. 根据权利要求11所述的手写板，其中，所述盖板设置有公共电极层。
  13. 一种板擦，设置有至少一个擦除单元；所述擦除单元包括光源和NFC芯片；
    所述擦除单元被配置为：在所述NFC芯片感测到NFC信号时，所述光源发出预设光；在所述NFC芯片感测不到NFC信号时，所述光源不发光。
  14. 根据权利要求13所述的板擦，其中，所述擦除单元还包括控制电路，所述控制电路与所述NFC芯片和所述光源电连接；
    所述控制电路被配置为：在接收到所述NFC芯片响应所述NFC信号而产生的启动信号后，驱动所述光源发光；在接收不到所述启动信号时，不驱动所述光源发光。
  15. 根据权利要求13所述的板擦，其中，所述擦除单元中的NFC芯片与所述光源交叠设置，或者相邻设置。
  16. 根据权利要求13所述的板擦，其中，所述板擦包括相对设置的正面和背面，以及包括正面和背面之间的多个侧面；
    所述板擦的正面设置有至少一个所述擦除单元。
  17. 根据权利要求16所述的板擦，其中，至少一个所述侧面设置有至少一个所述擦除单元。
  18. 根据权利要求16所述的板擦，其中，所述板擦在所述正面和所述侧面之间设置有倒角；所述倒角处设置有至少一个所述擦除单元。
  19. 一种手写板系统，包括权利要求11～12任意一项所述的手写板和权利要求13～18任意一项所述板擦。
  20. 一种图案擦除方法，应用于权利要求19所述的手写板系统；所 述图案擦除方法包括：
    所述手写板的NFC线圈发出NFC信号；
    当所述板擦的NFC芯片感测到所述NFC信号时，所述板擦的光源发出预设光；当所述板擦的NFC芯片感测不到所述NFC信号时，所述板擦的光源不发光；
    当所述手写板的驱动电路被所述预设光照射时，向所述手写板的擦除电极加载擦除电压。
PCT/CN2021/134290 2021-11-30 2021-11-30 阵列基板、手写板、板擦、手写板系统及图案擦除方法 WO2023097425A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN202180003669.4A CN116529660A (zh) 2021-11-30 2021-11-30 阵列基板、手写板、板擦、手写板系统及图案擦除方法
PCT/CN2021/134290 WO2023097425A1 (zh) 2021-11-30 2021-11-30 阵列基板、手写板、板擦、手写板系统及图案擦除方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2021/134290 WO2023097425A1 (zh) 2021-11-30 2021-11-30 阵列基板、手写板、板擦、手写板系统及图案擦除方法

Publications (1)

Publication Number Publication Date
WO2023097425A1 true WO2023097425A1 (zh) 2023-06-08

Family

ID=86611247

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/134290 WO2023097425A1 (zh) 2021-11-30 2021-11-30 阵列基板、手写板、板擦、手写板系统及图案擦除方法

Country Status (2)

Country Link
CN (1) CN116529660A (zh)
WO (1) WO2023097425A1 (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4711977A (en) * 1986-01-09 1987-12-08 Wacom Co., Ltd. Electronic blackboard apparatus
CN103218963A (zh) * 2012-01-19 2013-07-24 元太科技工业股份有限公司 感光式显示装置及其操作方法
CN112684618A (zh) * 2020-11-30 2021-04-20 山东蓝贝思特教装集团股份有限公司 一种利用光照实现局部擦除的液晶书写装置及方法
CN113284471A (zh) * 2021-06-28 2021-08-20 山东蓝贝思特教装集团股份有限公司 基于光照擦除的液晶书写装置局部擦除控制方法及系统
CN113419388A (zh) * 2021-08-23 2021-09-21 山东蓝贝思特教装集团股份有限公司 一种自适应环境光的液晶书写装置及方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4711977A (en) * 1986-01-09 1987-12-08 Wacom Co., Ltd. Electronic blackboard apparatus
CN103218963A (zh) * 2012-01-19 2013-07-24 元太科技工业股份有限公司 感光式显示装置及其操作方法
CN112684618A (zh) * 2020-11-30 2021-04-20 山东蓝贝思特教装集团股份有限公司 一种利用光照实现局部擦除的液晶书写装置及方法
CN113284471A (zh) * 2021-06-28 2021-08-20 山东蓝贝思特教装集团股份有限公司 基于光照擦除的液晶书写装置局部擦除控制方法及系统
CN113419388A (zh) * 2021-08-23 2021-09-21 山东蓝贝思特教装集团股份有限公司 一种自适应环境光的液晶书写装置及方法

Also Published As

Publication number Publication date
CN116529660A (zh) 2023-08-01

Similar Documents

Publication Publication Date Title
CN214151299U (zh) 一种光擦除液晶书写装置、书写板、黑板及画板
JP4924393B2 (ja) ディスプレイ装置
CN101571633B (zh) 液晶显示设备
US6456279B1 (en) Liquid crystal display device with a touch panel
WO2023045667A1 (zh) 液晶手写板、手写系统及手写系统的控制方法
US20090231497A1 (en) Liquid crystal display, display system including the liquid crystal display and method of recognizing an object using the liquid crystal display
EP3511807A1 (en) Display device and flexible circuit board
TWI566025B (zh) 電子書寫板
US9588601B2 (en) Information display apparatus
CN104238806A (zh) 触控显示面板及触控显示装置
US20080030484A1 (en) Dual liquid crystal display having touch screen
JP2006522980A (ja) 液晶表示装置
JP2022130416A (ja) 入出力装置
US20200363676A1 (en) Display device
CN208654805U (zh) 显示屏组件及电子设备
CN114442350B (zh) 液晶书写装置及其驱动方法
JP2010026693A (ja) 情報入力装置、画像表示装置およびスタイラスペン
WO2023097425A1 (zh) 阵列基板、手写板、板擦、手写板系统及图案擦除方法
US20120092271A1 (en) Computer input device with el panel and touch pad
CN116185214A (zh) 擦除工具及手写系统
CN115616802A (zh) 液晶手写板及其控制方法、手写装置
WO2023050067A1 (zh) 阵列基板、面板、手写板及其驱动方法
US20240231603A1 (en) Array substrate, panel, handwriting tablet and method for driving the same
CN116368425A (zh) 液晶手写面板、手写装置及其控制方法
CN114236927B (zh) 感光基板及其驱动方法、液晶书写装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21965873

Country of ref document: EP

Kind code of ref document: A1