WO2023095287A1 - 構造体、量子ビット、量子演算装置及び構造体の製造方法 - Google Patents

構造体、量子ビット、量子演算装置及び構造体の製造方法 Download PDF

Info

Publication number
WO2023095287A1
WO2023095287A1 PCT/JP2021/043410 JP2021043410W WO2023095287A1 WO 2023095287 A1 WO2023095287 A1 WO 2023095287A1 JP 2021043410 W JP2021043410 W JP 2021043410W WO 2023095287 A1 WO2023095287 A1 WO 2023095287A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
hinge
helical channel
groove
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2021/043410
Other languages
English (en)
French (fr)
Japanese (ja)
Inventor
淳一 山口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to PCT/JP2021/043410 priority Critical patent/WO2023095287A1/ja
Priority to JP2023563447A priority patent/JP7729398B2/ja
Publication of WO2023095287A1 publication Critical patent/WO2023095287A1/ja
Priority to US18/660,129 priority patent/US20240306518A1/en
Anticipated expiration legal-status Critical
Priority to JP2025114844A priority patent/JP2025135013A/ja
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/80—Constructional details
    • H10N60/85—Superconducting active materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/01—Manufacture or treatment
    • H10N60/0156—Manufacture or treatment of devices comprising Nb or an alloy of Nb with one or more of the elements of group IVB, e.g. titanium, zirconium or hafnium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/01—Manufacture or treatment
    • H10N60/0912—Manufacture or treatment of Josephson-effect devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/10—Junction-based devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/10—Junction-based devices
    • H10N60/12—Josephson-effect devices

Definitions

  • the present disclosure relates to structures, quantum bits, quantum computing devices, and methods of manufacturing structures.
  • a structure combining a two-dimensional topological insulator and an s-wave superconductor has been proposed as a structure for generating Majorana particles.
  • a two-dimensional topological insulator a single-layer film of WTe2 , which is a layered material of transition metal ditelluride, is used.
  • Research has also been conducted on high-order topological insulator layers composed of multilayer WTe2 .
  • An object of the present disclosure is to provide a structure, a quantum bit, a quantum computing device, and a method of manufacturing the structure that can obtain good crystallinity in the transition metal ditelluride layer.
  • it has a substrate, a first layer provided on the substrate, and a second layer provided on the first layer, the first layer comprising: A structure is provided having a Te layer and said second layer comprising a transition metal ditelluride layer.
  • FIG. 1 is a cross-sectional view showing the structure according to the first embodiment.
  • FIG. 2 is a diagram showing the results of Raman spectroscopic measurement relating to the first embodiment.
  • FIG. 3 is a cross-sectional view showing a structure according to the second embodiment.
  • FIG. 4 is a diagram showing the results of Raman spectroscopic measurement relating to the second embodiment.
  • FIG. 5 is a cross-sectional view showing a structure according to the third embodiment.
  • FIG. 6 is a diagram showing the results of Raman spectroscopic measurement relating to the third embodiment.
  • FIG. 7 is a top view showing a quantum bit according to the fourth embodiment.
  • FIG. 8 is a cross-sectional view (Part 1) showing a quantum bit according to the fourth embodiment.
  • FIG. 9 is a cross-sectional view (Part 2) showing the quantum bit according to the fourth embodiment.
  • FIG. 10 is a perspective view showing a higher-order topological insulator layer.
  • FIG. 11 is a top view (No. 1) showing the method of manufacturing the quantum bit according to the fourth embodiment.
  • FIG. 12 is a top view (No. 2) showing the method of manufacturing the quantum bit according to the fourth embodiment.
  • FIG. 13 is a top view (No. 3) showing the method of manufacturing the quantum bit according to the fourth embodiment.
  • FIG. 14 is a top view (No. 4) showing the method of manufacturing the quantum bit according to the fourth embodiment.
  • FIG. 15 is a top view (No. 5) showing the method of manufacturing the quantum bit according to the fourth embodiment.
  • FIG. 16 is a top view (No.
  • FIG. 17 is a cross-sectional view (part 1) showing the method of manufacturing the quantum bit according to the fourth embodiment.
  • FIG. 18 is a cross-sectional view (part 2) showing the method of manufacturing the quantum bit according to the fourth embodiment.
  • FIG. 19 is a cross-sectional view (No. 3) showing the method of manufacturing the quantum bit according to the fourth embodiment.
  • FIG. 20 is a cross-sectional view (No. 4) showing the method of manufacturing the quantum bit according to the fourth embodiment.
  • FIG. 21 is a cross-sectional view (No. 5) showing the method of manufacturing the quantum bit according to the fourth embodiment.
  • FIG. 22 is a cross-sectional view (No. 6) showing the method of manufacturing the quantum bit according to the fourth embodiment.
  • FIG. 23 is a diagram showing a quantum arithmetic device according to the fifth embodiment.
  • the X1-X2 direction, the Y1-Y2 direction, and the Z1-Z2 direction are mutually orthogonal directions.
  • a plane including the X1-X2 direction and the Y1-Y2 direction is referred to as the XY plane
  • a plane including the Y1-Y2 direction and the Z1-Z2 direction is referred to as the YZ plane
  • a plane including the Z1-Z2 direction and the X1-X2 direction. is described as the ZX plane.
  • the Z1-Z2 direction is the vertical direction
  • the Z1 side is the upper side
  • the Z2 side is the lower side.
  • the term “planar view” refers to viewing the object from the Z1 side
  • the term “planar shape” refers to the shape of the object viewed from the Z1 side.
  • FIG. 1 is a cross-sectional view showing the structure according to the first embodiment.
  • the structure 100 has a substrate 110, a first layer 120, and a second layer .
  • a first layer 120 is formed over the substrate 110 .
  • a second layer 130 is formed over the first layer 120 .
  • the substrate 110 is, for example, a single crystal substrate whose surface has a Miller index of (100).
  • the material of the substrate 110 is MgO, for example.
  • the substrate 110 in the first embodiment is an example of a base material.
  • the first layer 120 is a Te layer that does not contain W.
  • the thickness of the first layer 120 is, for example, 1 nm to 20 nm.
  • the second layer 130 is, for example, multi-layer WTe2 .
  • multilayer WTe 2 has 5 to 100 layers, preferably 10 to 50 layers of WTe 2 which is a two-dimensional material.
  • a single layer of WTe 2 has a thickness of 0.7 nm, so if the second layer 130 contains 70 layers of WTe 2 , the thickness of the second layer 130 is about 50 nm.
  • the substrate 110 is prepared, and the substrate 110 is annealed at about 1200° C. for 3 to 4 hours in an oxygen atmosphere of atmospheric pressure.
  • the substrate 110 is immersed in methanol for 20 to 30 minutes and rinsed with ultrapure water. These treatments can improve the flatness of the surface of the substrate 110 .
  • a first layer 120 is formed on the substrate 110 and a second layer 130 is formed on the first layer 120 .
  • the first layer 120 and the second layer 130 can be epitaxially grown in situ in the same vacuum chamber, for example by pulse laser deposition (PLD).
  • PLD pulse laser deposition
  • the basic degree of vacuum when forming the first layer 120 and the second layer 130 is, for example, 5 ⁇ 10 ⁇ 6 Pa or less.
  • the first layer 120 and the second layer 130 may be formed by a sputtering method, or the first layer 120 may be formed by a vapor deposition method and the second layer 130 may be formed by a co-evaporation method.
  • the first layer 120 and the second layer 130 can be formed by physical vapor deposition in a vacuum-integrated process.
  • a Te pure metal target can be used as the target.
  • the temperature of the substrate 110 is maintained at about 200° C.
  • the laser energy density is 1.0 J/cm 2
  • the irradiation frequency is 1 Hz
  • the distance between the substrate 110 and the target is about 5 cm
  • the deposition rate is 1.0 nm/min.
  • a WTe2 sintered body target can be used as the target.
  • the temperature of the substrate 110 is maintained at 325° C.
  • the laser energy density is 1.0 J/cm 2
  • the irradiation frequency is 10 Hz
  • the distance between the substrate 110 and the target is approximately 5 cm
  • the deposition rate is 1.0 nm/min.
  • the second layer 130 (multilayer WTe 2 ) is c-axis oriented on the first layer 120 and the crystal structure of the second layer 130 exhibits a Td structure.
  • the structure 100 according to the first embodiment can be manufactured.
  • first layer 120 is formed between substrate 110 and second layer 130 .
  • the first layer 120 acts as a seed layer in forming the second layer 130, although the lattice mismatch between MgO with (100) surface Miller index and WTe2 is 33%. Therefore, good crystallinity can be obtained in the second layer 130 .
  • FIG. 2 is a diagram showing the results of Raman spectroscopic measurement relating to the first embodiment.
  • the material of the substrate 110 may be mica, sapphire, SiC, or the like.
  • FIG. 3 is a cross-sectional view showing a structure according to the second embodiment.
  • a structure 200 according to the second embodiment has a substrate 210, a first layer 120, and a second layer .
  • a first layer 120 is formed over a substrate 210 .
  • a second layer 130 is formed over the first layer 120 .
  • the substrate 210 has a Si substrate 211 and a SiO 2 film 212 formed on the Si substrate 211 .
  • the SiO 2 film 212 is formed by thermal oxidation of the Si substrate 211, for example. That is, the substrate 210 is a Si substrate with a thermal oxide film.
  • a first layer 120 is provided on the SiO 2 film 212 .
  • the substrate 210 in the second embodiment is an example of a base material.
  • the substrate 210 is prepared, and the substrate 210 is annealed at about 800° C. for 15 minutes in an oxygen atmosphere of atmospheric pressure. Annealing can remove organic deposits on the surface of the SiO 2 film 212 .
  • a first layer 120 is formed on the substrate 210 and a second layer 130 is formed on the first layer 120. Then, as shown in FIG.
  • the first layer 120 and the second layer 130 can be formed by a method similar to that of the first embodiment.
  • the structure 200 according to the second embodiment can be manufactured.
  • first layer 120 is formed between substrate 210 and second layer 130 .
  • the SiO 2 film 212 present on the surface of the substrate 210 is amorphous, the first layer 120 functions as a seed layer when forming the second layer 130 . Therefore, good crystallinity can be obtained in the second layer 130 .
  • FIG. 4 is a diagram showing the results of Raman spectroscopic measurement relating to the second embodiment.
  • FIG. 5 is a cross-sectional view showing a structure according to the third embodiment.
  • a structure 300 according to the third embodiment has a substrate 110 , an s-wave superconductor layer 340 , a first layer 120 and a second layer 130 .
  • An s-wave superconductor layer 340 is formed over the substrate 110 .
  • a first layer 120 is formed over an s-wave superconductor layer 340 .
  • a second layer 130 is formed over the first layer 120 .
  • the s-wave superconductor layer 340 is, for example, a Nb layer with a surface Miller index of (110).
  • the thickness of the s-wave superconductor layer 340 is, for example, about 100 nm to 200 nm.
  • the laminate 310 of the substrate 110 and the s-wave superconductor layer 340 is an example of the base material.
  • the substrate 110 is prepared, and annealing and rinsing are performed in the same manner as in the first embodiment.
  • an s-wave superconductor layer 340 is formed on the substrate 110 , a first layer 120 is formed on the s-wave superconductor layer 340 , and a second layer 130 is formed on the first layer 120 .
  • the s-wave superconductor layer 340, the first layer 120 and the second layer 130 can be epitaxially grown in situ in the same vacuum chamber, for example by the PLD method.
  • the basic degree of vacuum when forming the s-wave superconductor layer 340, the first layer 120 and the second layer 130 is, for example, 5 ⁇ 10 ⁇ 6 Pa or less.
  • the method of forming the s-wave superconductor layer 340, the first layer 120 and the second layer 130 is not limited to the PLD method.
  • the s-wave superconductor layer 340, the first layer 120 and the second layer 130 may be formed by a sputtering method, the s-wave superconductor layer 340 and the first layer 120 are formed by a vapor deposition method, and the second layer 130 is formed by a vapor deposition method.
  • Layer 130 may be formed by co-evaporation.
  • a Nb pure metal target can be used as the target.
  • the temperature of the substrate 110 is maintained at about 400° C.
  • the laser energy density is 2.0 J/cm 2
  • the irradiation frequency is 10 Hz
  • the distance between the substrate 110 and the target is The distance between them is about 5 cm
  • the deposition rate is 1.0 nm/min.
  • the Nb layer is epitaxially grown while being oriented in the [110] direction on the substrate 110 kept at about 400.degree.
  • the first layer 120 is formed on the s-wave superconductor layer 340 and the second layer 130 is formed on the first layer 120 .
  • the first layer 120 and the second layer 130 can be formed by a method similar to that of the first embodiment.
  • the s-wave superconductor layer 340, first layer 120 and second layer 130 can be formed by physical vapor deposition in a vacuum integrated process.
  • the structure 300 according to the third embodiment can be manufactured.
  • first layer 120 is formed between s-wave superconductor layer 340 and second layer 130 .
  • the first layer 120 acts as a seed layer in forming the second layer 130, although the lattice mismatch between Nb with a surface Miller index of (110) and WTe2 is 25%. Therefore, good crystallinity can be obtained in the second layer 130 .
  • the thickness of the s-wave superconductor layer 340 was 150 nm
  • the thickness of the first layer 120 was 5 nm
  • the thickness of the second layer 130 was 20 nm.
  • FIG. 6 is a diagram showing the results of Raman spectroscopic measurement relating to the third embodiment.
  • the material of the layered transition metal ditelluride layer contained in the second layer is not limited to WTe2 .
  • the transition metal ditelluride layer may contain Mo, Nb, W, Ta, Ti, Zr, Fe, Pd, Ir or Pt or any combination thereof as the transition metal.
  • the layered transition metal ditelluride layer contained in the second layer may be a single layer.
  • the thickness of the first layer is preferably 1 nm to 20 nm. If the thickness of the first layer is less than 1 nm, it may be difficult to obtain excellent crystallinity in the second layer. Moreover, if the thickness of the first layer exceeds 20 nm, the electrical properties of the first layer may change. Furthermore, when the first layer is provided between the s-wave superconductor layer and the second layer, as in the third embodiment, if the thickness of the first layer is excessive, the superconducting proximity effect may decrease.
  • the thickness of the first layer is more preferably 2 nm to 15 nm, still more preferably 3 nm to 10 nm.
  • FIG. 7 is a top view showing a quantum bit according to the fourth embodiment.
  • 8 and 9 are cross-sectional views showing a quantum bit according to the fourth embodiment.
  • FIG. 8 corresponds to a cross-sectional view taken along line VIII-VIII in FIG.
  • FIG. 9 corresponds to a cross-sectional view taken along line IX-IX in FIG.
  • the qubit 1 includes a substrate 90, an s-wave superconductor layer 10, a Te layer 70, a high-order topological insulator layer 20, a first ferromagnetic insulator layer 31, a second It has a ferromagnetic insulator layer 32 and a third ferromagnetic insulator layer 33 .
  • the quantum bit 1 further includes a first gate electrode 41, a second gate electrode 42, a third gate electrode 43, a first superconducting quantum interference device (SQUID) 61, a second SQUID 62, and a third SQUID 63 .
  • SQUID superconducting quantum interference device
  • the substrate 90 is, for example, a single crystal substrate whose surface has a Miller index of (100).
  • Materials for substrate 90 include MgO, mica, sapphire, and SiC.
  • the substrate 90 may be a Si substrate with a thermal oxide film.
  • the s-wave superconductor layer 10 is provided on part of the surface of the substrate 90 .
  • the s-wave superconductor layer 10 is, for example, a Nb layer with a surface Miller index of (110).
  • the thickness of the s-wave superconductor layer 10 is, for example, about 100 nm to 200 nm.
  • the planar shape of the s-wave superconductor layer 10 is a rectangle having two sides parallel to the X1-X2 direction and two sides parallel to the Y1-Y2 direction.
  • the Te layer 70 is provided on the s-wave superconductor layer 10 .
  • the thickness of the Te layer 70 is preferably 1 nm to 20 nm, more preferably 2 nm to 15 nm, even more preferably 3 nm to 10 nm.
  • the thickness of the Te layer 70 is, for example, 5 nm.
  • Higher-order topological insulator layer 20 is provided on Te layer 70 .
  • the higher-order topological insulator layer 20 is, for example, multi-layer WTe2 .
  • multilayer WTe 2 has 5 to 100 layers, preferably 10 to 50 layers of WTe 2 which is a two-dimensional material.
  • the thickness of the high-order topological insulator layer 20 is, for example, 20 nm.
  • FIG. 10 is a perspective view showing the high-order topological insulator layer 20.
  • the shape of the high-order topological insulator layer 20 is a substantially rectangular parallelepiped.
  • the a-axis direction of the high-order topological insulator layer 20 is parallel to the Y1-Y2 direction, the b-axis direction is parallel to the X1-X2 direction, and the c-axis direction is parallel to the Z1-Z2 direction.
  • the Miller index of the top surface of the high-order topological insulator layer 20 is (001), the Miller index of the side surface on the Y2 side is (100), and the Miller index of the side surface on the X2 side is (010).
  • a T-shaped groove 50 is formed in the surface of the high-order topological insulator layer 20 in plan view.
  • the groove 50 has a first groove 51 , a second groove 52 and a third groove 53 .
  • the width of the first groove 51, the second groove 52 and the third groove 53 is 20 nm, and the depth is 10 nm.
  • the first groove 51 and the third groove 53 extend parallel to the X1-X2 direction, and the second groove 52 extends parallel to the Y1-Y2 direction.
  • the first groove 51 is provided near the center of the high-order topological insulator layer 20 in the Y1-Y2 direction and extends from the end of the high-order topological insulator layer 20 on the X2 side to the center in the X1-X2 direction.
  • the third groove 53 is provided near the center of the high-order topological insulator layer 20 in the Y1-Y2 direction, and extends from the end of the high-order topological insulator layer 20 on the X1 side to the center in the X1-X2 direction. Therefore, the first groove 51 and the third groove 53 are formed in a straight line.
  • the second groove 52 is provided near the center of the high-order topological insulator layer 20 in the X1-X2 direction and extends from the Y1-side end of the high-order topological insulator layer 20 to the center in the Y1-Y2 direction. Therefore, the second groove 52 is perpendicular to the first groove 51 and the third groove 53 .
  • the high-order topological insulator layer 20 has the first region 21 on the Y2 side of the first groove 51 and the third groove 53 .
  • the high-order topological insulator layer 20 has a second region 22 on the Y1 side of the first groove 51 and on the X2 side of the second groove 52 .
  • the high-order topological insulator layer 20 has a third region 23 on the Y1 side of the third groove 53 and on the X1 side of the second groove 52 .
  • Each of the first region 21, the second region 22 and the third region 23 has a hinge helical channel on one of two intersection lines of a plane perpendicular to the a-axis direction and a plane perpendicular to the c-axis direction.
  • the hinge-helical channel is parallel to the b-axis.
  • the first region 21 includes the first hinge helical channel 11 at the line of intersection (ridge line) between the top surface and the side surface on the Y1 side.
  • the second region 22 has the second hinge helical channel 12 at the line of intersection between the side surface on the Y2 side and the bottom surface of the first groove 51 .
  • the third region 23 has the third hinge helical channel 13 at the line of intersection between the side surface on the Y2 side and the bottom surface of the third groove 53 .
  • the first hinge helical channel 11 is located at the line of intersection between the Y1 side surface of the first region 21 and the bottom surface of the groove 50
  • the second hinge helical channel 12 is located between the upper surface of the second region 22 and the Y2 side surface. It may be on the line of intersection
  • the third hinge-helical channel 13 may be on the line of intersection between the upper surface of the third region 23 and the side surface on the Y2 side.
  • the first ferromagnetic insulator layer 31 is provided over part of the first region 21 , the second region 22 and the groove 50 and covers part of the first hinge helical channel 11 and the second hinge helical channel 12 . cover.
  • a second ferromagnetic insulator layer 32 is provided over portions of the second region 22 , the third region 23 and the grooves 50 and partially overlies the second hinge helical channel 12 and the third hinge helical channel 13 . cover.
  • a third ferromagnetic insulator layer 33 is provided over part of the third region 23 , the first region 21 and the groove 50 and covers part of the third hinge helical channel 13 and the first hinge helical channel 11 . cover.
  • Examples of materials for the first ferromagnetic insulator layer 31, the second ferromagnetic insulator layer 32, and the third ferromagnetic insulator layer 33 include Cr2Ga2Te6 .
  • the materials of the first ferromagnetic insulator layer 31, the second ferromagnetic insulator layer 32 and the third ferromagnetic insulator layer 33 may be other diluted magnetic semiconductors.
  • the thicknesses of the first ferromagnetic insulator layer 31, the second ferromagnetic insulator layer 32, and the third ferromagnetic insulator layer 33 are, for example, about 30 nm.
  • the second ferromagnetic insulator layer 32 is separated from the first ferromagnetic insulator layer 31 to the X1 side on the second hinge-helical channel 12 in the X1-X2 direction.
  • the third ferromagnetic insulator layer 33 is separated from the second ferromagnetic insulator layer 32 to the X1 side on the third hinge-helical channel 13 in the X1-X2 direction.
  • the third ferromagnetic insulator layer 33 is separated from the first ferromagnetic insulator layer 31 to the X1 side on the first hinge-helical channel 11 in the X1-X2 direction.
  • the first gate electrode 41 is provided on the first ferromagnetic insulator layer 31 .
  • a second gate electrode 42 is provided on the second ferromagnetic insulator layer 32 .
  • a third gate electrode 43 is provided on the third ferromagnetic insulator layer 33 .
  • Materials for the first gate electrode 41, the second gate electrode 42, and the third gate electrode 43 include Au.
  • the thicknesses of the first gate electrode 41, the second gate electrode 42, and the third gate electrode 43 are, for example, about 100 nm.
  • the first SQUID 61 has a lower superconductor layer 61A, a lower superconductor layer 61B, a tunnel barrier layer 61C, and an upper superconductor layer 61D.
  • the lower superconductor layer 61A and the lower superconductor layer 61B protrude from the side surface of the s-wave superconductor layer 10 on the X2 side to the X2 side.
  • the lower superconductor layer 61A is on the Y2 side of the lower superconductor layer 61B.
  • the lower superconductor layer 61A protrudes from the first region 21 toward the X2 side
  • the lower superconductor layer 61B protrudes from the second region 22 toward the X2 side.
  • the lower superconductor layer 61 A and the lower superconductor layer 61 B are formed integrally with the s-wave superconductor layer 10 from the same material as the s-wave superconductor layer 10 .
  • the lower superconductor layer 61 A and the lower superconductor layer 61 B are connected to the s-wave superconductor layer 10 .
  • the lower superconductor layer 61A and the lower superconductor layer 61B are, for example, Nb layers with a thickness of about 100 nm to 200 nm.
  • the tunnel barrier layer 61C and the upper superconductor layer 61D have a U-shaped planar shape.
  • a material for the tunnel barrier layer 61C is NbOx
  • a material for the upper superconductor layer 61D is Nb.
  • the thickness of the tunnel barrier layer 61C is, for example, about 1 nm to 5 nm
  • the thickness of the upper superconductor layer 61D is, for example, about 100 nm to 200 nm.
  • One end of the tunnel barrier layer 61C contacts the lower superconductor layer 61A and the other end contacts the lower superconductor layer 61B.
  • An upper superconductor layer 61D is provided on the tunnel barrier layer 61C.
  • a tunnel barrier layer 61C is sandwiched between the lower superconductor layer 61A and the upper superconductor layer 61D and between the lower superconductor layer 61B and the upper superconductor layer 61D.
  • the first SQUID 61 is composed of such a Josephson junction.
  • the first SQUID 61 detects changes in magnetic flux between the first hinge helical channel 11 and the second hinge helical channel 12 .
  • the second SQUID 62 has a lower superconductor layer 62A, a lower superconductor layer 62B, a tunnel barrier layer 62C, and an upper superconductor layer 62D.
  • the lower superconductor layer 62A and the lower superconductor layer 62B protrude from the side surface of the s-wave superconductor layer 10 on the Y1 side to the Y1 side.
  • the lower superconductor layer 62A is on the X2 side of the lower superconductor layer 62B.
  • the lower superconductor layer 62A protrudes from the second region 22 toward the Y1 side
  • the lower superconductor layer 62B protrudes from the third region 23 toward the Y1 side.
  • the lower superconductor layer 62A and the lower superconductor layer 62B are formed integrally with the s-wave superconductor layer 10 from the same material as the s-wave superconductor layer 10.
  • Lower superconductor layer 62 A and lower superconductor layer 62 B are connected to s-wave superconductor layer 10 .
  • the lower superconductor layer 62A and the lower superconductor layer 62B are, for example, Nb layers with a thickness of about 100 nm to 200 nm.
  • the tunnel barrier layer 62C and the upper superconductor layer 62D have a U-shaped planar shape.
  • a material for the tunnel barrier layer 62C is NbOx
  • a material for the upper superconductor layer 62D is Nb.
  • the thickness of the tunnel barrier layer 62C is, for example, about 1 nm to 5 nm
  • the thickness of the upper superconductor layer 62D is, for example, about 100 nm to 200 nm.
  • One end of the tunnel barrier layer 62C contacts the lower superconductor layer 62A and the other end contacts the lower superconductor layer 62B.
  • An upper superconductor layer 62D is provided over the tunnel barrier layer 62C.
  • a tunnel barrier layer 62C is sandwiched between the lower superconductor layer 62A and the upper superconductor layer 62D and between the lower superconductor layer 62B and the upper superconductor layer 62D.
  • the second SQUID 62 is composed of such a Josephson junction.
  • the second SQUID 62 detects changes in magnetic flux between the second hinge-helical channel 12 and the third hinge-helical channel 13 .
  • the third SQUID 63 has a lower superconductor layer 63A, a lower superconductor layer 63B, a tunnel barrier layer 63C, and an upper superconductor layer 63D.
  • the lower superconductor layer 63A and the lower superconductor layer 63B protrude from the side surface of the s-wave superconductor layer 10 on the X1 side to the X1 side.
  • the lower superconductor layer 63A is on the Y1 side of the lower superconductor layer 63B.
  • the lower superconductor layer 63A protrudes from the third region 23 toward the X1 side
  • the lower superconductor layer 63B protrudes from the first region 21 toward the X1 side.
  • the lower superconductor layer 63 A and the lower superconductor layer 63 B are formed integrally with the s-wave superconductor layer 10 from the same material as the s-wave superconductor layer 10 .
  • the lower superconductor layer 63 A and the lower superconductor layer 63 B are connected to the s-wave superconductor layer 10 .
  • the lower superconductor layer 63A and the lower superconductor layer 63B are, for example, Nb layers with a thickness of about 100 nm to 200 nm.
  • the tunnel barrier layer 63C and the upper superconductor layer 63D have a U-shaped planar shape.
  • a material for the tunnel barrier layer 63C is NbOx
  • a material for the upper superconductor layer 63D is Nb.
  • the thickness of the tunnel barrier layer 63C is, for example, about 1 nm to 5 nm
  • the thickness of the upper superconductor layer 63D is, for example, about 100 nm to 200 nm.
  • One end of the tunnel barrier layer 63C contacts the lower superconductor layer 63A and the other end contacts the lower superconductor layer 63B.
  • An upper superconductor layer 63D is provided on the tunnel barrier layer 63C.
  • a tunnel barrier layer 63C is sandwiched between the lower superconductor layer 63A and the upper superconductor layer 63D and between the lower superconductor layer 63B and the upper superconductor layer 63D.
  • the third SQUID 63 is composed of such a Josephson junction.
  • the third SQUID 63 detects changes in magnetic flux between the third hinge helical channel 13 and the first hinge helical channel 11 .
  • the Majorana particle ⁇ 1 is stably expressed near the first gate electrode 41 of the first hinge-helical channel 11
  • the Majorana particle ⁇ 4 is stably expressed near the third gate electrode 43 of the first hinge-helical channel 11.
  • the Majorana particle ⁇ 2 is stably expressed between the first gate electrode 41 and the second gate electrode 42 of the second hinge-helical channel 12
  • the Majorana particle ⁇ 3 is stably expressed in the third hinge-helical channel 13. It is stably developed between the second gate electrode 42 and the third gate electrode 43 .
  • Exchange of the Majorana particles ⁇ 1 to ⁇ 4 is carried out by a change in electrostatic potential caused by application of gate voltages to the first gate electrode 41, the second gate electrode 42, and the third gate electrode 43.
  • the first gate electrode 41 when the Majorana particles ⁇ 1 and ⁇ 2 are exchanged, an electric field is applied from the first gate electrode 41, and the first SQUID 61 detects a minute change in magnetic flux as a minute change in voltage signal when the Majorana particles ⁇ 1 and ⁇ 2 are exchanged. detected.
  • the second SQUID 62 detects minute changes in the magnetic flux during the exchange of the Majorana particles ⁇ 2 and ⁇ 3 as minute voltage signal changes.
  • a monolayer film of WTe2 which is a layered material of transition metal dichalcogenide, is easily oxidized, and its properties change when exposed to the atmosphere. It is possible to suppress oxidation by sandwiching a single layer of WTe 2 between hexagonal boron nitride (h-BN), graphene, or other chemically stable substances. It complicates the process. It is also difficult to adjust the size of the WTe2 monolayer film.
  • the high-order topological insulator layer 20 such as multilayer WTe 2 is used, a structure for suppressing oxidation is not required.
  • adjusting the size of the high-order topological insulator layer 20 is easier than adjusting the size of a single layer film of WTe 2 .
  • 11 to 16 are top views showing the manufacturing method of the quantum bit 1 according to the fourth embodiment.
  • 17 to 22 are cross-sectional views showing the manufacturing method of the quantum bit 1 according to the fourth embodiment.
  • FIGS. 11 and 17 corresponds to a cross-sectional view taken along line XVII-XVII in FIG.
  • the s-wave superconductor layer 19 is formed on the substrate 90 , the Te layer 79 is formed on the s-wave superconductor layer 19 , and the high-order topological insulator layer 29 is formed on the Te layer 79 .
  • an Nb layer is formed as the s-wave superconductor layer 19 and a multi-layered WTe 2 is formed as the high-order topological insulator layer 29 .
  • the s-wave superconductor layer 19, the Te layer 79, and the high-order topological insulator layer 29 can be epitaxially grown in situ in the same vacuum chamber by, for example, the PLD method.
  • the basic degree of vacuum at the time of forming the s-wave superconductor layer 19, Te layer 79, and high-order topological insulator layer 29 is, for example, 5 ⁇ 10 ⁇ 6 Pa or less.
  • the method of forming the s-wave superconductor layer 19, the Te layer 79, and the high-order topological insulator layer 29 is not limited to the PLD method.
  • the s-wave superconductor layer 19, the Te layer 79, and the high-order topological insulator layer 29 may be formed by a sputtering method, and the s-wave superconductor layer 19 and the Te layer 79 may be formed by a vapor deposition method.
  • the next topological insulator layer 29 may be formed by co-evaporation.
  • the s-wave superconductor layer 19, Te layer 79 and higher topological insulator layer 29 can be formed by physical vapor deposition in a vacuum integrated process.
  • a Nb pure metal target can be used as the target.
  • the temperature of the substrate 90 is maintained at about 400° C.
  • the laser energy density is 2.0 J/cm 2 to 5.0 J/cm 2
  • the irradiation frequency is 10 Hz.
  • the distance between the substrate 90 and the target is about 5 cm
  • the deposition rate is 0.5 nm/min to 1.0 nm/min.
  • the Nb layer is epitaxially grown while being oriented in the [110] direction on the substrate 90 kept at about 400.degree.
  • a Te pure metal target can be used as a target.
  • the temperature of the substrate 90 is maintained at about 200° C.
  • the laser energy density is 1.0 J/cm 2 to 2.0 J/cm 2
  • the irradiation frequency is 1 Hz
  • the substrate 110 and The distance from the target is about 5 cm
  • the deposition rate is 0.5 nm/min to 1.5 nm/min.
  • a WTe2 sintered body target can be used as the target.
  • the temperature of the substrate 90 is maintained at about 325° C.
  • the laser energy density is 1.0 J/cm 2 to 2.0 J/cm 2
  • the irradiation frequency is 10 Hz
  • the distance between the substrate 90 and the target is about 5 cm
  • the deposition rate is 0.5 nm/min to 1.5 nm/min.
  • the higher-order topological insulator layer 29 (multilayer WTe 2 ) is oriented in the c-axis direction on the s-wave superconductor layer 19 (Nb layer), and the crystal structure of the higher-order topological insulator layer 29 exhibits a Td structure.
  • FIG. 18 corresponds to a cross-sectional view taken along line XVIII-XVIII in FIG.
  • the high-order topological insulator layer 29 is spin-coated with a first electron beam resist.
  • a first mask pattern is formed from the first electron beam resist.
  • the first mask pattern is the s-wave superconductor layer 10, the lower superconductor layer 61A, the lower superconductor layer 61B, the lower superconductor layer 62A, and the lower superconductor layer 62B of the s-wave superconductor layer 19.
  • the portion where the lower superconductor layer 63A and the lower superconductor layer 63B are to be formed are covered from above the high-order topological insulator layer 29, and other portions are exposed.
  • the first electron beam resist for example, a resist obtained by diluting ZEP 520A (manufactured by Nippon Zeon Co., Ltd.) with ZEP-A (manufactured by Nippon Zeon Co., Ltd.) at a ratio of 1:1 can be used.
  • the s-wave superconductor layer 19, Te layer 79 and high-order topological insulator layer 29 are processed by Ar ion milling.
  • Ar ion milling for example, the beam acceleration voltage is 280 V and the beam current is 150 mA.
  • FIG. 19 corresponds to a cross-sectional view taken along line XIX-XIX in FIG.
  • a second electron beam resist is spin-coated on the high-order topological insulator layer 29 and the substrate 90 .
  • a second mask pattern is formed from a second electron beam resist by electron beam lithography.
  • the second mask pattern covers the portion of the higher-order topological insulator layer 29 on the s-wave superconductor layer 10, the lower superconductor layer 61A, the lower superconductor layer 61B, the lower superconductor layer 62A, the lower superconductor layer 62A, the lower superconductor layer The conductor layer 62B, the lower superconductor layer 63A and the upper portions of the lower superconductor layer 63B are exposed.
  • the second electron beam resist for example, a resist obtained by diluting ZEP 520A (manufactured by Nippon Zeon Co., Ltd.) with ZEP-A (manufactured by Nippon Zeon Co., Ltd.) at a ratio of 1:1 can be used.
  • the high-order topological insulator layer 29 and the Te layer 79 are processed by Ar ion milling.
  • the higher-order topological insulator layer 29A and the Te layer 70 are formed, and the lower superconductor layer 61A, the lower superconductor layer 61B, the lower superconductor layer 62A, the lower superconductor layer 62B, the lower superconductor Layer 63 A and lower superconductor layer 63 B are exposed from higher topological insulator layer 29 A and Te layer 70 .
  • the beam acceleration voltage is 280 V and the beam current is 150 mA.
  • FIG. 20 corresponds to a cross-sectional view taken along line XX-XX in FIG.
  • the high-order topological insulator layer 29A When processing the high-order topological insulator layer 29A, first, the high-order topological insulator layer 29A, the substrate 90, the lower superconductor layer 61A, the lower superconductor layer 61B, the lower superconductor layer 62A, the lower superconductor layer A third electron beam resist is spin-coated on the conductor layer 62B, the lower superconductor layer 63A and the lower superconductor layer 63B. Next, by electron beam lithography, a third mask pattern is formed from a third electron beam resist. The third mask pattern exposes the portion of the high-order topological insulator layer 29A where the trench 50 is to be formed and covers the other portion.
  • the third electron beam resist for example, a resist obtained by diluting ZEP 520A (manufactured by Nippon Zeon Co., Ltd.) with ZEP-A (manufactured by Nippon Zeon Co., Ltd.) at a ratio of 1:1 can be used.
  • the high-order topological insulator layer 29A is processed by Ar ion milling. As a result, a trench 50 comprising a first trench 51, a second trench 52 and a third trench 53 is formed, and a high-order topological insulator layer 20 comprising a first region 21, a second region 22 and a third region 23 is formed. is obtained.
  • the first region 21 comprises the first hinge helical channel 11
  • the second region 22 comprises the second hinge helical channel 12
  • the third region 23 comprises the third hinge helical channel 13 (see Figure 10).
  • the beam acceleration voltage is 280 V and the beam current is 150 mA.
  • FIG. 21 corresponds to a cross-sectional view taken along line XXI-XXI in FIG.
  • the first ferromagnetic insulator layer 31 When forming the first ferromagnetic insulator layer 31, the second ferromagnetic insulator layer 32, the third ferromagnetic insulator layer 33, the first gate electrode 41, the second gate electrode 42 and the third gate electrode 43, First, the higher-order topological insulator layer 20, the substrate 90, the lower superconductor layer 61A, the lower superconductor layer 61B, the lower superconductor layer 62A, the lower superconductor layer 62B, the lower superconductor layer 63A and the lower A fourth electron beam resist is spin-coated on the superconductor layer 63B. Next, a fourth mask pattern is formed from a fourth electron beam resist by electron beam lithography.
  • the fourth mask pattern includes a first ferromagnetic insulator layer 31, a second ferromagnetic insulator layer 32, a third ferromagnetic insulator layer 33, a first gate electrode 41, a second gate electrode 42 and a third gate electrode 43. It exposes the part that is to form the , and covers the other part.
  • the fourth electron beam resist for example, a resist obtained by diluting ZEP 520A (manufactured by Nippon Zeon Co., Ltd.) with ZEP-A (manufactured by Nippon Zeon Co., Ltd.) at a ratio of 1:1 can be used.
  • a Cr 2 Ga 2 Te 6 layer and an Au layer are formed by the PLD method.
  • the temperature of the substrate 90 is maintained at 200° C.
  • the laser energy density is 1.0 J/cm 2 to 2.0 J/cm 2
  • the irradiation frequency is is 1 Hz
  • the distance between the substrate 90 and the target is about 5 cm
  • the deposition rate is 1.0 nm/min to 2.0 nm/min.
  • the temperature of the substrate 90 is kept at room temperature, the laser energy density is 1.0 J/cm 2 to 2.0 J/cm 2 , the irradiation frequency is 5 Hz, and the substrate 90 is The distance from the target is about 5 cm, and the deposition rate is 5.0 nm/min to 10.0 nm/min.
  • the fourth mask pattern is removed together with the Cr 2 Ga 2 Te 6 layer and the Au layer deposited thereon. That is, liftoff is performed.
  • a first ferromagnetic insulator layer 31 a second ferromagnetic insulator layer 32, a third ferromagnetic insulator layer 33, a first gate electrode 41, a second gate electrode 42 and a third gate electrode 43 are obtained.
  • four Majorana particles ⁇ 1, ⁇ 2, ⁇ 3 and ⁇ 4 are expressed.
  • FIG. 22 corresponds to a cross-sectional view taken along line XXII-XXII in FIG.
  • the tunnel barrier layers 61C-63C and the upper superconductor layers 61D-63D When forming the tunnel barrier layers 61C-63C and the upper superconductor layers 61D-63D, first, the higher-order topological insulator layer 20, the substrate 90, the lower superconductor layer 61A, the lower superconductor layer 61B, the lower fifth electrons on superconductor layer 62A, lower superconductor layer 62B, lower superconductor layer 63A, lower superconductor layer 63B, first gate electrode 41, second gate electrode 42 and third gate electrode 43; Spin coat the line resist. Next, by electron beam lithography, a fifth mask pattern is formed from a fifth electron beam resist.
  • the fifth mask pattern exposes portions where the tunnel barrier layers 61C-63C and upper superconductor layers 61D-63D are to be formed, and covers other portions.
  • the fifth electron beam resist for example, a resist obtained by diluting ZEP 520A (manufactured by Nippon Zeon Co., Ltd.) with ZEP-A (manufactured by Nippon Zeon Co., Ltd.) at a ratio of 1:1 can be used.
  • an NbOx layer and an Nb layer are formed by the PLD method.
  • the temperature of the substrate 90 is maintained at room temperature, and the oxygen partial pressure in the vacuum chamber is adjusted to about 50 Pa to 55 Pa.
  • the Nb layer can be formed under the same conditions as the s-wave superconductor layer 19 .
  • the fifth mask pattern is removed together with the NbOx and Nb layers deposited thereon. That is, liftoff is performed. As a result, tunnel barrier layers 61C-63C and upper superconductor layers 61D-63D are obtained, and a first SQUID 61, a second SQUID 62 and a third SQUID 63 are formed.
  • the quantum bit 1 according to the fourth embodiment can be manufactured.
  • the material of the higher topological insulator layer 20 is not limited to multi-layer WTe2 .
  • the higher topological insulator layer 20 may contain Mo, Nb, W, Ta, Ti, Zr, Fe, Pd, Ir or Pt or any combination thereof as transition metals.
  • the material of the s-wave superconductor layer 10 is not limited to Nb, and may be Al or Pd, for example.
  • the thickness of the Te layer 70 is preferably 1 nm to 20 nm, more preferably 2 nm to 15 nm, even more preferably 3 nm to 10 nm. If the Te layer 70 is excessively thick, the superconducting proximity effect of the s-wave superconductor layer may be degraded.
  • the fifth embodiment relates to a quantum arithmetic device including the quantum bit 1 according to the fourth embodiment.
  • FIG. 23 is a diagram showing a quantum arithmetic device according to the fifth embodiment.
  • the quantum arithmetic device 2 has a quantum bit chip 81, a signal generator 82, a signal demodulator 83, and a cryogenic dilution refrigerator 84, as shown in FIG.
  • a qubit chip 81 includes a plurality of qubits 1 according to the fourth embodiment.
  • a qubit chip 81 is housed in a cryogenic dilution refrigerator 84 and cooled to a temperature of 10 mK or less.
  • a signal generator 82 generates a microwave pulse signal, and the microwave pulse signal is input to the qubit chip 81 .
  • the quantum bit chip 81 outputs a signal corresponding to the microwave pulse signal, and the signal demodulator 83 demodulates the signal output from the quantum bit chip 81 .
  • the signal generator 82 and signal demodulator 83 are used, for example, at room temperature.
  • the quantum arithmetic device 2 according to the fifth embodiment includes the quantum bit 1 according to the fourth embodiment, the Majorana particles can be stably expressed, and stable computation can be performed.
  • Quantum bit 2 Quantum arithmetic device 10: s-wave superconductor layer 11: First hinge helical channel 12: Second hinge helical channel 13: Third hinge helical channel 20: Higher order topological insulator layer 21: First Region 22: Second region 23: Third region 31: First ferromagnetic insulator layer 32: Second ferromagnetic insulator layer 33: Third ferromagnetic insulator layer 41: First gate electrode 42: Second gate electrode 43: Third gate electrode 50: Groove 51: First groove 52: Second groove 53: Third groove 61: First SQUID 62: Second SQUID 63: Third SQUID 100, 200, 300: structure 110, 210: substrate 120: first layer 130: second layer 211: Si substrate 212: SiO 2 film 310: laminate 340: s-wave superconductor layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Superconductor Devices And Manufacturing Methods Thereof (AREA)
PCT/JP2021/043410 2021-11-26 2021-11-26 構造体、量子ビット、量子演算装置及び構造体の製造方法 Ceased WO2023095287A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
PCT/JP2021/043410 WO2023095287A1 (ja) 2021-11-26 2021-11-26 構造体、量子ビット、量子演算装置及び構造体の製造方法
JP2023563447A JP7729398B2 (ja) 2021-11-26 2021-11-26 構造体及び構造体の製造方法
US18/660,129 US20240306518A1 (en) 2021-11-26 2024-05-09 Structure, quantum bit, and method for manufacturing structure
JP2025114844A JP2025135013A (ja) 2021-11-26 2025-07-08 量子ビット及び量子演算装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2021/043410 WO2023095287A1 (ja) 2021-11-26 2021-11-26 構造体、量子ビット、量子演算装置及び構造体の製造方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US18/660,129 Continuation US20240306518A1 (en) 2021-11-26 2024-05-09 Structure, quantum bit, and method for manufacturing structure

Publications (1)

Publication Number Publication Date
WO2023095287A1 true WO2023095287A1 (ja) 2023-06-01

Family

ID=86539164

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2021/043410 Ceased WO2023095287A1 (ja) 2021-11-26 2021-11-26 構造体、量子ビット、量子演算装置及び構造体の製造方法

Country Status (3)

Country Link
US (1) US20240306518A1 (https=)
JP (2) JP7729398B2 (https=)
WO (1) WO2023095287A1 (https=)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2023181247A1 (https=) * 2022-03-24 2023-09-28

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20200320420A1 (en) * 2019-04-02 2020-10-08 International Business Machines Corporation Tunable superconducting resonator for quantum computing devices

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20200320420A1 (en) * 2019-04-02 2020-10-08 International Business Machines Corporation Tunable superconducting resonator for quantum computing devices

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
KONONOV ARTEM; ENDRES MARTIN; ABULIZI GULIBUSITAN; QU KEJIAN; YAN JIAQIANG; MANDRUS DAVID G.; WATANABE KENJI; TANIGUCHI TAKASHI; S: "Superconductivity in type-II Weyl-semimetal WTe2 induced by a normal metal contact", JOURNAL OF APPLIED PHYSICS, AMERICAN INSTITUTE OF PHYSICS, 2 HUNTINGTON QUADRANGLE, MELVILLE, NY 11747, vol. 129, no. 11, 19 March 2021 (2021-03-19), 2 Huntington Quadrangle, Melville, NY 11747, XP012254911, ISSN: 0021-8979, DOI: 10.1063/5.0021350 *
YOSHIDA MASARO, KUDO KAZUTAKA, NOHARA MINORU, IWASA YOSHIHIRO: "Metastable Superconductivity in Two-Dimensional IrTe 2 Crystals", NANO LETTERS, AMERICAN CHEMICAL SOCIETY, US, vol. 18, no. 5, 9 May 2018 (2018-05-09), US , pages 3113 - 3117, XP093068113, ISSN: 1530-6984, DOI: 10.1021/acs.nanolett.8b00673 *

Also Published As

Publication number Publication date
JP7729398B2 (ja) 2025-08-26
JP2025135013A (ja) 2025-09-17
US20240306518A1 (en) 2024-09-12
JPWO2023095287A1 (https=) 2023-06-01

Similar Documents

Publication Publication Date Title
Kumah et al. Epitaxial oxides on semiconductors: from fundamentals to new devices
US6753546B2 (en) Trilayer heterostructure Josephson junctions
TWI602960B (zh) Crystal-aligning laminate structure, an electronic memory, and a method of manufacturing a crystal-aligning laminate structure
JP2025135013A (ja) 量子ビット及び量子演算装置
Ngabonziza Quantum transport and potential of topological states for thermoelectricity in Bi2Te3 thin films
CA3168567A1 (en) A high-temperature superconducting qubit and fabrication method
Kneiß et al. Suppression of Grain Boundary Scattering in Multifunctional p‐Type Transparent γ‐CuI Thin Films due to Interface Tunneling Currents
CN106784279A (zh) 一种高性能掺杂钛酸锶氧化物热电薄膜的制备方法
JP7666617B2 (ja) 量子ビット、量子演算装置及び量子ビットの製造方法
Guo et al. Tunable multiple nonvolatile resistance states in a MnSe-based van der Waals multiferroic tunnel junction
US9530535B2 (en) Hydrogen-free amorphous dielectric insulating thin films with no tunneling states
WO2024023967A1 (ja) 構造体、量子ビット、量子演算装置及び構造体の製造方法
US9741921B2 (en) Hydrogen free amorphous silicon as insulating dielectric material for superconducting quantum bits
Averyanov et al. Thickness‐Dependent Superconductivity in a Layered Electride on Silicon
Cyberey et al. SuperGaN: synthesis of NbTiN/GaN/NbTiN tunnel junctions
WO2018100837A1 (ja) 磁化反転素子、磁気抵抗効果素子、集積素子及び集積素子の製造方法
JP2009302219A (ja) 超伝導配線構造
WO2024127469A1 (ja) 積層構造体、量子ビットデバイス、積層構造体の製造方法及び量子ビットデバイスの製造方法
Plucinski Band structure engineering in 3D topological insulators
JP7698225B2 (ja) トポロジカル絶縁体、量子ビット、トポロジカル絶縁体の製造方法、および量子ビットの製造方法
Zhang et al. Synthesis and characterization of PbTe thin films by atomic layer deposition
Zhou et al. Valley contrasting in epitaxial growth of In/Tl homoatomic monolayer with anomalous Nernst conductance
JP2025129796A (ja) 構造体、量子ビット、量子演算装置、構造体の製造方法及び量子ビットの製造方法
JP4795671B2 (ja) 超伝導体積層構造及びその作製方法
JP4439850B2 (ja) 微小トンネル接合回路の作製方法および微小トンネル接合回路

Legal Events

Date Code Title Description
ENP Entry into the national phase

Ref document number: 2023563447

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21965658

Country of ref document: EP

Kind code of ref document: A1