WO2023093446A1 - 一种发光二极管芯片、发光装置 - Google Patents

一种发光二极管芯片、发光装置 Download PDF

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Publication number
WO2023093446A1
WO2023093446A1 PCT/CN2022/127918 CN2022127918W WO2023093446A1 WO 2023093446 A1 WO2023093446 A1 WO 2023093446A1 CN 2022127918 W CN2022127918 W CN 2022127918W WO 2023093446 A1 WO2023093446 A1 WO 2023093446A1
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Prior art keywords
layer
electrode
ohmic contact
contact layer
emitting diode
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PCT/CN2022/127918
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English (en)
French (fr)
Inventor
熊伟平
王鑫
吴志伟
高迪
彭钰仁
郭桓邵
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泉州三安半导体科技有限公司
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Publication of WO2023093446A1 publication Critical patent/WO2023093446A1/zh
Priority to US18/667,346 priority Critical patent/US20240304759A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40—Materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/382—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending partially in or entirely through the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H01L33/46—Reflective coating, e.g. dielectric Bragg reflector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0016—Processes relating to electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0093—Wafer bonding; Removal of the growth substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen

Definitions

  • the invention relates to the technical field of semiconductors, in particular to a light emitting diode chip and a light emitting device.
  • a light emitting diode a device in which a light emitting material is contained to emit light, converts energy generated due to the recombination of electrons and holes into light emitted therefrom.
  • LED lighting has the advantages of high luminous intensity, high efficiency, small size, and long service life. It is considered to be one of the most potential light sources at present. It is widely used in fields such as lights and large-screen displays.
  • the etching angle and flatness of the opening of the insulating layer of the light-emitting diode chip are not good, so that the pad electrode is prone to produce gaps in the opening of the insulating layer.
  • tin is easy to enter through the gap, corrode the ohmic electrode containing gold element below, and affect the reliability of the chip.
  • the invention provides a light emitting diode chip with high reliability.
  • an embodiment of the present invention provides a light emitting diode chip, including:
  • a semiconductor epitaxial stack having opposite first and second surfaces including a first conductivity type semiconductor layer, a second conductivity type semiconductor layer, and a light emitting layer between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer ;
  • a first contact electrode and a second contact electrode are located on the first surface of the semiconductor epitaxial stack and are electrically connected to the first conductivity type semiconductor layer and the second conductivity type semiconductor layer, respectively;
  • the first contact electrode includes an ohmic contact layer of the first contact electrode and a first electrode barrier layer located on the ohmic contact layer of the first contact electrode;
  • the second contact electrode includes an ohmic contact layer of the second contact electrode and a second electrode barrier layer located on the ohmic contact layer of the second contact electrode;
  • the ohmic contact layer of the first contact electrode includes a first ohmic contact layer
  • the ohmic contact layer of the second contact electrode includes a second ohmic contact layer, and another first ohmic contact layer disposed between the second ohmic contact layer and the second electrode barrier layer.
  • the thickness of the ohmic contact layer of the second contact electrode is greater than the thickness of the ohmic contact layer of the first contact electrode.
  • the ohmic contact layer of the first contact electrode is composed of an n1-layer metal stack
  • the ohmic contact layer of the second contact electrode is composed of an n2-layer metal stack, where n1 ⁇ n2 .
  • the ohmic contact layer of the first contact electrode comprises a first ohmic contact layer
  • the ohmic contact layer of the second contact electrode includes a second ohmic contact layer, and a first ohmic contact layer located between the second ohmic contact layer and the second electrode barrier layer.
  • the first ohmic contact layer covers at least the upper surface of the second ohmic contact layer.
  • the first ohmic contact layer of the second contact electrode also covers an inclined side surface of the second ohmic contact layer.
  • the thickness of the first ohmic contact layer on the inclined side of the second ohmic contact layer is smaller than the thickness of the upper surface covered by the second ohmic contact layer. The thickness of the first ohmic contact layer.
  • the first electrode barrier layer and the second electrode barrier layer are composed of the same material.
  • the first ohmic contact layer includes Au, Ge, Ni or an alloy of any combination thereof or a stack of any combination thereof.
  • the thickness of the first ohmic contact layer is not less than 0.1 ⁇ m and not more than 2 ⁇ m.
  • the second ohmic contact layer includes Au, Be, Zn or an alloy of any combination thereof or a stack of any combination thereof.
  • the thickness of the second ohmic contact layer is not less than 0.1 ⁇ m and not more than 2 ⁇ m.
  • the first electrode barrier layer and the second electrode barrier layer include Ti, Pt, Cr or an alloy of any combination thereof or a stack of any combination thereof.
  • the thickness of the first electrode barrier layer and the second electrode barrier layer is not less than 0.1 ⁇ m and not more than 1 ⁇ m.
  • the wavelength radiated by the LED chip is 580-1000 nm.
  • the LED chip also includes:
  • the insulating layer is located on the semiconductor epitaxial stack, which at least covers the edge region and the sidewall of the semiconductor epitaxial stack.
  • a first pad electrode arranged on the upper portion of the insulating layer and electrically connected to the first contact electrode through the first opening of the insulating layer;
  • the second pad electrode is arranged on the upper part of the insulating layer, and is electrically connected to the second contact electrode through the second opening of the insulating layer.
  • the first pad electrode and the second pad electrode include Ti, Al, Pt, Au, Ni, Sn, In, or an alloy of any combination thereof or a stack of any combination thereof .
  • the width of the lower opening of the first opening and the second opening is smaller than the width of the upper surface of the electrode barrier layer located below the first opening and the second opening.
  • the first opening and/or the second opening has inclined sides, and the angle of inclination of the inclined sides is within 80° relative to the bottom surface.
  • the LED chip also includes:
  • a substrate is located on the second surface of the semiconductor epitaxial stack.
  • the LED chip also includes:
  • the bonding layer is located between the substrate and the semiconductor epitaxial stack.
  • At least part of the surface of the semiconductor epitaxial stack in contact with the bonding layer is a roughened surface.
  • An embodiment of the present invention also provides a light emitting device having the light emitting diode chip as described above.
  • the light emitting diode chip provided by the present invention can improve the reliability of the light emitting diode chip by adjusting the composition of the first contact electrode and the second contact electrode.
  • FIG. 1 is a schematic cross-sectional structure diagram of an existing light-emitting diode chip
  • FIG. 2 is a schematic diagram and an enlarged view of a cross-sectional structure of a light-emitting diode chip used to illustrate an embodiment of the present invention
  • FIG. 3 is a schematic cross-sectional structure diagram of a light-emitting diode chip used to illustrate another embodiment of the present invention.
  • 4 to 12 are cross-sectional views illustrating a method of manufacturing a light emitting diode chip according to an embodiment of the present invention.
  • the orthogonal coordinate system xyz is defined, and the positive side of z direction is made into upper direction.
  • FIG. 2 is a cross-sectional view of an LED chip according to an embodiment of the present invention.
  • an embodiment of the present invention provides a light emitting diode chip, including: a substrate 10, a semiconductor epitaxial stack 20, a first contact electrode 31. The second contact electrode 41 and the bonding layer 70.
  • the light emitting diode chip can be a conventional size light emitting diode chip.
  • the light emitting diode chip may have a horizontal cross-sectional area of about 90,000 ⁇ m 2 or more and about 2,000,000 ⁇ m 2 or less.
  • the light-emitting diode chip can also be a small-sized or micro-sized light-emitting diode chip.
  • the light emitting diode chip may have a horizontal cross-sectional area of about 90000 ⁇ m 2 or less.
  • the light emitting diode chip may have a length and/or width of not less than 100 ⁇ m and not more than 300 ⁇ m, and further may have a thickness of not less than 40 ⁇ m and not more than 100 ⁇ m.
  • the light emitting diode chip can also be a miniature light emitting diode chip with a smaller size.
  • the light emitting diode chip may have a light emitting diode chip having a horizontal cross-sectional area of about 10000 ⁇ m 2 or less.
  • the light emitting diode chip may have a length and/or width of not less than 2 ⁇ m and not more than 100 ⁇ m, and further may have a thickness of not less than 2 ⁇ m and not more than 100 ⁇ m.
  • the light emitting diode chip of this embodiment can have the above-mentioned horizontal cross-sectional area and thickness, so the light emitting diode chip can be easily applied to various electronic devices requiring small and/or micro light emitting devices.
  • the semiconductor epitaxial stack 20 has a first surface 20 a and a second surface 20 b opposite to the first surface 20 a.
  • the semiconductor epitaxial stack 20 includes a first conductivity type semiconductor layer 21, a second conductivity type semiconductor layer 23, and a light emitting layer 22 located between the first conductivity type semiconductor layer 21 and the second conductivity type semiconductor layer 23; wherein, the first surface 20 a is the upper surface of the first conductivity type semiconductor layer 21 , and the second surface 20 b is the lower surface of the second conductivity type semiconductor layer 23 .
  • the first conductivity type semiconductor layer 21 and the second conductivity type semiconductor layer 23 have different conductivity types, electrical properties, polarities or doped elements to provide electrons or holes, that is: the first conductivity type semiconductor layer 21 has A first conductivity, the second conductivity type semiconductor layer 23 has a second conductivity, wherein the first conductivity is different from the second conductivity, for example, the first conductivity type semiconductor layer 21 can be an n-type semiconductor layer, the second The conductivity type semiconductor layer 23 can be a p-type semiconductor layer. Electrons from the n-type semiconductor layer and holes from the p-type semiconductor layer are driven by an external current to convert electrical energy into light energy in the light-emitting layer 22 and emit light.
  • the semiconductor epitaxial stack 20 is gallium arsenide (gallium arsenide) arsenide, GaAs) series materials, wherein the doping of the semiconductor layer 21 of the first conductivity type is N-type, and the doping of the semiconductor layer 23 of the second conductivity type is P-type.
  • the material of the first conductivity type semiconductor layer 21 includes a II-VI group material (for example, zinc selenide (ZnSe)) or a III-V nitrogen compound material (for example, gallium arsenide ( GaAs), Gallium Nitride (GaN), Aluminum Nitride (AlN), Indium Nitride (InN), Indium Gallium Nitride (InGaN), Aluminum Gallium Nitride (AlGaN), or Aluminum Indium Gallium Nitride (AlInGaN)), Moreover, the material of the first conductive type semiconductor layer 21 may also include dopants such as silicon (Si) or germanium (Ge), but the embodiment of the present disclosure is not limited thereto. In some other embodiments, the first conductivity type semiconductor layer 21 may also be a single-layer or multi-layer structure.
  • a II-VI group material for example, zinc selenide (ZnSe)
  • a III-V nitrogen compound material for example, gallium arsenide ( GaAs), Gallium Ni
  • the material of the second conductivity type semiconductor layer 23 includes III-V nitrogen compound materials (for example, gallium arsenide (GaAs), gallium nitride (GaN), aluminum nitride (AlN) , indium nitride (InN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN) or aluminum indium gallium nitride (AlInGaN)), and the material of the second conductivity type semiconductor layer 23 may include magnesium ( Mg), carbon (C) and other dopants, but the embodiments of the present disclosure are not limited thereto.
  • the second conductivity type semiconductor layer 23 may also be a single-layer or multi-layer structure.
  • gallium arsenide (GaAs) series semiconductor materials are used for the light emitting layer 22 .
  • the light-emitting layer 22 is based on aluminum indium gallium phosphide (AlGaInP) series, gallium arsenide (GaAs) series semiconductor materials, it can emit red light, orange light or yellow light; Indium (AlGaInN) series semiconductor materials can emit blue or green light.
  • the light-emitting layer 22 may include at least one undoped (un-doped) semiconductor layer or at least one low-doped semiconductor layer.
  • the light-emitting layer 22 may be a single heterostructure (single heterostructure; SH), a double heterostructure (double heterostructure; DH), a double-sided double heterostructure (double-side double heterostructure; DDH), or a multi-quantum well structure (multi-quantumwell; MQW), but the embodiments of the present disclosure are not limited thereto.
  • the substrate 10 is disposed on the second surface 1 b of the semiconductor epitaxial stack 20 through the bonding layer 70 .
  • the substrate 10 is a sapphire substrate.
  • the substrate 10 may be a transparent substrate, and the material of the transparent substrate includes inorganic materials or group III-V semiconductor materials.
  • the inorganic material includes silicon carbide (SiC), germanium (Ge), sapphire, lithium aluminate (LiAlO 2 ), zinc oxide (ZnO), glass, or quartz.
  • Group III-V semiconductor materials include indium phosphide (InP), gallium phosphide (GaP), gallium nitride (GaN), and aluminum nitride (AlN) materials.
  • the substrate 10 has sufficient strength to mechanically support the semiconductor epitaxial stack 20 and transmits light emitted from the semiconductor epitaxial stack 20 .
  • the thickness of the substrate 10 is preferably 50 ⁇ m or more. In addition, in order to facilitate machining of the substrate 10 after bonding to the semiconductor epitaxial stack 20, the thickness is preferably not more than 300 ⁇ m.
  • the light emitting diode chip of the present invention is not limited to only one semiconductor light emitting stack 20, and may also include a plurality of semiconductor light emitting stacks 20 located on the substrate 10, wherein the plurality of semiconductor light emitting stacks 20 can be There is a wire structure to electrically connect a plurality of semiconductor light-emitting stacks 20 on the substrate 10 in series, parallel, series-parallel and other ways.
  • the LED chip includes a bonding layer 70, the bonding layer 70 covers the second surface 1b of the semiconductor epitaxial stack 20, and the substrate 10 is bonded The layer 70 is bonded and formed on the second surface 1b, and the light emitted by the light emitting layer 23 can pass through the bonding layer 70 and the substrate 10 .
  • the light emitting surface of the LED chip is the surface of the substrate 10 away from the semiconductor epitaxial stack 20 .
  • the material of the bonding layer 70 may be an insulating material and/or a conductive material.
  • Insulating materials include but are not limited to polyimide (PI), benzocyclobutene (BCB), perfluorocyclobutane (PFCB), magnesium oxide (MgO), Su8, epoxy resin (Epoxy), acrylic resin (AcrylicResin ), cycloolefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide (Polyetherimide), fluorocarbon Polymer (FluorocarbonPolymer), Glass (Glass), Aluminum Oxide (Al 2 O 3 ), Silicon Oxide (SiO x ), Titanium Oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), Silicon Nitride (SiN x ) or spin-on-glass (SOG).
  • PI polyimide
  • BCB benzocyclobutene
  • Conductive materials include but are not limited to indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide ( ZTO), zinc oxide (ZnO), indium zinc oxide (IZO), diamond-like carbon film (DLC) or gallium zinc oxide (GZO), etc.
  • ITO indium tin oxide
  • InO indium oxide
  • SnO tin oxide
  • CTO cadmium tin oxide
  • ATO antimony tin oxide
  • zinc tin oxide ( ZTO) zinc oxide
  • ZnO zinc oxide
  • IZO indium zinc oxide
  • DLC diamond-like carbon film
  • GZO gallium zinc oxide
  • the second surface 20b of the semiconductor epitaxial stack 20 close to the substrate 10 can be a rough surface, and when the light emitted by the light emitting layer 22 passes through the bonding layer 70 and the second surface 20b, total reflection can be reduced. the occurrence of the situation.
  • the refractive index of the bonding layer 70 is preferably between the refractive index of the second conductivity type semiconductor layer 23 and the refractive index of the substrate 10 .
  • the second conductivity type semiconductor layer 23 has a refractive index n1
  • the bonding layer 70 has a refractive index n2
  • the substrate 10 has a refractive index n3, wherein the refractive index n1>refractive index n2>refractive index n3.
  • the refractive index of the bonding layer 70 is in the range of 1.2-3.
  • the bonding layer 70 is a stacked structure, and the number of bonding layers in the stacked structure is not limited to 2 layers, and may be more than 2 layers.
  • the bonding layer 70 includes a first bonding layer 71 close to the second conductive type semiconductor layer 23 and a second bonding layer 72 far away from the second conductive type semiconductor layer 23 .
  • the first bonding layer 71 is adjacent to the second conductive type semiconductor layer 23
  • the second bonding layer 72 is adjacent to the substrate 10 .
  • the first bonding layer 71 and the second bonding layer 72 are sequentially formed on the second conductive type semiconductor layer 23 to form the bonding layer 70 .
  • the first bonding layer 71 is a transparent conductive layer capable of spreading current
  • the second bonding layer 71 is a bonding material layer capable of bonding the substrate 10 .
  • the bonding layer 70 is a structure with a graded refractive index, and the refractive index m1 of the first bonding layer 71 close to the second conductive type semiconductor layer 23 is different from that of the first bonding layer 71 far away from the second conductive type semiconductor layer 23.
  • the refractive index m2 of the bonding layer 72 is a continuous change or A gradient change changes the traveling direction of light from the light-emitting layer 23 to the substrate 10 through the change of the refractive index, reduces the probability of total reflection of the light, and prevents the light from being confined inside the LED chip.
  • the semiconductor epitaxial stack 20 includes at least one recess that at least partially penetrates the first conductivity type semiconductor layer 21 and the light emitting layer 22 to expose the second conductivity type semiconductor layer 23.
  • the mesa region M may be defined as a region where the first conductive type semiconductor layer 21 , the light emitting layer 22 , and the second conductive type semiconductor layer 23 are not etched.
  • the mesa region M may have a relatively protruding shape compared to the recessed region E in the z direction.
  • the recessed area E can also be defined as an etched area.
  • the embodiments of the present disclosure are not limited thereto.
  • the mesa region M can also be defined as a region where the first conductivity type semiconductor layer 21, the light emitting layer 22, and the second conductivity type semiconductor layer 23 are not etched, while the first conductivity type semiconductor layer in the recessed region E A portion of the semiconductor layer 21 of one conductivity type is removed.
  • the mesa region M may gradually narrow in an upward direction. Accordingly, the mesa region M may have inclined side surfaces.
  • the light emitting diode chip includes one or more first contact electrodes 31 located on the first conductivity type semiconductor layer 21 and electrically connected to the first conductivity type semiconductor layer 21 directly or indirectly, and located on the second conductivity type semiconductor layer 23 and One or more second contact electrodes 41 are electrically connected directly or indirectly to the second conductivity type semiconductor layer 23 .
  • first contact electrode 31 refers to the n-side contact electrode
  • first contact electrode 31 refers to the p side contact electrodes.
  • the second contact electrode 41 is opposite to the first contact electrode 31 .
  • the pad electrodes do not contain tin elements, but solder paste soldering is selected in the packaging process.
  • the tin has strong fluidity, and the tin contained in the solder paste can easily pass through the pad electrodes.
  • the slits enter the interior to corrode the ohmic electrodes containing Au, Sn, or In underneath, thereby affecting the reliability of the chip.
  • the tin has strong fluidity, so that when the pad electrode contains tin, the tin can easily enter the interior through the gap of the pad electrode, corrode the underlying ohmic electrode containing gold, and affect the reliability of the chip.
  • the first contact electrode 31 and the second contact electrode 41 may be metal electrodes, for example, nickel, gold, chromium, titanium, platinum, palladium, rhodium, iridium, aluminum, tin, indium, tantalum, copper, cobalt , iron, ruthenium, zirconium, tungsten, molybdenum, and one or a combination thereof.
  • the first contact electrode 31 includes the ohmic contact layer of the first contact electrode 31 and the The first electrode barrier layer 51 on the ohmic contact layer of the first contact electrode 31; preferably, the first contact electrode 31 is an n-side contact electrode.
  • the first electrode barrier layer 51 includes Ti, Pt, Cr or an alloy of any combination thereof or a stack of any combination of them.
  • the embodiments disclosed in the present invention are not limited thereto, and may also be other A metal that reacts with Sn or an alloy of a combination of multiple metals or a laminate of any combination of them.
  • the first ohmic contact layer is Au, Ge or Au, Ni or an alloy of Au, Ge, Ni, or a stack of Au, Ge or Au, Ni or Au, Ge, Ni, and the
  • the second ohmic contact layer is an alloy of Au, Be or Au, Zn or Au, Be, Zn, or a stack of Au, Be or Au, Zn or Au, Be, Zn, since the second ohmic contact layer adopts
  • the material contains Au and Be and/or Zn at the same time, resulting in the fusion temperature of the electrode being as high as 500°C or more, and the electrode barrier material is difficult to withstand such a high temperature, therefore, it cannot be directly connected to the unfused second ohmic contact layer.
  • the electrode barrier layer is directly vapor-deposited on the surface; instead, the electrode barrier layer needs to be evaporated after the second ohmic contact layer is fused, resulting in complicated procedures;
  • the second contact electrode 41 includes the ohmic electrode of the second contact electrode 41.
  • the second electrode barrier layer 52 includes Ti, Pt, Cr or an alloy of any combination thereof or a laminate of any combination thereof, the embodiments disclosed by the present invention are not limited thereto, and may also be other The reacted metal or the alloy of a combination of metals or a stack of any combination of them.
  • the first electrode barrier layer 51 and the second electrode barrier layer 52 are composed of the same material, but not limited thereto, the first electrode barrier layer 51 and the second electrode barrier layer
  • the electrode barrier layer 52 can also be composed of different materials.
  • the thickness of the ohmic contact layer of the second contact electrode 41 is greater than the thickness of the first contact electrode 31 .
  • the thickness of the first electrode barrier layer 51 and the second electrode barrier layer 52 is more than 0.1 ⁇ m and less than 1 ⁇ m. If the electrode barrier layer is too thin, it will be easily etched during the subsequent etching process of the insulating layer 60, resulting in loss of function. Too thick will increase the manufacturing cost.
  • the first contact electrode 31 is an n-side contact electrode
  • the second contact electrode 41 is a p-side contact electrode.
  • the first contact electrode 31 includes a first ohmic contact layer 31a and a first electrode barrier layer 51 located on the first ohmic contact layer 31a;
  • the second contact electrode 41 includes a second ohmic contact layer 41a, located on the second The second electrode barrier layer 52 on the ohmic contact layer 41 a and the first ohmic contact layer 31 a between the second ohmic contact layer 41 a and the second electrode barrier layer 52 .
  • a first ohmic contact layer 31a is covered on the second ohmic contact layer 41a to ensure that the second electrode barrier layer 52
  • the surface of the first ohmic contact layer 31 a is formed by vapor deposition, so as to prevent tin from entering through the gap at the opening of the insulating layer and corroding the contact electrodes below.
  • the covering method is to completely cover the second ohmic contact layer 41a, so as to To prevent the deviation of the first ohmic contact layer 31a from exposing part of the second ohmic contact layer 32a, thereby affecting the reliability of the light emitting diode chip, and the complete covering method is not easy to expose the second ohmic contact layer 32a.
  • the embodiments disclosed in the present invention are not limited thereto.
  • the first ohmic contact layer covers at least the upper surface of the second ohmic contact layer .
  • the first ohmic contact layer of the second contact electrode also covers the inclined side surface of the second ohmic contact layer. Further optionally, in the ohmic contact layer of the second contact electrode, the thickness of the first ohmic contact layer on the inclined side of the second ohmic contact layer is smaller than the thickness of the first ohmic contact layer covered on the upper surface of the second ohmic contact layer. The thickness of the one-ohm contact layer.
  • the thickness of the first ohmic contact layer 31 a is not less than 0.1 ⁇ m and not more than 2 ⁇ m. If the thickness of the first ohmic contact layer 31 a is too thin, the formation of ohmic contact will be unfavorable, and if the thickness of the first ohmic contact layer 31 a is too thick, it will be unfavorable to cover the electrode barrier layer.
  • the material of the first ohmic contact layer 31 a includes Au, Ge, Ni, or an alloy of any combination thereof, or a stack of any combination thereof. In this embodiment, the material of the first ohmic contact layer 31a is Au/Ge/Ni.
  • the material of the first ohmic contact layer 31a may be a metal layer containing Au, or an alloy layer containing Au, etc., the embodiments disclosed in the present invention are not limited thereto, the first The material of the ohmic contact layer 31a may also be an alloy of any combination of Au and Ge or Ni or a stack of any combination thereof; the disclosed embodiments of the present invention are not limited thereto, the first ohmic contact layer 31a
  • the material can also be other metals that easily react with Sn or alloys of multiple metals or any combination of them.
  • the thickness of the second ohmic contact layer 41a is not less than 0.1 ⁇ m and not more than 2 ⁇ m. If the thickness of the second ohmic contact layer 41a is too thin, it will be unfavorable for the formation of ohmic contact, and if it is too thick, it will be unfavorable for the coverage of the electrode barrier layer. .
  • the second ohmic contact layer 41 a includes Au, Be, Zn or an alloy of any combination thereof or a stack of any combination thereof. In this embodiment, the material of the second ohmic contact layer 41a is Au/Be. In another embodiment, the material of the second ohmic contact layer 41a is Au/Zn.
  • the material of the second ohmic contact layer 41a may be a metal layer containing Au, or an alloy layer containing Au, etc., the embodiments disclosed in the present invention are not limited thereto, the second The material of the ohmic contact layer 41a may also be an alloy of any combination of Au and Be or Zn or a stack of any combination thereof; the disclosed embodiments of the present invention are not limited thereto, the second ohmic contact layer 41a The material can also be other metals that easily react with Sn or alloys of multiple metals or any combination of them.
  • the insulating layer 60 covers the upper surface and side surfaces of the semiconductor epitaxial stack 20, and covers the first contact electrode 31 and the second contact electrode 41.
  • the insulating layer 60 can be extended to partially expose the periphery of the semiconductor epitaxial stack 20.
  • the upper surface of the substrate 10 is formed.
  • the insulating layer 60 can be in contact with the upper surface of the substrate 10 , and thus can more stably cover the side surfaces of the semiconductor epitaxial stack 20 .
  • the insulating layer 60 extends from the semiconductor epitaxial stack 20 to cover part of the upper surface 11 of the substrate 10 , and exposes a portion around the upper surface 11 of the substrate 10 . That is, the periphery of the upper surface 11 of the substrate 10 is not covered with the insulating layer 60 . Thus, in the process of dividing the wafer to form a plurality of light-emitting diode chips, it is prevented from being damaged by laser light etc.
  • the damage (for example, peeling, cracking, etc.) of the insulating layer 60 is caused.
  • the insulating layer 60 includes a distributed Bragg reflector, if the insulating layer 60 is damaged, on the one hand, the light reflectivity will decrease, and on the other hand, the leakage problem will easily occur. According to the present embodiment, it is also possible to prevent problems such as a decrease in luminous efficiency and chip abnormality due to such damage to the insulating layer 60 .
  • the first pad electrode 32 and the second pad electrode 42 are disposed on the upper portion of the insulating layer 60 .
  • the first pad electrode 32 may be electrically connected to the first contact electrode 31 through the first opening 61 of the insulating layer 60 .
  • the second pad electrode 42 may be electrically connected to the second contact electrode 41 through the second opening 62 .
  • the first opening 61 and the second opening 62 can be in a circular shape, and in some other embodiments, the first opening 61 and the second opening 62 can also be square, etc., the shape of each opening
  • the number of openings is not particularly limited, and only one opening may be provided. If multiple openings are provided, the current can be more evenly distributed.
  • the first pad electrode includes Ti, Al, Pt, Au, Ni, Sn or an alloy of any combination thereof or a stack of any combination thereof.
  • the second pad electrode includes Ti, Al, Pt, Au, Ni, Sn or an alloy of any combination thereof or a stack of any combination thereof.
  • the width of the lower opening of the first opening 61 is smaller than the width of the upper surface of the first electrode barrier layer 51 located below the first opening 61 , that is, the lower opening of the first opening 61
  • the orthographic projection on the horizontal plane is within the range of the orthographic projection of the upper surface of the first electrode barrier layer 51 below the first opening 61 on the horizontal plane, so as to protect the contact electrodes below.
  • the difference between the width of the lower opening of the first opening 61 and the width of the upper surface of the first electrode barrier layer 51 below the first opening 61 is more than 5 ⁇ m. If the difference is too small, the first opening may occur. An opening 61 deviates from the position of the first electrode barrier layer 51 .
  • the width of the lower opening of the second opening 62 is smaller than the width of the upper surface of the second electrode barrier layer 52 located below the second opening 62 , that is, the lower opening of the second opening 62
  • the orthographic projection on the horizontal plane is within the range of the orthographic projection of the upper surface of the second electrode barrier layer 52 below the second opening 62 on the horizontal plane, so as to protect the contact electrodes below.
  • the difference between the width of the lower opening of the second opening 62 and the width of the upper surface of the second electrode barrier layer 52 below the second opening 62 is more than 5 ⁇ m. If the difference is too small, the second opening may occur.
  • the second opening 62 deviates from the position of the second electrode barrier layer 52 .
  • the first opening 61 and/or the second opening 62 have inclined sides, and the inclination angle ⁇ of the inclined sides is within 80° relative to the bottom surface, so as to avoid The sidewall of the hole in the insulating layer 60 is completely fractured, resulting in no conduction.
  • 4 to 12 are cross-sectional views for illustrating the method of manufacturing the LED chip according to the embodiment shown in FIG. 2 of the present invention.
  • the semiconductor epitaxial stack 20 is formed on the growth substrate 80, which can generally be grown by known various methods, for example, metalorganic chemical vapor deposition (Metal Organic Chemical VaporDeposition, MOCVD), molecular beam epitaxy (Molecular Beam Epitaxy, MBE) or hydride vapor phase epitaxy (Hydride Vapor Phase Epitaxy, HVPE) and other growth techniques.
  • MOCVD Metal Organic Chemical VaporDeposition
  • MBE molecular beam epitaxy
  • HVPE hydride vapor phase epitaxy
  • the growth substrate 80 is a gallium arsenide substrate.
  • the semiconductor epitaxial stack 20 is gallium arsenide (gallium arsenide, GaAs) series of materials, the semiconductor epitaxial stack 20 includes a first conductivity type semiconductor layer 21, a second conductivity type semiconductor layer 23 and a semiconductor layer located between the first conductivity type semiconductor layer 21 and the second conductivity type semiconductor layer 23 The luminescent layer 22.
  • gallium arsenide gallium arsenide, GaAs
  • the method of forming the roughened surface is not particularly limited, for example, etching or mechanical grinding can be used.
  • a bonding layer 70 is deposited on the surface of the roughened semiconductor layer 23 of the second conductivity type, and the surface of the bonding layer 70 is polished, and the bonding layer 70 is silicon dioxide.
  • the growth substrate 80 is removed, and the semiconductor epitaxial stack 20 is bonded to the substrate 10 through the bonding layer 70 , and the substrate 10 is a sapphire substrate.
  • a photoresist pattern is formed on the surface of the semiconductor epitaxial stack 20, and the semiconductor epitaxial stack 20 exposing the edge of the chip is removed to form a dicing line.
  • a first contact electrode 31 and a second contact electrode 32 are formed on the surface of the semiconductor epitaxial stack 20;
  • a layer of the first ohmic contact layer 31a is simultaneously covered on the second ohmic contact layer 32a, and then an electrode barrier layer is evaporated on the surfaces of the two pairs of first ohmic contact layers 31a,
  • the evaporation of the first electrode barrier layer 51 and the second electrode barrier layer 52 can be performed step by step according to the material selection of the actual electrode barrier layer, or can be evaporated simultaneously, and the embodiments of the present disclosure are not limited thereto.
  • an insulating layer 70 is deposited.
  • the insulating layer 70 completely covers the surface of the semiconductor epitaxial stack 20 , the sidewalls of the semiconductor epitaxial stack 20 , and the exposed surface of the bonding layer 70 .
  • the first opening 61 and the second opening 62 are formed in the insulating layer 70 on the first conductivity type semiconductor layer 21 and the second conductivity type semiconductor layer 23 respectively, and the first pad electrode 32 and the second pad electrode 32 are prepared.
  • the pad electrode 42 is electrically connected to the first conductivity type semiconductor layer 21 and the second conductivity type semiconductor layer 23 respectively through the corresponding first opening 61 and the second opening 62 .

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Abstract

本发明涉及一种发光二极管芯片包括：半导体外延叠层，具有相对的第一表面和第二表面，包括第一导电类型半导体层、第二导电类型半导体层以及位于第一导电类型半导体层和第二导电类型半导体层之间的发光层；第一接触电极和第二接触电极，位于所述半导体外延叠层的第一表面之上，分别与所述第一导电类型半导体层和所述第二导电类型半导体层电连接；所述第一接触电极包括第一接触电极的欧姆接触层以及位于所述第一接触电极的欧姆接触层之上的第一电极阻挡层；所述第二接触电极包括第二接触电极的欧姆接触层以及位于所述第二接触电极的欧姆接触层之上的第二电极阻挡层。本发明提供的发光二极管芯片具有高可靠性。

Description

一种发光二极管芯片、发光装置 技术领域
本发明涉及半导体技术领域，特别涉及一种发光二极管芯片、发光装置。
 背景技术
发光二极管(LED) (其中包含发光材料以发光的器件)将由于电子和空穴的复合而产生的能量转换成从其发射的光。与传统的电气照明方式相比，LED照明具有发光强度大、效率高、体积小、使用寿命长等优点，被认为是当前最具有潜力的光源之一，在照明、信号显示、背光源、车灯和大屏幕显示等领域得到广泛的应用。
现有技术中，发光二极管芯片的绝缘层开口的蚀刻角度及平整度不佳，使得焊盘电极在绝缘层开口内容易产生缝隙，参考图1所示，在经由锡膏焊接或者采用锡电极时，锡容易经缝隙进入，侵蚀下方的含有金元素的欧姆电极，影响芯片的可靠性。
 技术解决方案
本发明提供一种可靠性高的发光二极管芯片。
本发明所采用的技术方案具体如下：
具体来说，本发明一实施例提供一种发光二极管芯片，包括：
半导体外延叠层，具有相对的第一表面和第二表面，包括第一导电类型半导体层、第二导电类型半导体层以及位于第一导电类型半导体层和第二导电类型半导体层之间的发光层；
第一接触电极和第二接触电极，位于所述半导体外延叠层的第一表面之上，分别与所述第一导电类型半导体层和所述第二导电类型半导体层电连接；
所述第一接触电极包括第一接触电极的欧姆接触层以及位于所述第一接触电极的欧姆接触层之上的第一电极阻挡层；
所述第二接触电极包括第二接触电极的欧姆接触层以及位于所述第二接触电极的欧姆接触层之上的第二电极阻挡层；
所述第一接触电极的欧姆接触层包括一第一欧姆接触层；
所述第二接触电极的欧姆接触层包括一第二欧姆接触层，以及设置于第二欧姆接触层和第二电极阻挡层之间的另一第一欧姆接触层。
在一些实施例中，所述第二接触电极的欧姆接触层的厚度大于所述第一接触电极的欧姆接触层的厚度。
在一些实施例中，所述第一接触电极的欧姆接触层由n1层的金属叠层组成，所述第二接触电极的欧姆接触层由n2层的的金属叠层组成，所述n1＜n2。
在一些实施例中，所述第一接触电极的欧姆接触层包括第一欧姆接触层；
所述第二接触电极的欧姆接触层包括第二欧姆接触层，以及位于第二欧姆接触层和第二电极阻挡层之间的第一欧姆接触层。
在一些实施例中，在所述第二接触电极的欧姆接触层中，所述第一欧姆接触层至少覆盖所述第二欧姆接触层的上表面。
在一些实施例中，在所述第二接触电极的欧姆接触层中，所述第一欧姆接触层还覆盖所述第二欧姆接触层的倾斜侧面。
在一些实施例中，在所述第二接触电极的欧姆接触层中，所述第二欧姆接触层的倾斜侧面上的第一欧姆接触层的厚度小于所述第二欧姆接触层上表面覆盖的第一欧姆接触层的厚度。
在一些实施例中，所述第一电极阻挡层和第二电极阻挡层由相同的材料组成。
在一些实施例中，所述第一欧姆接触层包括Au、Ge、Ni或它们中的任意组合的合金或它们中的任意组合的叠层。
在一些实施例中，所述第一欧姆接触层的厚度在0.1μm以上且2μm以下。
在一些实施例中，所述第二欧姆接触层包括Au、Be、Zn或它们中的任意组合的合金或它们中的任意组合的叠层。
在一些实施例中，所述第二欧姆接触层的厚度在0.1μm以上且2μm以下。
在一些实施例中，所述第一电极阻挡层和第二电极阻挡层包括Ti、Pt、Cr或它们中的任意组合的合金或它们中的任意组合的叠层。
在一些实施例中，所述第一电极阻挡层和第二电极阻挡层的厚度在0.1μm以上且1μm以下。
在一些实施例中，所述发光二极管芯片辐射出的波长为580~1000nm。
在一些实施例中，所述发光二极管芯片还包括：
绝缘层，位于所述半导体外延叠层上，其至少覆盖所述半导体外延叠层的边缘区域及侧壁。
第一焊盘电极，布置于所述绝缘层的上部，并通过所述绝缘层的第一开口电连接至所述第一接触电极；
第二焊盘电极，布置于所述绝缘层的上部，并通过所述绝缘层的第二开口电连接至所述第二接触电极。
在一些实施例中，所述第一焊盘电极和第二焊盘电极包括Ti、Al、Pt、Au、Ni、Sn、In或它们中的任意组合的合金或它们中的任意组合的叠层。
在一些实施例中，所述第一开口和第二开口的下开口宽度小于位于所述第一开口和第二开口下方的电极阻挡层的上表面宽度。
在一些实施例中，所述第一开口和/或所述第二开口具有倾斜的侧面，所述倾斜的侧面的倾斜角度相对于底面在80°以内。
在一些实施例中，所述发光二极管芯片还包括：
衬底，位于所述半导体外延叠层的第二表面之上。
在一些实施例中，所述发光二极管芯片还包括：
键合层，位于所述衬底与所述半导体外延叠层之间。
在一些实施例中，至少部分所述半导体外延叠层与所述键合层相接触的表面为粗化面。
本发明实施例还提供一种发光装置，具有如上所述的发光二极管芯片。
 有益效果
本发明提供的发光二极管芯片通过调整第一接触电极和第二接触电极的组成，可提升发光二极管芯片的可靠性。
 附图说明
图1为现有的发光二极管芯片的剖面结构示意图；
图2是用以说明本发明的一实施例的发光二极管芯片的剖面结构示意图及放大图；
图3是用以说明本发明的另一实施例的发光二极管芯片的剖面结构示意图；
图4至图12是用以说明本发明的一实施例的发光二极管芯片的制造方法的剖面图。
附图标记：
10衬底； 20半导体外延叠层； 20a第一表面； 20b第二表面；21第一导电类型半导体层； 22发光层； 23第二导电类型半导体层31第一接触电极； 31a第一欧姆接触层； 32第一焊盘电极；41第二接触电极； 41a第二欧姆接触层； 42第二焊盘电极； 51第一电极阻挡层； 52第二电极阻挡层；60绝缘层； 61第一开口； 62第二开口70键合层； 71第一键合层； 72第二键合层80生长衬底；E 凹陷区域； M台面区域。
 本发明的实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例；下面所描述的本发明不同实施方式中所设计的技术特征只要彼此之间未构成冲突就可以相互结合；基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
另外，在以下的说明中，为了方便，定义正交坐标系xyz并将z方向的正侧设为上方。
图2为本发明一实施例的一种发光二极管芯片的剖面图。
请参考图2，为达本发明欲实现的优点至少其中之一或其他优点，本发明的一实施例提供一种发光二极管芯片，包括：衬底10、半导体外延叠层20、第一接触电极31、第二接触电极41及键合层70。
发光二极管芯片可为常规尺寸的发光二极管芯片。发光二极管芯片可具有约90000μm 2以上且约2000000μm 2以下的水平截面积。
发光二极管芯片也可为小尺寸或者微尺寸的发光二极管芯片。发光二极管芯片可具有约90000μm 2以下的水平截面积。例如，发光二极管芯片的可具有100μm以上至300μm以下的长度和/或宽度，进而可具有40μm以上至100μm以下的厚度。
发光二极管芯片还可为更小尺寸的微型发光二极管芯片。发光二极管芯片可具有约10000μm 2以下的水平截面积的发光二极管芯片。例如，发光二极管芯片可具有2μm以上至100μm以下的长度和/或宽度，进而可具有2μm以上至100μm以下的厚度。本实施例的发光二极管芯片可以具有上述水平截面积及厚度，因此所述发光二极管芯片可容易地应用到要求小型和/或微型发光装置的各种电子装置。
请再参考图2，半导体外延叠层20具有第一表面20a和与第一表面20a相对的第二表面20b。半导体外延叠层20包括第一导电类型半导体层21、第二导电类型半导体层23以及位于第一导电类型半导体层21和第二导电类型半导体层23之间的发光层22；其中，第一表面20a为第一导电类型半导体层21的上表面，第二表面20b为第二导电类型半导体层23的下表面。
第一导电类型半导体层21和第二导电类型半导体层23具有不同的导电型态、电性、极性或依掺杂的元素以提供电子或空穴，即：第一导电类型半导体层21具有一第一导电性，第二导电类型半导体层23具有一第二导电性，其中第一导电性与第二导电性不同，例如第一导电类型半导体层21可为一n型半导体层，第二导电类型半导体层23可为一p型半导体层。来自于n型半导体层的电子与来自于p型半导体层的空穴在一外加电流驱动的下，在发光层22实现将电能转换成光能并发射出光线。
在本实施例中，半导体外延叠层20为砷化镓(gallium arsenide，GaAs)系列的材料，其中，第一导电类型半导体层21的掺杂为N型，第二导电类型半导体层23的掺杂为P型。
在本发明公开的其他实施例中，第一导电类型半导体层21的材料包含Ⅱ-Ⅵ族材料(例如，硒化锌(ZnSe))或Ⅲ-Ⅴ氮族化合物材料(例如，砷化镓(GaAs)、氮化镓(GaN)、氮化铝(AlN)、氮化铟(InN)、氮化铟镓(InGaN)、氮化铝镓(AlGaN)或氮化铝铟镓(AlInGaN))，且第一导电类型半导体层21的材料还可包含硅(Si)或锗(Ge)等掺杂物，但本公开实施例并非以此为限。在一些其他实施例中，第一导电类型半导体层21也可以是单层或多层结构。
在本发明公开的其他实施例中，第二导电类型半导体层23的材料包含Ⅲ-Ⅴ氮族化合物材料(例如，砷化镓(GaAs)、氮化镓(GaN)、氮化铝(AlN)、氮化铟(InN)、氮化铟镓(InGaN)、氮化铝镓(AlGaN)或氮化铝铟镓(AlInGaN))，且所述第二导电类型半导体层23的材料可包含镁(Mg)、碳(C)等掺杂物，但本公开实施例并非以此为限。在一些其他实施例中，第二导电类型半导体层23也可以是单层或多层结构。
在本实施例中，发光层22采用的砷化镓(GaAs)系列的半导体材料。具体来说，当发光层22以磷化铝铟镓(AlGaInP)系列、砷化镓(GaAs)系列的半导体材料为基础时，可以发出红光、橙光或黄光；当以氮化铝镓铟(AlGaInN)系列的半导体材料为基础时，可以发出蓝光或绿光。在本发明的一些实施例中，所述发光层22可包含至少一无掺杂(un-doped)半导体层或是至少一低掺杂层。在本发明的一些实施例中，所述发光层22可为单异质结构(singleheterostructure；SH)，双异质结构(doubleheterostructure；DH)，双侧双异质结构(double-sidedoubleheterostructure；DDH)，或多层量子阱结构(multi-quantumwell；MQW)，但本公开实施例并非以此为限。
请再参考图2，衬底10通过键合层70设置在半导体外延叠层20的第二表面1b上。在本实施例中，所述衬底10为蓝宝石衬底。衬底10可以是透明衬底，透明衬底的材料包含无机材料或Ⅲ-Ⅴ族半导体材料。无机材料包含碳化硅(SiC)、锗(Ge)、蓝宝石(sapphire)、铝酸锂(LiAlO 2)、氧化锌(ZnO)、玻璃或石英。Ⅲ-Ⅴ族半导体材料包含磷化铟(InP)、磷化镓(GaP)、氮化镓(GaN)、氮化铝(AlN)材料。衬底10具有足以机械性地支撑半导体外延叠层20的强度，并且能透过从半导体外延叠层20射出的光。衬底10的厚度优选为50μm以上。另外，为了便于在向半导体外延叠层20键合后对衬底10的机械加工，优选为厚度不超过300μm的厚度。
需要指明的是，本发明的发光二极管芯片并不局限于只包含一个半导体发光叠层20，亦可包含多个半导体发光叠层20位于衬底10上，其中多个半导体发光叠层20间可具有一导线结构使多个半导体发光叠层20于此衬底10上以串联、并联、串并联等方式彼此电连接。
请再参考图2，在本实施例中，所述发光二极管芯片包括一键合层70，所述键合层70覆盖在半导体外延叠层20的第二表面1b上，衬底10通过键合层70贴合形成于第二表面1b上，发光层23所发出的光可穿透键合层70和衬底10。在本实施例中，所述发光二极管芯片的出光面为所述衬底10远离半导体外延叠层20的表面。
键合层70的材料可为绝缘材料和/或导电材料。绝缘材料包含但不限于聚亚酰胺(PI)、苯并环丁烯(BCB)、过氟环丁烷(PFCB)、氧化镁(MgO)、Su8、环氧树脂(Epoxy)、丙烯酸树脂(AcrylicResin)、环烯烃聚合物(COC)、聚甲基丙烯酸甲酯(PMMA)、聚对苯二甲酸乙二酯(PET)、聚碳酸酯(PC)、聚醚酰亚胺(Polyetherimide)、氟碳聚合物(FluorocarbonPolymer)、玻璃(Glass)、氧化铝(Al 2O 3)、氧化硅(SiO x)、氧化钛(TiO 2)、氧化钽(Ta 2O 5)、氮化硅(SiN x)或旋涂玻璃(SOG)。导电材料包含但不限于氧化铟锡(ITO)、氧化铟(InO)、氧化锡(SnO)、氧化镉锡(CTO)、氧化锑锡(ATO)、氧化铝锌(AZO)、氧化锌锡(ZTO)、氧化锌(ZnO)、氧化铟锌(IZO)、类钻碳薄膜(DLC)或氧化镓锌(GZO)等。当键合层70采用导电材料与第二导电类型半导体层23接触，可起电流扩展层的作用，改善电流扩展的效果，提升电流分布的均匀性。
在一些实施例中，半导体外延叠层20靠近衬底10的第二表面20b可为一粗化面，当发光层22发出的光线通过键合层70与第二表面20b时，可以减少全反射情况的发生。
在一些实施例中，键合层70的折射率优选介于第二导电类型半导体层23的折射率和衬底10的折射率之间。举例来说，第二导电类型半导体层23具一折射率n1，键合层70具有一折射率n2，衬底10具有一折射率n3，其中，折射率n1＞折射率n2＞折射率n3。在一些实施例中，键合层70的折射率范围为1.2～3。
请参考图3，在一些实施例中，键合层70为一叠层结构，叠层结构的键合层数目并不限于2层，也可为2层以上。举例来说，键合层70包含靠近第二导电类型半导体层23的一第一键合层71与远离第二导电类型半导体层23的一第二键合层72。在本发明的一实施例中，第一键合层71与第二导电类型半导体层23邻接，而第二键合层72则与衬底10邻接。第一键合层71 与第二键合层72 是依序形成于第二导电类型半导体层23之上以构成键合层70。例如，第一键合层71为可起电流扩展作用的透明导电层，而第二键合层71为可起键合衬底10的键合材料层。
在一些实施例中，键合层70为一具有渐变折射率的结构，靠近第二导电类型半导体层23的第一键合层71的折射率m1不同于远离第二导电类型半导体层23的第二键合层72的折射率m2。换言之，在第二导电类型半导体层23、键合层70及衬底10之间，第一折射率n1、折射率m1、折射率m2、到第二折射率n2之间是呈现一连续变化或一梯度变化，通过折射率的变化从而改变光线从发光层23射向衬底10的行进方向，减少光线全反射的机率，避免光线局限在发光二极管芯片的内部。
为了将后述的第一接触电极31及第二接触电极41配置于第一导电类型半导体层21及第二导电类型半导体层23的同一面侧，可以以第一导电类型半导体层21的一部分露出的方式将第二导电类型半导体层23层积于第一导电类型半导体层21上，或者以第二导电类型半导体层23的一部分露出的方式将第一导电类型半导体层21层积于第二导电类型半导体层23上。举例来说，请再参考图2，在本实施例中，半导体外延叠层20包括至少局部地贯通第一导电类型半导体层21、发光层22而露出第二导电类型半导体层23的至少一个凹陷区域E；在凹陷区域E中第一导电类型半导体层21、发光层22被完全去除，只留下第二导电类型半导体层23；以及台面区域M，所述台面区域M围绕凹陷区域E。台面区域M可以被定义为不蚀刻第一导电类型半导体层21、发光层22、第二导电类型半导体层23的区域。台面区域M沿z方向与凹陷区域E相比，可以具有相对突出的形状。相对的，凹陷区域E也可以定义为被蚀刻的区域。但本公开实施例并非以此为限。在一些其他的实施例中，所述台面区域M也可以被定义为不蚀刻第一导电类型半导体层21、发光层22、第二导电类型半导体层23的区域，而在凹陷区域E中的第一导电类型半导体层21的一部分被去除。在本发明的一些实施例中，台面区域M可以在向上的方向上逐渐变窄。因此，台面区域M可以具有倾斜的侧表面。
发光二极管芯片包括位于第一导电类型半导体层21上并且直接或间接地电连接至第一导电类型半导体层21的一个或多个第一接触电极31，以及位于第二导电类型半导体层23上并且直接或间接地电连接至第二导电类型半导体层23的一个或多个第二接触电极41。在第一导电类型半导体层21为n型的情况下，第一接触电极31是指n侧接触电极；在第一导电类型半导体层21为p型的情况下，第一接触电极31是指p侧接触电极。而第二接触电极41与第一接触电极31相反。
举例来说，在一些实施例中，其焊盘电极不含有锡元素，而在封装过程中选择采用的是锡膏焊接，锡流动性较强，锡膏中所含有的锡容易经焊盘电极的缝隙进入内部，以侵蚀下方含有Au、Sn、或者In的欧姆电极，从而影响芯片的可靠性。在另一些实施例中，锡流动性较强，导致焊盘电极含有锡的情况下，锡容易经焊盘电极的缝隙进入内部，侵蚀下方的含有金元素的欧姆电极，影响芯片的可靠性。
为此，所述第一接触电极31和第二接触电极41可以是金属电极，例如，镍、金、铬、钛、铂、钯、铑、铱、铝、锡、铟、钽、铜、钴、铁、钌、锆、钨、钼及其一种或其组合。
为了解决Sn侵蚀下方的含有金元素的欧姆电极，影响芯片的可靠性的技术问题，在一些可选的实施例中，所述第一接触电极31包括第一接触电极31的欧姆接触层以及位于第一接触电极31的欧姆接触层之上的第一电极阻挡层51；优选所述第一接触电极31为n侧接触电极。所述第一电极阻挡层51包括Ti、Pt、Cr或它们中的任意组合的合金或它们中的任意组合的叠层，本发明公开的实施例并不以此为限，还可以为其他不与Sn发生反应的金属或多种金属组合的合金或它们中的任意组合的叠层。
本实施例中所述第一欧姆接触层为Au、Ge或Au、Ni或Au、Ge、Ni的合金，或为Au、Ge或Au、Ni或Au、Ge、Ni的叠层，以及所述第二欧姆接触层为Au、Be或Au、Zn或Au、Be、Zn的合金，或为Au、Be或Au、Zn或Au、Be、Zn的叠层时，由于第二欧姆接触层所采用的材料为含有Au的同时还含有Be和/或Zn，导致其电极的熔合温度高达500℃以上，而电极阻挡层材料难以承受如此高温，因此，导致无法直接在未熔合的第二欧姆接触层表面直接蒸镀电极阻挡层；转而需要在第二欧姆接触层熔合完成后，再进行电极阻挡层的蒸镀，导致工序的繁杂；因此，优选第一接触电极31包括第一接触电极31的欧姆接触层以及位于第一接触电极31的欧姆接触层之上的第一电极阻挡层51。
为了进一步解决第二电极侧Sn侵蚀下方的含有金元素的欧姆电极，影响芯片的可靠性的技术问题，本实施例中，更优选的所述第二接触电极41包括第二接触电极41的欧姆接触层以及位于第二接触电极41的欧姆接触层之上的第二电极阻挡层52。第二电极阻挡层52包括Ti、Pt、Cr或它们中的任意组合的合金或它们中的任意组合的叠层，本发明公开的实施例并不以此为限，还可以为其他不与Sn发生反应的金属或多种金属组合的合金或它们中的任意组合的叠层。此外，在本公开的实施例中，所述第一电极阻挡层51和第二电极阻挡层52由相同的材料组成，但并不以此为限，所述第一电极阻挡层51和第二电极阻挡层52也可以为不相同的材料组成。
所述第二接触电极41的欧姆接触层的厚度大于所述第一接触电极31的厚度。所述第一电极阻挡层51和第二电极阻挡层52的厚度在0.1μm以上且1μm以下，若电极阻挡层过薄在后续绝缘层60的蚀刻制程中易被蚀刻，导致失去作用，而若过厚则会增加制造成本。
请再参考图2中的放大图A和B，具体来说，在本实施例中，第一接触电极31为n侧接触电极，第二接触电极41为p侧接触电极。所述第一接触电极31包括第一欧姆接触层31a和位于第一欧姆接触层31a之上的第一电极阻挡层51；所述第二接触电极41包括第二欧姆接触层41a、位于第二欧姆接触层41a之上的第二电极阻挡层52以及位于所述第二欧姆接触层41a和第二电极阻挡层52之间的第一欧姆接触层31a。本实施例在第二导电类型半导体层23表面形成第二欧姆接触层41a后，再覆盖一第一欧姆接触层31a于第二欧姆接触层41a之上，用以确保第二电极阻挡层52在第一欧姆接触层31a表面蒸镀形成，从而避免锡经绝缘层开口处的缝隙进入并侵蚀下方的接触电极。
请再参考图2中的放大图A，在一些实施例中，第一欧姆接触层31a覆盖于第二欧姆接触层41a上时，采用的覆盖方式为完全包覆第二欧姆接触层41a，以防止第一欧姆接触层31a发生偏离，导致露出部分第二欧姆接触层32a，从而影响发光二极管芯片的可靠性，而采用完全包覆的方式则不易发生露出第二欧姆接触层32a的情况。本发明公开的实施例并不以此为限，一些实施例中，在所述第二接触电极的欧姆接触层中，所述第一欧姆接触层至少覆盖所述第二欧姆接触层的上表面。另一些实施例中，在所述第二接触电极的欧姆接触层中，所述第一欧姆接触层还覆盖所述第二欧姆接触层的倾斜侧面。进一步可选地，在所述第二接触电极的欧姆接触层中，所述第二欧姆接触层的倾斜侧面上的第一欧姆接触层的厚度小于所述第二欧姆接触层上表面覆盖的第一欧姆接触层的厚度。
所述第一欧姆接触层31a的厚度在0.1μm以上且2μm以下，所述第一欧姆接触层31a的厚度过薄会不利于欧姆接触的形成，过厚则不利于电极阻挡层的覆盖。所述第一欧姆接触层31a的材料包括Au、Ge、Ni或它们中的任意组合的合金或它们中的任意组合的叠层。在本实施例中，所述第一欧姆接触层31a的材料为Au/Ge/Ni。在另一些实施例中，所述第一欧姆接触层31a的材料可以为含有Au的金属层、或含有Au的合金层等，本发明公开的实施例并不以此为限，所述第一欧姆接触层31a的材料也可以为Au与Ge或Ni中的任意组合的合金或它们中的任意组合的叠层；本发明公开的实施例并不以此为限，第一欧姆接触层31a的材料还可以为其他容易与Sn发生反应的金属或多种金属组合的合金或它们中的任意组合的叠层。
所述第二欧姆接触层41a的厚度在0.1μm以上且2μm以下，若所述第二欧姆接触层41a的厚度过薄会不利于欧姆接触的形成，而过厚则不利于电极阻挡层的覆盖。所述第二欧姆接触层41a包括Au、Be、Zn或它们中的任意组合的合金或它们中的任意组合的叠层。在本实施例中，所述第二欧姆接触层41a的材料为Au/Be。在另一实施例中，所述第二欧姆接触层41a的材料为Au/Zn。在另一些实施例中，所述第二欧姆接触层41a的材料可以为含有Au的金属层、或含有Au的合金层等，本发明公开的实施例并不以此为限，所述第二欧姆接触层41a的材料也可以为Au与Be或Zn中的任意组合的合金或它们中的任意组合的叠层；本发明公开的实施例并不以此为限，第二欧姆接触层41a的材料还可以为其他容易与Sn发生反应的金属或多种金属组合的合金或它们中的任意组合的叠层。绝缘层60覆盖半导体外延叠层20的上表面及侧面，并且覆盖第一接触电极31、第二接触电极41，同时，该绝缘层60能够以延伸覆盖至部分露出在半导体外延叠层20的周边的衬底10的上表面的方式形成。由此，绝缘层60可与衬底10的上表面相接，因此可更稳定地覆盖在半导体外延叠层20的侧面。
在几乎覆盖半导体外延叠层20的上表面及侧面整体的绝缘层60的分布式布拉格反射镜反射光，由此可提高所述发光二极管芯片的发光效率。此外，绝缘层60从半导体外延叠层20延伸覆盖至部分所述衬底10的上表面11，并使所述衬底10的上表面11周边的部分露出。即，所述衬底10的上表面11外沿的周围未覆盖有绝缘层60。由此，在分割晶片而形成多个发光二极管芯片的过程中，防止在衬底10的分割过程(例如，通过内部加工切割、刻划和/或断裂进行的衬底10分割)中因激光等造成的绝缘层60的损伤(例如，剥离、破裂等)。尤其，在绝缘层60包括分布式布拉格反射镜的情况下，若绝缘层60受损，一方面光反射率会下降，另一方面容易发生漏电问题。根据本实施例，还可防止因这种绝缘层60的损伤引起的发光效率下降、芯片异常等问题。
第一焊盘电极32及第二焊盘电极42布置于所述绝缘层60的上部。第一焊盘电极32可通过所述绝缘层60的第一开口61电连接至所述第一接触电极31。第二焊盘电极42可通过所述第二开口62电连接至所述第二接触电极41。参照图2所示，第一开口61和第二开口62可以是呈圆形形状，在一些其他的实施例中，该第一开口61和第二开口62也可是方形等，各开口部的形状与个数不受特别的限制，可以是仅设置有一个开口部，若是设置有多个开口部，则可以更为均匀地分散电流。此外，在一些其他的实施例中，设置有多个开口部的情况下，各开口部可依据实际需求，而选择等间距或非等间距的分布形式，并不以本发明公开的实施例为限。在一些实施例中，所述第一焊盘电极包括Ti、Al、Pt、Au、Ni、Sn或它们中的任意组合的合金或它们中的任意组合的叠层。在一些实施例中，所述第二焊盘电极包括Ti、Al、Pt、Au、Ni、Sn或它们中的任意组合的合金或它们中的任意组合的叠层。
请参考图2，在一些实施例中，第一开口61的下开口宽度小于位于所述第一开口61下方的第一电极阻挡层51的上表面宽度，即所述第一开口61的下开口在水平面上的正投影位于所述第一开口61下方的第一电极阻挡层51的上表面在水平面上的正投影范围内，得以保护下方的接触电极。较佳的，所述第一开口61的下开口宽度与位于所述第一开口61下方的第一电极阻挡层51的上表面宽度差值在5μm以上，若差值过小，可能会发生第一开口61偏离第一电极阻挡层51所在位置。
请参考图2，在一些实施例中，第二开口62的下开口宽度小于位于所述第二开口62下方的第二电极阻挡层52的上表面宽度，即所述第二开口62的下开口在水平面上的正投影位于所述第二开口62下方的第二电极阻挡层52的上表面在水平面上的正投影范围内，得以保护下方的接触电极。较佳的，所述第二开口62的下开口宽度与位于所述第二开口62下方的第二电极阻挡层52的上表面宽度差值在5μm以上，若差值过小，可能会发生第二开口62偏离第二电极阻挡层52所在位置。
请参考图2，在一些实施例中，所述第一开口61和/或所述第二开口62具有倾斜的侧面，所述倾斜的侧面的倾斜角度θ相对于底面在80°以内，以避免绝缘层60的孔侧壁出现完全断裂导致无法导通。
图4至图12是用以说明本发明图2所示实施例的发光二极管芯片的制造方法的剖面图。
请参考图4，在生长衬底80上形成半导体外延叠层20，通常可利用已知的各种方法生长，例如可利用有机金属化学气相沉积(Metal Organic Chemical VaporDeposition，MOCVD)、分子束磊晶(Molecular Beam Epitaxy，MBE)或氢化物气相磊晶(Hydride Vapor Phase Epitaxy，HVPE)等技术生长。所述生长衬底80为砷化镓衬底。所述半导体外延叠层20为砷化镓(gallium arsenide，GaAs)系列的材料，所述半导体外延叠层20包括第一导电类型半导体层21、第二导电类型半导体层23以及位于第一导电类型半导体层21和第二导电类型半导体层23之间的发光层22。
请参考图5，通过粗化处理制成，在第二导电类型半导体层23表面形成粗化面，形成粗化面的方法没有特别限制，例如可使用蚀刻或机械研磨。
请参考图6，在粗化后的第二导电类型半导体层23表面沉积键合层70，抛光键合层70的表面，所述键合层70为二氧化硅。
请参考图7，去除生长衬底80，半导体外延叠层20与衬底10通过键合层70键合，所述衬底10为蓝宝石衬底。
请参考图8，定义半导体外延叠层20表面形成光刻胶图形，在第一导电类型半导体层21表面部分区域去除第一导电类型半导体层21、发光层22，直至露出部分第二导电类型半导体层23。
请参考图9，定义半导体外延叠层20表面形成光刻胶图形，露出芯片边缘的半导体外延叠层20被去除，形成切割道.
请参考图10，在半导体外延叠层20表面形成第一接触电极31和第二接触电极32；具体来说，先蒸镀第二欧姆接触层32a，并于第一导电类型半导体层21上蒸镀第一欧姆接触层31a时，同步覆盖一层第一欧姆接触层31a于所述第二欧姆接触层32a之上，进而在两处第一欧姆接触层31a对的表面蒸镀电极阻挡层，可以根据实际电极阻挡层的材料选择分步进行第一电极阻挡层51和第二电极阻挡层52的蒸镀，也可以同步蒸镀，本公开实施例并不以此为限。
请参考图11，沉积绝缘层70，所述绝缘层70完全覆盖半导体外延叠层20的表面，半导体外延叠层20的侧壁，以及裸露出的键合层70表面。
请参考图12，分别在位于第一导电类型半导体层21和第二导电类型半导体层23上的绝缘层70的形成第一开口61和第二开口62，制备第一焊盘电极32和第二焊盘电极42并通过相对应的第一开口61和第二开口62分别与第一导电类型半导体层21和第二导电类型半导体层23形成电连接。
另外，本领域技术人员应当理解，尽管现有技术中存在许多问题，但是，本发明的每个实施例或技术方案可以仅在一个或几个方面进行改进，而不必同时解决现有技术中或者背景技术中列出的全部技术问题。本领域技术人员应当理解，对于一个权利要求中没有提到的内容不应当作为对于该权利要求的限制。

Claims (19)

  1. 一种发光二极管芯片，包括：
    半导体外延叠层，具有相对的第一表面和第二表面，包括第一导电类型半导体层、第二导电类型半导体层以及位于第一导电类型半导体层和第二导电类型半导体层之间的发光层；
    第一接触电极和第二接触电极，位于所述半导体外延叠层的第一表面之上，分别与所述第一导电类型半导体层和所述第二导电类型半导体层电连接；
    所述第一接触电极包括第一接触电极的欧姆接触层以及位于所述第一接触电极的欧姆接触层之上的第一电极阻挡层；
    所述第二接触电极包括第二接触电极的欧姆接触层以及位于所述第二接触电极的欧姆接触层之上的第二电极阻挡层；
    所述第一接触电极的欧姆接触层包括一第一欧姆接触层；
    所述第二接触电极的欧姆接触层包括一第二欧姆接触层，以及设置于第二欧姆接触层和第二电极阻挡层之间的另一第一欧姆接触层。
  2. 根据权利要求1所述的发光二极管芯片，其特征在于：所述第二接触电极的欧姆接触层的厚度大于所述第一接触电极的欧姆接触层的厚度。
  3. 根据权利要求2所述的发光二极管芯片，其特征在于：所述第一接触电极的欧姆接触层由n1层的金属叠层组成，所述第二接触电极的欧姆接触层由n2层的的金属叠层组成，所述n1＜n2。
  4. 根据权利要求1所述的发光二极管芯片，其特征在于：在所述第二接触电极的欧姆接触层中，所述第一欧姆接触层至少覆盖所述第二欧姆接触层的上表面。
  5. 根据权利要求4所述的发光二极管芯片，其特征在于：在所述第二接触电极的欧姆接触层中，所述第一欧姆接触层还覆盖所述第二欧姆接触层的倾斜侧面。
  6. 根据权利要求5所述的发光二极管芯片，其特征在于：在所述第二接触电极的欧姆接触层中，所述第二欧姆接触层的倾斜侧面上的第一欧姆接触层的厚度小于所述第二欧姆接触层上表面覆盖的第一欧姆接触层的厚度。
  7. 根据权利要求1所述的发光二极管芯片，其特征在于：所述第一电极阻挡层和第二电极阻挡层由相同的材料组成。
  8. 根据权利要求1所述的发光二极管芯片，其特征在于：所述第一欧姆接触层为Au、Ge或Au、Ni或Au、Ge、Ni的合金，或为Au、Ge或Au、Ni或Au、Ge、Ni的叠层。
  9. 根据权利要求1所述的发光二极管芯片，其特征在于：所述第一欧姆接触层的厚度在0.1μm以上且2μm以下。
  10. 根据权利要求1所述的发光二极管芯片，其特征在于：所述第二欧姆接触层Au、Be或Au、Zn或Au、Be、Zn的合金，或为Au、Be或Au、Zn或Au、Be、Zn的叠层。
  11. 根据权利要求1所述的发光二极管芯片，其特征在于：所述第二欧姆接触层的厚度在0.1μm以上且2μm以下。
  12. 根据权利要求1所述的发光二极管芯片，其特征在于：所述第一电极阻挡层和第二电极阻挡层包括Ti、Pt、Cr或它们中的任意组合的合金或它们中的任意组合的叠层。
  13. 根据权利要求1所述的发光二极管芯片，其特征在于：所述第一电极阻挡层和第二电极阻挡层的厚度在0.1μm以上且1μm以下。
  14. 根据权利要求1所述的发光二极管芯片，其特征在于：所述发光二极管芯片辐射出的波长为580~1000nm。
  15. 根据权利要求1所述的发光二极管芯片，其特征在于，所述发光二极管芯片还包括：
    绝缘层，位于所述半导体外延叠层上，其至少覆盖所述半导体外延叠层的边缘区域及侧壁。
    第一焊盘电极，布置于所述绝缘层的上部，并通过所述绝缘层的第一开口电连接至所述第一接触电极；
    第二焊盘电极，布置于所述绝缘层的上部，并通过所述绝缘层的第二开口电连接至所述第二接触电极。
  16. 根据权利要求15所述的发光二极管芯片，其特征在于：所述第一焊盘电极和第二焊盘电极包括Ti、Al、Pt、Au、Ni、Sn、In或它们中的任意组合的合金或它们中的任意组合的叠层。
  17. 根据权利要求15所述的发光二极管芯片，其特征在于：所述第一开口和第二开口的下开口宽度小于位于所述第一开口和第二开口下方的电极阻挡层的上表面宽度。
  18. 根据权利要求15所述的发光二极管芯片，其特征在于：所述第一开口和/或所述第二开口具有倾斜的侧面，所述倾斜的侧面的倾斜角度相对于底面在80°以内。
  19. 一种发光装置，其特征在于：具有权利要求1至权利要求18中任一项所述的发光二极管芯片。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011124296A (ja) * 2009-12-09 2011-06-23 Showa Denko Kk 半導体発光素子の製造方法
CN108258095A (zh) * 2018-01-18 2018-07-06 湘能华磊光电股份有限公司 Led芯片电极及其制作方法和led芯片
CN111933770A (zh) * 2020-09-04 2020-11-13 佛山市国星半导体技术有限公司 一种高可靠性uvc led芯片及其制作方法
CN113675310A (zh) * 2020-05-13 2021-11-19 日机装株式会社 半导体发光元件及半导体发光元件的制造方法
CN113851567A (zh) * 2021-11-26 2021-12-28 泉州三安半导体科技有限公司 一种发光二极管芯片、发光装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101546929B1 (ko) * 2013-09-24 2015-08-25 서울바이오시스 주식회사 발광 다이오드 및 그것을 갖는 발광 다이오드 모듈
KR102641239B1 (ko) * 2015-07-10 2024-02-29 서울바이오시스 주식회사 발광 다이오드, 그것을 제조하는 방법 및 그것을 갖는 발광 소자 모듈
TWM542252U (zh) * 2015-10-16 2017-05-21 首爾偉傲世有限公司 小型發光二極體晶片
WO2017078368A1 (ko) * 2015-11-05 2017-05-11 서울바이오시스주식회사 자외선 발광 소자 및 그것을 제조하는 방법
CN111128987A (zh) * 2016-05-03 2020-05-08 首尔伟傲世有限公司 发光二极管
KR102550005B1 (ko) * 2016-07-15 2023-07-03 서울바이오시스 주식회사 자외선 발광 다이오드

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011124296A (ja) * 2009-12-09 2011-06-23 Showa Denko Kk 半導体発光素子の製造方法
CN108258095A (zh) * 2018-01-18 2018-07-06 湘能华磊光电股份有限公司 Led芯片电极及其制作方法和led芯片
CN113675310A (zh) * 2020-05-13 2021-11-19 日机装株式会社 半导体发光元件及半导体发光元件的制造方法
CN111933770A (zh) * 2020-09-04 2020-11-13 佛山市国星半导体技术有限公司 一种高可靠性uvc led芯片及其制作方法
CN113851567A (zh) * 2021-11-26 2021-12-28 泉州三安半导体科技有限公司 一种发光二极管芯片、发光装置

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