WO2023092964A1 - 同源异相时钟生成装置、方法和设备 - Google Patents

同源异相时钟生成装置、方法和设备 Download PDF

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Publication number
WO2023092964A1
WO2023092964A1 PCT/CN2022/094187 CN2022094187W WO2023092964A1 WO 2023092964 A1 WO2023092964 A1 WO 2023092964A1 CN 2022094187 W CN2022094187 W CN 2022094187W WO 2023092964 A1 WO2023092964 A1 WO 2023092964A1
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delay
phase difference
module
information
unit
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PCT/CN2022/094187
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English (en)
French (fr)
Inventor
吴劲
李洋
胡建国
王德明
丁颜玉
段志奎
秦军瑞
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广州智慧城市发展研究院
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Publication of WO2023092964A1 publication Critical patent/WO2023092964A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom

Definitions

  • the present invention relates to the technical field of signal processing, in particular to a homologous out-of-phase clock generation device, method and equipment.
  • the clock is the basis of sequential logic. It determines when the state in the logic unit is updated. It is the key to ensure that the electronic components can work completely synchronously. If the clock is inaccurate, it will lead to the disorder of the system function. Therefore, the accuracy of the clock determines whether the system can Healthy good run.
  • the same-source out-of-phase clocks used in actual scenarios are usually generated by a phase-locked loop or a delay phase-locked loop.
  • the phases do not need to be the same, but only require a fixed phase; however, due to the influence of process angle, temperature and humidity, voltage, circuit structure, etc.,
  • the difference between the same-source and out-of-phase clocks often has individual differences, which cannot be precisely controlled.
  • the usual solution to the problem of clock accuracy is to configure the pins to connect to the oscilloscope, and manually compare the waveforms of the oscilloscope to calibrate the clock generation circuit. A lot of time, less efficient.
  • embodiments of the present invention provide a homologous out-of-phase clock generation device, method and equipment.
  • the embodiment of the present invention provides a homologous out-of-phase clock generation device, including:
  • the automatic calibration module is used to obtain the first information of the delay unit corresponding to the target phase difference according to the input automatic calibration enabling signal; according to the first information, determine the second information of the delay unit corresponding to the input first phase difference ;
  • a delay configuration module configured to output the first control signal according to the second information
  • the delay module is used to turn on the delay unit in the delay module according to the first control signal and the source clock, and output the same-source and out-of-phase clock.
  • the automatic calibration module includes:
  • the input end of the adaptive control circuit is used to receive the input automatic calibration enable signal and the first phase difference;
  • the output end of the adaptive control circuit is connected to the input end of the operation circuit, so The output end of the operation circuit is connected with the input end of the delay configuration module, the output end of the delay configuration module is connected with the input end of the delay module;
  • the input end of the sampling register is connected with the delay time The output end of the module is connected, and the output end of the sampling register is connected with the adaptive control circuit;
  • the adaptive control circuit is specifically used to turn on the delay units in the delay module step by step according to the automatic calibration enable signal, and sequentially perform different phases generated by the delay module according to the sampling register. Determine whether a target phase difference is detected based on the sampling result of the clock sampling, and if the target phase difference is detected, acquire first information corresponding to the target phase difference;
  • the sampling register is used to sample the out-of-phase clock generated by the delay module to obtain the sampling result
  • the arithmetic circuit is configured to determine second information of a delay unit corresponding to the first phase difference according to the first information corresponding to the target phase difference.
  • the adaptive control circuit includes:
  • the output terminals of the automatic calibration start judgment unit are respectively connected with the step-by-step start control unit and the delay configuration module;
  • the output end of the step-by-step opening control unit is respectively connected with the delay configuration module and the sampling register;
  • the input end of the clock inversion detection unit is connected with the output end of the sampling register, and the clock inversion The output end of the detection unit is connected to the input end of the operation unit;
  • the automatic calibration start judging unit is configured to output a second control signal and the first phase difference according to the automatic calibration enabling signal
  • the step-by-step opening control unit is used to turn on the delay units in the delay module step by step according to the second control signal, and output the target information of the turned-on delay units to the sampling register;
  • the clock inversion detection unit is configured to determine whether a target phase difference is detected according to the sampling result of the sampling register; if the target phase difference is detected, use the target information as the first target phase difference corresponding A message is output to the operation circuit.
  • the operation circuit includes:
  • the first input end of the phase parameter operation unit is connected to the clock inversion detection unit; the first output end of the phase parameter operation unit is connected to the delay configuration module, and the phase parameter operation unit The second output end is connected to the full addition and subtraction circuit, and the output end of the full addition and subtraction circuit is connected to the second input end of the phase parameter calculation unit;
  • the phase parameter operation unit is used to determine the third information of the delay unit corresponding to the opening of the second phase difference and the delay unit corresponding to the opening of the third phase difference according to the first information corresponding to the target phase difference and the first phase difference the fourth information of
  • the full addition and subtraction circuit is configured to determine the second information of the delay unit corresponding to the first phase difference according to the third information and the fourth information of the enabled delay unit.
  • the full addition and subtraction circuit includes: an alternative circuit and a full adder
  • the input end of the one-of-two circuit is connected to the third output end of the phase parameter calculation unit, and the output end of the full adder is used as the output end of the full adder-subtraction circuit;
  • the one-of-two circuit is used to select a corresponding operation method according to the third control signal output by the phase parameter operation unit;
  • the full adder is configured to determine the second information of the delay unit corresponding to the first phase difference according to the third information and fourth information of the enabled delay unit and the operation mode.
  • the delay module includes:
  • the decoder is configured to control the corresponding delay unit to be turned on according to the first control signal.
  • a gating module wherein the output end of the gating module is connected to the input end of the automatic calibration module
  • the gate control module is configured to control the automatic calibration module to be synchronously reset and clock gated after the automatic calibration enable is turned off according to the input automatic calibration enable signal and the source clock.
  • the gate control module includes:
  • the two-level synchronization register is used to control the automatic calibration module to be reset synchronously after the automatic calibration enable is turned off according to the input automatic calibration enable signal and the source clock, and output a fourth control signal to the gate control unit;
  • the gating unit is configured to control the automatic calibration module to perform clock gating according to the fourth control signal output by the synchronization register and the source clock.
  • the embodiment of the present invention also provides a method for generating homologous and out-of-phase clocks, including:
  • the second information of the delay unit corresponding to the first phase difference According to the first phase difference and the first information of the delay unit corresponding to the target phase difference, determine the second information of the delay unit corresponding to the first phase difference;
  • the delay unit corresponding to the first phase difference is turned on, and the same-source out-of-phase clock is output.
  • an embodiment of the present invention further provides an electronic device, including the same-source out-of-phase clock generation device as described in the first aspect.
  • an embodiment of the present invention also provides a non-transitory computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the same-source out-of-phase clock as described in the second aspect is implemented. The steps to generate the method.
  • an embodiment of the present invention further provides a computer program product, including a computer program, and when the computer program is executed by a processor, the steps of the method for generating a clock with the same source and different phases as described in the second aspect are implemented.
  • the same-source out-of-phase clock generation device includes an automatic calibration module, a delay configuration module, and a delay module connected in sequence; wherein the automatic calibration module obtains the first information of the delay unit corresponding to the target phase difference, and combines the target The corresponding relationship between the phase difference and the first phase difference to be generated can accurately determine the second information of the delay unit corresponding to the first phase difference; the delay configuration module and the delay module control their corresponding delay according to the second information The timing unit is turned on, that is, through the automatic calibration module, the delay configuration module and the delay module, the homogeneous and out-of-phase clocks with accurate phase difference can be efficiently generated.
  • Fig. 1 is a structural schematic diagram 1 of a homologous out-of-phase clock generating device provided by the present invention
  • Fig. 2 is a schematic diagram of the automatic calibration module of the homologous out-of-phase clock generation device provided by the present invention
  • Fig. 3 is the full addition and subtraction circuit schematic diagram of homologous out-of-phase clock generating device provided by the present invention
  • FIG. 4 is a schematic diagram of a delay unit in the delay module of the homologous out-of-phase clock generating device provided by the present invention.
  • FIG. 5 is a schematic diagram of a gating module of a homologous out-of-phase clock generating device provided by the present invention.
  • Fig. 6 is a structural schematic diagram II of a homologous out-of-phase clock generating device provided by the present invention.
  • FIG. 7 is a schematic flowchart of a method for generating homologous and out-of-phase clocks provided by the present invention.
  • the device in the embodiment of the present invention can be applied to the scenario of generating homologous and out-of-phase clocks, and efficiently generates homologous and out-of-phase clocks with precise phase differences.
  • the same-source out-of-phase clock is usually generated by a phase-locked loop or a delay phase-locked loop.
  • the phases do not need to be the same, but only require a fixed phase; In various application scenarios of mass-produced equipment, there are often individual differences in the phase difference between the same-source and out-of-phase clocks, which cannot be precisely controlled.
  • the usual solution is to configure the pins to connect to the oscilloscope, and manually compare the waveforms of the oscilloscope to calibrate the clock generation circuit, but manual calibration is very unfriendly to batch research, production, and application, and it takes a lot of money time, the efficiency is low.
  • the same-source out-of-phase clock generation device in the embodiment of the present invention includes an automatic calibration module, a delay configuration module and a delay module connected in sequence; the automatic calibration module obtains the corresponding open delay of the target phase difference according to the input automatic calibration enable signal The first information of the unit; according to the first information, determine the second information of the delay unit corresponding to the first input phase difference; the delay configuration module outputs the first control signal according to the second information; the delay module outputs the first control signal according to the first control signal As well as the source clock, turn on the delay unit in the delay module, and finally efficiently generate homogeneous and out-of-phase clocks with accurate phase difference.
  • FIG. 1 is a schematic diagram of an embodiment of a homologous out-of-phase clock generation device provided by an embodiment of the present invention. As shown in Figure 1, the homologous out-of-phase clock generation device provided in this embodiment includes:
  • the automatic calibration module 101 is used to obtain the first information of the delay unit corresponding to the target phase difference according to the input automatic calibration enabling signal; according to the first information, determine the second delay unit corresponding to the input first phase difference. information;
  • Delay configuration module 102 configured to output the first control signal according to the second information
  • the delay module 103 is configured to turn on the delay unit in the delay module according to the first control signal and the source clock, and output the same-source but out-of-phase clock.
  • the homologous out-of-phase clock generating device includes an automatic calibration module 101, a delay configuration module 102 and a delay module 103, and the three are connected in sequence.
  • the automatic calibration module 101 obtains the first information of the delay unit corresponding to the open target phase difference according to the input automatic calibration enable signal, wherein the target phase difference includes a 180-degree phase difference with the source clock inversion, and the first information includes a delay The number of units and the corresponding position information of the delay unit; then the automatic calibration module determines the second information of the delay unit corresponding to the input first phase difference according to the first information.
  • the automatic calibration module 101 of the same-source out-of-phase clock judges according to the input automatic calibration enable signal, if the automatic calibration enable signal is turned on, then the automatic calibration function is turned on; if the automatic calibration module 101 obtains a target phase difference of 180 degrees, The number of delay units included in the first information corresponding to the opened delay units is 54; when the automatic calibration module 101 determines that the first phase difference of the output is 90 degrees, then it can be determined according to the first information: the first phase difference
  • the number of delay units included in the second information of the delay unit corresponding to 90 degrees is the binary right shift of one bit corresponding to 54 in the first information, which is equivalent to dividing 54 by 2, that is, the delay included in the second information with a difference of 90°
  • the number of time units is 27.
  • the delay configuration module 102 outputs the first control signal to the delay module 103 by acquiring the second information of the delay unit corresponding to the first phase difference output by the automatic calibration module. It is mainly composed of three input selectors, which select the input and use it as the output to control the decoder.
  • the delay configuration module 102 obtains the number of delay units included in the second information of the delay unit corresponding to the first difference of 90 degrees through the automatic calibration module 101, and then outputs its corresponding information as the first control signal to the delay unit.
  • the delay module 103 is configured to turn on the delay unit 103 in the delay module according to the first control signal and the source clock, and output the same-source and out-of-phase clock.
  • the delay module 103 controls the decoder to determine which delay units in the delay module 103 are turned on according to the first control signal by obtaining the first control signal output by the delay configuration module 102 and the source clock, that is, it is determined according to the first control signal
  • the delay unit in the delay module 103 is turned on or off to generate homogeneous and out-of-phase clocks with precise phase difference.
  • the delay module 103 obtains the first control signal output by the delay configuration module 102 and the source clock, and activates 27 delay units to generate homologous and out-of-phase clocks with a phase difference of 90 degrees.
  • the same-source out-of-phase clock generation device includes an automatic calibration module, a delay configuration module, and a delay module connected in sequence; after the automatic calibration module obtains the first information of the delay unit corresponding to the target phase difference, it combines The corresponding relationship between the target phase difference and the first phase difference to be generated can accurately determine the second information of the delay unit corresponding to the first phase difference; the delay configuration module and the delay module control their correspondence according to the second information
  • the opening of the delay unit that is, the automatic calibration module, the delay configuration module and the delay module can efficiently generate homogeneous and out-of-phase clocks with accurate phase difference.
  • the automatic calibration module includes:
  • Adaptive control circuit 201 Adaptive control circuit 201, arithmetic circuit 202 and sampling register 205;
  • the input terminal of adaptive control circuit 201 is used for receiving the automatic calibration enabling signal of input and first difference;
  • the output end of delay configuration module 203 is connected with the input end of delay module 204;
  • the input end of sampling register 205 is connected with the output end of delay module 204, and the output end of sampling register 205 is connected with Adaptive control circuit 201 is connected;
  • the adaptive control circuit 201 is specifically used to turn on the delay unit in the delay module 204 step by step according to the automatic calibration enable signal, and sequentially sample the out-of-phase clock generated by the delay module 204 according to the sampling register 205 to determine whether to detect To the target difference, if the target difference is detected, obtain the first information corresponding to the target difference;
  • the sampling register 205 is used to sample the out-of-phase clock generated by the delay module 204 to obtain a sampling result
  • the arithmetic circuit 202 is configured to determine second information of a delay unit corresponding to the first phase difference according to the first information corresponding to the target phase difference.
  • the first input of the adaptive control circuit 201 is the automatic calibration enable signal and the first phase difference, if the automatic calibration enable signal is turned on, the adaptive control circuit turns on the delay units in the delay module 204 step by step;
  • the output end of the delay module 204 is connected with the input end of the sampling register 205, when the adaptive control circuit 201 opens the delay unit control step by step and adds once, the sampling register 205 just samples the clock output of the delay unit in the delay module 204 once;
  • the sampling register 205 includes a 64-bit register.
  • the adaptive control circuit 201 turns on the delay unit step by step to control self-adding once, the clock output of the delay module 204 is sampled once until the clock inversion detection unit detects the inversion. Stop sampling; its output is connected with the adaptive control circuit 201, and the adaptive control circuit 201 determines whether the target phase difference is detected according to the clock output of the delay unit in the delay module 204 sampled by the sampling register 205, if the target phase difference is detected , to obtain the first information corresponding to the target difference;
  • the output end of the adaptive control circuit 201 is connected to the input end of the operation circuit 202.
  • the operation circuit 202 combines the target phase difference with the first information according to the first information corresponding to the target phase difference.
  • the corresponding relation of the phase difference is to determine the second information of the delay unit corresponding to the first phase difference.
  • the output terminal of the arithmetic circuit 202 is connected to the input end of the delay configuration module 203, and the delay configuration module 203 obtains the second information output by the arithmetic circuit 202 to generate the first control signal;
  • the output terminal of the delay configuration module 203 is connected to the input terminal of the delay module 204, and the delay module 204 obtains the first control signal, and outputs a clock of the same source, different phase and different phase with the first phase difference.
  • the adaptive control circuit 201 when the input automatic calibration of the adaptive control circuit 201 is enabled and the first phase difference is 90 degrees, the adaptive control circuit 201 turns on the delay units in the delay module 204 step by step; Since adding once, the sampling register 205 samples the clock output of the delay unit in the delay module 204 once; then the adaptive control circuit 201 samples the clock output according to the sampling register 205, such as sampling a logic 0 or a logic 1, to determine whether to detect To the target phase difference, if the target phase difference is detected, the information corresponding to the target phase difference is obtained; if the delay unit increases step by step until 54 stages are turned on, the adaptive control circuit 201 determines that the target of 180 degrees is detected according to the clock output sampled by the sampling register 205 difference, then the 54 delay units and position information are the first information corresponding to the 180-degree target difference.
  • the arithmetic circuit 202 shifts the binary number of 54 in the first information to the right by one bit in combination with the corresponding relationship between the 180-degree target phase difference and the 90-degree first phase difference, which is equivalent to dividing 54 by 2, and then determines the corresponding 27
  • a delay unit is the second information that generates a 90° phase difference.
  • the delay configuration module 203 generates the first control signal according to the first information, that is, the first control signal is used to indicate which delay units the delay module 204 should open, for example, when the first control signal is binary 11011, the delay module 204 obtains Turning on the corresponding 27 delay units after the first control signal can generate the same-source out-of-phase clock with the first phase difference of 90 degrees.
  • the automatic calibration module includes: an adaptive control circuit, an arithmetic circuit, and a sampling register; wherein, the adaptive control circuit determines whether a target phase difference is detected according to the clock output sampled by the sampling register, and if the target phase difference is detected, Obtain the first information corresponding to the target phase difference; the operation circuit determines the second information of the delay unit corresponding to the first phase difference according to the first information and the corresponding relationship between the target phase difference and the first phase difference; that is, the automatic calibration module can accurately determine the desired
  • the information of the delay unit corresponding to the output phase difference clock provides accurate input information for the delay configuration module and the delay module to efficiently generate the same-source and out-of-phase clock with precise phase difference.
  • the adaptive control circuit includes:
  • the output end of the automatic calibration opening judgment unit 601 is connected with the step-by-step opening control unit 602 and the delay configuration module 607 respectively;
  • the output end of opening control unit 601 is connected with delay configuration module 607 and sampling register 604 step by step;
  • the automatic calibration start judging unit 601 is used to output the second control signal and the first phase difference according to the automatic calibration enabling signal;
  • the step-by-step opening control unit 602 is used to turn on the delay unit in the delay module step by step according to the second control signal, and output the target information of the delay unit to the sampling register 604;
  • the clock inversion detection unit 603 is used to determine whether the target phase difference is detected according to the sampling result of the sampling register 604; when the target phase difference is detected, the target information is used as the first information corresponding to the target phase difference, and is output to the arithmetic circuit .
  • the adaptive control circuit includes: an automatic calibration start judging unit 601, a step-by-step start control unit 602, and a clock inversion detection unit 603;
  • the output end of automatic calibration opening judgment unit 601 is connected with step by step opening control unit 602 and delay configuration module 607 respectively; Then output a second control signal to inform the step-by-step opening control unit 602 that automatic calibration needs to be started; if it is judged that the automatic calibration enable signal is off, then output a second control signal to notify the delay configuration module 607 that automatic calibration is not required.
  • the step-by-step opening control unit 602 includes a six-bit counter, whose count value corresponds to the input of the line decoder; before the clock inversion detection unit detects the inversion, add 1 every four cycles until the clock inversion detection unit detects Just stop computing when inverting; its output terminal is connected with delay configuration module 607 and sampling register 604 respectively; Open the delay unit in the delay module step by step, and output the target information of the delay unit to the sampling register 604, including the quantity and position of the delay unit currently opened in the target information;
  • the clock inversion detection unit 603 mainly performs abbreviation or operation on the sampling register 604. If the result of the operation is high level or low level, it is considered that the clock output of the delay unit and the source clock complete the inversion at this time; its input terminal and The output end of sampling register 604 is connected, and the output end of clock inversion detection unit 603 is connected with the input end of arithmetic unit 605; The clock output of the delay unit is sampled once; the clock inversion detection unit 603 determines whether the target phase difference is detected according to the sampling result of the sampling register 604; when the target phase difference is detected, the target output by the control unit 602 will be turned on step by step at this time. The information is used as the first information corresponding to the target phase difference, and is output to the operation circuit 605 .
  • the step-by-step start control unit 602 is notified to start the automatic calibration work;
  • the clock inversion detection unit 603 determines that the 180-degree target phase difference has been detected according to the sampling result of the sampling register 604, and now the step-by-step opening control unit 602 has opened 54 stages of delay units, then this information is used as the 180-degree target phase difference
  • the corresponding first information is output to the operation circuit.
  • the self-adaptive control circuit includes: an automatic calibration start judgment unit, a step-by-step start control unit and a clock inversion detection unit; where the automatic calibration start judgment unit determines that the automatic calibration enable signal is turned on, and then turns on the control unit step by step
  • the delay unit in the delay module is opened step by step, and the clock inversion detection unit determines whether the target phase difference is detected according to the sampling result of the sampling register;
  • the first information that is, the adaptive control circuit can accurately determine the corresponding relationship between the target phase difference and the delay unit, and provide accurate input information for the determination of the second information and the generation of homologous and out-of-phase clocks with accurate phase difference.
  • the computing circuit includes:
  • the first input terminal of the phase parameter calculation unit is connected with the clock inversion detection unit;
  • the first output terminal of the phase parameter calculation unit is connected with the delay configuration module, and the second output terminal of the phase parameter calculation unit is connected with the full addition and subtraction circuit , the output end of the full addition and subtraction circuit is connected to the second input end of the phase parameter operation unit;
  • the phase parameter operation unit is used to determine the third information of the delay unit corresponding to the second phase difference and the fourth information of the delay unit corresponding to the activation of the third phase difference according to the first information corresponding to the target phase difference and the first phase difference;
  • the full addition and subtraction circuit is used to determine the second information of the delay unit corresponding to the first phase difference according to the third information and the fourth information of the opened delay unit; the operation circuit calculates the phase difference by calling the full addition and subtraction unit Correct the delay unit configuration under the influence of process angle deviation, temperature and humidity at this time;
  • the operation circuit includes a phase parameter operation unit and a full addition and subtraction circuit; wherein, the first input terminal of the phase parameter operation unit is connected to the clock inversion detection unit; when the clock inversion detection unit detects the inversion phase difference, the inversion The number and position of the delay unit corresponding to the phase difference are output to the phase parameter calculation unit; the phase parameter unit determines the third information of the delay unit corresponding to the second phase difference and the third phase difference corresponding to the second phase difference according to the received information and the first phase difference The fourth information of the turned-on delay unit; wherein, the first phase difference includes the second phase difference and the third phase difference;
  • the second output terminal of the phase parameter calculation unit is connected with the full addition and subtraction circuit, and the output terminal of the full addition and subtraction circuit is connected with the second input terminal of the phase parameter calculation unit;
  • the third information and the fourth information are used to determine the second information of the delay unit corresponding to the first phase difference; and output the second information to the phase parameter calculation unit.
  • the first output end of the phase parameter operation unit is connected to the delay configuration module, and the phase parameter operation unit outputs the number and position of the delay units corresponding to the first phase difference to the delay configuration module.
  • the first input terminal of the phase parameter calculation unit is connected to the clock inversion detection unit, when the clock inversion detection unit detects a phase difference of 180 degrees corresponds to 54 delay units; the first phase difference is 33.75 degrees, and the second phase difference is 45 degrees , the third phase difference is 11.25 degrees, and the first phase difference can be obtained by subtracting the second phase difference and the third phase difference.
  • the information of the delay unit corresponding to the second phase difference can be obtained by shifting the binary number of the delay unit number 54 corresponding to the 180-degree phase difference, and shifting one bit to the right is equivalent to dividing by 2, then it can be known that turning on 27
  • the group delay unit is the configuration parameter that produces a 90-degree phase difference; and so on, shifting two digits to the right is the configuration parameter that produces a 45-degree phase difference; moving three digits to the right is the configuration parameter that produces a 22.5-degree phase difference; moving four digits to the right is 11.25 13 is the number of start-up delay units corresponding to a 45° difference, and 3 is the number of start-up delay units corresponding to a 11.25° difference.
  • the second output end of the phase parameter operation unit is connected with the full addition and subtraction circuit, and the output end of the full addition and subtraction circuit is connected with the second input end of the phase parameter operation unit; the phase parameter operation unit outputs 13 and 3 to the full addition and subtraction circuit, Determine the delay unit corresponding to the first phase difference of 33.75 degrees, that is, the number of delay units that are turned on corresponding to the first phase difference is 10, and output it to the delay configuration module.
  • the computing circuit after the computing circuit obtains the first information corresponding to the target phase difference output by the adaptive control circuit, it can accurately determine the second information of the delay unit corresponding to the first phase difference, and generate a phase difference for the delay module. Precise homologous out-of-phase clocks provide accurate input information.
  • the full addition and subtraction circuit includes: a two-choice circuit and a full adder; wherein, the input of the two-choice circuit is connected to the third output of the phase parameter calculation unit, and the output of the full adder serves as the output of the module;
  • the one-of-two circuit is used to select the corresponding operation mode according to the third control signal output by the phase parameter operation unit;
  • the full adder is configured to determine the second information of the delay unit corresponding to the first phase difference according to the third information and the fourth information of the enabled delay unit and the operation mode.
  • the full addition and subtraction circuit is shown in Figure 3, including: a two-choice circuit and a full adder; wherein, the two-choice circuit is used to select addition or subtraction, and the input terminal is connected to the third output terminal of the phase parameter operation unit Connection; two alternative circuits, used to select the corresponding operation method according to the third control signal output by the phase parameter operation unit; the third control signal includes the operation method it should adopt, addition operation or subtraction operation; CAL_A and CAL_B in the figure It includes the third information and the fourth information of the turn-on delay unit output by the phase parameter operation unit, and CAL_SUB includes the enablement of the full addition and subtraction circuit.
  • the full adder includes six 1-bit full adders connected end to end to form a six-bit full adder for data operations.
  • ADDER in the figure includes an adder and subtractor; its output terminal is used as the output terminal of the full addition and subtraction circuit, according to the phase parameter
  • the third information and the fourth information of the opening delay unit output by the operation unit, and the operation method determined by the two-choice module, and the operation of the third information and the fourth information can determine the delay unit corresponding to the first difference.
  • the second information and as the output of the full addition and subtraction circuit.
  • the number of delay units included in the third information and the fourth information that the phase parameter operation unit outputs to the full addition and subtraction circuit is 13 and 3, and the calculation mode adopted by the 2-choice 1 circuit is subtraction, then it is determined that the first phase difference corresponds to the opening The number of delay units is 10, and it is output.
  • the full addition and subtraction circuit can accurately determine the second information of the delay unit corresponding to the first phase difference after obtaining the third information and the fourth information output by the phase parameter operation unit and the operation mode, which is the delay
  • the timing module generates homogeneous and out-of-phase clocks with precise phase difference to provide accurate input information.
  • the delay module includes: a decoder and a plurality of delay units; wherein the decoder is used to control the corresponding delay unit to be turned on according to the first control signal.
  • the delay module includes a decoder and multiple delay units.
  • the delay module includes a plurality of end-to-end delay units, which are used to form the entire delay circuit; the decoder controls the first control signal of the delay unit corresponding to the second information output by the delay configuration module, and selects Corresponding delay units to form different phase differences; the decoder includes a 6-64-line decoder, which controls the opening or closing of the 64-level delay unit through six inputs; the delay module includes a 64-level delay unit, Delays with different phase differences are realized by turning on different numbers of delay units;
  • the clock has two directions: one is through the decoding control to enable, select the tri-state gate and the input 0 of the two-choice circuit, the clock is input from the delay unit, and then output to the tri-state gate, through the tri-state gate After that, it is output to the one-of-two circuit, and the one-of-two circuit is output to the next-stage delay small unit.
  • the second is to enable the decoding control, close the three-state gate, and select the input terminal 1 of the one-of-two circuit.
  • the clock does not pass through the delay circuit of the current stage, and directly enters the delay unit of the next stage through the input terminal 1 of the one-two circuit. .
  • the decoder includes a 6-64-line decoder
  • the first control signal of the delay unit corresponding to the second information output by the delay configuration module includes turning on 10 delay units, then the decoder controls to turn on the corresponding 10 delay units to generate accurate homologous and out-of-phase clocks.
  • the delay module after the delay module obtains the first control signal of the delay unit corresponding to the second information, it controls the corresponding delay unit to be turned on, so as to generate a homologous and out-of-phase clock with precise phase difference.
  • the homologous out-of-phase clock generation device further includes:
  • a gate control module wherein the output end of the gate control module is connected with the input end of the automatic calibration module
  • the gate control module is configured to control the automatic calibration module to be synchronously reset and clock gated after the automatic calibration enable is turned off according to the input automatic calibration enable signal and the source clock.
  • the output terminal of the gating module is connected to the input terminal of the automatic calibration module, and according to the input automatic calibration enable signal and source clock, when the automatic calibration function is completed, the automatic calibration module is controlled to reset to the preset state and shut down Automatically calibrates modules to save power consumption.
  • the gating module when a 33.75-degree homologous and out-of-phase clock is generated, when the gating module receives an automatic calibration signal to enable the shutdown and source clock, that is, after the calibration work is completed, the automatic automatic calibration module is controlled to reset to the preset initial state and shut down Automatically calibrate the module to save power consumption.
  • the gating module controls the automatic calibration module to reset to the preset state and shut down the automatic calibration module according to the input automatic calibration enable signal and the source clock. Automatically calibrate the module to save power consumption.
  • the gate control module includes:
  • the two-level synchronization register is used to control the automatic calibration module to be reset synchronously after the automatic calibration enable is turned off according to the input automatic calibration enable signal and the source clock, and output the fourth control signal to the gate control unit;
  • the gating unit is used to control the automatic calibration module to perform clock gating according to the fourth control signal output by the synchronization register and the source clock;
  • the gate control unit includes an exclusive OR gate, a storage and an AND gate circuit to achieve the purpose of gate control.
  • the gating module is shown in Figure 5, which mainly includes a two-stage synchronization register and a gating unit; the synchronization register is used to delay the enable signal for a certain period of time, such as two clock cycles, so that the automatic calibration of the single-module off After it is cut off, reset it to the preset state synchronously; and output the fourth control signal for turning off the automatic calibration module to the gating unit, and then the gating unit performs clock gating on the automatic calibration module, after the calibration task is completed , turn off the automatic calibration module to save power consumption.
  • the synchronization register is used to delay the enable signal for a certain period of time, such as two clock cycles, so that the automatic calibration of the single-module off After it is cut off, reset it to the preset state synchronously; and output the fourth control signal for turning off the automatic calibration module to the gating unit, and then the gating unit performs clock gating on the automatic calibration module, after the calibration task is completed , turn off the automatic calibration module
  • the gating module when a 33.75-degree homologous and out-of-phase clock is generated, when the gating module receives an automatic calibration signal to enable the shutdown and source clock, that is, after the calibration work is completed, the two-stage synchronization register will delay the enable signal for a certain period of time, for example, two cycle, so that after the automatic calibration module is turned off, it is reset to the preset state synchronously; the gate control unit turns off the automatic calibration module to achieve the purpose of saving power consumption.
  • the gating module controls the automatic calibration according to the input automatic calibration enable signal and the source clock, and the two-stage synchronization register and the gating unit The module resets to the preset state and turns off the automatic calibration module to save power consumption.
  • Automatic calibration start judgment unit 601 step-by-step start control unit 602, clock inversion detection unit 603, sampling register 604, phase parameter operation unit 605, full addition and subtraction circuit 606, delay configuration module 607, decoder 608 and multiple Delay unit 609;
  • the automatic calibration module includes: an automatic calibration start judgment unit 601, a step-by-step start control unit 602, a clock inversion detection unit 603, a sampling register 604, a phase parameter operation unit 605, and a full addition and subtraction circuit 606;
  • the delay module includes: a decoder 608 and a plurality of delay units 609;
  • the adaptive control circuit includes: a dynamic calibration start judgment unit 601, a step-by-step start control unit 602 and a clock inversion detection unit 603;
  • the operation circuit includes: a phase parameter operation unit 605 and a full addition and subtraction circuit 606 .
  • the output terminal of the automatic calibration opening judgment unit 601 in the automatic calibration module is respectively connected with the step-by-step opening control unit 602 and the delay configuration module 607;
  • a second control signal is output to notify the step-by-step opening control unit 602 to start the automatic calibration work; automatic calibration;
  • the output terminal of opening control unit 602 is connected with delay configuration module 607 and sampling register 604 step by step; Stage opens the delay unit 609 in the delay module, and outputs the target information of the delay unit that is opened to sampling register 604, and comprises the quantity and the position of the delay unit that opens at present in the target information;
  • sampling register 604 The output end of sampling register 604 is connected with adaptive control circuit, and adaptive control circuit determines whether to detect target phase difference according to the clock output of delay unit 609 in the delay module sampled by sampling register 604, if detect target phase difference, obtain The first information corresponding to the target difference;
  • the input end of clock inversion detection unit 603 is connected with the output end of sampling register 604, and the output end of clock inversion detection unit 603 is connected with the input end of phase parameter operation unit 605;
  • the sampling register 604 samples the clock output of the delay unit 609 in the delay module;
  • the clock inversion detection unit 603 determines whether the target phase difference is detected according to the sampling result of the sampling register 604; when the target phase difference is detected In this case, the target information output by the step-by-step opening control unit 602 at this time is used as the first information corresponding to the target phase difference, and is output to the arithmetic circuit;
  • the adaptive control circuit when the input automatic calibration of the adaptive control circuit is enabled and the first phase difference is 90 degrees, the adaptive control circuit turns on the delay unit 609 in the delay module step by step; , the sampling register 604 samples the clock output of the delay unit 609 in the delay module once; then the adaptive control circuit determines whether the target phase difference is detected according to the clock output sampled by the sampling register 604, and obtains the target phase difference if the target phase difference is detected Corresponding information; if the control unit 602 is turned on step by step until the 54 levels are turned on, the adaptive control circuit determines that the target phase difference of 180 degrees is detected according to the clock output sampled by the sampling register 604, then 54 delay units and position information are 180 degrees The degree target differs from the corresponding first information.
  • the first input terminal of the phase parameter operation unit 605 in the arithmetic circuit is connected with the clock inversion detection unit 603; when the clock inversion detection unit 603 detects the inversion phase difference, then the quantity and the position of the delay unit corresponding to the inversion phase difference Output to the phase parameter operation unit 605; the phase parameter operation unit 605 determines the third information of the delay unit corresponding to the opening of the second phase difference and the fourth information of the delay unit corresponding to the opening of the third phase difference according to the received information and the first phase difference. information; wherein, the first phase difference includes the second phase difference and the third phase difference and is obtained through calculation;
  • the second output end of the phase parameter operation unit 605 is connected with the full addition and subtraction circuit 606, and the output end of the full addition and subtraction circuit 606 is connected with the second input end of the phase parameter operation unit 605;
  • the outputted third information and fourth information for turning on the delay unit determine the second information of the delay unit corresponding to the first phase difference; and output the second information to the phase parameter calculation unit 605 .
  • the first output terminal of the phase parameter calculation unit 605 is connected to the delay configuration module 607 , and the phase parameter calculation unit 605 outputs the number and position of the delay units corresponding to the first phase difference to the delay configuration module 607 .
  • the first input terminal of the phase parameter calculation unit 605 is connected to the clock inversion detection unit 603, when the clock inversion detection unit 603 detects a phase difference of 180 degrees corresponds to 54 delay units; the first phase difference is 33.75 degrees, and the second phase difference is 45 degrees, the third phase difference is 11.25 degrees, and the first phase difference can be obtained by subtracting the second phase difference and the third phase difference.
  • the information of the delay unit corresponding to the second phase difference can be obtained by shifting the binary number of the delay unit number 54 corresponding to the 180-degree phase difference, and shifting one bit to the right is equivalent to dividing by 2, then it can be known that turning on 27
  • the group delay unit is the configuration parameter that produces a 90-degree phase difference; and so on, shifting two digits to the right is the configuration parameter that produces a 45-degree phase difference; moving three digits to the right is the configuration parameter that produces a 22.5-degree phase difference; moving four digits to the right is 11.25 13 is the number of start-up delay units corresponding to a 45° difference, and 3 is the number of start-up delay units corresponding to a 11.25° difference.
  • phase parameter operation unit 605 is connected with full addition and subtraction circuit 606, and the output end of full addition and subtraction circuit 606 is connected with the second input end of phase parameter operation unit 605;
  • Phase parameter operation unit 605 outputs 13 and 3 to The full addition and subtraction circuit determines the delay unit corresponding to the first phase difference of 33.75 degrees, that is, the number of delay units that are turned on corresponding to the first phase difference is 10, and outputs it to the delay configuration module 607 .
  • the delay configuration module 607 outputs the first control signal to the delay module by acquiring the second information of the delay unit corresponding to the first phase difference output by the automatic calibration module;
  • the delay configuration module obtains the second information of the delay unit corresponding to the first phase difference of 33.75 degrees through the automatic calibration module.
  • the number of delay units included is 10, and then outputs its corresponding information as the first control signal to the delay module ;
  • the delay module includes a decoder 608 and a plurality of delay units 609, wherein the decoder 608 controls the corresponding delay unit according to the first control signal of the delay unit corresponding to the second information output by the delay configuration module 607 open.
  • the delay module obtains the first control signal and the source clock output by the delay configuration module 607, and controls the line decoder according to the first control signal to determine which delay units 609 in the delay module are turned on, that is, according to the first control signal.
  • the delay unit in the delay module is turned on or off to generate accurate homologous and out-of-phase clocks.
  • the delay module obtains the first control signal output by the delay configuration module 607 and the source clock, and enables 10 delay units to realize a delay with a phase difference of 33.75 degrees.
  • the same-source out-of-phase clock generation device includes an automatic calibration module, a delay configuration module, and a delay module connected in sequence; after the automatic calibration module obtains the first information of the delay unit corresponding to the target phase difference, it combines The corresponding relationship between the target phase difference and the first phase difference to be generated can accurately determine the second information of the delay unit corresponding to the first phase difference; the delay configuration module and the delay module control their correspondence according to the second information
  • the opening of the delay unit that is, the automatic calibration module, the delay configuration module and the delay module can efficiently generate homogeneous and out-of-phase clocks with accurate phase difference.
  • FIG. 7 is a schematic flowchart of a method for generating homologous and out-of-phase clocks provided by the present invention.
  • the homologous out-of-phase clock generation method provided in this embodiment includes:
  • Step 701 obtaining the first phase difference
  • Step 702 according to the first phase difference and the first information of the delay unit corresponding to the target phase difference, determine the second information of the delay unit corresponding to the first phase difference;
  • Step 703 Turn on the delay unit corresponding to the first phase difference according to the second information of the delay unit corresponding to the first phase difference and the source clock, and output a same-source but out-of-phase clock.
  • the first phase difference of the same-source out-of-phase clock to be generated obtains the first phase difference of the same-source out-of-phase clock to be generated, and determine the first phase difference and the corresponding delay according to the first information of the delay unit that is corresponding to the target phase difference and the corresponding relationship between the first phase difference and the target phase difference
  • the second information of the time unit that is, the number and position of the delay units to be turned on to generate the homologous out-of-phase clock with the first phase difference
  • the delay unit corresponding to the first phase difference is turned on, that is, the corresponding delay unit is turned on according to the determined second information, and the required The first phase difference of the same-source out-of-phase clock.
  • the obtained first phase difference is 90 degrees
  • the target phase difference is the opposite phase difference, that is, 180 degrees.
  • the corresponding relationship between the 90-degree phase difference determine the number of delay units included in the second information of the delay unit with a 90-degree phase difference enabled is 27, and then open the corresponding 27 delay units according to the second information and the source clock to generate Homologous and out-of-phase clocks with a 90-degree phase difference.
  • the delay corresponding to the first phase difference can be accurately determined according to the corresponding relationship between the first phase difference and the target phase difference
  • the second information of the unit according to the source clock and the second information to control the opening of its corresponding delay unit, it can efficiently generate a homogeneous and out-of-phase clock with precise phase difference.
  • An embodiment of the present invention also provides an electronic device, including the same-source out-of-phase clock generation device.
  • the present invention also provides a computer program product
  • the computer program product includes a computer program stored on a non-transitory computer-readable storage medium
  • the computer program includes program instructions, and when the program instructions are executed by a computer During execution, the computer can execute the homologous out-of-phase clock generation method provided by the above methods, the method includes: obtaining the first phase difference; according to the first phase difference and the first information of the delay unit corresponding to the target phase difference, determine the first The second information of the delay unit corresponding to the phase difference; according to the second information of the delay unit corresponding to the first phase difference and the source clock, turn on the delay unit corresponding to the first phase difference, and output the same-source out-of-phase clock.
  • the present invention also provides a non-transitory computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, it is implemented to perform the method for generating a clock with the same source and different phases provided above, the method
  • the method includes: acquiring the first phase difference; determining the second information of the delay unit corresponding to the first phase difference according to the first information of the delay unit corresponding to the first phase difference and the target phase difference; according to the first information of the delay unit corresponding to the first phase difference
  • the second information and the source clock turn on the delay unit corresponding to the first phase difference, and output the same-source and out-of-phase clock.
  • the device embodiments described above are only illustrative, wherein the small units described as separate components may or may not be physically separated, and the components displayed as small units may or may not be physical small units, That is, it can be located in one place, or it can be distributed to multiple small network units. Part or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. It can be understood and implemented by those skilled in the art without any creative efforts.
  • each implementation can be implemented by means of software plus a necessary general-purpose hardware platform, and of course also by hardware.
  • the essence of the above technical solution or the part that contributes to the prior art can be embodied in the form of software products, and the computer software products can be stored in computer-readable storage media, such as ROM/RAM, magnetic discs, optical discs, etc., including several instructions to make a computer device (which may be a personal computer, server, or network device, etc.) execute the methods described in various embodiments or some parts of the embodiments.

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Abstract

本发明提供一种同源异相时钟生成装置、方法和设备。该装置包括：依次连接的自动校准模块、延时配置模块和延时模块；其中，自动校准模块用于根据输入的自动校准使能信号，获取目标相差对应开启的延时单元的第一信息；根据第一信息，确定输入的第一相差对应的延时单元的第二信息；延时配置模块，用于根据第二信息，输出第一控制信号；延时模块，用于根据第一控制信号以及源时钟，开启延时模块中的延时单元，并输出同源异相时钟。本发明可以高效地生成相差精准的同源异相时钟。

Description

同源异相时钟生成装置、方法和设备 技术领域
本发明涉及信号处理技术领域，尤其涉及一种同源异相时钟生成装置、方法和设备。
背景技术
时钟是时序逻辑的基础，决定着逻辑单元中的状态何时更新，是保证电子组件能够完全同步工作的关键，若时钟不精准会导致系统功能的紊乱，因此时钟的精准性决定着系统能否健康良好的运行。
实际场景中应用的同源异相时钟，通常由一个锁相环或者延时锁相环产生，相位不需要相同，只要求相位固定；但由于工艺角、温湿度、电压、电路结构等影响，同批的量产设备在各个应用场景中，其同源异相时钟的相差往往存在个体差异性，不能精准控制。
目前对于时钟的精准性问题，通常的解决方法是配置引脚接入示波器,通过人工比对示波器的波形去校准时钟产生电路，但人工校准对批量化研究、生产、应用很不友好，需要耗费大量时间，效率较低。
发明内容
针对现有技术中的问题，本发明实施例提供一种同源异相时钟生成装置、方法和设备。
具体地，本发明实施例提供了以下技术方案：
第一方面，本发明实施例提供了一种同源异相时钟生成装置，包 括：
依次连接的自动校准模块、延时配置模块和延时模块；
其中，自动校准模块用于根据输入的自动校准使能信号，获取目标相差对应开启的延时单元的第一信息；根据第一信息，确定输入的第一相差对应的延时单元的第二信息；
延时配置模块，用于根据第二信息，输出第一控制信号；
延时模块，用于根据第一控制信号以及源时钟，开启延时模块中的延时单元，并输出同源异相时钟。
进一步地，所述自动校准模块，包括：
自适应控制电路、运算电路和采样寄存器；
其中，所述自适应控制电路的输入端用于接收输入的所述自动校准使能信号和所述第一相差；所述自适应控制电路的输出端与所述运算电路的输入端连接，所述运算电路的输出端与所述延时配置模块的输入端连接，所述延时配置模块的输出端与所述延时模块的输入端连接；所述采样寄存器的输入端与所述延时模块的输出端连接，所述采样寄存器的输出端与所述自适应控制电路连接；
所述自适应控制电路，具体用于根据所述自动校准使能信号，逐级开启所述延时模块中的延时单元，并依次根据所述采样寄存器对所述延时模块产生的异相时钟进行采样的采样结果，确定是否检测到目标相差，如果检测到所述目标相差，获取所述目标相差对应的第一信息；
所述采样寄存器，用于对所述延时模块产生的异相时钟进行采样，获取所述采样结果；
所述运算电路，用于根据所述目标相差对应的第一信息，确定所述第一相差对应的延时单元的第二信息。
进一步地，所述自适应控制电路包括：
自动校准开启判断单元、逐级开启控制单元和时钟反相检测单元；
其中，所述自动校准开启判断单元的输出端分别与所述逐级开启控制单元和所述延时配置模块连接；
所述逐级开启控制单元的输出端分别与所述延时配置模块和所述采样寄存器连接；所述时钟反相检测单元的输入端与所述采样寄存器的输出端连接，所述时钟反相检测单元的输出端与所述运算单元的输入端连接；
所述自动校准开启判断单元，用于根据所述自动校准使能信号，输出第二控制信号和所述第一相差；
所述逐级开启控制单元，用于根据所述第二控制信号，逐级开启所述延时模块中的延时单元，并向所述采样寄存器输出开启的延时单元的目标信息；
所述时钟反相检测单元，用于根据所述采样寄存器的采样结果，确定是否检测到目标相差；在检测到所述目标相差的情况下，将所述目标信息作为所述目标相差对应的第一信息，并向所述运算电路输出。
进一步地，所述运算电路，包括：
相位参数运算单元和全加减电路；
其中，所述相位参数运算单元的第一输入端与所述时钟反相检测单元连接；所述相位参数运算单元的第一输出端与所述延时配置模块连接，所述相位参数运算单元的第二输出端与所述全加减电路连接，所述全加减电路的输出端与所述相位参数运算单元的第二输入端连接；
所述相位参数运算单元用于根据所述目标相差对应的第一信息，以及所述第一相差，确定第二相差对应开启的延时单元的第三信息以及第三相差对应开启的延时单元的第四信息；
所述全加减电路，用于根据所述开启的延时单元的第三信息和第四信息，确定所述第一相差对应的延时单元的第二信息。
进一步地，所述全加减电路，包括：二选一电路和全加器；
其中，所述二选一电路的输入端与所述相位参数运算单元的第三输出端连接，所述全加器的输出端作为所述全加减电路的输出端；
所述二选一电路，用于根据所述相位参数运算单元输出的第三控制信号，选择对应的运算方式；
所述全加器，用于根据所述开启的延时单元的第三信息和第四信息以及所述运算方式，确定所述第一相差对应的延时单元的第二信息。
进一步地，所述延时模块，包括：
译码器和多个延时单元；
其中，所述译码器用于根据所述第一控制信号，控制对应的延时单元开启。
进一步地，门控模块，其中，所述门控模块的输出端与所述自动校准模块的输入端连接；
所述门控模块，用于根据输入的自动校准使能信号和源时钟，控制自动校准模块在自动校准使能关闭后被同步复位以及时钟门控。
进一步地，所述门控模块，包括：
依次连接的两级同步寄存器和门控单元；
其中，所述两级同步寄存器，用于根据输入的自动校准使能信号和源时钟，控制自动校准模块在自动校准使能关闭后被同步复位，向所述门控单元输出第四控制信号；
所述门控单元，用于根据所述同步寄存器输出的第四控制信号和所述源时钟控制所述自动校准模块进行时钟门控。
第二方面，本发明实施例还提供了一种同源异相时钟生成方法，包括：
获取第一相差；
根据第一相差以及目标相差对应开启的延时单元的第一信息，确定第一相差对应的延时单元的第二信息；
根据第一相差对应的延时单元的第二信息以及源时钟，开启第一 相差对应的延时单元，并输出同源异相时钟。
第三方面，本发明实施例还提供了一种电子设备，包括如第一方面所述同源异相时钟生成装置。
第四方面，本发明实施例还提供了一种非暂态计算机可读存储介质，其上存储有计算机程序，所述计算机程序被处理器执行时实现如第二方面所述同源异相时钟生成方法的步骤。
第五方面，本发明实施例还提供了一种计算机程序产品，包括计算机程序，所述计算机程序被处理器执行时实现如第二方面所述同源异相时钟生成方法的步骤。
本发明提供的同源异相时钟生成装置，包括依次连接的自动校准模块、延时配置模块和延时模块；其中自动校准模块获取目标相差对应开启的延时单元的第一信息后，结合目标相差与所要生成的第一相差之间的对应关系，即可以精准地确定出第一相差所对应的延时单元的第二信息；延时配置模块和延时模块根据第二信息控制其对应延时单元的开启，即通过自动校准模块、延时配置模块和延时模块就可以高效地生成相差精准的同源异相时钟。
附图说明
为了更清楚地说明本发明或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明提供的同源异相时钟生成装置的结构示意图一；
图2是本发明提供的同源异相时钟生成装置的自动校准模块示意图；
图3是本发明提供的同源异相时钟生成装置的全加减电路示意 图；
图4是本发明提供的同源异相时钟生成装置的延时模块中的延时单元示意图；
图5是本发明提供的同源异相时钟生成装置的门控模块示意图；
图6是本发明提供的同源异相时钟生成装置的结构示意图二；
图7是本发明提供的同源异相时钟生成方法的流程示意图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，下面将结合本发明中的附图，对本发明中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明实施例的装置可以应用于同源异相时钟生成的场景中，高效地生成相差精准的同源异相时钟。
相关技术中，同源异相时钟通常由一个锁相环或者延时锁相环产生，相位不需要相同，只要求相位固定；但由于工艺角、温湿度、电压、电路结构等影响，同批的量产设备在各个应用场景中，其同源异相时钟的相差往往存在个体差异性，不能精准控制。
对于时钟的精准性问题，通常的解决方法是配置引脚接入示波器,通过人工比对示波器的波形去校准时钟产生电路，但人工校准对批量化研究、生产、应用很不友好，需要耗费大量时间，效率较低。
本发明实施例的同源异相时钟生成装置，包括依次连接的自动校准模块、延时配置模块和延时模块；自动校准模块根据输入的自动校准使能信号，获取目标相差对应开启的延时单元的第一信息；根据第一信息，确定输入的第一相差对应的延时单元的第二信息；延时配置模块根据第二信息，输出第一控制信号；延时模块根据第一控制信号 以及源时钟，开启延时模块中的延时单元，最终高效地生成相差精准的同源异相时钟。
下面结合图1-图7以具体的实施例对本发明的技术方案进行详细说明。下面这几个具体的实施例可以相互结合，对于相同或相似的概念或过程可能在某些实施例不再赘述。
图1是本发明实施例提供的同源异相时钟生成装置一实施例的示意图。如图1所示，本实施例提供的同源异相时钟生成装置，包括：
依次连接的自动校准模块101、延时配置模块102和延时模块103；
其中，自动校准模块101用于根据输入的自动校准使能信号，获取目标相差对应开启的延时单元的第一信息；根据第一信息，确定输入的第一相差对应的延时单元的第二信息；
延时配置模块102，用于根据第二信息，输出第一控制信号；
延时模块103，用于根据第一控制信号以及源时钟，开启延时模块中的延时单元，并输出同源异相时钟。
具体的，同源异相时钟生成装置包括自动校准模块101、延时配置模块102和延时模块103，三者依次连接。其中自动校准模块101根据输入的自动校准使能信号，获取目标相差对应开启的延时单元的第一信息，其中，目标相差包括与源时钟反相的180度相差，第一信息中包括延时单元的数量和还有延时单元相应的位置信息；然后自动校准模块根据第一信息，确定输入的第一相差对应的延时单元的第二信息。
例如，同源异相时钟的自动校准模块101根据输入的自动校准使能信号进行判断，如果自动校准使能信号打开，则开启自动校准功能；若自动校准模块101获取到目标相差是180度，其对应开启的延时单元的第一信息包括的延时单元的数量为54个；当自动校准模块101确定输出的第一相差为90度，则根据第一信息就可以确定出：第一相差90度对应的延时单元的第二信息包括的延时单元的数量为第一 信息中54对应的二进制右移一位，等同于54除以2，即90°相差的第二信息包括的延时单元的数量为27个。
延时配置模块102通过获取自动校准模块输出的第一相差对应的延时单元的第二信息，输出第一控制信号给延时模块103。其主要由三输入选择器构成，对输入进行选择并将其作为输出控制译码器。
例如，延时配置模块102通过自动校准模块101获取第一相差90度对应的延时单元的第二信息包括的延时单元的数量为27个，则输出其对应信息作为第一控制信号给延时模块103；
延时模块103，用于根据第一控制信号以及源时钟，开启延时模块中103的延时单元，并输出同源异相时钟。
延时模块103通过获取延时配置模块102输出的第一控制信号以及源时钟，根据第一控制信号控制译码器确定开启延时模块中103的哪些延时单元，即根据第一控制信号确定延时模块103中的延时单元的开启或关闭，生成相差精准的同源异相时钟。
例如，延时模块103通过获取延时配置模块102输出的第一控制信号以及源时钟，开启27个延时单元即可生成90度相差的同源异相时钟。
本实施例的装置，同源异相时钟生成装置包括依次连接的自动校准模块、延时配置模块和延时模块；其中自动校准模块获取目标相差对应开启的延时单元的第一信息后，结合目标相差与所要生成的第一相差之间的对应关系，即可以精准地确定出第一相差所对应的延时单元的第二信息；延时配置模块和延时模块根据第二信息控制其对应延时单元的开启，即通过自动校准模块、延时配置模块和延时模块就可以高效地生成相差精准的同源异相时钟。
在一实施例中，如图2所示，自动校准模块，包括：
自适应控制电路201、运算电路202和采样寄存器205；
其中，自适应控制电路201的输入端用于接收输入的自动校准使 能信号和第一相差；自适应控制电路201的输出端与运算电路202的输入端连接，运算电路202的输出端与延时配置模块203的输入端连接，延时配置模块203的输出端与延时模块204的输入端连接；采样寄存器205的输入端与延时模块204的输出端连接，采样寄存器205的输出端与自适应控制电路201连接；
自适应控制电路201，具体用于根据自动校准使能信号，逐级开启延时模块204中的延时单元，并依次根据采样寄存器205对延时模块204产生的异相时钟进行采样确定是否检测到目标相差，如果检测到目标相差，获取目标相差对应的第一信息；
采样寄存器205，用于对延时模块204产生的异相时钟进行采样，获取采样结果；
运算电路202，用于根据目标相差对应的第一信息，确定第一相差对应的延时单元的第二信息。
具体的，自适应控制电路201的第一输入为自动校准使能信号和第一相差，若自动校准使能信号打开，则自适应控制电路逐级开启延时模块204中的延时单元；
延时模块204的输出端与采样寄存器205的输入端连接，当自适应控制电路201逐级开启延时单元控制自加一次，采样寄存器205就对延时模块204中的延时单元时钟输出采样一次；
采样寄存器205包括一个64位寄存器，当自适应控制电路201逐级开启延时单元控制自加一次，就对延时模块204的时钟输出采样一次，直至时钟反相检测单元检测到反相，就停止采样；其输出端与自适应控制电路201连接，自适应控制电路201根据采样寄存器205采样的延时模块204中的延时单元的时钟输出，确定是否检测到目标相差，如果检测到目标相差，获取目标相差对应的第一信息；
自适应控制电路201的输出端与运算电路202的输入端连接，当自适应控制电路201获取目标相差对应的第一信息，运算电路202根 据目标相差对应的第一信息，结合目标相差与第一相差的对应关系，确定第一相差对应的延时单元的第二信息。
运算电路202的输出端与延时配置模块203的输入端连接，延时配置模块203获取运算电路202输出的第二信息，生成第一控制信号；
延时配置模块203的输出端与延时模块204的输入端连接，延时模块204获取第一控制信号，输出第一相差的同源异相异相时钟。
例如，当自适应控制电路201的输入自动校准使能打开，第一相差为90度，则自适应控制电路201逐级开启延时模块204中的延时单元；当延时单元逐级开启控制自加一次，采样寄存器205就对延时模块204中的延时单元时钟输出采样一次；然后自适应控制电路201根据采样寄存器205采样的时钟输出，例如采样到逻辑0或逻辑1，确定是否检测到目标相差，如果检测到目标相差，获取目标相差对应的信息；如果延时单元逐级增加直至开启54级时，自适应控制电路201根据采样寄存器205采样的时钟输出确定检测到180度的目标相差，则54个延时单元及位置信息就是180度目标相差对应的第一信息。
运算电路202根据第一信息，结合180度目标相差与90度第一相差的对应关系，将第一信息中54的二进制数右移一位，等同于54除以2，即确定出对应的27个延时单元就是产生90°相差的第二信息。
延时配置模块203根据第一信息生成第一控制信号，即第一控制信号用于指示延时模块204应当开启哪些延时单元，例如当第一控制信号为二进制的11011，延时模块204获取第一控制信号后开启对应的27个延时单元即可以生成90度第一相差的同源异相时钟。
上述实施例的装置，自动校准模块，包括：自适应控制电路、运算电路和采样寄存器；其中，自适应控制电路根据采样寄存器采样的时钟输出，确定是否检测到目标相差，如果检测到目标相差，获取目 标相差对应的第一信息；运算电路根据第一信息，结合目标相差与第一相差的对应关系，确定第一相差对应的延时单元的第二信息；即自动校准模块可以精准地确定所要输出的相差时钟对应的延时单元的信息，为延时配置模块及延时模块高效地生成相差精准的同源异相时钟提供准确的输入信息。
在一实施例中，如图6所示，自适应控制电路包括：
自动校准开启判断单元601、逐级开启控制单元602和时钟反相检测单元603；
其中，自动校准开启判断单元601的输出端分别与逐级开启控制单元602和延时配置模块607连接；
逐级开启控制单元601的输出端分别与延时配置模块607和采样寄存器604连接；时钟反相检测单元603的输入端与采样寄存器604的输出端连接，时钟反相检测单元603的输出端与运算单元的输入端连接；
自动校准开启判断单元601，用于根据自动校准使能信号，输出第二控制信号和第一相差；
逐级开启控制单元602，用于根据第二控制信号，逐级开启延时模块中的延时单元，并向采样寄存器604输出开启的延时单元的目标信息；
时钟反相检测单元603，用于根据采样寄存器604的采样结果，确定是否检测到目标相差；在检测到目标相差的情况下，将目标信息作为目标相差对应的第一信息，并向运算电路输出。
具体的，自适应控制电路包括：自动校准开启判断单元601、逐级开启控制单元602和时钟反相检测单元603；
其中，自动校准开启判断单元601的输出端分别与逐级开启控制单元602和延时配置模块607连接；当自动校准开启判断单元601接收自动校准使能信号后，判断自动校准使能信号打开，则输出第二控 制信号通知逐级开启控制单元602需要开始进行自动校准工作；若判断自动校准使能信号关闭，则输出第二控制信号通知延时配置模块607，不需要进行自动校准。
逐级开启控制单元602包括一个六位计数器，其计数值对应线译码器的输入；在时钟反相检测单元检测到反相前，每隔四个周期加1，直至时钟反相检测单元检测到反相就停止运算；其输出端分别与延时配置模块607和采样寄存器604连接；逐级开启控制单元602若收到自动校准开启判断单元601的第二控制信号，则根据第二控制信号逐级开启延时模块中的延时单元，并向采样寄存器604输出开启的延时单元的目标信息，目标信息中包括目前开启的延时单元的数量和位置；
时钟反相检测单元603主要对采样寄存器604进行缩位或运算，如果运算结果为高电平或低电平，即认为此时延时单元的时钟输出与源时钟完成反相；其输入端与采样寄存器604的输出端连接，时钟反相检测单元603的输出端与运算单元605的输入端连接；当延时单元逐级开启控制单元602自加一次，采样寄存器604就对延时模块中的延时单元时钟输出采样一次；时钟反相检测单元603根据采样寄存器604的采样结果，确定是否检测到目标相差；在检测到目标相差的情况下，将此时逐级开启控制单元602输出的目标信息作为目标相差对应的第一信息，并向运算电路605输出。
例如，当自动校准开启判断单元601接收自动校准使能信号后，判断自动校准使能信号打开，则通知逐级开启控制单元602需要开始进行自动校准工作；逐级开启控制单元602逐级开启延时模块中的延时单元，并向采样寄存器604输出开启的延时单元的目标信息；逐级开启控制单元602每自加一次，采样寄存器604就对延时模块中的延时单元时钟输出采样一次；若时钟反相检测单元603根据采样寄存器604的采样结果，确定已检测到180度目标相差，此时逐级开启控制单元602已开启54级延时单元，则将此信息作为180目标相差对应 的第一信息，并输出给运算电路。
上述实施例的装置，自适应控制电路包括：自动校准开启判断单元、逐级开启控制单元和时钟反相检测单元；其中自动校准开启判断单元确定自动校准使能信号打开后，逐级开启控制单元逐级开启延时模块中的延时单元，时钟反相检测单元根据采样寄存器的采样结果，确定是否检测到目标相差；如果检测到目标相差即将此时开启的延时单元的数量和位置作为第一信息；即自适应控制电路可以精准地确定出目标相差与延时单元的对应关系，为第二信息的确定及生成相差精准的同源异相时钟提供准确的输入信息。
在一实施例中，运算电路，包括：
相位参数运算单元和全加减电路；
其中，相位参数运算单元的第一输入端与时钟反相检测单元连接；相位参数运算单元的第一输出端与延时配置模块连接，相位参数运算单元的第二输出端与全加减电路连接，全加减电路的输出端与相位参数运算单元的第二输入端连接；
相位参数运算单元用于根据目标相差对应的第一信息，以及第一相差，确定第二相差对应开启的延时单元的第三信息以及第三相差对应开启的延时单元的第四信息；
全加减电路，用于根据开启的延时单元的第三信息和第四信息，确定第一相差对应的延时单元的第二信息；运算电路通过调用全加减单元进行运算，运算出相差对应此时工艺角偏差、温湿度等影响下修正延时单元配置；
具体的，运算电路包括相位参数运算单元和全加减电路；其中，相位参数运算单元的第一输入端与时钟反相检测单元连接；当时钟反相检测单元检测到反相相差，则将反相相差对应的延时单元的数量和位置输出给相位参数运算单元；相位参数单元根据收到的信息和第一相差，确定第二相差对应开启的延时单元的第三信息以及第三相差对 应开启的延时单元的第四信息；其中，第一相差包括第二相差和第三相差进行运算得到；
相位参数运算单元的第二输出端与全加减电路连接，全加减电路的输出端与相位参数运算单元的第二输入端连接；全加减单元根据相位参数运算单元输出的开启延时单元的第三信息和第四信息，确定第一相差对应的延时单元的第二信息；并将第二信息输出至相位参数运算单元。
相位参数运算单元的第一输出端与延时配置模块连接，相位参数运算单元将第一相差对应的延时单元的数量和位置输出至延时配置模块。
例如，相位参数运算单元的第一输入端与时钟反相检测单元连接，当时钟反相检测单元检测到180度相差对应54个延时单元；第一相差为33.75度，第二相差为45度，第三相差为11.25度，第二相差和第三相差减法运算可以得到第一相差。其中，第二相差对应的延时单元的信息可以通过180度相差对应的延时单元数量54的二进制数通过移位得到，右移一位，等同于除以2，那么就可以知道，开启27组延时单元就是产生90度相差的配置参数；依次类推，右移两位，就是产生45度相差的配置参数；右移三位，就是产生22.5度相差的配置参数；右移四位就是11.25度相差的配置参数；最终得到13为45°相差对应的开启延时单元的数量，3为11.25°相差对应的开启延时单元的数量。
相位参数运算单元的第二输出端与全加减电路连接，全加减电路的输出端与相位参数运算单元的第二输入端连接；相位参数运算单元将13和3输出给全加减电路，确定第一相差33.75度对应的延时单元，即第一相差对应开启的延时单元的数量为10，并将其输出至延时配置模块。
上述实施例的装置，运算电路在获取自适应控制电路输出的目标 相差对应的第一信息后，就可以精准地确定出第一相差对应的延时单元的第二信息，为延时模块生成相差精准的同源异相时钟提供准确的输入信息。
在一实施例中，全加减电路，包括：二选一电路和全加器；其中，二选一电路的输入端与相位参数运算单元的第三输出端连接，全加器的输出端作为模块的输出端；
二选一电路，用于根据相位参数运算单元输出的第三控制信号，选择对应的运算方式；
全加器，用于根据开启的延时单元的第三信息和第四信息以及运算方式，确定第一相差对应的延时单元的第二信息。
具体的，全加减电路如图3所示，包括：二选一电路和全加器；其中，二选一电路用于选择加法还是减法运算，输入端与相位参数运算单元的第三输出端连接；二选一电路，用于根据相位参数运算单元输出的第三控制信号，选择对应的运算方式；第三控制信号包含其应采用的运算方式，加运算还是减运算；图中CAL_A和CAL_B包括相位参数运算单元输出的开启延时单元的第三信息和第四信息，CAL_SUB包括全加减电路的使能。
全加器包括六个首尾相连的1位全加器，构成六位全加器，用于数据运算，图中ADDER包括加减器；其输出端作为全加减电路的输出端，根据相位参数运算单元输出的开启延时单元的第三信息和第四信息，以及二选一模块确定的运算方式，对第三信息和第四信息进行运算，即可确定第一差对应的延时单元的第二信息，并作为全加减电路的输出。
例如，相位参数运算单元输出至全加减电路的第三信息和第四信息包括的延时单元的数量为13和3，二选1电路采用的运算方式为减法，则确定第一相差对应开启的延时单元的数量为10，并将其输出。
上述实施例的装置，全加减电路在获取相位参数运算单元输出的第三信息和第四信息以及运算方式，就可以精准地确定出第一相差对应的延时单元的第二信息，为延时模块生成相差精准的同源异相时钟提供准确的输入信息。
在一实施例中，延时模块，包括：译码器和多个延时单元；其中，译码器用于根据第一控制信号，控制对应的延时单元开启。
具体的，延时模块中包括译码器和多个延时单元。其中，延时模块中包含多个首尾相连的延时单元，用于构成整个延时电路；译码器根据延时配置模块输出的第二信息对应的延时单元的第一控制信号，选通对应的延时单元，以形成不同的相差；译码器包括6线-64线译码器，通过六输入，控制64级延时单元的开启或关闭；延时模块包括64级延时单元，通过开启不同数量的延时单元实现不同相差的延时；延时单元结构如图4所示：每个延时单元均包括延时电路、三态门、二选一电路；单就延时单元而言，时钟有两条走向：一是通过译码控制使能，选通三态门和二选一电路输入0端，时钟从延时单元输入，后输出至三态门，经过三态门后，输出至二选一电路，由二选一电路输出至下一级延时小单元。二是通过译码控制使能，关闭三态门，选通二选一电路输入1端，时钟不经过当前级延时电路，经有二选一电路输入1端直接进入下一级延时单元。
例如，译码器包括6线-64线译码器，延时配置模块输出的第二信息对应的延时单元的第一控制信号包括开启10个延时单元，则译码器控制开启对应的10个延时单元，生成相差精准的同源异相时钟。
上述实施例的装置，延时模块获取第二信息对应的延时单元的第一控制信号后，控制对应的延时单元开启，就可以生成相差精准的同源异相时钟。
在一实施例中，同源异相时钟生成装置，还包括：
门控模块，其中，门控模块的输出端与自动校准模块的输入端连 接；
门控模块，用于根据输入的自动校准使能信号和源时钟，控制自动校准模块在自动校准使能关闭后被同步复位以及时钟门控。
具体的，门控模块的输出端与自动校准模块的输入端连接，根据输入的自动校准使能信号和源时钟，当自动校准功能完成后，控制自动校准模块复位至预设状态，并关断自动校准模块，节省功耗。
例如，当生成33.75度同源异相时钟后，当门控模块收到自动校准信号使能关闭和源时钟，即校准工作结束后，控制自动自动校准模块复位至预设的初始状态，并关断自动校准模块，达到节省功耗的目的。
上述实施例的装置，当生成相差精准的同源异相时钟后，即校准工作完成后，门控模块根据输入的自动校准使能信号和源时钟，控制自动校准模块复位至预设状态并关断自动校准模块，达到节省功耗的目的。
在一实施例中，门控模块，包括：
依次连接的两级同步寄存器和门控单元；
其中，两级同步寄存器，用于根据输入的自动校准使能信号和源时钟，控制自动校准模块在自动校准使能关闭后被同步复位，向门控单元输出第四控制信号；
门控单元，用于根据同步寄存器输出的第四控制信号和源时钟控制自动校准模块进行时钟门控；
可选地，门控单元如图5所示，包括异或门、储存器和与门电路，达到门控的目的。
具体的，门控模块如图5所示，主要包括一个两级同步寄存器和门控单元；同步寄存器用于对使能信号进行延时一定时长，例如两个时钟周期，使得自动校准单模块关断后，将其同步复位至预设状态；并将用于关断自动校准模块的第四控制信号输出至门控单元，然后门 控单元对自动校准模块进行时钟门控，在校准任务结束后，关断自动校准模块，节省功耗。
例如，当生成33.75度同源异相时钟后，当门控模块收到自动校准信号使能关闭和源时钟，即校准工作结束后，两级同步寄存器将使能信号延时一定时长，例如两个周期，使得自动校准模块被关断后，同步复位至预设状态；门控单元关断自动校准模块，达到节省功耗的目的。
上述实施例的装置，当生成相差精准的同源异相时钟后，即校准工作完成后，门控模块根据输入的自动校准使能信号和源时钟，两级同步寄存器和门控单元控制自动校准模块复位至预设状态并关断自动校准模块，达到节省功耗的目的。
示例性的，同源异相时钟生成装置结构示意图如图6所示：
本实施例提供的装置，包括：
自动校准开启判断单元601、逐级开启控制单元602、时钟反相检测单元603、采样寄存器604、相位参数运算单元605、全加减电路606、延时配置模块607、译码器608和多个延时单元609；
其中，自动校准模块包括：自动校准开启判断单元601、逐级开启控制单元602、时钟反相检测单元603、采样寄存器604、相位参数运算单元605和全加减电路606；
延时模块包括：译码器608和多个延时单元609；
自适应控制电路包括：动校准开启判断单元601、逐级开启控制单元602和时钟反相检测单元603；
运算电路包括：相位参数运算单元605和全加减电路606。
其中，自动校准模块中的自动校准开启判断单元601的输出端分别与逐级开启控制单元602和延时配置模块607连接；当自动校准开启判断单元601接收自动校准使能信号后，判断自动校准使能信号打开，则输出第二控制信号通知逐级开启控制单元602需要开始进行自 动校准工作；若判断自动校准使能信号关闭，则输出第二控制信号通知延时配置模块607，不需要进行自动校准；
逐级开启控制单元602的输出端分别与延时配置模块607和采样寄存器604连接；逐级开启控制单元602若收到自动校准开启判断单元601的第二控制信号，则根据第二控制信号逐级开启延时模块中的延时单元609，并向采样寄存器604输出开启的延时单元的目标信息，目标信息中包括目前开启的延时单元的数量和位置；
采样寄存器604的输出端与自适应控制电路连接，自适应控制电路根据采样寄存器604采样的延时模块中的延时单元609的时钟输出，确定是否检测到目标相差，如果检测到目标相差，获取目标相差对应的第一信息；
时钟反相检测单元603的输入端与采样寄存器604的输出端连接，时钟反相检测单元603的输出端与相位参数运算单元605的输入端连接；当逐级开启控制单元602每4个时钟周期自加一次，采样寄存器604就对延时模块中的延时单元609时钟输出采样一次；时钟反相检测单元603根据采样寄存器604的采样结果，确定是否检测到目标相差；在检测到目标相差的情况下，将此时逐级开启控制单元602输出的目标信息作为目标相差对应的第一信息，并向运算电路输出；
例如，当自适应控制电路的输入自动校准使能打开，第一相差为90度，则自适应控制电路逐级开启延时模块中的延时单元609；当逐级开启控制单元602自加一次，采样寄存器604就对延时模块中的延时单元609时钟输出采样一次；然后自适应控制电路根据采样寄存器604采样的时钟输出，确定是否检测到目标相差，如果检测到目标相差，获取目标相差对应的信息；如果逐级开启控制单元602增加直至开启54级时，自适应控制电路根据采样寄存器604采样的时钟输出确定检测到180度的目标相差，则54个延时单元及位置信息就是180度目标相差对应的第一信息。
运算电路中的相位参数运算单元605的第一输入端与时钟反相检测单元603连接；当时钟反相检测单元603检测到反相相差，则将反相相差对应的延时单元的数量和位置输出给相位参数运算单元605；相位参数运算单元605根据收到的信息和第一相差，确定第二相差对应开启的延时单元的第三信息以及第三相差对应开启的延时单元的第四信息；其中，第一相差包括第二相差和第三相差进行运算得到；
相位参数运算单元605的第二输出端与全加减电路606连接，全加减电路606的输出端与相位参数运算单元605的第二输入端连接；全加减电路606根据相位参数运算单元605输出的开启延时单元的第三信息和第四信息，确定第一相差对应的延时单元的第二信息；并将第二信息输出至相位参数运算单元605。
相位参数运算单元605的第一输出端与延时配置模块607连接，相位参数运算单元605将第一相差对应的延时单元的数量和位置输出至延时配置模块607。
例如，相位参数运算单元605的第一输入端与时钟反相检测单元603连接，当时钟反相检测单元603检测到180度相差对应54个延时单元；第一相差为33.75度，第二相差为45度，第三相差为11.25度，第二相差和第三相差减法运算可以得到第一相差。其中，第二相差对应的延时单元的信息可以通过180度相差对应的延时单元数量54的二进制数通过移位得到，右移一位，等同于除以2，那么就可以知道，开启27组延时单元就是产生90度相差的配置参数；依次类推，右移两位，就是产生45度相差的配置参数；右移三位，就是产生22.5度相差的配置参数；右移四位就是11.25度相差的配置参数；最终得到13为45°相差对应的开启延时单元的数量，3为11.25°相差对应的开启延时单元的数量。
相位参数运算单元605的第二输出端与全加减电路606连接，全加减电路606的输出端与相位参数运算单元605的第二输入端连接； 相位参数运算单元605将13和3输出给全加减电路，确定第一相差33.75度对应的延时单元，即第一相差对应开启的延时单元的数量为10，并将其输出至延时配置模块607。
延时配置模块607通过获取自动校准模块输出的第一相差对应的延时单元的第二信息，输出第一控制信号给延时模块；
例如，延时配置模块通过自动校准模块获取第一相差33.75度对应的延时单元的第二信息包括的延时单元的数量为10个，则输出其对应信息作为第一控制信号给延时模块；
延时模块包括译码器608和多个延时单元609，其中，译码器608根据延时配置模块607输出的第二信息对应的延时单元的第一控制信号，控制对应的延时单元开启。
延时模块通过获取延时配置模块607输出的第一控制信号以及源时钟，根据第一控制信号控制线译码器确定开启延时模块中的哪些延时单元609，即根据第一控制信号确定延时模块中的延时单元的开启或关闭，生成相差精准的同源异相时钟。
例如，延时模块通过获取延时配置模块607输出的第一控制信号以及源时钟，开启10个延时单元即可实现33.75度相差的延时。
本实施例的装置，同源异相时钟生成装置包括依次连接的自动校准模块、延时配置模块和延时模块；其中自动校准模块获取目标相差对应开启的延时单元的第一信息后，结合目标相差与所要生成的第一相差之间的对应关系，即可以精准地确定出第一相差所对应的延时单元的第二信息；延时配置模块和延时模块根据第二信息控制其对应延时单元的开启，即通过自动校准模块、延时配置模块和延时模块就可以高效地生成相差精准的同源异相时钟。
图7是本发明提供的同源异相时钟生成方法的流程示意图。本实施例提供的同源异相时钟生成方法，包括：
步骤701、获取第一相差；
步骤702、根据第一相差以及目标相差对应开启的延时单元的第一信息，确定第一相差对应的延时单元的第二信息；
步骤703、根据第一相差对应的延时单元的第二信息以及源时钟，开启第一相差对应的延时单元，并输出同源异相时钟。
具体的，获取所要生成的同源异相时钟的第一相差，根据目标相差对应开启的延时单元的第一信息，及第一相差与目标相差的对应关系，确定第一相差与对应的延时单元的第二信息，即要生成第一相差的同源异相时钟所要开启的延时单元的数量和位置；
然后，根据第一相差对应的延时单元的第二信息及源时钟，开启第一相差对应的延时单元，即根据确定的第二信息进行相应的延时单元的开启，即可生成所需的第一相差的同源异相时钟。
例如，获取的第一相差为90度，目标相差为反相相差即180度相差，180度相差开启的延时单元为对应的54个延时单元，根据目标相差180度相差与第一相差90度相差的对应关系，确定90度相差开启的延时单元的第二信息包括的延时单元的数量为27个，然后根据第二信息和源时钟开启对应的27个延时单元，即可生成90度相差的同源异相时钟。
本实施例的方法，获取第一相差和目标相差对应开启的延时单元的第一信息后，根据第一相差和目标相差的对应关系，即可以精准地确定出第一相差所对应的延时单元的第二信息；根据源时钟及第二信息控制其对应延时单元的开启，就可以高效地生成相差精准的同源异相时钟。
本发明实施例还提供了一种电子设备，包括所述同源异相时钟生成装置。
另一方面，本发明还提供一种计算机程序产品，所述计算机程序产品包括存储在非暂态计算机可读存储介质上的计算机程序，所述计算机程序包括程序指令，当所述程序指令被计算机执行时，计算机能 够执行上述各方法所提供的同源异相时钟生成方法，该方法包括：获取第一相差；根据第一相差以及目标相差对应开启的延时单元的第一信息，确定第一相差对应的延时单元的第二信息；根据第一相差对应的延时单元的第二信息以及源时钟，开启第一相差对应的延时单元，并输出同源异相时钟。
又一方面，本发明还提供一种非暂态计算机可读存储介质，其上存储有计算机程序，该计算机程序被处理器执行时实现以执行上述提供的同源异相时钟生成方法，该方法包括：获取第一相差；根据第一相差以及目标相差对应开启的延时单元的第一信息，确定第一相差对应的延时单元的第二信息；根据第一相差对应的延时单元的第二信息以及源时钟，开启第一相差对应的延时单元，并输出同源异相时钟。
以上所描述的装置实施例仅仅是示意性的，其中所述作为分离部件说明的小单元可以是或者也可以不是物理上分开的，作为小单元显示的部件可以是或者也可以不是物理小单元，即可以位于一个地方，或者也可以分布到多个网络小单元上。可以根据实际的需要选择其中的部分或者全部模块来实现本实施例方案的目的。本领域普通技术人员在不付出创造性的劳动的情况下，即可以理解并实施。
通过以上的实施方式的描述，本领域的技术人员可以清楚地了解到各实施方式可借助软件加必需的通用硬件平台的方式来实现，当然也可以通过硬件。基于这样的理解，上述技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品可以存储在计算机可读存储介质中，如ROM/RAM、磁碟、光盘等，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行各个实施例或者实施例的某些部分所述的方法。
最后应说明的是：以上实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述实施例对本发明进行了详细的说明，本领 域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的精神和范围。

Claims (10)

  1. 一种同源异相时钟生成装置，其特征在于，包括：
    依次连接的自动校准模块、延时配置模块和延时模块；
    其中，所述自动校准模块用于根据输入的自动校准使能信号，获取目标相差对应开启的延时单元的第一信息；根据所述第一信息，确定输入的第一相差对应的延时单元的第二信息；
    所述延时配置模块，用于根据所述第二信息，输出第一控制信号；
    所述延时模块，用于根据所述第一控制信号以及源时钟，开启所述延时模块中的延时单元，并输出同源异相时钟。
  2. 根据权利要求1所述的同源异相时钟生成装置，其特征在于，所述自动校准模块，包括：
    自适应控制电路、运算电路和采样寄存器；
    其中，所述自适应控制电路的输入端用于接收输入的所述自动校准使能信号和所述第一相差；所述自适应控制电路的输出端与所述运算电路的输入端连接，所述运算电路的输出端与所述延时配置模块的输入端连接，所述延时配置模块的输出端与所述延时模块的输入端连接；所述采样寄存器的输入端与所述延时模块的输出端连接，所述采样寄存器的输出端与所述自适应控制电路连接；
    所述自适应控制电路，具体用于根据所述自动校准使能信号，逐级开启所述延时模块中的延时单元，并依次根据所述采样寄存器对所述延时模块产生的异相时钟进行采样的采样结果，确定是否检测到目标相差，如果检测到所述目标相差，获取所述目标相差对应的第一信息；
    所述采样寄存器，用于对所述延时模块产生的异相时钟进行采样，获取所述采样结果；
    所述运算电路，用于根据所述目标相差对应的第一信息，确定所述第一相差对应的延时单元的第二信息。
  3. 根据权利要求2所述的同源异相时钟生成装置，其特征在于，所述自适应控制电路包括：
    自动校准开启判断单元、逐级开启控制单元和时钟反相检测单元；
    其中，所述自动校准开启判断单元的输出端分别与所述逐级开启控制单元和所述延时配置模块连接；
    所述逐级开启控制单元的输出端分别与所述延时配置模块和所述采样寄存器连接；所述时钟反相检测单元的输入端与所述采样寄存器的输出端连接，所述时钟反相检测单元的输出端与所述运算单元的输入端连接；
    所述自动校准开启判断单元，用于根据所述自动校准使能信号，输出第二控制信号和所述第一相差；
    所述逐级开启控制单元，用于根据所述第二控制信号，逐级开启所述延时模块中的延时单元，并向所述采样寄存器输出开启的延时单元的目标信息；
    所述时钟反相检测单元，用于根据所述采样寄存器的采样结果，确定是否检测到目标相差；在检测到所述目标相差的情况下，将所述目标信息作为所述目标相差对应的第一信息，并向所述运算电路输出。
  4. 根据权利要求2或3所述的同源异相时钟生成装置，其特征在于，所述运算电路，包括：
    相位参数运算单元和全加减电路；
    其中，所述相位参数运算单元的第一输入端与所述时钟反相检测单元连接；所述相位参数运算单元的第一输出端与所述延时配置模块连接，所述相位参数运算单元的第二输出端与所述全加减电路连接，所述全加减电路的输出端与所述相位参数运算单元的第二输入端连接；
    所述相位参数运算单元用于根据所述目标相差对应的第一信息，以及所述第一相差，确定第二相差对应开启的延时单元的第三信息以 及第三相差对应开启的延时单元的第四信息；
    所述全加减电路，用于根据所述开启的延时单元的第三信息和第四信息，确定所述第一相差对应的延时单元的第二信息。
  5. 根据权利要求4所述的同源异相时钟生成装置，其特征在于，所述全加减电路，包括：二选一电路和全加器；
    其中，所述二选一电路的输入端与所述相位参数运算单元的第三输出端连接，所述全加器的输出端作为所述全加减电路的输出端；
    所述二选一电路，用于根据所述相位参数运算单元输出的第三控制信号，选择对应的运算方式；
    所述全加器，用于根据所述开启的延时单元的第三信息和第四信息以及所述运算方式，确定所述第一相差对应的延时单元的第二信息。
  6. 根据权利要求2或3所述的同源异相时钟生成装置，其特征在于，所述延时模块，包括：
    译码器和多个延时单元；
    其中，所述译码器用于根据所述第一控制信号，控制对应的延时单元开启。
  7. 根据权利要求1-3任一项所述的同源异相时钟生成装置，其特征在于，还包括：
    门控模块，其中，所述门控模块的输出端与所述自动校准模块的输入端连接；
    所述门控模块，用于根据输入的自动校准使能信号和源时钟，控制自动校准模块在自动校准使能关闭后被同步复位以及时钟门控。
  8. 根据权利要求7所述的同源异相时钟生成装置，其特征在于，所述门控模块，包括：
    依次连接的两级同步寄存器和门控单元；
    其中，所述两级同步寄存器，用于根据输入的自动校准使能信号和源时钟，控制自动校准模块在自动校准使能关闭后被同步复位，向 所述门控单元输出第四控制信号；
    所述门控单元，用于根据所述同步寄存器输出的第四控制信号和所述源时钟控制所述自动校准模块进行时钟门控。
  9. 一种同源异相时钟生成方法，其特征在于，应用于如权利要求1-8任一项所述的同源异相时钟生成装置，所述方法包括：
    获取第一相差；
    根据所述第一相差以及目标相差对应开启的延时单元的第一信息，确定所述第一相差对应的延时单元的第二信息；
    根据所述第一相差对应的延时单元的第二信息以及源时钟，开启所述第一相差对应的延时单元，并输出同源异相时钟。
  10. 一种电子设备，其特征在于，包括：
    如权利要求1-8任一项所述的同源异相时钟生成装置。
PCT/CN2022/094187 2021-11-29 2022-05-20 同源异相时钟生成装置、方法和设备 WO2023092964A1 (zh)

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