WO2023092291A1 - 一种芯片中光波导结构的刻蚀方法、芯片以及光通信设备 - Google Patents

一种芯片中光波导结构的刻蚀方法、芯片以及光通信设备 Download PDF

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WO2023092291A1
WO2023092291A1 PCT/CN2021/132481 CN2021132481W WO2023092291A1 WO 2023092291 A1 WO2023092291 A1 WO 2023092291A1 CN 2021132481 W CN2021132481 W CN 2021132481W WO 2023092291 A1 WO2023092291 A1 WO 2023092291A1
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layer
optical waveguide
waveguide structure
pattern
etching
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PCT/CN2021/132481
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English (en)
French (fr)
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袁俊
张艳武
李世梁
马庆艳
江先鑫
杨莉
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华为技术有限公司
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Priority to PCT/CN2021/132481 priority Critical patent/WO2023092291A1/zh
Publication of WO2023092291A1 publication Critical patent/WO2023092291A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type

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  • the embodiments of the present application relate to the semiconductor field and the field of optoelectronic integration, and in particular to a method for etching an optical waveguide structure in a chip, a chip, and an optical communication device.
  • the optical waveguide structure can be obtained by patterning the single crystal silicon (Si) layer on the surface of the silicon-on-insulator (SOI) wafer (wafer) through a photolithography process.
  • the patterning of the Si layer can be achieved by etching in the photolithography process to obtain an optical waveguide structure composed of Si layers of different thicknesses.
  • shallow etching can be used.
  • the deposited amorphous carbon will form near the steps of the Si layer formed by the shallow etching. Voids or sharp corners will cause Si residue problems in subsequent etching, resulting in unnecessary scattering, diffraction, etc., which will further affect the communication performance of the chip.
  • Embodiments of the present application provide an etching method for an optical waveguide structure in a chip, a chip, and an optical communication device, which can avoid unnecessary scattering and diffraction caused by residual Si, and improve the communication performance of the chip.
  • a method for etching an optical waveguide structure in a chip is provided, the method is used for a silicon-on-insulator substrate SOI, and the SOI includes a base layer, a buried oxide layer and a single crystal silicon layer, comprising: according to the first a pattern, etching the single crystal silicon layer to form a first optical waveguide structure; according to a second pattern, etching the first optical waveguide structure to form a second optical waveguide structure, wherein the hypotenuse of the second pattern is aligned with the The hypotenuses of the first figure are parallel.
  • the voids or sharp corners that cause the problem of Si residue are usually located parallel to the edge of the first pattern, therefore, by setting the hypotenuse of the first pattern parallel to the hypotenuse of the second pattern, so that the side parallel to the first pattern will cause Si residue
  • the positions of the holes or sharp corners of the problem are included in the second pattern, so that when the first optical waveguide structure is etched, the partial area of the first optical waveguide structure corresponding to the second pattern is no longer etched, so that the problem of Si residue can be avoided
  • the resulting unnecessary scattering, diffraction, etc. improve the communication performance of the chip.
  • the first right-angled side of the first figure is parallel to the second right-angled side of the first figure.
  • the method before etching the single crystal silicon layer according to the first pattern to form the first optical waveguide structure, the method further includes: A silicon dioxide SiO2 layer, a silicon nitride SiN layer, and a first photoresist layer are sequentially formed on the surface of the single crystal silicon layer; according to the first pattern, the single crystal silicon layer is etched to form a first optical waveguide structure, including : According to the first pattern, sequentially etch the first photoresist layer, the SiN layer, the SiO2 layer and the single crystal silicon layer to form the first optical waveguide structure.
  • the remaining part of the first photoresist layer is removed.
  • the method before etching the first optical waveguide structure to form the second optical waveguide structure according to the second pattern, the method further includes: The surface of the first optical waveguide structure is sequentially formed with an amorphous carbon a-C layer, a silicon oxynitride SiON layer and a second photoresist layer, wherein a cavity or a sharp angle is formed on the surface of the a-C layer, and the cavity or sharp angle is covered SiON filling; said etching the first optical waveguide structure to form a second optical waveguide structure according to the second pattern includes: sequentially etching the second photoresist layer, the SiON layer, the a-C layer, and the first optical waveguide structure form the second optical waveguide structure, and the positions of the cavities or sharp corners are inside the second pattern.
  • the distance between the hypotenuse of the second pattern and the hypotenuse of the first pattern ranges from 0 nm to half the thickness of the a-C layer one.
  • the distance between the first right-angled side of the first figure and the second right-angled side of the first figure ranges from the line width of the process platform to the a-C layer thickness.
  • a chip in a second aspect, includes an optical waveguide structure, and the optical waveguide structure is an optical waveguide structure fabricated by adopting the above-mentioned first aspect or any possible implementation manner of the first aspect.
  • an optical communication device in a third aspect, includes the chip in the second aspect above.
  • the optical communication device includes any one of an optical module, an optical switch, and an optical modem.
  • an optical module in a fourth aspect, includes the chip in the second aspect above.
  • a communication device including: a receiver including the chip in the second aspect; and/or a transmitter including the chip in the second aspect.
  • a communication device including: a transceiver, configured to receive or transmit a signal, the transceiver including the chip in the second aspect, the chip configured to modulate or demodulate the signal; A processor, configured to perform signal processing on the signal.
  • Fig. 1 is a structural schematic diagram of an exemplary SOIwafer and SOI waveguide applicable to the embodiments of the present application;
  • Fig. 2 is an exemplary schematic diagram of the basic flow of the SOI waveguide fabricated by CMOS process in the embodiment of the present application;
  • Fig. 3 is a top view schematic diagram of the process of forming Si residues in the SOI waveguide manufacturing process in the embodiment of the present application;
  • Fig. 4 is a schematic flowchart of an etching method for an optical waveguide structure in a chip provided by an embodiment of the present application;
  • FIG. 5 is a schematic flowchart of a method for etching an optical waveguide structure in a chip provided by an embodiment of the present application
  • FIG. 6 is a schematic diagram of an etching method for an optical waveguide structure in a chip provided by an embodiment of the present application
  • Fig. 7 is a top view of the etching region and the positions where holes or sharp corners are formed on the a-C layer of an etching method for an optical waveguide structure in an optical chip provided by an embodiment of the present application;
  • FIG. 8 is a schematic diagram of another etching method for an optical waveguide structure in a chip provided by an embodiment of the present application.
  • Fig. 9 is a top view of the etching region and the positions where holes or sharp corners are formed on the a-C layer of an etching method for an optical waveguide structure in an optical chip provided by an embodiment of the present application;
  • FIG. 10 is an exemplary schematic diagram of an optical communication device provided by an embodiment of the present application.
  • FIG. 11 is an exemplary schematic diagram of another optical communication device provided by an embodiment of the present application.
  • Fig. 12 is an exemplary schematic diagram of another optical communication device provided by an embodiment of the present application.
  • Planar optical waveguide technology is developed on the basis of integrated circuit technology and has its unique features.
  • the basic components of integrated circuits are resistors, capacitors, inductors, and transistors (diodes, triodes).
  • Integrated circuit technology is to manufacture these basic components on silicon substrates through processes such as thin film deposition, diffusion, epitaxy, photolithography, etching, and annealing. , and interconnected with wires.
  • the basic components of planar optical waveguides are lasers, optical waveguides, and detectors.
  • the substrate materials used are different, such as III-V compound semiconductors (InP and GaAs), silicon dioxide (SiO 2 ), lithium niobate (LiNbO 3 ), silicon on insulator substrate (silicon on insulator, SOI), polymer (polymer), glass, etc. Due to the different materials, there are many types of manufacturing processes.
  • Planar optical waveguide devices are devices manufactured using planar optical waveguide technology, and are divided into passive devices, active devices, and active/passive hybrid integrated devices.
  • a passive device can be understood as a device that does not require an energy (electric) source, and can be used to realize functions such as transmission, splitting, combining, and filtering of light wave signals.
  • Passive components mainly include planar optical waveguide splitters, arrayed waveguide gratings (arrayed waveguide grating, AWG), optical filters, etc.
  • FIG. 1 shows a schematic structural diagram of an exemplary SOI wafer and SOI waveguide applicable to the embodiments of the present application.
  • SOIwafer includes a base layer 101a, an oxide buried layer 102a, and a single crystal silicon layer 103a, which are respectively a silicon (Si) substrate layer, a silicon dioxide (SiO 2 ) layer, and a Si layer, generally , the thickness of the Si substrate layer is 500 ⁇ m to 725 ⁇ m, the thickness of the SiO 2 layer is 2 ⁇ m or 3 ⁇ m, and the thickness of the Si layer is 200nm to 300nm.
  • the SOI waveguide includes a bottom layer 101b, a lower cladding layer 102b, a core layer 103b, and an upper cladding layer 104b, which are respectively a Si substrate layer, a SiO layer, a Si layer, and air. It should be understood that the SOI waveguide Various structures are possible, such as the ridge waveguide structure shown in (b) of FIG. 1 .
  • CMOS complementary metal-oxide semiconductor
  • a hardmask is an inorganic thin film material produced by chemical vapor deposition (CVD). Its main components are titanium nitride (TiN), silicon nitride (SiN), silicon dioxide (SiO 2 ), amorphous carbon (amorphous carbon, aC) and the like.
  • amorphous carbon is widely used in CMOS processes due to its high etching selectivity to silicon oxide, silicon nitride, and silicon in etching.
  • the hard mask is mainly used in the multiple photolithography process. First, the multiple photoresist images are transferred to the hard mask, and then the final pattern is transferred to the substrate through the hard mask.
  • Fig. 2 is the exemplary schematic diagram of the basic process of making SOI waveguide by CMOS process
  • (a) of Fig. 2 has shown the shadow filling indicator figure corresponding to different patterns of different materials in the SOI waveguide of making transition conversion structure
  • Fig. 2 ( b)-(h) show top views in the SOI waveguide fabrication process of the transition conversion structure
  • (i)-(o) of Figure 2 show cross-sectional views in the SOI waveguide fabrication process of the transition conversion structure, wherein the cross-section
  • the figures correspond to the positions shown along the dotted lines in the top view.
  • the basic process includes S1-S7:
  • the etching process of the first photolithography can be carried out according to the pattern transferred to the photoresist, that is, from the exposed The SiN layer starts to etch.
  • the dotted line indicates the position of the cross section shown in (k) of Figure 2, and the two rectangles with a symmetrical structure in the middle indicate that on the basis of the above process S2, along the exposed SiN continues to etch until the desired waveguide structure is obtained, thereby revealing the Si layer; as shown in (k) of Figure 2, through the etching process, a certain thickness of the Si layer is etched away (at the obtained pit position, The thickness of the etched Si layer is small, so the etching in the first photolithography can be called shallow etching), and the photoresist shown in the dotted line box in the figure can be removed before the next flow process (such as oxidation to remove Glue, solvent stripping, plasma stripping, etc.), wherein the etching process in the first photolithography can be dry etching, such as ion beam etching (ion beam etching, IBM), reactive ion beam etching (reactive ion beam etching, RIE
  • the second photolithography is performed, and the pattern on the mask plate is first transferred to the photoresist.
  • the two dotted lines represent the positions of the cross-sections shown in (l 1 ) and (l 2 ) of Figure 2 respectively, and the four pentagons with symmetrical structures in the middle represent the The area to be etched in the second photolithography, and the four pentagonal boxes are filled with white to indicate the exposed silicon oxynitride (SiON) layer, or in other words, the four pentagonal boxes indicate the second photolithography Part of the steps, the pattern on the mask plate is transferred to the photoresist to reveal the SiON layer, specifically, through glue coating (photoresist), pre-baking, exposure, post-baking, developing, fixing, hardening, etc.
  • glue coating photoresist
  • the step is to transfer the pattern on the mask plate to the photoresist; as shown in (l 1 ) and (l 2 ) of Figure 2, the aC layer is sequentially formed on the basis of the removal of the photoresist in the above process S3, silicon oxynitride (SiON) layer, photoresist (photoresist) layer, wherein, the SiON layer is used as a dielectric anti-reflection layer (dielectric anti-reflection coating, DARC), and the aC layer is used as a hard mask layer.
  • SiON silicon oxynitride
  • DARC dielectric anti-reflection coating
  • the etching process of the second photolithography can be carried out according to the pattern transferred to the photoresist, that is, the exposed The SiON layer and aC layer are etched.
  • the two dotted lines in (f) of Figure 2 represent the positions of the cross-sections shown in (m 1 ) and (m 2 ) of Figure 2 respectively
  • the four pentagons with a symmetrical structure in the middle indicate that on the basis of the above process S4, etching is carried out along the pattern transferred to the photoresist until the Si layer obtained by the first photolithography is revealed, and the four pentagons Filled with a wider slash hatch, indicating the Si layer exposed after etching; that is, it is etched along the four pentagonal regions until the Si layer obtained by the first photolithography is exposed; that is, it is etched away in sequence Part of the SiON layer, part of the aC layer, until the Si layer obtained by the first photolithography is exposed.
  • SiON layer is etched with a substance that is highly etchable to SiON, due to the existence of cavities or sharp corners, the SiON at the cavities or sharp corners cannot be completely etched away.
  • SiON needs to be etched first at the cavity or sharp corner. Due to the etching selectivity, the etching of SiON is slow, and the aC below it will be etched only after SiON is etched. Etching, which will lead to the residue of aC, that is, the smaller black shadow filled rectangle at the pit shown in (m) of Figure 2;
  • FIG. 3 is a schematic top view of the process of forming Si residues in the SOI waveguide manufacturing process.
  • the two solid-line rectangles with a symmetrical structure in the middle represent the etched area in the first photolithography
  • the dotted-line sides of the two dotted-line rectangles with a symmetrical structure in the middle represent the area etched in the second photolithography.
  • the positions of holes or sharp corners are formed on the a-C layer, and the solid line rectangle is similar to the dotted line rectangle.
  • the distance between the solid line rectangle and the dotted line rectangle is approximately equal to 1/2 of the thickness of the a-C layer, that is, a cavity or sharp corner that cannot be covered by a-C will be formed near the step formed by the first photolithography, and perpendicular to In the direction of the thickness of the a-C layer, the distance between the cavity or the sharp angle and the step is substantially the same as half of the thickness of the a-C layer, and the formation reason of the cavity or the sharp angle can refer to the specific description in the flow process S4 in Fig. 2, here I won't repeat them here.
  • the pentagon filled with four dotted shades represents the etched area in the second photolithography, so due to the existence of voids or sharp corners and the etching selectivity, it will be in the dotted line Si residues are formed at the positions where the side overlaps with the shaded part of the pentagon, that is, Si residues are formed at the positions corresponding to the cavities or sharp corners, that is, Si residues are formed at the positions indicated by the dotted lines in (c) of FIG. 3 .
  • the embodiment of the present application provides an etching method for the optical waveguide structure in the chip, which can avoid the problem of Si residues on the chip and improve the communication performance of the chip.
  • FIG. 4 is a schematic flowchart of a method 400 for etching an optical waveguide structure in a chip according to an embodiment of the present application. This method can be applied to SOI, which includes a base layer, a buried oxide layer, and a single crystal silicon layer, such as the structure shown in (a) of FIG. 1 .
  • the method 400 includes:
  • the first pattern may represent the etching area, for example, the first pattern is the layout design in the photolithography process; etching the single crystal silicon layer may be etching the single crystal silicon layer in SOI A certain thickness is removed, and the etched thickness is less than the thickness of the SOI single crystal silicon layer.
  • the projection of the first optical waveguide structure in the thickness direction may be the same as that of the first pattern.
  • the second pattern can be understood as, when the first optical waveguide structure is etched to obtain the second optical waveguide structure, the masked area, that is, the part corresponding to the second pattern is no longer etched. part.
  • the second pattern may be the same as the projection of the second optical waveguide structure in the thickness direction.
  • the voids or sharp corners that cause the problem of Si residue are usually located parallel to the edge of the first pattern, therefore, by setting the hypotenuse of the first pattern parallel to the hypotenuse of the second pattern, so that the side parallel to the first pattern will cause Si residue
  • the positions of the holes or sharp corners of the problem are included in the second pattern, so that when the first optical waveguide structure is etched, the partial area of the first optical waveguide structure corresponding to the second pattern is no longer etched, so that the problem of Si residue can be avoided
  • the generation of the chip improves the communication performance of the chip.
  • the area of the first figure is larger than the area of the second figure
  • the first right-angled side of the first figure overlaps the first side of the second figure
  • the first hypotenuse of the first figure overlaps with the first side of the second figure parallel to the second side.
  • the first right-angled side of the first figure is parallel to the second right-angled side of the first figure.
  • the foregoing S401 and S402 may be specifically implemented through the method 500 shown in FIG. 5 .
  • FIG. 5 is a schematic flowchart of a method 500 for etching an optical waveguide structure in a chip provided by an embodiment of the present application.
  • the method 500 includes:
  • the first photolithography is performed on the surface of the SOI wafer
  • the photoresist used is the above-mentioned first photoresist layer
  • the hard mask layer is a SiN layer
  • the SiO2 layer can be used to increase
  • the adhesiveness of the hard mask layer to the substrate makes it difficult for the hard mask layer to fall off due to factors such as vibration.
  • the etching methods of the first photoresist layer, the SiN layer, the SiO2 layer and the single crystal silicon layer may be different.
  • the first photoresist layer can be etched by methods such as exposure and development, while the SiN layer, SiO2 layer and single crystal silicon layer can be etched by methods such as ion beam etching, which is not limited in this application.
  • the method 500 may also include S503:
  • the first photoresist layer is etched, so that the first photoresist layer of the first pattern part is etched away, but there are other remaining parts of the first photoresist layer, S503 removing other remaining parts of the first photoresist layer.
  • removal There are many methods of removal, which are not limited in this application, for example, it can be removed by wet method.
  • the method 500 may also include S504-S505:
  • S504 may be the step of starting the second photolithography
  • the second photoresist layer is the photoresist used in the second photolithography
  • the a-C layer and the SiON layer are the second Hard mask layer in secondary lithography.
  • voids or sharp corners are formed on the surface of the a-C layer, and the voids or sharp corners are filled with SiON.
  • the distance between the hypotenuse of the second pattern and the hypotenuse of the first pattern ranges from 0 nm to half of the thickness of the a-C layer.
  • the distance between the hypotenuse of the second pattern and the hypotenuse of the first pattern can be set to any value from 0nm to 200nm.
  • the maximum distance between the hypotenuse of the second figure and the hypotenuse of the first figure is set to 1/2 of the thickness of the a-C layer. It can be understood that the distance between the hypotenuse of the second figure and the hypotenuse of the first figure The maximum distance between them can be set to be approximately equal to one-half of the thickness of layers a-C, there may be some errors in actual production, and it is only necessary to ensure that the position of the cavity or sharp corner is located inside the second figure.
  • the distance between the first right-angled side of the first pattern and the second right-angled side of the first pattern ranges from the line width of the process platform to the thickness of the a-C layer.
  • the distance between the first right-angled side of the first pattern and the second right-angled side of the first pattern can be set to any value from 65nm to 400nm.
  • the line width of the process platform may also be 45nm, 90nm or 130nm, etc., which is not limited in this application.
  • the maximum distance between the first right-angled side of the first figure and the second right-angled side of the first figure is set as the thickness of the a-C layer. It can be understood that in order to avoid the formation of voids or sharp corners, the maximum distance of the distance The value is approximately equal to the thickness of the a-C layer, there may be errors in actual production, and it is sufficient to ensure that no cavity or sharp corner is formed between the first right-angle side and the second right-angle side.
  • the positions of the holes or sharp corners are placed inside the second pattern, so that the holes or sharp corners are not etched, so that Si residues will not be caused, and the communication performance of the chip can be improved.
  • FIGS. 6-9 exemplarily introduces an etching method for an optical waveguide structure in a chip provided by an embodiment of the present application with reference to FIGS. 6-9 , wherein FIGS. 6 and 7 correspond to the desired transition conversion in FIGS. 2 and 3 above.
  • Structure, Figures 8 and 9 correspond to the polarization rotator-splitter (polarization rotator-splitters, PSR) structure.
  • PSR polarization rotator-splitters
  • FIG. 6 is a schematic diagram of an etching method for an optical waveguide structure in an optical chip provided by an embodiment of the present application. Specifically, (a) of Figure 6 shows the different shadow filling indication diagrams corresponding to different materials in the optical waveguide structure for making the transition conversion structure, and (b)-(h) of Figure 6 show the light of the transition conversion structure.
  • the top view in the fabrication process of the waveguide structure, (i)-(o) of FIG. 6 shows the cross-sectional view in the fabrication process of the optical waveguide structure of the transition conversion structure, wherein the cross-sectional view corresponds to the position shown along the dotted line in the top view.
  • the etching method includes basic processes S1-S7:
  • the dotted line indicates the position of the cross-section shown in Figure 6 (i), with a symmetrical structure in the middle and a shape
  • the two polygons similar to the two wings indicate the area to be etched in the first photolithography; as shown in (i) of Figure 6, first a SiO2 layer with a thickness of 5nm-20nm is grown on the surface of the SOIwafer by thermal oxidation, and then by Low pressure chemical vapor deposition (low pressure chemical vapor deposition, LPCVD) deposits a silicon nitride (SiN) layer, wherein, the SiN layer is used as a hard mask layer for the first photolithography described below, and the SiO2 layer is used to increase the thickness of the SiN layer.
  • Low pressure chemical vapor deposition low pressure chemical vapor deposition
  • Adhesion; S2 (introduced in conjunction with (c) and (j) of Figure 6), the first photolithography is carried out, and the pattern on the mask plate is transferred to the photoresist, specifically, as shown in Figure 6 (c) ), the dotted line indicates the position of the cross-section shown in (j) of Figure 6, the middle is a symmetrical structure, and the shape of two polygons similar to the two wings indicates that after the first photolithography part of the steps, the mask on the mask plate After the pattern is transferred to the photoresist, the SiN layer is revealed (fork-shape hatching indicates SiN), specifically, through the steps of coating (photoresist), pre-baking, exposure, post-baking, developing, fixing, hardening, etc.
  • Transfer the pattern on the mask plate to the photoresist refers to removing part of the photoresist according to the pattern on the mask plate.
  • the resist exposes the SiN layer below, so that the SiN layer, SiO2 layer, and Si layer can be etched continuously in the following process S3, and then the desired waveguide structure is obtained on the Si layer;
  • the etching process of the first photolithography can be carried out according to the pattern transferred to the photoresist, that is, from the exposed The SiN layer starts to etch.
  • the dotted line indicates the position of the cross section shown in (k) of Figure 6, the middle is a symmetrical structure, and the two polygons whose shape is similar to two wings are expressed on the basis of the above process S2 , continue etching along the exposed SiN until the desired waveguide structure is obtained, thereby revealing the Si layer; as shown in (k) of Figure 6, through the etching process, a certain thickness of the Si layer is etched away, and can The photoresist shown in the dotted box in the figure is removed before the next process (for example, oxidation stripping, solvent stripping, plasma stripping, etc.).
  • the etching process in the first photolithography can be dry etching, such as ion beam etching (ion beam etching, IBM), reactive ion beam etching (reactive ion beam etching, RIE), inductive coupling Plasma etching (inductively coupled plasma etching, ICP), etc., this application is not limited to this;
  • the two dotted lines indicate the positions of the cross-sections shown in (l 1 ) and (l 2 ) of Figure 6 respectively, and the four pentagons with symmetrical structures in the middle represent the The area that needs to be etched in the second photolithography, and the four pentagons are filled with white to indicate the exposed silicon nitride oxide (SiON) layer, or in other words, the four pentagons represent the part that has undergone the second photolithography step, the pattern on the mask plate is transferred to the photoresist to reveal the SiON layer, specifically, through the steps of applying glue (photoresist), pre-baking, exposing, post-baking, developing, fixing, hardening, etc.
  • glue photoresist
  • the pattern on the mask plate is transferred to the photoresist; as shown in (l 1 ) and (l 2 ) of Figure 6, the aC layer is sequentially formed on the basis of the removal of the photoresist in the above process S3, and silicon oxynitride (SiON ) layer, a photoresist (photoresist) layer, wherein, the SiON layer is used as a dielectric anti-reflection layer (dielectric anti-reflection coating, DARC), and the aC layer is used as a hard mask layer.
  • the SiON layer is used as a dielectric anti-reflection layer (dielectric anti-reflection coating, DARC)
  • DARC dielectric anti-reflection coating
  • the etching process of the second photolithography can be carried out according to the pattern transferred to the photoresist, that is, the exposed The SiON layer and aC layer are etched.
  • the two dotted lines in (f) of Figure 6 represent the positions of the cross-sections shown in (m 1 ) and (m 2 ) of Figure 6 respectively
  • the four pentagons with a symmetrical structure in the middle indicate that on the basis of the above process S4, etching is carried out along the pattern transferred to the photoresist until the Si layer obtained by the first photolithography is revealed, and the four pentagons Covered by a wider oblique line shadow, it represents the Si layer exposed after etching; that is, it is etched along the four pentagons until the Si layer obtained by the first photolithography is exposed; that is, it is etched away in sequence Part of the SiON layer, part of the aC layer, until the Si layer obtained by the first photolithography is exposed. At this time, since there is no need to etch the positions where cavities or sharp corners are formed, no residue of aC will be formed.
  • FIG. 7 is a top view of an etching region and a position where a cavity or a sharp corner is formed on layers a-C in a method for etching an optical waveguide structure in an optical chip according to an embodiment of the present application.
  • the center is filled with dotted shadows with a symmetrical structure, and the shape is similar to the two wings of the two polygons representing the etched area in the first photolithography; the two triangles located in the two polygons The dotted edges of , indicate the positions where cavities or sharp corners of layers a-c are formed.
  • the four pentagons filled with diagonal hatching in the middle with a symmetrical structure represent the etched area in the second photolithography, and the four pentagons overlap with the two polygons (the overlapping part of dotted filling and oblique filling in the figure), it should be understood that the shape and size of the four pentagons are the same. Since the two decagons and the four pentagons are symmetrical structures, the overlapping portion includes the same four overlapping areas. To avoid repetition, one of the overlapping areas of the overlapping portion will be described below.
  • FIG. 7 it is a partially enlarged schematic diagram of (b) in FIG .
  • Side A2 is also a side of the above-mentioned polygon
  • side A3 and side A4 of the overlapping area A are also sides of a pentagon
  • side A1 is parallel to side A3
  • the distance between side A2 and side A3 is c1.
  • the 4 sides of A are parallel and the distance is c 2 .
  • the overlapping area A is composed of at least two trapezoids, and the heights of the two trapezoids included in the at least two trapezoids are respectively c 1 and c 2 .
  • the hypotenuse of the first figure is, for example, side A1 in (c) of FIG. 7
  • the hypotenuse of the second figure is, for example, side A3 in (c) of FIG. 7 .
  • the A4 side in (c) is a benchmark, and the side parallel to the A4 side is the right-angled side of the first figure, for example, the first right-angled side of the first figure is the A4 side in (c) of Fig. 7, and
  • the second right-angled side of the first figure is side A2 in (c) of FIG. 7 .
  • the above-mentioned distance c1 or height c1 satisfies the range from 0 nm to half of the thickness of the aC layer
  • the above-mentioned distance c2 or height c2 satisfies the range from the line width of the process platform to the thickness of the aC layer.
  • c2 can be any value from 65nm to 400nm.
  • the position of the cavity generated at the step can be excluded from the area etched in the second lithography, as shown in Figure 7
  • the dotted lines indicating the positions of the voids shown in (b) and (c) are not included in the overlapping area, so that the etching of the second photolithography will not etch the SiON-filled voids, so that Si residues will not be formed, avoiding The Si residual problem can be solved, and the optical performance of the optical chip can be further improved.
  • FIG. 8 is a schematic diagram of another method for etching an optical waveguide structure in an optical chip according to an embodiment of the present application. Specifically, (a) of Figure 8 shows the different shaded filling indication diagrams corresponding to different materials in the optical waveguide structure of the PSR structure, and (b)-(h) of Figure 8 show the optical waveguide structure of the PSR structure The top view in the fabrication process, (i)-(o) of FIG. 8 shows the cross-sectional view in the fabrication process of the optical waveguide structure of the PSR structure, wherein the cross-sectional view corresponds to the position shown along the dotted line in the top view.
  • the etching method includes basic processes S1-S7: It should be noted that some of the processes in Figure 8 are the same as those in Figure 6 (such as S1-S3), and details can be referred to in Figure 6. The corresponding description will not be repeated here.
  • the two dotted lines indicate the interception positions of the sections shown in (l 1 ) and (l 2 ) of Figure 8 respectively, and the two pentagons with symmetrical structures in the middle represent the The area to be etched in the second lithography, and the two pentagons are filled with white to indicate the exposed silicon oxynitride (SiON) layer, or in other words, the two pentagons indicate the part that has undergone the second lithography step, the pattern on the mask plate is transferred to the photoresist to reveal the SiON layer, specifically, through the steps of applying glue (photoresist), pre-baking, exposing, post-baking, developing, fixing, hardening, etc.
  • glue photoresist
  • the pattern on the mask plate is transferred to the photoresist; as shown in (l 1 ) and (l 2 ) of Figure 8, the aC layer is sequentially formed on the basis of the removal of the photoresist in the above process S3, silicon oxynitride (SiON ) layer, a photoresist (photoresist) layer, wherein, the SiON layer is used as a dielectric anti-reflection layer (dielectric anti-reflection coating, DARC), and the aC layer is used as a hard mask layer.
  • DARC dielectric anti-reflection coating
  • the etching process of the second photolithography can be carried out according to the pattern transferred to the photoresist, that is, the exposed The SiON layer and aC layer are etched. Specifically, as shown in (f) and (m) of FIG . 8, the two dotted lines in (f) of FIG.
  • the two pentagons with a symmetrical structure in the middle indicate that on the basis of the above process S4, etching is carried out along the pattern transferred to the photoresist until the Si layer obtained by the first photolithography is exposed, and the four pentagons Covered by a wider oblique line shadow, it indicates the Si layer exposed after etching; that is, it is etched along the two pentagonal parts until the Si layer obtained by the first photolithography is exposed; that is, it is etched away in sequence Part of the SiON layer, part of the aC layer, until the Si layer obtained by the first photolithography is exposed. At this time, since there is no need to etch the positions where cavities or sharp corners are formed, no residue of aC will be formed.
  • FIG. 9 is a top view of an etching region and a position where a cavity or a sharp corner is formed on layers a-C in another method for etching an optical waveguide structure in an optical chip according to an embodiment of the present application.
  • the center is filled with dotted shadows with a symmetrical structure, and the shape is similar to the two wings of the two polygons representing the etched area in the first photolithography; the dotted line of the triangle located in the two polygons Edges indicate where cavities or sharp corners of layers a-c are formed.
  • the two polygons filled with slash hatches with a symmetrical structure in the middle indicate the etched area in the second photolithography, and the polygons covered by dot-shaped shading overlap with the polygons covered by slash shading Partly, due to the symmetry of the structure, the overlapping portion includes two symmetrical overlapping areas. To avoid repetition, one of the overlapping areas of the overlapping portion will be described below.
  • FIG. 9 it is a partially enlarged schematic diagram of (b) in Figure 9, in which the overlapping part of the dotted hatching and the oblique hatching is the overlapping area B, and the B 1 side of the overlapping area B and Side B 2 is also the side of the polygon filled with dotted shadows, and sides B 3 and B 4 of the overlapping area B are also sides of the polygon filled with oblique line shadows, and side B 1 is parallel to side B 3 , which The distance is c 1 , and the side B 2 is parallel to the side B 4 with a distance of c 2 .
  • the overlapping area B is composed of two trapezoids whose heights are c 1 , c 2 .
  • the above-mentioned distance c1 or height c1 satisfies the range from 0 nm to half of the thickness of the aC layer
  • the above-mentioned distance c2 or height c2 satisfies the range from the line width of the process platform to the thickness of the aC layer.
  • c2 can be any value from 65nm to 400nm.
  • the position of the cavity generated at the step can be excluded from the area etched in the second lithography, as shown in Figure 9
  • the dotted lines indicating the positions of the voids shown in (b) and (c) are not included in the overlapping area, that is, the etching of the second photolithography will not etch the voids filled with SiON, so that Si residues will not be formed, avoiding The Si residual problem can be solved, and the optical performance of the optical chip can be further improved.
  • An embodiment of the present application provides a chip, and the chip includes an optical waveguide structure, and the optical waveguide structure is an optical waveguide structure fabricated by the above method.
  • An embodiment of the present application further provides an optical communication device, where the optical communication device includes the above-mentioned chip.
  • the foregoing optical communication device includes any one of an optical module, an optical switch, and an optical modem.
  • Fig. 10 is an exemplary schematic diagram of an optical communication device provided by an embodiment of the present application.
  • the optical communication device includes an optical module 1010 .
  • the optical module 1010 includes a chip fabricated by the method shown in FIGS. 4-9 above.
  • the optical communication device may further include one or more other optical modules, for example, the optical module 1020 .
  • the optical module 1010 is used to process signals received in the optical communication device
  • the optical module 1020 is used to process signals sent from the optical communication device.
  • Fig. 11 is an exemplary schematic diagram of another optical communication device provided by an embodiment of the present application.
  • the optical communication device includes an optical switch 1110 .
  • the optical switch 1110 includes a chip fabricated by the method shown in FIGS. 4-9 above.
  • the optical communication device may further include one or more other optical switches, for example, the optical switch 1120 .
  • the optical switch 1110 is used to process signals received in the optical communication device, and the optical switch 1120 is used to process signals sent from the optical communication device.
  • Fig. 12 is an exemplary schematic diagram of another optical communication device provided by an embodiment of the present application.
  • the optical communication device includes an optical modem 1210 .
  • the optical modem 1210 includes a chip fabricated by the method shown in FIGS. 4-9 above.
  • the optical communication device may further include one or more other optical modems, for example, the optical modem 1220 .
  • the optical modem 1210 is used to process signals received in the optical communication device, and the optical modem 1220 is used to process signals sent from the optical communication device.
  • An embodiment of the present application further provides an optical module, where the optical module includes the above-mentioned chip.
  • An embodiment of the present application further provides a communication device, including: a receiver including the above-mentioned chip; and/or a transmitter including the above-mentioned chip.
  • the embodiment of the present application also provides a communication device, including: a transceiver, used to receive or send a signal, the transceiver includes the above-mentioned chip, and the chip is used to modulate or demodulate the signal; a processor, Used to perform signal processing on the signal.
  • Skilled artisans may use different methods to implement the described functions for each specific application, but such implementation should not be regarded as exceeding the scope of the present application.
  • the disclosed systems, devices and methods may be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division. In actual implementation, there may be other division methods.
  • multiple units or components can be combined or May be integrated into another system, or some features may be ignored, or not implemented.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, each unit may exist separately physically, or two or more units may be integrated into one unit.

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Abstract

本申请实施例提供了一种芯片中光波导结构的刻蚀方法、芯片以及光通信设备，能够避免Si残留问题导致的不必要散射和衍射，提升芯片的通信性能。具体地，所述方法用于绝缘体上硅衬底SOI，所述SOI包括基底层、氧化掩埋层和单晶硅层，包括：根据第一图形，刻蚀所述单晶硅层，形成第一光波导结构；根据第二图形，刻蚀所述第一光波导结构形成第二光波导结构，其中所述第二图形的斜边与所述第一图形的斜边平行。

Description

一种芯片中光波导结构的刻蚀方法、芯片以及光通信设备 技术领域
本申请实施例涉及半导体领域和光电集成领域，尤其涉及一种芯片中光波导结构的刻蚀方法、芯片以及光通信设备。
背景技术
在芯片的光波导结构制作中，可以在绝缘体上硅衬底(silicon on insulator，SOI)晶圆(wafer)表面，通过光刻工艺将单晶硅(Si)层图案化获得光波导结构。Si层图案化可以是通过光刻工艺中的刻蚀，获得由不同厚度的Si层构成的光波导结构，当需要获得的光波导结构中部分结构的Si层厚度较大时，可以采用浅刻蚀和深刻蚀相结合的方法。
然而，在浅刻蚀完成后进行深刻蚀，且采用的硬掩膜材料为无定形碳(amorphous carbon，a-C)时，由于沉积的无定形碳会在浅刻蚀形成的Si层台阶附近会形成空洞或尖角，从而造成后续刻蚀中的Si残留问题，导致不必要的散射、衍射等，进一步会影响芯片的通信性能。
发明内容
本申请实施例提供一种芯片中光波导结构的刻蚀方法、芯片以及光通信设备，能够避免Si残留问题导致的不必要散射和衍射，提升芯片的通信性能。
第一方面，提供了一种芯片中光波导结构的刻蚀方法，所述方法用于绝缘体上硅衬底SOI，所述SOI包括基底层、氧化掩埋层和单晶硅层，包括：根据第一图形，刻蚀所述单晶硅层，形成第一光波导结构；根据第二图形，刻蚀所述第一光波导结构形成第二光波导结构，其中所述第二图形的斜边与所述第一图形的斜边平行。
由于引起Si残留问题的空洞或尖角等通常位于平行于第一图形边缘位置，因此，通过设置第一图形的斜边与第二图形斜边平行，使得平行于第一图形的，引起Si残留问题的空洞或尖角的位置包括于第二图形中，从而在刻蚀第一光波导结构时，不再刻蚀第二图形对应的第一光波导结构的部分区域，从而能够避免Si残留问题导致的不必要散射、衍射等，提升芯片的通信性能。
结合第一方面，在第一方面的某些实现方式中，所述第一图形的第一直角边与所述第一图形的第二直角边平行。
结合第一方面，在第一方面的某些实现方式中，在所述根据第一图形，刻蚀所述单晶硅层，形成第一光波导结构之前，所述方法还包括：在所述单晶硅层表面依次形成二氧化硅SiO2层、氮化硅SiN层和第一光刻胶层；所述根据第一图形，刻蚀所述单晶硅层，形成第一光波导结构，包括：根据所述第一图形，依次刻蚀所述第一光刻胶层、所述SiN层、所述SiO2层以及所述单晶硅层，形成所述第一光波导结构。
结合第一方面，在第一方面的某些实现方式中，去除所述第一光刻胶层的剩余部分。
结合第一方面，在第一方面的某些实现方式中，在所述根据第二图形，刻蚀所述第一光波导结构形成第二光波导结构之前，所述方法还包括：在所述第一光波导结构表面依次形成无定形碳a-C层、氮氧化硅SiON层和第二光刻胶层，其中，在所述a-C层的表面形成有空洞或尖角，所述空洞或尖角被SiON填充；所述根据第二图形，刻蚀所述第一光波导结构形成第二光波导结构，包括：根据所述第二图形，依次刻蚀所述第二光刻胶层、所述SiON层、所述a-C层以及所述第一光波导结构，形成所述第二光波导结构，所述空洞或尖角的位置在所述第二图形的内部。
通过将引起Si残留的空洞或尖角的位置设置于第二图形的内部，使得在刻蚀中不刻蚀空洞或尖角的位置，能够避免空洞或尖角引起的Si残留问题，从而能够提升芯片的通信性能。
结合第一方面，在第一方面的某些实现方式中，所述第二图形的斜边与所述第一图形的斜边之间的距离范围为0nm至所述a-C层的厚度的二分之一。
结合第一方面，在第一方面的某些实现方式中，所述第一图形的第一直角边与所述第一图形的第二直角边之间的距离范围为工艺平台线宽至所述a-C层的厚度。
第二方面，提供了一种芯片，所述芯片包括光波导结构，所述光波导结构为采用上述第一方面或第一方面中任一种可能实现方式制作的光波导结构。
第三方面，提供了一种光通信设备，所述光通信设备包括上述第二方面中的芯片。
结合第三方面，在第三方面的某些实现方式中，所述光通信设备包括光模块，光交换机和光调制解调器中的任一项。
第四方面，提供了一种光模块，所述光模块包括上述第二方面中的芯片。
第五方面，提供了一种通信设备，包括：接收机，包括第二方面中的芯片；和/或，发射机，包括第二方面中的芯片。
第六方面，提供了一种通信设备，包括：收发器，用于接收或发送信号，所述收发器包括第二方面中的芯片，所述芯片用于对所述信号进行调制或解调；处理器，用于对所述信号进行信号处理。
附图说明
图1是适用于本申请实施例的一种示例性SOIwafer和SOI波导的结构示意图；
图2是本申请实施例中CMOS工艺制作SOI波导的基本流程的示例性示意图；
图3是本申请实施例中SOI波导制作流程中形成Si残留所处位置过程的俯视示意图；
图4是本申请实施例提供的一种芯片中光波导结构的刻蚀方法的示意性流程图；
图5是本申请实施例提供的一种芯片中光波导结构的刻蚀方法的示意性流程图；
图6是本申请实施例提供的一种芯片中光波导结构的刻蚀方法的示意图；
图7是本申请实施例提供的一种光芯片中光波导结构的刻蚀方法的刻蚀区域和a-C层上空洞或尖角形成位置的俯视图；
图8是本申请实施例提供的另一种芯片中光波导结构的刻蚀方法的示意图；
图9是本申请实施例提供的一种光芯片中光波导结构的刻蚀方法的刻蚀区域和a-C层上空洞或尖角形成位置的俯视图；
图10是本申请实施例提供的一种光通信设备的示例性示意图；
图11是本申请实施例提供的另一种光通信设备的示例性示意图；
图12是本申请实施例提供的另一种光通信设备的示例性示意图。
具体实施方式
下面将结合附图，对本申请实施例中的技术方案进行描述。
1969年，贝尔实验室的Miller S.E.首次提出了“集成光学”的概念，宣告了光纤通信产业进入集成器件的时代。采用集成电路技术(integrated circuit)制造波导芯片的光路，将常规分立光学元件的各种功能集成到同一光学衬底表面，完成常规由多个分立光学元件所构成的庞大光学系统的光信息处理能力，实现光波信号生产与探测、光功率分配、光开关、光滤波等功能。随着光纤通信技术的快速发展，该技术也得到了快速发展，逐步形成了自身特色。且大多数功能结构均在同一光学衬底上，主要结构是光波导通道，因此称该技术为平面光波导技术(planar lightwave circuit，PLC)。
平面光波导技术是在集成电路技术的基础上发展起来的，有其独特的地方。集成电路的基本元件是电阻、电容、电感和晶体管(二极管、三极管)，集成电路技术是在硅衬底上通过薄膜沉积、扩散、外延、光刻、刻蚀、退火等工艺制作这些基本的元件，并用导线互联。平面光波导的基本元件是激光器、光波导和探测器，所用的衬底材料各异，例如Ⅲ-Ⅴ族化合物半导体(InP和GaAs)、二氧化硅(SiO 2)、铌酸锂(LiNbO 3)、绝缘体上硅衬底(silicon on insulator，SOI)、聚合物(polymer)、玻璃等。而由于材料各异导致制作工艺具有多种类型。
平面光波导器件是采用平面光波导技术制造而成的器件，分为无源器件、有源器件以及有源/无源混合集成器件。其中，无源器件可以理解为无需能(电)源的器件，并且可以用于实现光波信号的传输、分波、合波、滤波等功能。无源器件主要有平面光波导分路器、阵列波导光栅(arrayed waveguide grating，AWG)、光滤波器等。
对于基于SOI晶圆(wafer)制作的平面光波导器件，可以称之为SOI波导。由于SOI波导是在SOI基片上制作的，SOIwafer的截面图和SOI波导的立体图如图1所示。即图1示出了适用于本申请实施例的一种示例性SOIwafer和SOI波导的结构示意图。如图1的(a)所示，SOIwafer包括基底层101a、氧化掩埋层102a和单晶硅层103a，分别为硅(Si)衬底层、二氧化硅(SiO 2)层、Si层，一般地，Si衬底层的厚度为500μm～725μm，SiO 2层的厚度为2μm或3μm，Si层的厚度为200nm～300nm。如图1的(b)所示，SOI波导包括底层101b、下包层102b、芯层103b和上包层104b，分别为Si衬底层、SiO 2层、Si层和空气，应理解，SOI波导可以有多种结构，例如图1的(b)所示的脊形波导结构。
由于在半导体集成电路制作流程中，可以利用光刻、刻蚀、注入和沉积等一系列工艺在同一硅衬底上形成大量各种类型的复杂器件，并将之互相连接以具有完整的电子功能。其中，使用的一种较为成熟的工艺为补充金属氧化物半导体(complementary metal-oxide semiconductor，CMOS)工艺，通过该CMOS工艺可以获得硅基集成电路。因此，在平面光波导的制作过程中类似地可以通过CMOS工艺在SOI基片上制备出SOI波导。
其中，在CMOS工艺的光刻中，主要采用硬掩膜技术，当半导体工艺进入90nm后，由于光刻尺寸越来越小，常需要在晶圆的表面形成硬掩膜层配合光刻胶形成的掩膜图形。硬掩膜(hardmask)是一种通过化学气相沉积(chemical vapor deposition，CVD)生成的 无机薄膜材料。其主要成分有氮化钛(TiN)、氮化硅(SiN)、二氧化硅(SiO 2)、无定形碳(amorphous carbon，a-C)等。其中，无定形碳由于在刻蚀中相对于氧化硅、氮化硅和硅的高刻蚀选择比，被广泛应用在CMOS工艺中。硬掩膜主要运用于多重光刻工艺中，首先把多重光刻胶图像转移到硬掩膜上，然后通过硬掩膜将最终图形转移到衬底上。
下面示例性地，以一种传导(transition)转换结构的SOI波导为例，结合图2和图3对CMOS工艺制作SOI波导的基本流程进行说明。
图2为CMOS工艺制作SOI波导的基本流程的示例性示意图，图2的(a)示出了制作transition转换结构的SOI波导中的不同材料对应的不同图案的阴影填充指示图，图2的(b)-(h)示出了transition转换结构的SOI波导制作流程中的俯视图，图2的(i)-(o)示出了transition转换结构的SOI波导制作流程中的截面图，其中，截面图对应于俯视图中沿虚线所示的位置。如图2所示，该基本流程包括S1-S7：
S1(结合图2的(b)和(i)进行介绍)，如图2的(b)所示，虚线表示图2的(i)所示的截面截取的位置，中间呈对称结构的两个矩形表示第一次光刻需要刻蚀的区域；如图2的(i)所示，首先在SOIwafer表面通过热氧化生长厚度为5nm～20nm的SiO 2层，然后通过低压力化学气相沉积(low pressure chemical vapor deposition，LPCVD)沉积氮化硅(SiN)层，其中，SiN层作为下述第一次光刻的硬掩膜层，SiO 2层用于增加SiN层的粘合度；
S2(结合图2的(c)和(j)进行介绍)，进行第一次光刻，将掩膜板上的图形转移至光刻胶，具体地，如图2的(c)所示，虚线表示图2的(j)所示的截面截取的位置，中间呈对称结构的两个矩形表示经过第一次光刻的部分步骤，将掩膜板上的图形转移至光刻胶后，显露出了SiN层(叉状阴影填充表示SiN)，具体地，通过涂胶(光刻胶)、前烘、曝光、后烘、显影、定影、坚膜等步骤将掩膜版上的图形转移至光刻胶上；如图2的(j)所示，将掩膜板上的图形转移至光刻胶，是指根据掩膜板上的图形，去除部分光刻胶，显露出下面的SiN层，从而可以在下述流程S3中继续刻蚀SiN层、SiO 2层、Si层，进而在Si层上获得期望的波导结构；
S3(结合图2的(d)和(k)进行介绍)，在完成上述流程S2后，可以根据转移到光刻胶上的图形进行第一次光刻的刻蚀流程，即从显露出的SiN层开始进行刻蚀。具体地，如图2的(d)所示，虚线表示图2的(k)所示的截面截取的位置，中间呈对称结构的两个矩形表示在上述流程S2的基础上，沿着显露出的SiN继续刻蚀，直至获得期望的波导结构，从而显露出Si层；如图2的(k)所示，通过刻蚀工艺，刻蚀掉Si层的一定厚度(在获得的凹坑位置，刻蚀掉的Si层的厚度较小，因此第一次光刻中的刻蚀可以称为浅刻蚀)，并且可以在下一个流程之前去除图中虚线框所示的光刻胶(例如氧化去胶、溶剂去胶、等离子去胶等)，其中第一次光刻中的刻蚀工艺可以是干法刻蚀，例如离子束刻蚀(ion beam etching，IBM)、反应离子束刻蚀(reactive ion beam etching，RIE)、电感耦合等离子体刻蚀(inductively coupled plasma etching，ICP)等；
S4(结合图2的(e)和(l)进行介绍)，在完成上述第一次光刻后，进行第二次光刻，首先将掩膜版上的图形转移至光刻胶。具体地，如图2的(e)所示，两条虚线分别表示图2的(l 1)和(l 2)所示的截面截取的位置，中间呈对称结构的四个五边形表示进行第二次光刻需要刻蚀的区域，并且该四个五边形框为白色填充表示显露出的氮氧化硅(SiON)层，或者说，四个五边形框表示经过第二次光刻的部分步骤，将掩膜板上的图形转移至光刻胶后显 露出了SiON层，具体地，通过涂胶(光刻胶)、前烘、曝光、后烘、显影、定影、坚膜等步骤将掩膜版上的图形转移至光刻胶上；如图2的(l 1)和(l 2)所示，在上述流程S3去除光刻胶的基础上依次形成a-C层，氮氧化硅(SiON)层，光刻胶(photoresist)层，其中，SiON层作为介电质抗反射层(dielectric anti-reflection coating，DARC)，a-C层作为硬掩膜层，在形成a-C层时，由于制作工艺本身的原因，会在a-C层靠近台阶处的位置形成空洞或尖角，从而在形成SiON层时，SiON会填充至该空洞或尖角中，即图中黑色a-C层上形成的凹坑底部的两个白色尖角，然后将掩膜版上的图形转移至光刻胶上，即去除图2的(e)所示的四个五边形所示区域的光刻胶；
S5(结合图2的(f)和(m)进行介绍)，在完成上述流程S4后，可以根据转移到光刻胶上的图形进行第二次光刻的刻蚀流程，即依次对显露出的SiON层、a-C层进行刻蚀。具体地，如图2的(f)和(m)所示，图2的(f)中的两条虚线分别表示图2的(m 1)和(m 2)所示的截面截取的位置，中间呈对称结构的四个五边形表示在上述流程S4的基础上通过沿着转移到光刻胶的图形进行刻蚀，直至显露出第一次光刻获得的Si层，四个五边形被较宽的斜线阴影填充，表示刻蚀后显露出的Si层；即沿着四个五边形区域刻蚀，直至显露出第一次光刻获得的Si层；也即依次刻蚀掉部分SiON层、部分a-C层，直至显露出第一次光刻获得的Si层。具体地，在使用对SiON刻蚀性强的物质对SiON层进行刻蚀时，由于空洞或尖角的存在，使得空洞或尖角处的SiON无法完全刻蚀掉，从而在使用对a-C刻蚀性强的物质对a-C层进行刻蚀时，在空洞或尖角处需要先刻蚀SiON，由于刻蚀选择性导致对SiON的刻蚀较慢，刻蚀掉SiON后才会对其下面的a-C进行刻蚀，从而会导致a-C的残留，即图2的(m)所示的凹坑处的较小的黑色阴影填充的矩形；
S6(结合图2的(g)和(n)进行介绍)，在上述流程S5的基础上继续刻蚀，直至显露出SOIwafer中间的SiO 2层。具体地，如图2的(g)和(n)所示，图2的(g)中的两条虚线分别表示图2的(n 1)和(n 2)所示的截面截取的位置，中间呈对称结构的四个五边形表示在上述流程S5的基础上继续刻蚀，直至显露出的SOIwafer中间的SiO 2层，四个五边形被点状阴影填充，表示刻蚀后显露出的SiO 2层；如图2的(n 1)和(n 2)所示，通过刻蚀工艺，刻蚀掉Si层的一定厚度(刻蚀掉的Si层厚度较大，因此第二次光刻中的刻蚀可以称为深刻蚀)，从而在Si层获得期望的结构。具体地，由于在上述流程S5中a-C的残留，在刻蚀Si层时，会导致Si刻蚀的不均匀，并进一步导致Si残留，如图2的(n 1)和(n 2)所示的凹坑处的较小的斜线阴影填充的矩形；
S7(结合图2的(h)和(o)进行介绍)，在完成上述流程S6之后，可以通过湿法清洗去除光刻胶、SiON层、a-C层、SiN层、SiO 2层以及，即可获得流程S7中所示的结构，如图2的(h)所示，两条虚线分别表示图2的(o 1)和(o 2)所示的截面截取的位置，中间呈对称结构的，形状类似于两翼的两个六边形表示厚度较小的Si层部分，中间呈对称结构的点状阴影填充的四个五边形表示显露出的SOIwafer中间的SiO 2层部分，其余斜线阴影填充的区域表示厚度较大的Si层部分；如图2的(o 1)和(o 2)所示，为获得的光波导结构的截面图，其中凹坑处的较小的斜线阴影填充的矩形表示Si残留。
为了更具体地说明存在Si残留位置，下面结合图3，对图2中transition转换结构的SOI波导中Si残留的位置进行详细说明。图3为SOI波导制作流程中形成Si残留过程的俯视示意图。
如图3的(a)所示，中间呈对称结构的两个实线矩形表示第一次光刻中刻蚀的区域，中间呈对称结构的两个虚线矩形的虚线边表示在进行第二次光刻过程中，a-C层上形成空洞或尖角的位置，并且实线矩形与虚线矩形相似。该实线矩形与虚线矩形之间的距离约等于a-C层的厚度的二分之一，即在第一次光刻形成的台阶附近会形成a-C无法覆盖到的空洞或尖角，且在垂直于a-C层厚度的方向上，该空洞或尖角与台阶之间的距离与a-C层的厚度的一半基本相同，关于空洞或尖角的形成原因可参考图2中的流程S4中的具体说明，此处不再赘述。如图3的(b)所示，四个点状阴影填充的五边形表示第二次光刻中刻蚀的区域，从而由于空洞或尖角的存在以及刻蚀选择性，将会在虚线边与五边形阴影部分重叠的位置形成Si残留，即在空洞或尖角对应的位置形成Si残留，即如图3的(c)中虚线所指示的位置会形成Si残留。
由上可知，由于a-C层上空洞或尖角的形成以及刻蚀选择性，会在空洞或尖角对应的位置形成Si残留，从而会导致散射、衍射等，从而严重影响光芯片的通信性能。
或者换句话说，由于a-C层上的空洞或尖角处于第二次光刻中刻蚀的位置，从而造成了Si的残留，并且该Si残留问题将会进一步导致严重的散射发射，严重影响光芯片的通信性能。
为了避免SOI波导上形成Si残留，提高光芯片的光学性能，本申请实施例提供了一种芯片中光波导结构的刻蚀方法，能够避免芯片上的Si残留问题，提升芯片的通信性能。
图4为本申请实施例提供的一种芯片中光波导结构的刻蚀方法400的示意性流程图。该方法可以用于SOI，该SOI包括基底层、氧化掩埋层和单晶硅层，例如图1的(a)中所示的结构。该方法400包括：
S401，根据第一图形，刻蚀单晶硅层，形成第一光波导结构。
具体地，在本申请实施例中，第一图形可以表示刻蚀区域，例如第一图形为光刻工艺中的版图设计；刻蚀单晶硅层可以是将SOI中的单晶硅层刻蚀掉一定的厚度，刻蚀掉的厚度小于SOI单晶硅层的厚度。此外，第一光波导结构在厚度方向的投影可以与第一图形相同。
S402，根据第二图形，刻蚀第一光波导结构，形成第二光波导结构，其中第二图形的斜边与第一图形的斜边平行。
具体地，在本申请实施例中，第二图形可以理解为，在刻蚀第一光波导结构获得第二光波导结构时，掩蔽的区域，即第二图形对应的部分是不再进行刻蚀的部分。或者说，第二图形可以与第二光波导结构在厚度方向上的投影相同。
由于引起Si残留问题的空洞或尖角等通常位于平行于第一图形边缘位置，因此，通过设置第一图形的斜边与第二图形斜边平行，使得平行于第一图形的，引起Si残留问题的空洞或尖角的位置包括于第二图形中，从而在刻蚀第一光波导结构时，不再刻蚀第二图形对应的第一光波导结构的部分区域，从而能够避免Si残留问题的产生，提升芯片的通信性能。
一种可能的实现方式中，第一图形的面积大于第二图形的面积，第一图形的第一直角边与第二图形的第一边重叠，第一图形的第一斜边与第二图形的第二边平行。
可选的，第一图形的第一直角边与第一图形的第二直角边平行。
另一种可能的实现方式中，上述S401和S402可以具体通过图5所示的方法500实现。
需要说明的是图5中的部分内容与图4中相同，可参考图4中的相关介绍，此处不再赘述。
图5为本申请实施例提供的一种芯片中光波导结构的刻蚀方法500的示意性流程图，该方法500包括：
S501，在单晶硅层表面依次形成SiO2层、SiN层和第一光刻胶层。
具体地，在本申请实施例中，在SOI晶圆表面进行第一次光刻，使用的光刻胶为上述第一光刻胶层，硬掩膜层为SiN层，SiO2层可以用来增加硬掩膜层与的粘合性，即使得硬掩膜层不易因振动等因素脱落。
S502，根据第一图形，依次刻蚀第一光刻胶层、SiN层、SiO2层以及单晶硅层，形成第一光波导结构。
关于第一图形、第一光波导结构的相关说明可参考图4中S401的相关介绍，此处不再赘述。
在本申请实施例中，第一光刻胶层、SiN层、SiO2层以及单晶硅层的刻蚀方法可以是不同的。例如，第一光刻胶层可以通过曝光、显影等方法刻蚀，而SiN层、SiO2层以及单晶硅层可以通过离子束刻蚀等方法刻蚀，本申请对此不作限定。
可选的，该方法500还可以包括S503：
S503，去除第一光刻胶层的剩余部分。
具体地，在上述步骤S502中对第一光刻胶层进行了刻蚀，从而刻蚀掉了第一图形部分的第一光刻胶层，但是第一光刻胶层还有其他剩余部分，S503去除掉第一光刻胶层的其他剩余部分。去除的方法可以有多种，本申请对此不作限定，例如可以通过湿法去除。
可选的，该方法500还可以包括S504-S505：
S504，在第一光波导结构表面依次形成a-C层、SiON层和第二光刻胶层，其中，在a-C层的表面形成有空洞或尖角，该空洞或尖角被SiON填充。
具体地，在本申请实施例中，S504可以为开始进行第二次光刻的步骤，第二光刻胶层为第二次光刻中采用的光刻胶，a-C层和SiON层为第二次光刻中的硬掩膜层。其中由于制作工艺本身的原因，在a-C层的表面会形成空洞或尖角，该空洞或尖角被SiON填充。
S505，根据第二图形，依次刻蚀第二光刻胶层、SiON层、a-C层以及第一光波导结构，形成第二光波导结构，空洞或尖角的位置在第二图形的内部。
关于第二图形、第二光波导结构的相关说明可参考图4中S402的相关介绍，此处不再赘述。
可选的，第二图形的斜边与第一图形的斜边之间的距离范围为0nm至a-C层的厚度的二分之一。例如，当a-C层厚度为400nm时，可以设置第二图形的斜边与第一图形的斜边之间的距离为0nm至200nm中的任意值。
应理解，第二图形的斜边与第一图形的斜边之间的最大距离设置为a-C层的厚度的二分之一，可以理解为，第二图形的斜边与第一图形的斜边之间的最大距离可以设置为近似等于a-C层的厚度的二分之一，在实际制作中可以存在一定的误差，保证空洞或尖角的位置位于第二图形的内部即可。
可选的，第一图形的第一直角边与第一图形的第二直角边之间的距离范围为工艺平台线宽至所述a-C层的厚度。例如，当a-C层厚度为400nm，工艺平台的线宽为65nm时， 可以设置第一图形的第一直角边与第一图形的第二直角边之间的距离为65nm至400nm中的任意值。此外，可选的，工艺平台的线宽还可以为45nm、90nm或130nm等，本申请对此不作限定。
应理解，第一图形的第一直角边与第一图形的第二直角边之间的最大距离设置为a-C层的厚度，可以理解为，为了避免空洞或尖角的形成，限制该距离的最大值近似等于a-C层的厚度，在实际制作中可以存在误差，保证在第一直角边与第二直角边之间不形成空洞或尖角即可。
因此，通过上述方法，将空洞或尖角的位置置于第二图形的内部，使得不刻蚀该空洞或尖角，从而不会导致Si残留，能够提升芯片的通信性能。
下面示例性地，结合图6-9，对本申请实施例提供的一种芯片中光波导结构的刻蚀方法进行介绍，其中，图6和7对应于上述图2和3中期望获得的transition转换结构，图8和9对应于偏振旋转-分束器(polarization rotator-splitters，PSR)结构。
图6为本申请实施例提供的一种光芯片中光波导结构的刻蚀方法示意图。具体地，图6的(a)示出了制作transition转换结构的光波导结构中的不同材料对应的不同阴影填充指示图，图6的(b)-(h)示出了transition转换结构的光波导结构制作流程中的俯视图，图6的(i)-(o)示出了transition转换结构的光波导结构制作流程中的截面图，其中，截面图对应于俯视图中沿虚线所示的位置。如图6所示，该刻蚀方法包括基本流程S1-S7：
S1(结合图6的(b)和(i)进行介绍)，如图6的(b)所示，虚线表示图6的(i)所示的截面截取的位置，中间呈对称结构的，形状类似于两翼的两个多边形表示第一次光刻中需要刻蚀的区域；如图6的(i)所示，首先在SOIwafer表面通过热氧化生长厚度为5nm～20nm的SiO 2层，然后通过低压力化学气相沉积(low pressure chemical vapor deposition，LPCVD)沉积氮化硅(SiN)层，其中，SiN层作为下述第一次光刻的硬掩膜层，SiO 2层用于增加SiN层的粘合度；S2(结合图6的(c)和(j)进行介绍)，进行第一次光刻，将掩膜板上的图形转移至光刻胶，具体地，如图6的(c)所示，虚线表示图6的(j)所示的截面截取的位置，中间呈对称结构，形状类似于两翼的两个多边形表示经过第一次光刻的部分步骤，将掩膜板上的图形转移至光刻胶后，显露出了SiN层(叉状阴影填充指示SiN)，具体地，通过涂胶(光刻胶)、前烘、曝光、后烘、显影、定影、坚膜等步骤将掩膜版上的图形转移至光刻胶上；如图6的(j)所示，将掩膜板上的图形转移至光刻胶，是指按照掩膜板上的图形，去除部分光刻胶，显露出下面的SiN层，从而可以在下述流程S3中继续刻蚀SiN层、SiO 2层、Si层，进而在Si层上获得期望的波导结构；
S3(结合图6的(d)和(k)进行介绍)，在完成上述流程S2后，可以根据转移到光刻胶上的图形进行第一次光刻的刻蚀流程，即从显露出的SiN层开始进行刻蚀。具体地，如图6的(d)所示，虚线表示图6的(k)所示的截面截取的位置，中间呈对称结构，形状类似于两翼的两个多边形表示在上述流程S2的基础上，沿着显露出的SiN继续刻蚀，直至获得期望的波导结构，从而显露出Si层；如图6的(k)所示，通过刻蚀工艺，刻蚀掉Si层的一定厚度，并且可以在下一个流程之前去除图中虚线框所示的光刻胶(例如氧化去胶、溶剂去胶、等离子去胶等)。可选的，第一次光刻中刻蚀的工艺可以是干法刻蚀，例如离子束刻蚀(ion beam etching，IBM)、反应离子束刻蚀(reactive ion beam etching，RIE)、电感耦合等离子体刻蚀(inductively coupled plasma etching，ICP)等，本申请对此不作限定；
S4(结合图6的(e)和(l)进行介绍)，在完成上述第一次光刻后，进行第二次光刻，首先将掩膜版上的图形转移至光刻胶。具体地，如图6的(e)所示，两条虚线分别表示图6的(l 1)和(l 2)所示的截面截取的位置，中间呈对称结构的四个五边形表示进行第二次光刻需要刻蚀的区域，并且该四个五边形为白色填充表示显露出的氮氧化硅(SiON)层，或者说，四个五边形表示经过第二次光刻的部分步骤，将掩膜板上的图形转移至光刻胶后显露出了SiON层，具体地，通过涂胶(光刻胶)、前烘、曝光、后烘、显影、定影、坚膜等步骤将掩膜版上的图形转移至光刻胶上；如图6的(l 1)和(l 2)所示，在上述流程S3去除光刻胶的基础上依次形成a-C层，氮氧化硅(SiON)层，光刻胶(photoresist)层，其中，SiON层作为介电质抗反射层(dielectric anti-reflection coating，DARC)，a-C层作为硬掩膜层。
此外，如图6的(l 1)所示，在沉积a-C的过程中，当凹坑的宽度小于或等于a-C层的厚度时，或者说当相对的两个台阶之间的距离小于或等于a-C层的厚度时，在凹坑处或在台阶附近的a-C层中将不会形成空洞或尖角。如图6的(l 2)所示，在沉积a-C的过程中，当凹坑的宽度大于a-C层的厚度时，或者说当相对的两个台阶之间的距离大于a-C层的厚度时，在凹坑处或在台阶附近的a-C层中将会形成空洞或尖角即图中黑色a-C层上形成的凹坑底部的两个白色尖角，从而在形成SiON层时，SiON会填充至该空洞或尖角中。对应于俯视图中，即图6的(e)中，图中两个三角形的虚线边表示空洞或尖角形成的位置，从图中可以看出，空洞或尖角形成的位置并不处于图中白色填充的五边形框的覆盖范围内，而处于第二次光刻中被光刻胶掩蔽的区域内。并且在图6的(e)中，白色填充的五边形框与形状类似于两翼的多边形存在重叠区域，关于该重叠区域的详细介绍可参考下述图7中的相关描述。
S5(结合图6的(f)和(m)进行介绍)，在完成上述流程S4后，可以根据转移到光刻胶上的图形进行第二次光刻的刻蚀流程，即依次对显露出的SiON层、a-C层进行刻蚀。具体地，如图6的(f)和(m)所示，图6的(f)中的两条虚线分别表示图6的(m 1)和(m 2)所示的截面截取的位置，中间呈对称结构的四个五边形表示在上述流程S4的基础上通过沿着转移到光刻胶的图形进行刻蚀，直至显露出第一次光刻获得的Si层，四个五边形被较宽的斜线阴影覆盖，表示刻蚀后显露出的Si层；即沿着四个五边形部分刻蚀，直至显露出第一次光刻获得的Si层；也即依次刻蚀掉部分SiON层、部分a-C层，直至显露出第一次光刻获得的Si层。此时，由于不需要对形成空洞或尖角的位置进行刻蚀，因此不会形成a-C的残留。
S6(结合图6的(g)和(n)进行介绍)，在上述流程S5的基础上继续刻蚀，直至显露出SOIwafer中间的SiO 2层。具体地，如图6的(g)和(n)所示，图6的(g)中的两条虚线分别表示图6的(n 1)和(n 2)所示的截面截取的位置，中间呈对称结构的四个五边形表示在上述流程S5的基础上继续刻蚀，直至显露出的SOIwafer中间的SiO 2层，四个五边形被点状阴影覆盖，表示刻蚀后显露出的SiO 2层；如图6的(n 1)和(n 2)所示，通过刻蚀工艺，刻蚀掉Si层的一定厚度，从而在Si层获得期望的结构。此时，由于在流程S5中并未产生a-C残留，因此，在流程S6中不会产生Si残留；
S7(结合图6的(h)和(o)进行介绍)，在完成上述流程S6之后，可以通过湿法清洗去除光刻胶、SiON层、a-C层、SiN层、SiO 2层以及，即可获得流程S7中所示的结构，如图6的(h)所示，两条虚线分别表示图6的(o 1)和(o 2)所示的截面截取的位置，中间呈对称结 构的，形状类似于两翼的两个六边形表示厚度较小的Si层部分，中间呈对称结构的点状阴影填充的四个五边形表示显露出的SOIwafer中间的SiO 2层部分，其余斜线阴影填充的区域表示厚度较大的Si层部分；如图6的(o 1)和(o 2)所示，为获得的光波导结构的截面图，此时，凹坑处将不会存在Si残留。
因此，通过上述刻蚀方法，避免了第二次光刻中对空洞或尖角位置出的刻蚀，从而避免了Si残留的产生。
为了详细地说明图6中第一次光刻的刻蚀区域、第二次光刻的刻蚀区域以及空洞或尖角形成位置之间的关系，下面结合图7进行详细介绍。
即图7为本申请实施例提供的一种光芯片中光波导结构的刻蚀方法的刻蚀区域和a-C层上空洞或尖角形成位置的俯视图。
如图7的(a)所示，中间呈对称结构的点状阴影填充的，形状类似于两翼的两个多边形表示第一次光刻中刻蚀的区域；位于两个多边形中的两个三角形的虚线边表示a-C层的空洞或尖角形成的位置。
如图7的(b)所示，中间呈对称结构的斜线阴影填充的四个五边形表示第二次光刻中刻蚀的区域，该四个五边形与两个多边形存在重叠部分(图中点状填充与斜线填充重叠的部分)，应理解，该四个五边形的形状和尺寸均相同。由于两个十边形以及四个五边形为对称结构，因此重叠部分包括相同的四个重叠区域，为避免重复，下述对重叠部分的其中一个重叠区域进行说明。
如图7的(c)所示，为图7的(b)的局部放大示意图，图中点状阴影填充与斜线阴影填充重叠的部分为重叠区域A，该重叠区域A的A 1边与A 2边同时也是上述多边形的边，该重叠区域A的A 3边与A 4边同时也是五边形的边，并且A 1边与A 3边平行，其距离为c 1，A 2边与A 4边平行，其距离为c 2。或者换句话说，重叠区域A由至少两个梯形组成，该至少两个梯形包括的两个梯形的高分别为c 1、c 2。
应理解，在本申请实施例中，对于上述图4和图5所示方法中的第一图形的斜边和第二图形的斜边，可以理解为，以图7的(c)中的A 4边为基准，不平行且不垂直于该A 4边的边为第一图形的斜边或第二图形的斜边，其中，在图7中，第一图形为中间呈对称结构的点状阴影填充的，形状类似于两翼的两个多边形，第二图形为第一图形中除去重叠区域A后的图形。从而，第一图形的斜边例如为图7的(c)中的A 1边，第二图形的斜边例如为图7的(c)中的A 3边。
还应理解，在本申请实施例中，对于上述图4和图5所示方法中的第一图形的第一直角边和第一图形的第二直角边，可以理解为，同样以图7的(c)中的A 4边为基准，平行于A 4边的边为第一图形的直角边，例如，第一图形的第一直角边为图7的(c)中的A 4边，又例如，第一图形的第二直角边为图7的(c)中的A 2边。
此外，上述距离c 1或高c 1满足的范围为0nm至a-C层厚度的二分之一，上述距离c 2或高c 2满足的范围为工艺平台线宽至a-C层厚度。例如，当工艺平台线宽为65nm，a-C层厚度为400nm时，c 2可以为65nm至400nm中的任意值。
因此，通过上述对第一次光刻中刻蚀区域限制，使其满足一定的条件，能够将台阶处产生的空洞的位置不包括在第二次光刻中刻蚀的区域，如图7的(b)和(c)所示的指示空洞位置的虚线不包括于重叠区域中，使得第二次光刻的刻蚀不会对SiON填充的空洞进 行刻蚀，从而不会形成Si残留，避免了Si残留问题，能够进一步提升光芯片的光学性能。
图8为本申请实施例提供的另一种光芯片中光波导结构的刻蚀方法的示意图。具体地，图8的(a)示出了制作PSR结构的光波导结构中的不同材料对应的不同阴影填充指示图，图8的(b)-(h)示出了PSR结构的光波导结构制作流程中的俯视图，图8的(i)-(o)示出了PSR结构的光波导结构制作流程中的截面图，其中，截面图对应于俯视图中沿虚线所示的位置。如图8所示，该刻蚀方法包括基本流程S1-S7：需要说明的是，图8中的部分流程与图6中的部分流程相同(例如S1-S3)，详细可参考图6中的相应描述，此处不再赘述。
S1(结合图8的(b)和(i)进行介绍)，关于该步骤的详细描述可参考图6中S1的相关介绍，此处不再赘述。
S2(结合图8的(c)和(j)进行介绍)，关于该步骤的详细描述可参考图6中S2的相关介绍，此处不再赘述。
S3(结合图8的(d)和(k)进行介绍)，关于该步骤的详细描述可参考图6中S3的相关介绍，此处不再赘述。
S4(结合图8的(e)和(l)进行介绍)，在完成上述第一次光刻后，进行第二次光刻，首先将掩膜版上的图形转移至光刻胶。具体地，如图8的(e)所示，两条虚线分别表示图8的(l 1)和(l 2)所示的截面截取的位置，中间呈对称结构的两个五边形表示进行第二次光刻需要刻蚀的区域，并且该两个五边形为白色填充表示显露出的氮氧化硅(SiON)层，或者说，两个五边形表示经过第二次光刻的部分步骤，将掩膜板上的图形转移至光刻胶后显露出了SiON层，具体地，通过涂胶(光刻胶)、前烘、曝光、后烘、显影、定影、坚膜等步骤将掩膜版上的图形转移至光刻胶上；如图8的(l 1)和(l 2)所示，在上述流程S3去除光刻胶的基础上依次形成a-C层，氮氧化硅(SiON)层，光刻胶(photoresist)层，其中，SiON层作为介电质抗反射层(dielectric anti-reflection coating，DARC)，a-C层作为硬掩膜层。
此外，如图8的(l 1)所示，在沉积a-C的过程中，当凹坑的宽度小于或等于a-C层的厚度时，或者说当相对的两个台阶之间的距离小于或等于a-C层的厚度时，在凹坑处或在台阶附近的a-C层中将不会形成空洞或尖角。如图8的(l 2)所示，在沉积a-C的过程中，当凹坑的宽度大于a-C层的厚度时，或者说当相对的两个台阶之间的距离大于a-C层的厚度时，在凹坑处或在台阶附近的a-C层中将会形成空洞或尖角即图中黑色a-C层上形成的凹坑底部的两个白色尖角，从而在形成SiON层时，SiON会填充至该空洞或尖角中。对应于俯视图中，即图8的(e)中，图中两个三角形的虚线边表示空洞或尖角形成的位置，从图中可以看出，空洞或尖角形成的位置并不处于图中白色填充的五边形框的覆盖范围内，而处于第二次光刻中被光刻胶掩蔽的区域内。并且在图8的(e)中，白色填充的五边形框与形状类似于两翼的多边形存在重叠区域，关于该重叠区域的详细介绍可参考下述图9中的相关描述。
S5(结合图8的(f)和(m)进行介绍)，在完成上述流程S4后，可以根据转移到光刻胶上的图形进行第二次光刻的刻蚀流程，即依次对显露出的SiON层、a-C层进行刻蚀。具体地，如图8的(f)和(m)所示，图8的(f)中的两条虚线分别表示图8的(m 1)和(m 2)所示的截面截取的位置，中间呈对称结构的两个五边形表示在上述流程S4的基础上通过沿着转移到光刻胶的图形进行刻蚀，直至显露出第一次光刻获得的Si层，四个五边形被较宽的斜线阴影覆盖，表示刻蚀后显露出的Si层；即沿着两个五边形部分刻蚀，直至显露出第一 次光刻获得的Si层；也即依次刻蚀掉部分SiON层、部分a-C层，直至显露出第一次光刻获得的Si层。此时，由于不需要对形成空洞或尖角的位置进行刻蚀，因此不会形成a-C的残留。
S6(结合图8的(g)和(n)进行介绍)，在上述流程S5的基础上继续刻蚀，直至显露出SOIwafer中间的SiO 2层。具体地，如图8的(g)和(n)所示，图8的(g)中的两条虚线分别表示图8的(n 1)和(n 2)所示的截面截取的位置，中间呈对称结构的两个五边形表示在上述流程S5的基础上继续刻蚀，直至显露出的SOIwafer中间的SiO 2层，两个五边形被点状阴影覆盖，表示刻蚀后显露出的SiO 2层；如图8的(n 1)和(n 2)所示，通过刻蚀工艺，刻蚀掉Si层的一定厚度，从而在Si层获得期望的结构。此时，由于在流程S5中并未产生a-C残留，因此，在流程S6中不会产生Si残留；
S7(结合图8的(h)和(o)进行介绍)，在完成上述流程S6之后，可以通过湿法清洗去除光刻胶、SiON层、a-C层、SiN层、SiO 2层以及，即可获得流程S7中所示的结构，如图8的(h)所示，两条虚线分别表示图8的(o 1)和(o 2)所示的截面截取的位置，中间呈对称结构的，形状类似于两翼的两个三角形表示厚度较小的Si层部分，中间呈对称结构的点状阴影填充的四个五边形表示显露出的SOIwafer中间的SiO 2层部分，其余斜线阴影填充的区域表示厚度较大的Si层部分；如图8的(o 1)和(o 2)所示，为获得的光波导结构的截面图，此时，凹坑处将不会存在Si残留。
因此，通过上述刻蚀方法，避免了第二次光刻中对空洞或尖角位置出的刻蚀，从而避免了Si残留的产生。
为了详细地说明图8中第一次光刻的刻蚀区域、第二次光刻的刻蚀区域以及空洞或尖角形成位置之间的关系，下面结合图9进行详细介绍。
即图9为本申请实施例提供的另一种光芯片中光波导结构的刻蚀方法的刻蚀区域和a-C层上空洞或尖角形成位置的俯视图。
如图9的(a)所示，中间呈对称结构的点状阴影填充的，形状类似于两翼的两个多边形表示第一次光刻中刻蚀的区域；位于两个多边形中的三角形的虚线边表示a-C层的空洞或尖角形成的位置。
如图9的(b)所示，中间呈对称结构的斜线阴影填充的两个多边形表示第二次光刻中刻蚀的区域，点状阴影覆盖的多边形与斜线阴影覆盖的多边形存在重叠部分，由于结构的对称性，重叠部分包括对称的两个重叠区域，为避免重复，下述对重叠部分的其中一个重叠区域进行说明。
如图9的(c)所示，为图9的(b)的局部放大示意图，图中点状阴影填充与斜线阴影填充重叠的部分为重叠区域B，该重叠区域B的B 1边和B 2边同时也是上述点状阴影填充的多边形的边，该重叠区域B的B 3边和B 4边同时也是上述斜线阴影填充的多边形的边，并且B 1边与B 3边平行，其距离为c 1，B 2边与B 4边平行，其距离为c 2。或者换句话说，重叠区域B由两个梯形组成，该两个梯形的高分别为c 1、c 2。
应理解，在本申请实施例中，类似与上述图7中的相关说明，对于上述图4和图5所示方法中的第一图形的斜边和第二图形的斜边，可以理解为，以图9的(c)中的B 4边为基准，不平行且不垂直于该B 4边的边为第一图形的斜边或第二图形的斜边，其中，在图9中，第一图形为中间呈对称结构的点状阴影填充的，形状类似于两翼的两个多边形，第二 图形为第一图形中除去重叠区域B后的图形。从而，第一图形的斜边例如为图9的(c)中的B 1边，第二图形的斜边例如为图9的(c)中的B 3边。
还应理解，在本申请实施例中，类似与上述图7中的相关说明，对于上述图4和图5所示方法中的第一图形的第一直角边和第一图形的第二直角边，可以理解为，同样以图9的(c)中的B 4边为基准，平行于B 4边的边为第一图形的直角边，例如，第一图形的第一直角边为图9的(c)中的B 4边，又例如，第一图形的第二直角边为图9的(c)中的B 2边。
此外，上述距离c 1或高c 1满足的范围为0nm至a-C层厚度的二分之一，上述距离c 2或高c 2满足的范围为工艺平台线宽至a-C层厚度。例如，当工艺平台线宽为65nm，a-C层厚度为400nm时，c 2可以为65nm至400nm中的任意值。
因此，通过上述对第一次光刻中刻蚀区域限制，使其满足一定的条件，能够将台阶处产生的空洞的位置不包括在第二次光刻中刻蚀的区域，如图9的(b)和(c)所示的指示空洞位置的虚线不包括于重叠区域中，即第二次光刻的刻蚀不会对SiON填充的空洞进行刻蚀，从而不会形成Si残留，避免了Si残留问题，能够进一步提升光芯片的光学性能。
本申请实施例提供了一种芯片，所述芯片包括光波导结构，所述光波导结构为采用上述方法制作的光波导结构。
本申请实施例还提供了一种光通信设备，所述光通信设备包括上述芯片。
一种可能的实现方式中，上述光通信设备包括光模块，光交换机和光调制解调器中的任一项。
图10是本申请实施例提供的一种光通信设备的示例性示意图。如图10所示，该光通信设备包括光模块1010。可选的，该光模块1010包括采用上述图4-9所示的方法制作获得的芯片。可选的，该光通信设备还可以包括其他一个或多个光模块，例如，光模块1020。
一种可能的实现方式中，光模块1010用于对光通信设备中接收的信号进行处理，而光模块1020用于对光通信设备中发送的信号进行处理。
图11是本申请实施例提供的另一种光通信设备的示例性示意图。如图11所示，该光通信设备包括光交换机1110。可选的，该光交换机1110包括采用上述图4-9所示的方法制作获得的芯片。可选的，该光通信设备还可以包括其他一个或多个光交换机，例如，光交换机1120。
一种可能的实现方式中，光交换机1110用于对光通信设备中接收的信号进行处理，而光交换机1120用于对光通信设备中发送的信号进行处理。
图12是本申请实施例提供的另一种光通信设备的示例性示意图。如图11所示，该光通信设备包括光调制解调器1210。可选的，该光调制解调器1210包括采用上述图4-9所示的方法制作获得的芯片。可选的，该光通信设备还可以包括其他一个或多个光调制解调器，例如，光调制解调器1220。
一种可能的实现方式中，光调制解调器1210用于对光通信设备中接收的信号进行处理，而光调制解调器1220用于对光通信设备中发送的信号进行处理。
本申请实施例还提供了一种光模块，所述光模块包括上述芯片。
本申请实施例还提供了一种通信设备，包括：接收机，包括上述芯片；和/或，发射机，包括上述芯片。
本申请实施例还提供了一种通信设备，包括：收发器，用于接收或发送信号，所述收发器包括上述芯片，所述芯片用于对所述信号进行调制或解调；处理器，用于对所述信号进行信号处理。
专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (10)

  1. 一种芯片中光波导结构的刻蚀方法，所述方法用于绝缘体上硅衬底SOI，所述SOI包括基底层、氧化掩埋层和单晶硅层，其特征在于，包括：
    根据第一图形，刻蚀所述单晶硅层，形成第一光波导结构；
    根据第二图形，刻蚀所述第一光波导结构形成第二光波导结构，其中所述第二图形的斜边与所述第一图形的斜边平行。
  2. 如权利要求1所述的方法，其特征在于，所述第一图形的第一直角边与所述第一图形的第二直角边平行。
  3. 如权利要求1或2所述的方法，其特征在于，在所述根据第一图形，刻蚀所述单晶硅层，形成第一光波导结构之前，所述方法还包括：
    在所述单晶硅层表面依次形成二氧化硅SiO 2层、氮化硅SiN层和第一光刻胶层；
    所述根据第一图形，刻蚀所述单晶硅层，形成第一光波导结构，包括：
    根据所述第一图形，依次刻蚀所述第一光刻胶层、所述SiN层、所述SiO 2层以及所述单晶硅层，形成所述第一光波导结构。
  4. 如权利要求3所述的方法，其特征在于，所述方法还包括：
    去除所述第一光刻胶层的剩余部分。
  5. 如权利要求1-4任一项所述的方法，其特征在于，在所述根据第二图形，刻蚀所述第一光波导结构形成第二光波导结构之前，所述方法还包括：
    在所述第一光波导结构表面依次形成无定形碳a-C层、氮氧化硅SiON层和第二光刻胶层，其中，在所述a-C层的表面形成有空洞或尖角，所述空洞或尖角被SiON填充；
    所述根据第二图形，刻蚀所述第一光波导结构形成第二光波导结构，包括：
    根据所述第二图形，依次刻蚀所述第二光刻胶层、所述SiON层、所述a-C层以及所述第一光波导结构，形成所述第二光波导结构，所述空洞或尖角的位置在所述第二图形的内部。
  6. 如权利要求1-5任一项所述的方法，其特征在于，所述第二图形的斜边与所述第一图形的斜边之间的距离范围为0nm至所述a-C层的厚度的二分之一。
  7. 如权利要求1-6任一项所述的方法，其特征在于，所述第一图形的第一直角边与所述第一图形的第二直角边之间的距离范围为工艺平台线宽至所述a-C层的厚度。
  8. 一种芯片，其特征在于，所述芯片包括光波导结构，所述光波导结构为采用上述权利要求1-4中任一项方法制作的光波导结构。
  9. 一种光通信设备，其特征在于，所述光通信设备包括权利要求5中的芯片。
  10. 如权利要求9所述的光通信设备，其特征在于，所述光通信设备包括光模块，光交换机和光调制解调器中的任一项。
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