WO2023039892A1 - 光芯片及其制备方法、通信设备 - Google Patents

光芯片及其制备方法、通信设备 Download PDF

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Publication number
WO2023039892A1
WO2023039892A1 PCT/CN2021/119406 CN2021119406W WO2023039892A1 WO 2023039892 A1 WO2023039892 A1 WO 2023039892A1 CN 2021119406 W CN2021119406 W CN 2021119406W WO 2023039892 A1 WO2023039892 A1 WO 2023039892A1
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Prior art keywords
optical waveguide
sub
layer
optical
dielectric layer
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PCT/CN2021/119406
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English (en)
French (fr)
Inventor
袁俊
马庆艳
李世梁
沈淼
王根成
江先鑫
杨莉
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华为技术有限公司
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Priority to PCT/CN2021/119406 priority Critical patent/WO2023039892A1/zh
Priority to CN202180100152.7A priority patent/CN117616316A/zh
Publication of WO2023039892A1 publication Critical patent/WO2023039892A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind

Definitions

  • the present application relates to the technical field of optical communication, in particular to an optical chip, a preparation method thereof, and a communication device.
  • a communication device 1 mainly includes an optical chip 10 and an optical fiber 20 , and optical signals between different optical chips 10 are transmitted through the optical fiber 20 .
  • the optical chip 10 includes a substrate 100 and an optical waveguide (also referred to as a speckle converter) 101 disposed on the substrate 100, one end of the optical waveguide 101 is coupled with the optical fiber 20, and the optical signal is transmitted through the optical waveguide 101 through the optical chip 101. 10 and the transmission between the optical fiber 20.
  • the core size R of the optical fiber 20 is usually 8um-10um
  • the width H of the optical waveguide 101 is usually 300nm-500nm. Due to the huge gap between the two in terms of geometric dimensions, this leads to a serious mismatch of the optical mode field, increasing the coupling loss and port reflections.
  • the process of preparing the wedge-shaped optical waveguide 101 is: first forming an optical waveguide layer on the substrate 100 , and then etching the optical waveguide layer to form the wedge-shaped optical waveguide 101 .
  • the lithography equipment can lithographically develop the photoresist with a line width of less than 100nm, but because the thickness of the optical waveguide layer is relatively large, usually 220nm or thicker, in the process of etching the optical waveguide layer , the tip of the optical waveguide 101 is easily broken or damaged, which leads to difficulties in the actual manufacturing process.
  • Embodiments of the present application provide an optical chip, a manufacturing method thereof, and a communication device, which can solve the problem that the tip of an optical waveguide in an existing optical chip is easily broken during the manufacturing process.
  • the application adopts the following technical solutions:
  • a method for preparing an optical chip comprising: firstly, forming a strip-shaped optical waveguide body on a substrate; next, forming a first dielectric thin film on the side of the optical waveguide body away from the substrate Next, the first dielectric film is ground and processed to form the first dielectric layer, and the surface of the optical waveguide body away from the substrate is exposed to the first dielectric layer to form the first through hole in the first dielectric layer, and the optical waveguide body Located in the first through hole; next, a sacrificial layer is formed on the first dielectric layer; the projection of the sacrificial layer on the optical waveguide body covers the first sub-optical waveguide in the optical waveguide body, and does not cover the third sub-optical waveguide in the optical waveguide body.
  • the optical waveguide In the optical waveguide, at least part of the first sub-optical waveguide gradually decreases in width along the direction close to the third sub-optical waveguide; next, the sacrificial layer and the third sub-optical waveguide are etched to remove the sacrificial layer and the third sub-optical waveguide , to form an optical waveguide, the optical waveguide includes a first sub-optical waveguide; next, filling the second dielectric layer in the first through hole; the optical waveguide is in contact with both the sidewall of the first through hole and the side surface of the second dielectric layer, The other side of the second dielectric layer is in contact with the other side wall of the first through hole.
  • the third sub-optical waveguide in the optical waveguide body is etched away, and the first sub-optical waveguide in the optical waveguide body is retained as an optical waveguide. Since at least part of the first sub-optical waveguide gradually decreases in width along the direction approaching the third sub-optical waveguide, the formed optical waveguide includes a portion whose width gradually decreases, that is, at least part of the formed optical waveguide is wedge-shaped, and also That is, the formed optical waveguide includes the tip.
  • the tip area of the optical waveguide body that needs to be etched (that is, the area where the third sub-optical waveguide is located) is supplemented by the sacrificial layer to a no-tip area, so the sacrificial layer and the third sub-waveguide
  • the optical waveguide is etched at the same time, there are no sharp corners in the etched part and the unetched part, so there will be no residue in the unetched part, and there will be no broken parts in the etched part.
  • Risk and rat-tooth phenomenon that is, the third sub-optical waveguide that needs to be removed will be completely removed, and there will be no residue. There is no sharp corner area in the etched part and the unetched part, so that the small line width effect can be avoided.
  • the optical waveguide body includes an optical waveguide layer and a protective layer stacked; the optical waveguide layer is closer to the substrate relative to the protective layer; after the sacrificial layer is formed on the first dielectric layer, the sacrificial layer and the second Before the etching of the third sub-optical waveguide, the preparation method further includes: removing the protective layer on the third sub-optical waveguide. Since the optical waveguide body includes an optical waveguide layer and a protective layer, the final prepared optical waveguide includes an optical waveguide layer and a protective layer that are laminated.
  • the protective layer can be used to protect the optical waveguide layer and prevent damage to the optical waveguide layer.
  • the protective layer on the third sub-optical waveguide is removed so that the third sub-optical waveguide and the sacrificial layer can be simultaneously etched in subsequent steps.
  • the above preparation method further includes: forming a second dielectric thin film on the sacrificial layer.
  • the aforementioned removal of the protective layer on the third sub-optical waveguide includes: firstly, etching the second dielectric thin film to form a third dielectric layer, the third dielectric layer includes a second through hole, the sacrificial layer and the third sub-optical waveguide are exposed on the first Two through holes; next, removing the protective layer on the third sub-optical waveguide; filling the second dielectric layer in the first through hole includes: filling the second dielectric layer in the first through hole and the second through hole.
  • the protective layer on the third sub-optical waveguide can be removed while etching the second dielectric film, which can simplify the process; filling the second dielectric layer in the first through hole and the second through hole can play a role in the optical waveguide.
  • the optical waveguide body further includes a second optical sub-waveguide arranged on the side of the first optical sub-waveguide away from the third optical sub-waveguide and in contact with the first optical sub-waveguide, the second optical sub-waveguide The etching need not be performed.
  • the optical waveguide body includes the first sub-optical waveguide, the second sub-optical waveguide and the third sub-optical waveguide
  • the finally prepared optical waveguide includes the first sub-optical waveguide and the second sub-optical waveguide
  • the optical waveguide includes For the first sub-optical waveguide, the length of the optical waveguide can be increased.
  • the width of at least another part of the first sub-optical waveguide gradually decreases along the direction away from the third sub-optical waveguide, and at least part of the second sub-optical waveguide The direction gradually decreases; the sacrificial layer and the third sub-optical waveguide are etched to remove the sacrificial layer and the third sub-optical waveguide, including: the sacrificial layer, the first sub-optical waveguide and the third sub-optical waveguide located below the sacrificial layer Carry out etching at the same time, remove the sacrificial layer, the part of the first sub-optical waveguide close to the sacrificial layer and the third sub-optical waveguide to form the optical waveguide, the optical waveguide includes the first sub-optical waveguide and the second sub-optical waveguide; the first sub-optical waveguide The thickness of is smaller than the thickness of the second sub-optical waveguide.
  • the first sub-optical waveguide and the second sub-optical waveguide are different, and the thickness of the second sub-optical waveguide is greater than the thickness of the first sub-optical waveguide, the first sub-optical waveguide and the second sub-optical waveguide Steps are formed at the junction of the two layers, and the formed optical waveguide includes steps.
  • the steps can divide the optical waveguide into two layers of optical waveguides stacked, namely, the first layer of optical waveguides and the second layer of optical waveguides, and the first layer of optical waveguides are opposite to each other.
  • the optical waveguide in the second layer is close to the substrate.
  • the first-layer optical waveguide since at least part of the first sub-optical waveguide gradually decreases in width along the direction away from the second sub-optical waveguide, the first-layer optical waveguide includes a portion whose width gradually decreases, that is, at least part of the first-layer optical waveguide The shape of the part is wedge-shaped.
  • the second optical waveguide since at least part of the second sub-optical waveguide gradually decreases in width along the direction approaching the first sub-optical waveguide, and the thickness of the second sub-optical waveguide is greater than the thickness of the first sub-optical waveguide, the second optical waveguide includes The portion where the width gradually decreases, that is, at least part of the second-layer optical waveguide is wedge-shaped.
  • the shape of at least part of the two layers of optical waveguides is wedge-shaped, when the optical chip and optical fiber are coupled, the optical field mode spot at the optical chip and optical fiber coupling can be further increased, and the coupling loss and port reflection can be further reduced, thereby further Improve the coupling efficiency of optical waveguide and optical fiber, and improve the quality of signal transmission.
  • forming the sacrificial layer on the first dielectric layer includes: forming a sacrificial film on the first dielectric layer; patterning the sacrificial film to form a sacrificial layer and an auxiliary pattern; and forming the auxiliary pattern on the optical waveguide body There is no overlapping area between the projection of the optical waveguide and the optical waveguide body; etching the sacrificial layer and the third sub-optical waveguide to remove the sacrificial layer and the third sub-optical waveguide, including: etching the sacrificial layer, the auxiliary pattern and the third sub-optical waveguide , removing the sacrificial layer, the auxiliary pattern and the third sub-optical waveguide.
  • the auxiliary pattern since the auxiliary pattern is formed while forming the sacrificial layer, the auxiliary pattern can be etched while the sacrificial layer is etched, and during the etching process, since the auxiliary pattern can consume The energy generated by the plasma during the etching of the region can increase the etched area. In this way, the microscopic loading effect of the plasma during etching can be greatly improved, and the etching process has good stability and large tolerance.
  • the above preparation method further includes: forming a second dielectric film on the sacrificial layer; Removing the protective layer on the third sub-optical waveguide includes: first, etching the second dielectric film to form a third dielectric layer, the third dielectric layer includes the second through hole and the third through hole, the sacrificial layer and the third sub-optical waveguide The waveguide is exposed in the second through hole, and the auxiliary pattern is exposed in the third through hole; next, removing the protective layer on the third sub-optical waveguide; next, filling the second dielectric layer in the first through hole, including: The first through hole, the second through hole and the third through hole are filled with the second dielectric layer.
  • a third through hole is formed in the third dielectric layer, and the auxiliary pattern is exposed in the third through hole, so that the auxiliary pattern can be etched while the sacrificial layer and the third sub-optical waveguide can be etched, Since the auxiliary pattern can consume the energy generated by the plasma during etching in areas other than the sacrificial layer, that is, the area to be etched can be increased. In this way, the microscopic loading effect of the plasma during etching can be greatly improved, and the etching process is stable. Good performance and large tolerance.
  • the optical waveguide body includes an optical waveguide layer and a barrier layer that are stacked; the optical waveguide layer is closer to the substrate relative to the barrier layer; Before the step of forming a sacrificial layer on the layer, the preparation method further includes: removing the barrier layer.
  • the optical waveguide body includes a barrier layer
  • the first dielectric film when the first dielectric film is ground, after the first dielectric film above the barrier layer in the optical waveguide body is polished, that is, when it is polished to the barrier layer of the optical waveguide body , because the optical waveguide body includes a barrier layer, and the hardness of the barrier layer is usually relatively high (for example, the material of the barrier layer is silicon nitride, and the hardness of silicon nitride is relatively high), so the barrier layer can force the grinding to stop when the barrier layer is polished, Avoid damage to the protective layer and optical waveguide layer during the grinding process.
  • the projected shape of the optical waveguide body on the substrate is a rectangle.
  • the material of the sacrificial layer includes one or more of polysilicon, amorphous silicon, silicon nitride, and silicon oxynitride.
  • the material of the sacrificial layer is polysilicon or amorphous silicon, it can be formed in the MOS tube.
  • the sacrificial layer is formed at the same time as the polysilicon layer or the amorphous silicon layer, that is to say, the sacrificial layer is compatible with the existing process. Therefore, adding the sacrificial layer in the process of manufacturing the optical chip in this application will not increase the process cost, and the product has high flexibility.
  • an optical chip in a second aspect, includes a substrate and a first dielectric layer disposed on the substrate; the first dielectric layer includes a first through hole; the optical chip also includes an optical chip filled in the first through hole An optical waveguide and a second medium layer; wherein, the projection of the optical waveguide on the substrate is strip-shaped, the optical waveguide includes a first sub-optical waveguide, and the width of at least part of the projection of the first sub-optical waveguide on the substrate gradually decreases ; The optical waveguide is in contact with both the side wall of the first through hole and the side of the second dielectric layer, and the other side of the second dielectric layer is also in contact with the other side wall of the first through hole. Since the optical chip provided by the second aspect has the same technical effect as the method for preparing the optical chip provided by the first aspect above, reference may be made to the relevant description of the first aspect above, and details will not be repeated here.
  • the optical waveguide further includes a second sub-optical waveguide in contact with the first sub-optical waveguide; at least part of the first sub-optical waveguide gradually decreases in width along a direction away from the second sub-optical waveguide.
  • the optical waveguide also includes a second sub-optical waveguide, so that the length of the optical waveguide can be increased.
  • the thickness of the first sub-optical waveguide is smaller than the thickness of the second sub-optical waveguide; wherein, at least part of the second sub-optical waveguide gradually decreases in width along a direction approaching the first sub-optical waveguide; At least another part of one sub-optical waveguide gradually decreases in width along a direction approaching the second sub-optical waveguide.
  • the difference between the thickness of the second sub-optical waveguide and the thickness of the first sub-optical waveguide ranges from 50 nm to 90 nm.
  • the difference between the thickness of the second sub-optical waveguide and the thickness of the first sub-optical waveguide ranges from 50nm to 90nm, it is beneficial to the transmission of optical signals.
  • the optical chip further includes a third dielectric layer disposed on the side of the first dielectric layer away from the substrate; the third dielectric layer includes a second through hole; the projection of the second through hole on the substrate Covering the first sub-optical waveguide, the second dielectric layer located in the first through hole, and the projection of the part of the first dielectric layer on the substrate; wherein, the second through hole is filled with the second dielectric layer.
  • the third dielectric layer covers the optical waveguide and can be used to protect the optical waveguide.
  • the third dielectric layer further includes a third through hole; the third through hole is filled with the second dielectric layer; wherein, the projection of the third through hole on the substrate and the optical waveguide on the substrate The projections of have no overlapping regions.
  • an auxiliary pattern may be formed at the third through hole.
  • the material of the third dielectric layer is the same as that of the first dielectric layer.
  • the projection of the first through hole on the substrate is a rectangle.
  • the space area occupied by the first through hole is the same as the space area occupied by the optical waveguide body in the process of preparing the optical chip.
  • the optical waveguide includes an optical waveguide layer and a protective layer that are stacked; the optical waveguide layer is closer to the substrate than the protective layer.
  • the protective layer can be used to protect the optical waveguide layer and prevent the optical waveguide layer from being damaged.
  • the optical waveguide includes an optical waveguide layer.
  • the optical waveguide layer has a thickness ranging from 200 nm to 300 nm; and/or, the protective layer has a thickness ranging from 5 nm to 20 nm.
  • the material of the optical waveguide layer includes one or more of silicon nitride, silicon oxynitride, silicon, germanium, silicon germanium, and indium phosphide; the material of the protective layer includes silicon oxide.
  • materials of the first dielectric layer and the second dielectric layer include silicon oxide.
  • a communication device which includes an optical fiber and the optical chip provided in the second aspect above; wherein, the tip of the optical waveguide in the optical chip is coupled to the optical fiber. Since the communication device provided by the third aspect has the same technical effect as the optical chip provided by the second aspect above, reference may be made to the description of the second aspect above, and details are not repeated here.
  • FIG. 1 is a schematic structural diagram of a communication device
  • FIG. 2 is a schematic top view structural diagram of a communication device provided by an embodiment of the present application.
  • Fig. 3a is a schematic top view structural diagram of an optical waveguide body provided by the related art
  • Fig. 3b is a schematic top view structure diagram of an optical waveguide body and a photoresist layer provided by the related art
  • Fig. 3c is a schematic top view structural diagram of an optical waveguide provided by the related art.
  • Fig. 4 is a schematic top view structural diagram of another optical waveguide body provided by the related art.
  • FIG. 5 is a first schematic cross-sectional structure diagram of an optical chip provided by an embodiment of the present application.
  • FIG. 6 is a flow chart of a method for preparing an optical chip provided by an embodiment of the present application.
  • Fig. 7 is a schematic cross-sectional structure diagram 1 in the process of manufacturing an optical chip provided by an embodiment of the present application;
  • Fig. 8 is a schematic cross-sectional structure diagram II in the process of manufacturing an optical chip provided by an embodiment of the present application.
  • Fig. 9 is a schematic cross-sectional structure diagram III in the process of manufacturing an optical chip provided by an embodiment of the present application.
  • FIG. 10 is a schematic diagram of a cross-sectional structure during the process of manufacturing an optical chip provided by an embodiment of the present application.
  • Fig. 11 is a schematic top view structural diagram of an optical waveguide body provided by an embodiment of the present application.
  • Fig. 12 is a schematic cross-sectional structure diagram 5 in the process of manufacturing an optical chip provided by the embodiment of the present application;
  • Fig. 13 is a schematic diagram of a cross-sectional structure during the process of manufacturing an optical chip provided by an embodiment of the present application;
  • Fig. 14 is a schematic diagram of a cross-sectional structure in the process of manufacturing an optical chip provided by an embodiment of the present application VII;
  • Fig. 15 is a schematic cross-sectional structure eighth in the process of manufacturing an optical chip provided by the embodiment of the present application.
  • Fig. 16 is a schematic top view of a sacrificial layer, an auxiliary pattern and an optical waveguide body provided by an embodiment of the present application;
  • FIG. 17 is a schematic top view of a process of manufacturing an optical chip provided by an embodiment of the present application.
  • Fig. 18 is a schematic cross-sectional structure diagram 9 in the process of manufacturing an optical chip provided by the embodiment of the present application.
  • Fig. 19 is a schematic cross-sectional structure diagram 10 in the process of manufacturing an optical chip provided by an embodiment of the present application.
  • Fig. 20 is a schematic cross-sectional structure eleventh in the process of manufacturing an optical chip provided by the embodiment of the present application.
  • Fig. 21 is a schematic top view of another process of manufacturing an optical chip provided by the embodiment of the present application.
  • Fig. 22 is a schematic cross-sectional structure diagram twelve in the process of manufacturing an optical chip provided by the embodiment of the present application.
  • Fig. 23 is a schematic cross-sectional structure schematic diagram of a process of manufacturing an optical chip provided by an embodiment of the present application.
  • Fig. 24 is a schematic cross-sectional structure schematic diagram of a process of manufacturing an optical chip provided by an embodiment of the present application.
  • Fig. 25 is a schematic cross-sectional structure fifteenth in the process of manufacturing an optical chip provided by the embodiment of the present application.
  • Fig. 26 is a sixteenth schematic cross-sectional structure diagram in the process of manufacturing an optical chip provided by the embodiment of the present application.
  • Fig. 27 is a schematic top view of an optical waveguide provided by an embodiment of the present application.
  • Fig. 28 is a schematic structural diagram of an optical chip provided by another embodiment of the present application.
  • Fig. 29 is a schematic top view of an optical chip provided by another embodiment of the present application.
  • FIG. 30 is a second schematic cross-sectional structure diagram of an optical chip provided by an embodiment of the present application.
  • Fig. 31 is a schematic diagram of the cross-sectional structure of an optical chip provided by the embodiment of the present application III;
  • Fig. 32 is a schematic top view structural diagram of an optical waveguide provided by another embodiment of the present application.
  • Fig. 33 is a schematic diagram 4 of a cross-sectional structure of an optical chip provided by an embodiment of the present application.
  • Fig. 34 is a schematic cross-sectional structure diagram five of an optical chip provided by the embodiment of the present application.
  • Fig. 35 is a schematic top view of an optical waveguide body provided by another embodiment of the present application.
  • Fig. 36 is a schematic cross-sectional structure schematic diagram during the process of fabricating an optical chip provided by another embodiment of the present application 17;
  • Fig. 37 is a schematic top view of a sacrificial layer and an optical waveguide body provided by an embodiment of the present application;
  • Fig. 38 is a schematic structural diagram of an optical chip provided by another embodiment of the present application.
  • Fig. 39 is a schematic top view structural diagram of an optical chip provided in the related art.
  • first”, second, etc. are used for convenience of description only, and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features.
  • a feature defined as “first”, “second”, etc. may expressly or implicitly include one or more of that feature.
  • plural means two or more.
  • Coupled may mean direct coupling or indirect coupling through an intermediary.
  • directional indications such as up, down, left, right, front and rear, etc. used to explain the structure and movement of various components in this application are relative. These indications are pertinent when the parts are in the positions shown in the figures. However, should the description of component locations change, these directional indications will change accordingly.
  • Embodiments of the present application provide a communication device, which can be, for example, a mobile phone, a tablet computer (pad), an IP (internet protocol, Internet Protocol) phone, a switch, a router, an optical transceiver (Optical transceiver), laser, etc. any communication equipment that uses light waves as the carrier, uses optical fiber as the transmission medium, and uses light to transmit information through photoelectric conversion.
  • a communication device can be, for example, a mobile phone, a tablet computer (pad), an IP (internet protocol, Internet Protocol) phone, a switch, a router, an optical transceiver (Optical transceiver), laser, etc. any communication equipment that uses light waves as the carrier, uses optical fiber as the transmission medium, and uses light to transmit information through photoelectric conversion.
  • the embodiment of the present application does not specifically limit the specific form of the communication equipment.
  • FIG. 2 exemplarily provides a structural diagram of a communication device.
  • the communication device 1 includes a circuit board 30 and a first optical chip 10a, a second optical chip 10b and an optical fiber 20 disposed on the circuit board 30 , both ends of the optical fiber 20 are respectively coupled to the first optical chip 10a and the second optical chip 10b.
  • the optical fiber 20 may be, for example, a single-mode optical fiber.
  • the structure shown in the embodiment of the present application does not constitute a specific limitation on the foregoing communication device.
  • the above-mentioned communication device may include more or fewer components than shown in the figure, or combine certain components, or separate certain components, or arrange different components.
  • the illustrated components can be realized in hardware, software or a combination of software and hardware.
  • the working process of the above-mentioned communication device 1 is as follows: first, the first optical chip 10a converts the electrical signal into an optical signal, and then couples the optical signal to the optical fiber 20, and then transmits the optical signal through the optical fiber 20, and couples the optical signal to the second In the chip 10b, the second chip 10b receives the optical signal and converts the optical signal into an electrical signal, thereby realizing the transmission of information between the first optical chip 10a and the second chip 10b.
  • the transmission of optical signals between the first optical chip 10a and the optical fiber 20 can be realized in the following two ways.
  • the first way it can be set in the first optical chip 10a
  • a lens-type lightwave cable, or a grating coupler (grating coupler) is coupled to the optical fiber 20 through the lens-type lightwave cable or the grating coupler, so as to realize the transmission of optical signals between the first optical chip 10a and the optical fiber 20 .
  • the lens-type lightwave cable is very expensive, when the grating coupler is coupled with the optical fiber 20, the coupling efficiency is sensitive to the wavelength, and it is difficult to support the wide spectrum of the high-bandwidth coarse wavelength division multiplexer and the C-band wavelength division multiplexer. Therefore, the application of the lens-type optical cable and the grating coupler in the first optical chip 10a is limited.
  • an optical waveguide may be provided in the first optical chip 10a, one end of the optical waveguide is coupled to the optical fiber 20, and the optical signal is transmitted between the first optical chip and the optical fiber 20 through the optical waveguide. Since the above-mentioned first method is expensive, the coupling efficiency is sensitive to wavelength, and the application range is narrow, etc., the second method is often used to realize the transmission of optical signals between the first optical chip 10 a and the optical fiber 20 .
  • the optical signal needs to be coupled between the first optical chip 10a and the optical fiber 20 and between the second optical chip 10b and the optical fiber 20, and the optical waveguide is to realize the optical signal in the optical chip.
  • the key component of the optical fiber 20 coupling plays a vital role in the integrated optical circuit. Because the optical signal will produce coupling loss when it is coupled between the optical waveguide of the first optical chip 10a and the optical fiber 20, or between the optical waveguide of the second optical chip 10b and the optical fiber 20, thereby causing the quality of the optical signal to degrade, therefore Reducing the coupling loss between the optical waveguide and the optical fiber 20 is a matter of great concern to the communication device 1 at present.
  • the optical field mode spot is larger, thus it is more favorable for the optical mode field of the optical waveguide to match the optical mode field of the optical fiber 20, thereby reducing the coupling loss and port Reflection improves the coupling efficiency, so it is possible to make an optical waveguide whose width gradually decreases and has a smaller tip, i.e. a taper optical waveguide, and the smaller end of the line width is coupled with the optical fiber 20, i.e. in the optical chip 10
  • the tip of the optical waveguide is coupled with the optical fiber 20 to reduce the coupling loss between the optical waveguide and the optical fiber 20 .
  • an optical waveguide layer is first formed on a substrate, and then the optical waveguide layer is etched to form an optical waveguide.
  • the minimum line width of the lithographic equipment when the size of the end of the optical waveguide close to the optical fiber 20 is less than 100 nm, it is difficult for the lithographic equipment to achieve; on the other hand, Even with high-cost, advanced ultraviolet (ultraviolet, UV) lithography or electron beam lithography (EBL), photoresist with a line width of less than 100nm can be photolithographically developed, but in the optical waveguide
  • the thickness of the optical waveguide layer is relatively large, usually 220nm or thicker, when the optical waveguide layer is etched, the tip of the optical waveguide is often easily broken or damaged, resulting in difficulties in actual process production. .
  • the related technology provides a preparation method of a wedge-shaped optical waveguide, as shown in Figure 3a, first on the substrate An optical waveguide body 1010 with a wider tip is etched out, and the width H of the optical waveguide body 1010 can be greater than 100nm; next, a photoresist film is formed on the optical waveguide body 1010, and the photoresist film is formed after exposure and development.
  • the photoresist layer 1000 shown in Figure 3b the photoresist layer 1000 includes a rectangular hollow area 1000a, the projection of the hollow area 1000a on the optical waveguide body 1010 has an overlapping area with the optical waveguide body 1010, and the overlapping area includes The part where the length direction X of the body 1010 gradually decreases; next, as shown in FIG. etch away.
  • the etched portion 1010a of the optical waveguide body 1010 includes a tip that gradually decreases along the length direction X of the optical waveguide body 1010
  • the unetched portion of the optical waveguide body 1010 that is, the formed optical waveguide 101 also includes The tip gradually decreases along the length direction X of the optical waveguide body 1010 , so that an optical waveguide 101 with a tip width H lower than 100 nm can be obtained, that is, a wedge-shaped optical waveguide 101 can be obtained.
  • the optical waveguide body 1010 is etched In the process, because the step will scatter the plasma, the damage to the optical waveguide body 1010 located at the inclined plane will be aggravated during etching. (plasma) and plasma micro loading effect (plasma micro loading), the tip area is easy to cut off, and there will be irregular gaps at the edge of the etching, that is, the mouse bite phenomenon, as shown in Figure 4 shown in area A.
  • an embodiment of the present application provides an optical chip 10 and a manufacturing method thereof.
  • the optical chip 10 includes an optical waveguide 101, and the optical chip 10
  • the preparation method includes the preparation method of the optical waveguide 101.
  • the optical chip 10 provided in the embodiment of the present application can be applied to the above-mentioned communication device 1 .
  • the optical chip 10 provided in the present application and its preparation method are exemplarily introduced below through several specific embodiments.
  • Embodiment 1 provides an optical chip 10.
  • the optical chip 10 mainly includes a substrate 100, a first dielectric layer 107, an optical waveguide 101, and a second dielectric layer 108;
  • the first dielectric layer 107 includes a first through hole 109 ; the first through hole 109 is filled with the optical waveguide 101 and the second dielectric layer 108 .
  • the projection of the optical waveguide 101 on the substrate 100 is strip-shaped, the optical waveguide 101 includes a first sub-optical waveguide 101a, and the width of at least part of the projection of the first sub-optical waveguide 101a on the substrate 100 gradually decreases, that is At least part of the shape of the optical waveguide 101 is wedge-shaped; the optical waveguide 101 is in contact with the side wall of the first through hole 109 and the side of the second dielectric layer 108, and the other side of the second dielectric layer 108 is also in contact with the first through hole 109. contact with the other side wall.
  • the optical chip 10 further includes a third dielectric layer 110 disposed on a side of the first dielectric layer 107 away from the substrate 100 ; the third dielectric layer 110 includes a second through hole 111 .
  • the second through hole 111 is filled with the second dielectric layer 108 .
  • the width of at least part of the projection of the first sub-optical waveguide 101a on the substrate 100 gradually decreases, and it may be that the width of the projection of the first sub-optical waveguide 101a on the substrate 100 gradually decreases, or it may be that the width of the first sub-optical waveguide 101a gradually decreases.
  • the width of the projected portion of a sub-optical waveguide 101a on the substrate 100 gradually decreases. That is to say, at least part of the optical waveguide 101 is wedge-shaped, and the overall shape of the optical waveguide 101 may be wedge-shaped; or a part of the optical waveguide 101 may be wedge-shaped.
  • the second dielectric layer 108 includes a surface close to the substrate 100 (ie, the lower surface of the second dielectric layer 108 in FIG. 5 ), a surface away from the substrate 100 (ie, the upper surface of the second dielectric layer 108 in FIG. surface) and sides.
  • preparing the optical chip 10 shown in FIG. 5 may include steps S10 - S19 : S10 , as shown in FIG. 7 , forming a strip-shaped optical waveguide body 1010 on the substrate 100 .
  • the number of optical waveguide bodies 1010 formed on the substrate 100 is not limited, and may be one or more.
  • FIG. 7 illustrates the formation of an optical waveguide body 1010 on a substrate 100 as an example.
  • step S10 may include:
  • the base plate 11 includes a substrate 100 and an optical waveguide layer 1011 that are stacked.
  • the substrate 100 includes a first sub-substrate 1001 and a second sub-substrate 1002 that are stacked, and the second sub-substrate 1002 is closer to the optical waveguide layer 1011 than the first sub-substrate 1001 .
  • the material of the first sub-substrate 1001 may include, for example, silicon nitride (SiNx), silicon oxynitride (SiOxNy), silicon (Si), germanium (Ge), silicon germanium (SixGey), indium phosphide (InP) one or more of.
  • the material of the above-mentioned second sub-substrate 1002 may include, for example, silicon oxide (SiOx), and the silicon oxide may be, for example, silicon dioxide (SiO2).
  • the material of the optical waveguide layer 1011 may include, for example, one or more of silicon nitride, silicon oxynitride, silicon, germanium, silicon germanium, and indium phosphide.
  • the material of the first subsubstrate 1001 is silicon
  • the material of the second subsubstrate 1002 is silicon oxide
  • the silicon oxide can be silicon dioxide, for example
  • the material of the optical waveguide layer 1011 is silicon.
  • the bottom plate 11 may be called a silicon wafer (silicon on insulator wafer, SOI wafer).
  • the thickness of the first sub-substrate 1001 may range from 500 ⁇ m to 725 ⁇ m.
  • the thickness of the first sub-substrate 1001 may be 500 ⁇ m, 600 ⁇ m, 700 ⁇ m or 725 ⁇ m and so on.
  • the thickness of the second sub-substrate 1002 may range from 2 ⁇ m to 3 ⁇ m.
  • the thickness of the second sub-substrate 1002 may be 2 ⁇ m, 2.5 ⁇ m or 3 ⁇ m and so on.
  • the thickness of the optical waveguide layer 1011 may range from 200 nm to 300 nm.
  • the thickness of the optical waveguide layer 1011 may be 200 nm, 250 nm or 300 nm and so on.
  • step S101 is an optional step, for example, in some examples, step S101 may be omitted.
  • the material of the protection layer 1012 may include, for example, silicon oxide, and the silicon oxide may be, for example, silicon dioxide.
  • step S101 can be implemented in the following two ways: first, thermal oxidation treatment can be performed on the surface of the optical waveguide layer 1011 away from the substrate 100 to form the protective layer 1012 .
  • thermal oxidation treatment may be performed on the surface of the optical waveguide layer 1011 away from the substrate 100 to obtain the protection layer 1012, and the material of the protection layer 1012 is silicon oxide.
  • the protective layer 1012 may be directly formed on the base plate 11 .
  • the protective layer 1012 can be formed by chemical vapor deposition (chemical vapor deposition, CVD), sputtering and other methods.
  • the protective layer 1012 has a thickness ranging from 5 nm to 20 nm.
  • the thickness of the protection layer 1012 can be, for example, 5 nm, 10 nm, 15 nm or 20 nm.
  • step S102 forming a barrier layer 1013 on the protection layer 1012 .
  • step S102 is an optional step, for example, in some examples, step S102 may be omitted.
  • the barrier layer 1013 can be formed on the protective layer 1012 by chemical vapor deposition, sputtering, and other methods.
  • the material of the barrier layer 1013 may be, for example, silicon nitride.
  • the thickness range of the barrier layer 1013 may be, for example, 20 nm ⁇ 100 nm.
  • the thickness of the barrier layer 1013 can be, for example, 20 nm, 40 nm, 60 nm, 80 nm or 100 nm.
  • step S10 includes step S101 and step S102
  • the optical waveguide body 1010 includes an optical waveguide layer 1011, a protective layer 1012, and a barrier layer 1013 that are sequentially stacked, and the optical waveguide layer 1011 is closer to the barrier layer 1013.
  • Substrate 100 When step S101 is omitted in step S10 , the optical waveguide body 1010 includes an optical waveguide layer 1011 and a barrier layer 1013 stacked in sequence, and the optical waveguide layer 1011 is closer to the substrate 100 than the barrier layer 1013 .
  • the optical waveguide body 1010 includes an optical waveguide layer 1011 and a protective layer 1012 stacked in sequence, and the optical waveguide layer 1011 is closer to the substrate 100 than the protective layer 1012 .
  • the protective layer 1012 can be used to protect the optical waveguide layer 1011 .
  • the patterning of the above-mentioned optical waveguide layer 1011 , protective layer 1012 and barrier layer 1013 includes processes such as coating photoresist, mask exposure, development and etching.
  • the projected shape of the optical waveguide body 1010 on the substrate 100 is a rectangle.
  • the projected shape of the optical waveguide body 1010 on the substrate 100 is a rectangle, since the optical waveguide body 1010 does not have a sharp point, the difficulty of manufacturing the optical waveguide body 1010 can be reduced in the process of etching the optical waveguide body 1010, and the light The waveguide body 1010 is not easy to break.
  • the width of the rectangle may be greater than 90 nm, for example, the width of the rectangle may be 90 nm or 100 nm.
  • the width of the rectangle is greater than 90 nm, the difficulty of manufacturing the optical waveguide body 1010 can be further reduced during the process of etching the optical waveguide body 1010 , and the requirements for photolithography equipment can be reduced.
  • the above-mentioned optical waveguide body 1010 includes a first sub-optical waveguide 101 a and a second sub-optical waveguide 101 b in contact with each other; at least part of the first sub-optical waveguide 101 a is away from the second sub-optical waveguide The direction width of 101b gradually decreases.
  • the above-mentioned optical waveguide body 1010 further includes a third sub-optical waveguide 101c disposed on the side of the first sub-optical waveguide 101a away from the second sub-optical waveguide 101b and in contact with the first sub-optical waveguide 101a.
  • the optical waveguide body 1010 includes the first sub-optical waveguide 101a and the third sub-optical waveguide 101c that are in contact with each other, the first sub-optical waveguide 101a and the third sub-optical waveguide 101c form a complementary pattern, and the first sub-optical waveguide 101a and the third sub-optical waveguide 101c form a complementary pattern, and the first The width of at least part of the sub-optical waveguide 101a gradually decreases along the direction away from the second sub-optical waveguide 101b, that is, the width of at least part of the first sub-optical waveguide 101a gradually decreases along the direction close to the third sub-optical waveguide 101c.
  • the third sub-optical waveguide 101c When the waveguide body 1010 is rectangular, at least part of the third sub-optical waveguide 101c also gradually decreases in width along the direction approaching the first sub-optical waveguide 101a, that is, the first sub-optical waveguide 101a and the third sub-optical waveguide 101c are both Including tip area.
  • the first sub-optical waveguide 101a gradually decreases in width along the direction approaching the third sub-optical waveguide 101c.
  • the directional width of the waveguide 101c is not limited, and the width may gradually decrease or gradually increase; of course, the width may also be the same.
  • the material of the first dielectric film 103 may include, for example, silicon oxide, and the silicon oxide may be, for example, silicon dioxide.
  • the first dielectric thin film 103 can be formed by chemical vapor deposition, sputtering and other methods. In some examples, the thickness of the first dielectric film 103 is greater than or equal to the thickness of the optical waveguide body 1010 .
  • the first dielectric film 103 is polished to form the first dielectric layer 107 , and the surface of the optical waveguide body 1010 away from the substrate 100 is exposed to the first dielectric layer 107 to form the first dielectric layer 107
  • the optical waveguide body 1010 is located in the first through hole 109 .
  • the shape of the projection of the optical waveguide body 1010 on the substrate 100 is the same as that of the first through hole 109 on the substrate 100 .
  • the projection of the first through hole 109 on the substrate 100 is also a rectangle.
  • the first dielectric thin film 103 may be smoothed by using a chemical mechanical polishing (CMP) process.
  • the optical waveguide body 1010 when the optical waveguide body 1010 includes the barrier layer 1013, when the first dielectric film 103 is polished, after the first dielectric film 103 above the barrier layer 1013 in the optical waveguide body 1010 is polished , that is, when polishing to the barrier layer 1013 of the optical waveguide body 1010, since the optical waveguide body 1010 includes the barrier layer 1013, the hardness of the barrier layer 1013 is generally relatively large (for example, the material of the barrier layer 1013 is silicon nitride, and the hardness of silicon nitride is relatively high. large), so the barrier layer 1013 can force the grinding to stop when the barrier layer 1013 is polished, so as to prevent the protective layer 1012 and the optical waveguide layer 1011 from being damaged during the grinding process.
  • the thickness of the first dielectric film 103 is greater than or equal to the thickness of the optical waveguide body 1010, as shown in FIG.
  • the surface of 107 away from the substrate 100 is flush with the surface of the optical waveguide body 1010 away from the substrate 100 .
  • step S13 is an optional step, for example, in the case that the above step S10 does not include S102, step S13 can be omitted.
  • the barrier layer 1013 may be removed by a chemical or physical method. In some examples, when the material of the barrier layer 1013 is silicon nitride, the barrier layer 1013 can be removed by using hot phosphoric acid because silicon nitride is etched after encountering hot phosphoric acid.
  • the auxiliary patterns 105 are on the optical waveguide body 1010
  • the projection of and the optical waveguide body 1010 have no overlapping area.
  • the projection of the sacrificial layer 104 on the optical waveguide body 1010 covers the first sub-optical waveguide 101 a in the optical waveguide body 1010 , and does not cover the second sub-optical waveguides 101 b and 101 b in the optical waveguide body 1010 .
  • the third sub-optical waveguide 101c at least part of the first sub-optical waveguide 101a gradually decreases in width along a direction approaching the third sub-optical waveguide 101c.
  • step S14 may include, for example: S140, as shown in FIG. 18 , forming a sacrificial film 1040 on the first dielectric film 103 .
  • the sacrificial thin film 1040 can be formed by chemical vapor deposition, sputtering and other methods.
  • the size of the sacrificial layer 104 can be set larger, and the shape of the sacrificial layer 104 should be able to cover the first sub-optical waveguide 101 a and be convenient for patterning.
  • the projected shape of the sacrificial layer 104 on the substrate 100 may be a trapezoid, a rectangle, a polygon, a circle, other regular or irregular shapes, and the like.
  • the sacrificial layer 104 is trapezoidal as an example.
  • the size of the auxiliary pattern 105 may be set larger, and the size of the auxiliary pattern 105 shall prevail.
  • the shape of the projection of the auxiliary pattern 105 on the substrate 100 is, for example, a trapezoid, a rectangle, a polygon, a circle, other regular or irregular shapes, and the like.
  • the shape of the auxiliary pattern 105 is a rectangle as an example.
  • auxiliary patterns 105 may be formed.
  • the auxiliary patterns 105 may be disposed between two adjacent optical waveguide bodies 1010 .
  • the shapes of the plurality of auxiliary patterns 105 may be the same or may not be completely the same.
  • the material of the sacrificial layer 104 and the auxiliary pattern 105 may include one of polysilicon (polysilicon, P-Si), amorphous silicon (amorphous-Si, a-Si), silicon nitride, and silicon oxynitride or more.
  • the sacrificial layer 104 and the auxiliary pattern 105 can be formed while forming the polysilicon layer or the amorphous silicon layer in the MOS tube, that is to say, the sacrificial layer 104
  • the auxiliary pattern 105 can be compatible with the existing process, for example, the SOI (silicon-on-insulator, silicon on the insulating layer) process compatible with the existing multilayer grating (ploy grating) structure, so the present embodiment one is in making optical Adding the sacrificial layer 104 and the auxiliary pattern 105 in the process of the chip 10 will not increase the process cost, and the product flexibility is high.
  • step S15 is an optional step, for example, in some examples, step S15 may be omitted.
  • the material of the second dielectric film 106 can be, for example, silicon oxide, and the silicon oxide can be, for example, silicon dioxide.
  • the material of the first dielectric film 103 and the material of the second dielectric film 106 may be the same or different.
  • the method for forming the second dielectric thin film 106 can refer to step S11, which will not be repeated here.
  • the third dielectric layer 110 includes second through holes 111 .
  • the sacrificial layer 104 and the third sub-optical waveguide 101c are exposed in the second through hole 111, that is, the projection of the second through hole 111 on the substrate 100 covers the sacrificial layer 104 and the third sub-optical waveguide 101c on the substrate. Projection on base 100. As shown in FIG. 21 , the sacrificial layer 104 and the third sub-optical waveguide 101c are exposed in the second through hole 111, that is, the projection of the second through hole 111 on the substrate 100 covers the sacrificial layer 104 and the third sub-optical waveguide 101c on the substrate. Projection on base 100. As shown in FIG.
  • the third dielectric layer 110 further includes a third through hole 114, the auxiliary pattern 105 is exposed in the third through hole 114, and the projection of the third through hole 114 on the substrate 100 is the same as that of the optical waveguide body 1010 on the substrate. Projections on 100 have no overlapping regions.
  • the projection of the second through hole 111 on the substrate 100 also covers the projection of part of the first dielectric layer 107 on the substrate 100 . It should be noted that since the projection of the sacrificial layer 104 on the optical waveguide body 1010 covers the first sub-optical waveguide 101a, the projection of the second through hole 111 on the substrate 100 covers the first sub-optical waveguide 101a and the third sub-optical waveguide 101a. Projection of the waveguide 101c on the substrate 100. It should be noted that the material of the third dielectric layer 110 and the material of the first dielectric layer 107 may be the same or different.
  • step S16 may include, for example: S160, as shown in FIG. 22 , forming an anti-reflection coating (bottom anti reflection coating, BARC) 112 on the second dielectric film 106 .
  • BARC bottom anti reflection coating
  • step S161 forming a photoresist film 113 on the antireflection coating 112 .
  • S162 perform a photolithography process (such as mask exposure, development, etc.) on the anti-reflection coating 112 and the photoresist film 113 to form a hollow area.
  • S163 as shown in FIG. 25 , etching the second dielectric film 106 to form a third dielectric layer 110 .
  • S164 as shown in FIG. 20 , removing the anti-reflection coating 112 and the photoresist film 113 .
  • step S16 may also be referred to as performing a window opening process on the second dielectric film 106 .
  • step S16 is an optional step, and step S16 may be omitted if the method for manufacturing the optical chip 10 does not include step S15. It should be noted that the performance difference between the material of the second dielectric film 106 and the material of the sacrificial layer 104 can be selected so that the sacrificial layer 104 will not be etched when the second dielectric film 106 is etched in step S16 .
  • step S17 removing the protective layer 1012 on the third sub-optical waveguide 101c to expose the surface of the third sub-optical waveguide 101c away from the substrate 100 .
  • step S17 is an optional step, for example, when step S10 does not include step S101 , that is, when step S10 does not include the step of forming the protective layer 1012 , step S17 can be omitted.
  • step S16 and step S17 can be performed at the same time, that is, when the second dielectric film 106 is etched, the protective layer 1012 on the third sub-optical waveguide 101c is etched away.
  • step S16 may also be performed first, and then step S17 is performed, that is, after the second dielectric film 106 is etched, the protective layer 1012 on the third sub-optical waveguide 101c is etched away to expose the third sub-optical waveguide 101c.
  • the waveguide 101c is remote from the surface of the substrate 100 .
  • the optical waveguide 101 includes a first optical waveguide 101a and a second optical waveguide 101b.
  • step S14 forms the auxiliary pattern 105 while forming the sacrificial layer 104
  • the material of the auxiliary pattern 105 is the same as that of the sacrificial layer 104, so in step S18, when the sacrificial layer 104 is etched, the auxiliary pattern 105 is also etched.
  • the auxiliary pattern 105 can consume the energy generated by the plasma during etching of the area other than the sacrificial layer 104, the area of etching can be increased, so that the etching can be greatly improved.
  • the microscopic load effect of the plasma during etching, the etching process has good stability and large tolerance.
  • the thickness of the sacrificial layer 104 and the third sub-optical waveguide 101c can be adjusted according to the etching rate of the sacrificial layer 104 and the third sub-optical waveguide 101c, So that when the sacrificial layer 104 is etched, the third sub-optical waveguide 101c is just completely etched away.
  • the sacrificial layer 104 covers the first sub-optical waveguide 101a
  • the second dielectric layer 108 covers the second sub-optical waveguide 101b
  • the sacrificed The first sub-optical waveguide 101a covered by the layer 104 and the second sub-optical waveguide 101b covered by the second dielectric layer 108 will remain, and the third sub-optical waveguide 101c will be etched away to form the above-mentioned optical waveguide 101 .
  • the optical waveguide body 1010 is filled in the first through hole 109 of the first dielectric layer 107, after removing the third sub-optical waveguide 101c in the optical waveguide body 1010, part of the area in the first through hole 109 is not filled.
  • the formed optical waveguide 101 since at least part of the first sub-optical waveguide 101a gradually decreases in width along the direction approaching the third sub-optical waveguide 101c, the formed optical waveguide 101 includes a portion whose width gradually decreases, that is, At least part of the formed optical waveguide 101 is wedge-shaped, that is to say the formed optical waveguide 101 comprises a pointed end.
  • FIG. 28 schematically shows a wedge-shaped optical waveguide 101 formed on a substrate 100 .
  • FIG. 28 takes forming a wedge-shaped optical waveguide 101 on the substrate 100 as an example.
  • multiple optical waveguides 101 may also be formed on the substrate 100 at the same time.
  • the projection of the third through hole 114 on the substrate 100 has no overlapping area with the projection of the optical waveguide body 1010 on the substrate 100 , the projection of the third through hole 114 on the substrate 100 is different from the final formed The projection of the optical waveguide 101 on the substrate 100 has no overlapping area.
  • the finally formed optical waveguide 101 includes the optical waveguide layer 1011 and the protective layer 1012 that are stacked, that is, the first sub-optical
  • the waveguide 101a and the second sub-optical waveguide 101b include an optical waveguide layer 1011 and a protective layer 1012 that are stacked, and the optical waveguide layer 1011 is closer to the substrate 100 than the protective layer 1012 .
  • the finally formed optical waveguide 101 includes only the optical waveguide layer 1011 and does not include the protective layer 1012, that is, the first sub-optical waveguide 101a and the second sub-optical waveguide 101b include only The optical waveguide layer 1011 is included, and the protective layer 1012 is not included.
  • S19 form the second dielectric layer 108 in the first through hole 109, the second through hole 111 and the third through hole 114, that is, the first through hole 109, the second through hole 111 and the The third through holes 114 are filled with the second dielectric layer 108 .
  • the optical waveguide 101 is in contact with both the side wall of the first through hole 109 and the side of the second dielectric layer 108
  • the other side of the second dielectric layer 108 is in contact with the other side wall of the first through hole 109 .
  • the third through hole 114 is not shown in FIG. 30 and FIG. 31 .
  • the second dielectric layer 108 is only filled in the first through hole 109, the second through hole 111 and the third through hole 114.
  • the second dielectric layer 108 is formed, and then the second dielectric layer 108 is ground, so that the surface of the second dielectric layer 108 away from the substrate 100 is flush with the surface of the third dielectric layer 110 away from the substrate 100 .
  • the second dielectric layer 108 is filled in the first through hole 109 , the second through hole 111 and the third through hole 114 , and is also formed on the third dielectric layer 110 away from the substrate. 100 on one side.
  • the second through hole 111 on the substrate 100 covers the third sub-optical waveguide 101c, and the second dielectric layer 108 is filled in the position where the third sub-optical waveguide 101c is removed in the first through hole 109, the second The projection of the through hole 111 on the substrate 100 covers the second dielectric layer 108 inside the first through hole 109 .
  • the material of the second dielectric layer 108 and the material of the first dielectric layer 107 may be the same or different.
  • the material of the second dielectric layer 108 and the material of the third dielectric layer 110 may be the same or different.
  • the third sub-optical waveguide 101c in the optical waveguide body 1010 is etched away, and the light
  • the first sub-optical waveguide 101 a and the second sub-optical waveguide 101 b in the waveguide body 1010 remain as the optical waveguide 101 .
  • the formed optical waveguide 101 includes a portion whose width gradually decreases, that is, the shape of at least part of the formed optical waveguide 101 is wedge-shaped, that is, the formed optical waveguide 101 includes a tip.
  • the first sub-optical waveguide 101a and the third sub-optical waveguide 101c form a complementary figure, such as a rectangle, and at least part of the first sub-optical waveguide 101a gradually decreases in width along the direction approaching the third sub-optical waveguide 101c, so that at least part of the third sub-optical waveguide 101c approaches the first sub-optical waveguide 101c
  • the directional width of the waveguide 101a is also gradually reduced, that is, both the first sub-optical waveguide 101a and the third sub-optical waveguide 101c include tip regions.
  • the tip region of the optical waveguide body 1010 that needs to be etched (that is, the third sub-optical waveguide 101c region) is supplemented with a region without sharp corners, so when the sacrificial layer 104 and the third sub-optical waveguide 101c are etched at the same time, no sharp corner region exists in the etched part and the unetched part, thus First, there will be no residue in the unetched part, and there will be no risk of cutting or rattooth phenomenon in the etched part, that is, the third sub-optical waveguide 101c that needs to be removed will be completely
  • the optical waveguide body 1010 includes the first sub-optical waveguide 101a, the second sub-optical waveguide 101b, and the third sub-optical waveguide 101c, and the finally formed optical waveguide 101 includes the first sub-optical waveguide 101a and the second sub-optical waveguide 101a.
  • the waveguide 101b will be described as an example.
  • the optical waveguide body 1010 includes the first sub-optical waveguide 101a and the third sub-optical waveguide 101c, but does not include the second sub-optical waveguide 101b, so that the structure of the finally prepared optical waveguide 101 is shown in FIG. 32, only The first sub-optical waveguide 101a is included, and the second sub-optical waveguide 101b is not included.
  • step S19 includes: forming a second dielectric layer 108 in the first through hole 109 .
  • the structure of the prepared optical chip 10 is shown in FIG. 33 .
  • the finally prepared optical chip 10 is shown in FIG. 34, and it can be seen from FIG.
  • the optical waveguide layer 1011 does not include the protective layer 1012 .
  • the difference between the preparation method of the optical chip 10 provided in the second embodiment and the first embodiment is that in the first embodiment, the sacrificial layer 104 and the third sub-optical waveguide 101c are etched in step S18, and the sacrificial layer 104 and the third sub-waveguide 101c are removed.
  • the sub-optical waveguide 101c forms the optical waveguide 101.
  • the first sub-optical waveguide 101a located below the sacrificial layer is also etched simultaneously. part.
  • Embodiment 1 does not limit the width of the first sub-optical waveguide 101a along the direction away from the third sub-optical waveguide 101c, for example, the width may gradually decrease or the width may gradually increase; of course, the width may also be the same, and
  • the width of the second sub-optical waveguide 101b along the direction approaching the first sub-optical waveguide 101a is not limited, for example, the width may gradually decrease or the width may gradually increase; of course, the width may also be the same. In the second embodiment, however, as shown in FIG.
  • At least another part of the first sub-optical waveguide 101a gradually decreases in width along the direction away from the third sub-optical waveguide 101c, that is, at least part of the first sub-optical waveguide 101a approaches
  • the directional width of the second sub-optical waveguide 101b gradually decreases, and at least part of the second sub-optical waveguide 101b gradually decreases in width along the direction approaching the first sub-optical waveguide 101a.
  • the width of the first sub-optical waveguide 101a gradually decreases along the direction of approaching the second sub-optical waveguide 101b and the direction away from the second sub-optical waveguide 101b.
  • Embodiment 2 provides a method for preparing an optical chip 10.
  • Step S20 includes:
  • the optical waveguide 101 includes a first sub-optical waveguide 101a and a second sub-optical waveguide 101b that are in contact with each other.
  • the thickness of the first sub-optical waveguide 101a in the finally formed optical waveguide 101 is smaller than the thickness of the second sub-optical waveguide 101b.
  • the sacrificial layer 104 and the third sub-optical waveguide 101c can be adjusted according to the etching rate of the sacrificial layer 104 and the third sub-optical waveguide 101c thickness, so that the sacrificial layer 104 and the part of the first sub-optical waveguide 101a below the sacrificial layer 104 are simultaneously etched away when the third sub-optical waveguide 101c is etched.
  • the thicknesses of the sacrificial layer 104 and the third sub-optical waveguide 101c can also be adjusted according to the thickness of the part of the first sub-optical waveguide 101a that needs to be etched away.
  • the material of the sacrificial layer 104 and the protective layer 1012 in the third sub-optical waveguide 101c is silicon dioxide
  • the material of the optical waveguide layer 1011 in the third sub-optical waveguide 101c is silicon
  • the The thickness of the sacrificial layer 104 and the third sub-optical waveguide 101c is designed according to the etching selectivity ratio of silicon dioxide, so that when the sacrificial layer 104 and the third sub-optical waveguide 101c are etched, the first sub-optical waveguide 101c below the sacrificial layer 104 will also be located.
  • Part of the sub-optical waveguide 101a is etched away so that there is a thickness difference between the second sub-optical waveguide 101b and the first sub-optical waveguide 101a, wherein the thickness difference is determined by the thickness difference between the sacrificial layer 104 and the third sub-optical waveguide 101c, And the etching rate of silicon and silicon dioxide is determined.
  • the thicknesses of the first sub-optical waveguide 101a and the second sub-optical waveguide 101b in the finally formed optical waveguide 101 are different, and the second The thickness of the second sub-optical waveguide 101b is greater than the thickness of the first sub-optical waveguide 101a.
  • the difference between the thickness of the second sub-optical waveguide 101b and the thickness of the first sub-optical waveguide 101a ranges from 50 nm to 90 nm.
  • the thickness of the second sub-optical waveguide 101b and the thickness of the first sub-optical waveguide 101a may be 50nm, 60nm, 70nm or 90nm and so on.
  • the difference in the structure of the optical chip 10 prepared in the embodiment 2 and the embodiment 1 is that in the embodiment 1, the first sub-chip in the formed optical waveguide 101
  • the optical waveguide 101a and the second sub-optical waveguide 101b have the same thickness.
  • the thicknesses of the first sub-optical waveguide 101a and the second sub-optical waveguide 101b in the formed optical waveguide 101 are different.
  • Embodiment 1 does not limit the width of the first sub-optical waveguide 101a along the direction away from the third sub-optical waveguide 101c, and the width may gradually decrease or gradually increase; of course, the width may also be the same.
  • at least another part of the first sub-optical waveguide 101a gradually decreases in width along the direction away from the third sub-optical waveguide 101c, that is, in the second embodiment, the first sub-optical waveguide 101a
  • Both the width of the sub-optical waveguide 101b and the direction away from the second sub-optical waveguide 101b gradually decrease.
  • the optical chip 10 provided in the second embodiment only introduces the parts that are different from the first embodiment, and does not introduce the same parts as the first embodiment, and can refer to the first embodiment.
  • the width of the first sub-optical waveguide 101a gradually decreases along the direction close to the second sub-optical waveguide 101b and the direction away from the second sub-optical waveguide 101b, and in the preparation method of the optical chip 10, the sacrificial The projection of the layer 104 on the optical waveguide body 1010 covers the first sub-optical waveguide 101a, so the shape of the projection of the sacrificial layer 104 on the optical waveguide body 1010 includes at least two crossings with the optical waveguide body 1010 as shown in FIG. hypotenuses, hypotenuse a and hypotenuse b.
  • the projected shape of the sacrificial layer 104 on the substrate 100 may be an irregular polygon as shown in FIG. 37 .
  • the finally formed optical waveguide 101 includes the first sub-optical waveguide 101a and the second sub-optical waveguide 101b, and the thickness of the second sub-optical waveguide 101b is greater than the thickness of the first sub-optical waveguide 101a
  • the first The junction of the sub-optical waveguide 101a and the second sub-optical waveguide 101b forms a step, so the optical waveguide 101 formed in the second embodiment includes a step, and the step can divide the optical waveguide 101 into two layers of optical waveguides stacked, as shown in FIG. 38 Shown are the first-layer optical waveguide 101d and the second-layer optical waveguide 101e respectively, and the first-layer optical waveguide 101d is closer to the substrate 100 than the second-layer optical waveguide 101e.
  • the first-layer optical waveguide 101d includes a portion whose width gradually decreases, that is, the first layer At least part of the optical waveguide 101d has a wedge shape.
  • the second The layered optical waveguide 101e includes a portion whose width gradually decreases, that is, at least part of the second layered optical waveguide 101e is wedge-shaped. Based on this, it can be seen that the optical waveguide 101 formed in the second embodiment includes two layers of optical waveguides 101, and the shape of at least part of the two layers of optical waveguides 101 is wedge-shaped, that is, the optical waveguide 101 formed in the second embodiment is double-layered. Layered double miter construction.
  • the optical waveguide 101 formed in the second embodiment includes two-layer optical waveguides, and at least part of the two-layer optical waveguides are wedge-shaped, when the optical chip 10 and the optical fiber 20 are coupled, the optical chip 10 and the optical fiber 20 can be further enlarged.
  • the optical field mode spot at the coupling point 20 can further reduce the coupling loss and port reflection, thereby further improving the coupling efficiency between the optical waveguide 101 and the optical fiber 20, and improving the signal transmission quality.
  • the related art provides an optical chip 10 as shown in FIG.
  • the layered optical waveguide 101d and the second layered optical waveguide 101e the thickness of the first layered optical waveguide 101d is greater than the thickness of the second layered optical waveguide 101e.
  • the sharp corners of the first-layer optical waveguide 101d and the second-layer optical waveguide 101e are easily broken.
  • the sacrificial layer 104, the first sub-optical waveguide 101a and the third sub-optical waveguide 101c located under the sacrificial layer 104 are simultaneously etched, and the tip region of the optical waveguide body 1010 that needs to be etched is made of the sacrificial layer 104.
  • the third sub-optical waveguide 101c (That is, the area where the third sub-optical waveguide 101c is located) is supplemented with an area without a tip, so the third sub-optical waveguide 101c that needs to be removed will be completely removed without residue, and the remaining tip of the first sub-optical waveguide 101a will not There is a risk of being cut off and a rat-tooth phenomenon, so the formed first-layer optical waveguide 101d and second-layer optical waveguide 101e do not have the risk of being cut off.
  • due to the etched part and the unetched part There are no sharp corner areas in some parts, so that the small line width effect can be avoided.
  • the difference between the manufacturing method of the optical chip 10 provided by the third embodiment and the first embodiment is that only the sacrificial layer 104 is formed on the first dielectric layer 107 in the third embodiment, and the auxiliary pattern 105 is not formed.
  • the manufacturing method of the optical chip 10 provided in the third embodiment may refer to the first embodiment above, and step S14 in the first embodiment is replaced with step S30, and step S18 is replaced with step S31.
  • step S30 forming a sacrificial layer 104 on the first dielectric layer 107; as shown in FIG. Three sub-optical waveguides 101c.
  • step S30 includes step S130 and step S131
  • step S131 is replaced by step S132
  • step S132 includes: S132, patterning the sacrificial film 1031 to form a sacrificial layer 104; the projection of the sacrificial layer 104 on the optical waveguide body 1010 covers the first A sub-optical waveguide 101a does not cover the second sub-optical waveguide 101b and the third sub-optical waveguide 101c.
  • the size of the sacrificial layer 104 can be set larger, and the shape of the sacrificial layer 104 should be able to cover the first sub-optical waveguide 101 a and be convenient for patterning.
  • the projected shape of the sacrificial layer 104 on the substrate 100 may be a trapezoid, a rectangle, a polygon, a circle, other regular or irregular shapes, and the like.
  • the sacrificial layer 104 is trapezoidal as an example.
  • Embodiment 3 has the same technical effect as Embodiment 1, and reference may be made to the relevant description of Embodiment 1 above, which will not be repeated here.

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Abstract

本申请的实施例提供一种光芯片及其制备方法、通信设备，涉及光通信技术领域，解决现有的光芯片中光波导在制备过程中尖端易断裂的问题。该光芯片包括衬底和设置在衬底上的第一介质层；第一介质层包括第一通孔；光芯片还包括填充在第一通孔内的光波导和第二介质层；其中，光波导在衬底上的投影呈条状，光波导包括第一子光波导，第一子光波导在衬底上的投影的至少部分的宽度逐渐减小；光波导与第一通孔的侧壁和第二介质层的另一侧面均接触，第二介质层的侧面还与第一通孔的另一侧壁接触。

Description

光芯片及其制备方法、通信设备 技术领域
本申请涉及光通信技术领域，尤其涉及一种光芯片及其制备方法、通信设备。
背景技术
如图1所示，通信设备1主要包括光芯片10和光纤20，不同光芯片10之间的光信号通过光纤20传输。其中，光芯片10包括衬底100和设置衬底100上的光波导(也可以称为模斑变换器)101，光波导101的一端与光纤20耦合，通过光波导101实现光信号在光芯片10和光纤20之间的传输。目前，光纤20的芯径尺寸R通常为8um～10um，光波导101的宽度H通常为300nm～500nm，由于二者在几何尺寸上存在巨大差距，从而导致了光模场的严重失配，增加了耦合损耗和端口反射。
由于光波导101靠近光纤20的一端的线宽越小，光场模斑越大，因而越有利于与光纤20的光模场匹配，从而有利于降低耦合损耗和端口反射，因而现有技术将光波导101靠近光纤20的一端的宽度制作地较小，即使制作的光波导101的形状为楔形。现有技术制备楔形的光波导101的过程中是：先在衬底100上形成光波导层，再对光波导层进行刻蚀形成楔形的光波导101。然而，在实际的制作过程中，受限于光刻设备最小线宽的限制，当光波导101靠近光纤20的一端的尺寸低于100nm时，光刻设备很难达到。此外，即使光刻设备能够光刻显影出低于100nm线宽的光刻胶，但是由于光波导层的厚度较大，通常为220nm或者更厚，因此在对光波导层进行刻蚀的过程中，光波导101的尖端容易断裂或缺损，从而导致实际制作工艺困难。
发明内容
本申请的实施例提供一种光芯片及其制备方法、通信设备，可以解决现有的光芯片中光波导在制备过程中尖端易断裂的问题。为达到上述目的，本申请采用如下技术方案：
第一方面，提供一种光芯片的制备方法，该制备方法包括：首先，在衬底上形成条状的光波导本体；接下来，在光波导本体远离衬底的一侧形成第一介质薄膜；接下来，对第一介质薄膜进行磨平处理形成第一介质层，光波导本体远离衬底的表面露出于第一介质层，以形成第一介质层内的第一通孔，光波导本体位于第一通孔内；接下来，在第一介质层上形成牺牲层；牺牲层在光波导本体上的投影覆盖光波导本体中第一子光波导，且不覆盖光波导本体中第三子光波导，第一子光波导的至少部分沿靠近第三子光波导的方向宽度逐渐减小；接下来，对牺牲层和第三子光波导进行刻蚀，去除牺牲层和第三子光波导，以形成光波导，光波导包括第一子光波导；接下来，在第一通孔内填充第二介质层；光波导与第一通孔的侧壁和第二介质层的侧面均接触，第二介质层的另一侧面与第一通孔的另一侧壁接触。本申请在制作光芯片的过程中，形成光芯片中的光波导时，是将光波导本体中的第三子光波导刻蚀掉，光波导本体中的第一子光波导保留作为光波导。由于第一子光波导的至少部分沿靠近第三子光波导的方向宽度逐渐减小，因而形成的光波导包括宽度逐渐减小的部分，即形成的光波导的至少部分的形状为楔形，也就是说， 形成的光波导包括尖端。此外，本申请在制备光芯片时，通过牺牲层将光波导本体需要刻蚀的尖端区域(即第三子光波导所在的区域)补充成没有尖端的区域，因而在对牺牲层和第三子光波导同时进行刻蚀时，被刻蚀的部分和未被刻蚀掉的部分均不存在尖角区域，因此未刻蚀的部分不会出现残留，被刻蚀的部分不会出现刻断的风险以及鼠齿现象，也就是需要去除的第三子光波导会被完全去除掉，不存在残留，保留的第一子光波导的尖端不存在被刻断的风险及鼠齿现象，因被刻蚀的部分和未被刻蚀掉的部分均不存在尖角区域，从而可以避免小线宽效应。
在一种可能的实施方式中，光波导本体包括层叠设置的光波导层和保护层；光波导层相对于保护层靠近衬底；在第一介质层上形成牺牲层之后，对牺牲层和第三子光波导进行刻蚀之前，该制备方法还包括：去除第三子光波导上的保护层。由于光波导本体包括光波导层和保护层，因而最终制备得到的光波导包括层叠设置的光波导层和保护层，保护层可以用于保护光波导层，防止光波导层损坏。此外，在对牺牲层和第三子光波导进行刻蚀之前，去除第三子光波导上的保护层，是为了后续步骤中可以同时刻蚀第三子光波导和牺牲层。
在一种可能的实施方式中，在第一介质层上形成牺牲层之后，去除第三子光波导上的保护层的步骤之前，上述制备方法还包括：在牺牲层上形成第二介质薄膜。上述去除第三子光波导上的保护层包括：首先，对第二介质薄膜进行刻蚀形成第三介质层，第三介质层包括第二通孔，牺牲层和第三子光波导露出于第二通孔；接下来，去除第三子光波导上的保护层；上述在第一通孔内填充第二介质层包括：在第一通孔和第二通孔内填充第二介质层。这样可以在刻蚀第二介质薄膜的同时，去除第三子光波导上的保护层，可以简化工艺；在第一通孔和第二通孔内填充第二介质层，可以对光波导起到保护作用。
在一种可能的实施方式中，光波导本体还包括设置在第一子光波导远离第三子光波导一侧，且与第一子光波导接触的第二子光波导，第二子光波导不需要进行所述刻蚀。在光波导本体包括第一子光波导、第二子光波导和第三子光波导的情况下，最终制备得到的光波导包括第一子光波导和第二子光波导，相对于光波导包括第一子光波导而言，可以增加光波导的长度。
在一种可能的实施方式中，第一子光波导的至少另一部分沿远离第三子光波导的方向宽度逐渐减小，第二子光波导的至少部分沿靠近第一子光波导的部分的方向逐渐减小；对牺牲层和第三子光波导进行刻蚀，去除牺牲层和第三子光波导，包括：对牺牲层、位于牺牲层下方的第一子光波导和第三子光波导同时进行刻蚀，去除牺牲层、第一子光波导靠近牺牲层的部分以及第三子光波导以形成光波导，光波导包括第一子光波导和第二子光波导；第一子光波导的厚度小于第二子光波导的厚度。这样形成的光波导中因第一子光波导和第二子光波导的厚度不同，且第二子光波导的厚度大于第一子光波导的厚度，第一子光波导和第二子光波导的交界处形成台阶，因而形成的光波导包括台阶，该台阶可以将光波导分为层叠设置的两层光波导，分别为第一层光波导和第二层光波导，第一层光波导相对于第二层光波导靠近衬底。在此基础上，由于第一子光波导的至少部分沿远离第二子光波导的方向宽度逐渐减小，因而第一层光波导包括宽度逐渐减小的部分，即第一层光波导的至少部分的形状为楔形。同样的，由于第二子光波导的至少部分沿靠近第一子光波导的方向宽度逐渐减小，且第二子光波导的厚度大于第一子光波导的 厚度，因而第二层光波导包括宽度逐渐减小的部分，即第二层光波导的至少部分的形状为楔形。由于这两层光波导的至少部分的形状为楔形，因而在光芯片和光纤耦合时，可以进一步增大光芯片与光纤耦合处的光场模斑，可以进一步降低耦合损耗和端口反射，从而进一步提高光波导和光纤的耦合效率，提高信号传输质量。
在一种可能的实施方式中，在第一介质层上形成牺牲层，包括：在第一介质层上形成牺牲薄膜；对牺牲薄膜进行构图形成牺牲层和辅助图案；辅助图案在光波导本体上的投影与光波导本体无重叠区域；对牺牲层和第三子光波导进行刻蚀，去除牺牲层和第三子光波导，包括：对牺牲层、辅助图案和第三子光波导进行刻蚀，去除牺牲层、辅助图案和第三子光波导。此处，由于在形成牺牲层的同时形成了辅助图案，因而在对牺牲层进行刻蚀的同时，可以对辅助图案进行刻蚀，而在刻蚀过程中，由于辅助图案可以消耗除牺牲层以外的区域的刻蚀时等离子体产生的能量，即可以增加刻蚀的面积，这样一来，能够大大改善刻蚀时等离子体的微观负载效应，刻蚀工艺稳定性好，容差大。
在一种可能的实施方式中，对牺牲薄膜进行构图形成牺牲层和辅助图案之后，去除第三子光波导上的保护层之前，上述制备方法还包括：在牺牲层上形成第二介质薄膜；去除第三子光波导上的保护层包括：首先，对第二介质薄膜进行刻蚀形成第三介质层，第三介质层包括第二通孔和第三通孔，牺牲层和第三子光波导露出于第二通孔，辅助图案露出于第三通孔；接下来，去除第三子光波导上的保护层；接下来，在第一通孔内填充第二介质层，包括：在第一通孔、第二通孔和第三通孔内填充第二介质层。此处，在第三介质层中形成第三通孔，辅助图案露出于第三通孔，这样可以在对牺牲层和第三子光波导进行可以刻蚀的同时，对辅助图案进行刻蚀，由于辅助图案可以消耗除牺牲层以外的区域的刻蚀时等离子体产生的能量，即可以增加刻蚀的面积，这样一来，能够大大改善刻蚀时等离子体的微观负载效应，刻蚀工艺稳定性好，容差大。
在一种可能的实施方式中，光波导本体包括层叠设置的光波导层和阻挡层；光波导层相对于阻挡层靠近衬底；在对第一介质薄膜进行磨平处理之后，在第一介质层上形成牺牲层的步骤之前，该制备方法还包括：去除阻挡层。在光波导本体包括阻挡层的情况下，对第一介质薄膜进行磨平处理时，当将光波导本体中阻挡层上方的第一介质薄膜打磨完之后，即打磨至光波导本体的阻挡层时，由于光波导本体包括阻挡层，而通常阻挡层的硬度较大(例如阻挡层的材料为氮化硅，氮化硅硬度较大)，因而阻挡层可以迫使在打磨至阻挡层时打磨停止，避免打磨过程中保护层和光波导层受到损坏。
在一种可能的实施方式中，光波导本体在衬底上投影的形状为矩形。当光波导本体在衬底上投影的形状为矩形时，由于光波导本体不存在尖端，因而可以在刻蚀形成光波导本体的过程中可以降低光波导本体的制作难度，且光波导本体不容易断裂。在一种可能的实施方式中，牺牲层的材料包括多晶硅、非晶硅、氮化硅、氮氧化硅中的一种或多种。由于光芯片中的其它功能器件，例如MOS管在制备时，也需要形成多晶硅层或非晶硅层，因而在牺牲层的材料为多晶硅或非晶硅的情况下，可以在形成MOS管中的多晶硅层或非晶硅层的同时形成牺牲层，也就是说牺牲层可与现有工艺兼容，因此本申请在制作光芯片的过程中增加牺牲层并不会增加工艺成本，产品灵活性高。
第二方面，提供一种光芯片，该光芯片包括衬底和设置在衬底上的第一介质层；第一介质层包括第一通孔；光芯片还包括填充在第一通孔内的光波导和第二介质层；其 中，光波导在衬底上的投影呈条状，光波导包括第一子光波导，第一子光波导在衬底上的投影的至少部分的宽度逐渐减小；光波导与第一通孔的侧壁和第二介质层的侧面均接触，第二介质层的另一侧面还与第一通孔的另一侧壁接触。由于第二方面提供的光芯片具有与上述第一方面提供的光芯片的制备方法相同的技术效果，因而可以参考上述第一方面的相关描述，此处不再赘述。
在一种可能的实施方式中，光波导还包括与第一子光波导接触的第二子光波导；第一子光波导的至少部分沿远离第二子光波导的方向宽度逐渐减小。光波导除了包括第一子光波导外，还包括第二子光波导，这样可以增加光波导的长度。
在一种可能的实施方式中，第一子光波导的厚度小于第二子光波导的厚度；其中，第二子光波导的至少部分沿靠近第一子光波导的方向宽度逐渐减小；第一子光波导的至少另一部分沿靠近第二子光波导的方向宽度逐渐减小。可以参考上述第一方面的相关描述，此处不再赘述。
在一种可能的实施方式中，第二子光波导的厚度和第一子光波导的厚度之差的范围为50nm～90nm。当第二子光波导的厚度和第一子光波导的厚度之差的范围为50nm～90nm时，有利于光信号的传输。
在一种可能的实施方式中，光芯片还包括设置在第一介质层远离衬底一侧的第三介质层；第三介质层包括第二通孔；第二通孔在衬底上的投影覆盖第一子光波导、位于第一通孔内的第二介质层、以及第一介质层的部分在衬底上的投影；其中，第二通孔内填充有第二介质层。此处，第三介质层覆盖光波导，可以用于保护光波导。
在一种可能的实施方式中，第三介质层还包括第三通孔；第三通孔内填充有第二介质层；其中，第三通孔在衬底上投影与光波导在衬底上的投影无重叠区域。在制备光芯片的过程中，可以在第三通孔处形成辅助图案。
在一种可能的实施方式中，第三介质层的材料和第一介质层的材料相同。
在一种可能的实施方式中，第一通孔在衬底上的投影为矩形。第一通孔所占的空间区域与制备光芯片的过程中光波导本体所占的空间区域相同，可以参考上述第一方面有关光波导本体在衬底上投影的形状为矩形的相关描述，此处不再赘述。
在一种可能的实施方式中，光波导包括层叠设置的光波导层和保护层；光波导层相对于保护层靠近衬底。此处，保护层可以用于保护光波导层，避免光波导层受到损坏。
在一种可能的实施方式中，光波导包括光波导层。
在一种可能的实施方式中，光波导层的厚度范围为200nm～300nm；和/或，保护层的厚度范围为5nm～20nm。
在一种可能的实施方式中，光波导层的材料包括氮化硅、氮氧化硅、硅、锗、锗化硅、磷化铟中的一种或多种；保护层的材料包括氧化硅。
在一种可能的实施方式中，第一介质层和第二介质层的材料包括氧化硅。
第三方面，提供一种通信设备，该通信设备包括光纤和上述第二方面提供的光芯片；其中，光芯片中光波导的尖端与光纤耦合。由于第三方面提供的通信设备具有与上述第二方面提供的光芯片相同的技术效果，因而可以参考上述第二方面的描述，此处不再赘述。
附图说明
图1为一种通信设备的结构示意图；
图2为本申请的实施例提供的一种通信设备的俯视结构示意图；
图3a为相关技术提供的一种光波导本体的俯视结构示意图；
图3b为相关技术提供的一种光波导本体和光刻胶层的俯视结构示意图；
图3c为相关技术提供的一种光波导的俯视结构示意图；
图4为相关技术提供的另一种光波导本体的俯视结构示意图；
图5为本申请的实施例提供的一种光芯片的剖面结构示意图一；
图6为本申请的实施例提供的一种光芯片的制备方法的流程图；
图7为本申请的实施例提供的一种制作光芯片的过程中的剖面结构示意图一；
图8为本申请的实施例提供的一种制作光芯片的过程中的剖面结构示意图二；
图9为本申请的实施例提供的一种制作光芯片的过程中的剖面结构示意图三；
图10为本申请的实施例提供的一种制作光芯片的过程中的剖面结构示意图四；
图11为本申请的实施例提供的一种光波导本体的俯视结构示意图；
图12为本申请的实施例提供的一种制作光芯片的过程中的剖面结构示意图五；
图13为本申请的实施例提供的一种制作光芯片的过程中的剖面结构示意图六；
图14为本申请的实施例提供的一种制作光芯片的过程中的剖面结构示意图七；
图15为本申请的实施例提供的一种制作光芯片的过程中的剖面结构示意图八；
图16为本申请的实施例提供的一种牺牲层、辅助图案和光波导本体的俯视结构示意图；
图17为本申请的实施例提供的一种制作光芯片的过程中的俯视结构示意图；
图18为本申请的实施例提供的一种制作光芯片的过程中的剖面结构示意图九；
图19为本申请的实施例提供的一种制作光芯片的过程中的剖面结构示意图十；
图20为本申请的实施例提供的一种制作光芯片的过程中的剖面结构示意图十一；
图21为本申请的实施例提供的另一种制作光芯片的过程中的俯视结构示意图；
图22为本申请的实施例提供的一种制作光芯片的过程中的剖面结构示意图十二；
图23为本申请的实施例提供的一种制作光芯片的过程中的剖面结构示意图十三；
图24为本申请的实施例提供的一种制作光芯片的过程中的剖面结构示意图十四；
图25为本申请的实施例提供的一种制作光芯片的过程中的剖面结构示意图十五；
图26为本申请的实施例提供的一种制作光芯片的过程中的剖面结构示意图十六；
图27为本申请的实施例提供的一种光波导的俯视结构示意图；
图28为本申请的另一实施例提供的一种光芯片的结构示意图；
图29为本申请的又一实施例提供的一种光芯片的俯视结构示意图；
图30为本申请的实施例提供的一种光芯片的剖面结构示意图二；
图31为本申请的实施例提供的一种光芯片的剖面结构示意图三；
图32为本申请的另一实施例提供的一种光波导的俯视结构示意图；
图33为本申请的实施例提供的一种光芯片的剖面结构示意图四；
图34为本申请的实施例提供的一种光芯片的剖面结构示意图五；
图35为本申请的另一实施例提供的一种光波导本体的俯视结构示意图；
图36为本申请的又一实施例提供的制作光芯片的过程中的剖面结构示意图十七；
图37为本申请的实施例提供的一种牺牲层和光波导本体的俯视结构示意图；
图38为本申请的又一实施例提供的一种光芯片的结构示意图；
图39为相关技术提供的一种光芯片的俯视结构示意图。
附图标记：1-通信设备；10-光芯片；10a-第一光芯片；10b-第二光芯片；11-底板；20-光纤；30-电路板；100-衬底；101-光波导；103-第一介质薄膜；104-牺牲层；105-辅助图案；106-第二介质薄膜；107-第一介质层；108-第二介质层；109-第一通孔；101a-第一子光波导；101b-第二子光波导；101c-第三子光波导；101d-第一层光波导；101e-第二层光波导；110-第三介质层；111-第二通孔；112-抗反射涂层；113-光刻胶薄膜；1000-光刻胶层；1000a-镂空区；1001-第一子衬底；1002-第二子衬底；1010-光波导本体；1010a-被刻蚀掉的部分；1010b-未被刻蚀掉的部分；1011-光波导层；1012-保护层；1013-阻挡层；1040-牺牲薄膜。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。
以下，术语“第一”、“第二”等仅用于描述方便，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”等的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在本申请中，除非另有明确的规定和限定，术语“耦合”可以是直接耦合，也可以通过中间媒介间接耦合。
在本申请中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其它实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或“例如”等词旨在以具体方式呈现相关概念。
在本申请实施例中，“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中A，B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。
在本申请中，例如上、下、左、右、前和后等用于解释本申请中不同部件的结构和运动的方向指示是相对的。当部件处于图中所示的位置时，这些指示是恰当的。但是，如果元件位置的说明发生变化，那么这些方向指示也将会相应地发生变化。
本申请的实施例提供一种通信设备，该通信设备例如可以为手机(mobile phone)、平板电脑(pad)、IP(internet protocol，网际协议)电话、交换机(switch)、路由器(router)、光端机(optical transceiver)、激光器等任意以光波为载波，利用光纤作为传输媒介，通过光电变换，用光来传输信息的通信设备，本申请实施例对通信设备的具体形式不作特殊限制。
图2示例性地提供了一种通信设备的结构图，如图2所示，通信设备1包括电路板30以及设置在电路板30上的第一光芯片10a、第二光芯片10b和光纤20，光纤20的两端分别与第一光芯片10a和第二光芯片10b耦合。此处，光纤20例如可以为单模光纤。
可以理解的是，本申请实施例示意的结构并不构成对上述通信设备的具体限定。在本申请另一些实施例中，上述通信设备可以包括比图示更多或更少的部件，或者组合某些部件，或者拆分某些部件，或者不同的部件布置。图示的部件可以以硬件，软件或软件和硬件的组合实现。
上述通信设备1的工作过程为：首先，第一光芯片10a将电信号转换为光信号，再将光信号耦合至光纤20上，之后光信号通过光纤20传输，并将光信号耦合至第二芯片10b中，第二芯片10b接收光信号，且将光信号转化为电信号，从而实现第一光芯片10a和第二芯片10b之间信息的传输。
以第一光芯片10a与光纤20的耦合为例，可以通过以下两种方式实现第一光芯片10a与光纤20之间光信号的传输，第一种方式：可以在第一光芯片10a中设置透镜式光波电缆，或者设置光栅耦合器(grating coupler)，通过透镜式光波电缆或光栅耦合器与光纤20耦合，以实现光信号在第一光芯片10a与光纤20之间传输。然而，由于透镜式光波电缆的价格非常昂贵，光栅耦合器与光纤20耦合时，耦合效率对波长敏感，难以支撑高带宽的粗波分复用器以及C频带的波分复用器的宽谱应用，因此限制了透镜式光波电缆和光栅耦合器在第一光芯片10a中的应用。
第二种方式：可以在第一光芯片10a中设置光波导，光波导的一端与光纤20耦合，通过光波导实现光信号在第一光芯片与光纤20之间的传输。由于上述第一种方式存在价格昂贵、耦合效率对波长敏感、应用范围较窄等问题，因此目前常采用第二种方式实现第一光芯片10a与光纤20之间光信号的传输。
基于上述通信设备1的工作过程可知，光信号需要在第一光芯片10a和光纤20之间以及第二光芯片10b和光纤20之间分别耦合，而光波导是实现光芯片内的光信号与光纤20耦合的关键器件，在集成光路中起着至关重要的作用。由于光信号在第一光芯片10a的光波导和光纤20之间，或者在第二光芯片10b的光波导和光纤20之间耦合时会产生耦合损耗，从而会导致光信号的质量降低，因此降低光波导与光纤20的耦合损耗是目前通信设备1极为关注的一个问题。
由于光波导中与光纤20耦合的一端的线宽越小，光场模斑越大，因而越有利于光波导的光模场与光纤20的光模场匹配，从而有利于降低耦合损耗和端口反射，提高耦合效率，因此可以制作一个宽度逐渐减小，且具有较小尖端的光波导，即楔形(taper)的光波导，并且线宽较小的一端与光纤20耦合，即光芯片10中光波导的尖端与光纤20耦合，来降低光波导与光纤20的耦合损耗。相关技术在制作楔形的光波导时，采用先在衬底上形成光波导层，再对光波导层进行刻蚀形成光波导的方式制作楔形的光波导。然而，在实际的制作过程中，一方面，受限于光刻设备最小线宽的限制，当光波导靠近光纤20的一端的尺寸低于100nm时，光刻设备很难达到；另一方面，即使采用成本高昂、先进的紫外(ultraviolet，UV)光刻机或电子束光刻机(electron beam lithography，EBL)，可以光刻显影出低于100nm线宽的光刻胶，但是在对光波导层进行刻蚀的过程中，由于光波导层的厚度较大，通常为220nm或者更厚，因此在对光波导层刻蚀时，光波导的尖端经常容易断裂或缺损，造成实际工艺制作的困难。
为了解决因光波导层厚度较大导致的刻蚀形成的光波导尖端容易断裂或缺损的问题，相关技术提供了一种楔形的光波导的制备方法，如图3a所示，先在衬底上刻蚀出 一个尖端较宽的光波导本体1010，光波导本体1010的宽度H可以大于100nm；接下来，在光波导本体1010上形成光刻胶薄膜，对光刻胶薄膜进行曝光显影后形成如图3b所示的光刻胶层1000，光刻胶层1000包括矩形的镂空区1000a，镂空区1000a在光波导本体1010上的投影与光波导本体1010具有重叠区域，该重叠区域包括沿光波导本体1010的长度方向X逐渐减小的部分；接下来，如图3c所示，对光波导本体1010进行刻蚀形成光波导101；其中，露出于光刻胶层1000的镂空区1000a的部分被刻蚀掉。由于光波导本体1010中被刻蚀掉的部分1010a包括沿光波导本体1010的长度方向X逐渐减小的尖端，因而光波导本体1010中未被刻蚀的部分，即形成的光波导101也包括沿光波导本体1010的长度方向X逐渐减小的尖端，这样一来，便可以得到尖端宽度H低于100nm的光波导101，即可以得到楔形的光波导101。
然而，采用上述相关技术提供的方法制备光波导101时，如图4所示，由于光波导本体1010中被刻蚀掉的部分1010a和未被刻蚀掉的部分1010b都包括三角形的尖端(如图4中虚线圈所示的位置)，因而刻蚀过程中容易刻断或残留，工艺问题多，难以稳定量产。具体的，由于光波导本体1010中被刻蚀掉的部分1010a和未被刻蚀掉的部分1010b都包括三角形的尖端，如图3b所示，光刻胶层1000的镂空区1000a和光波导本体1010的交界面为一个斜面，在这个斜面处光刻胶层1000和光波导本体1010会形成台阶，对于光波导本体1010中未被刻蚀掉的部分1010b而言，在对光波导本体1010进行刻蚀的过程中，由于台阶会对等离子体散射，从而导致位于斜面位置处的光波导本体1010刻蚀时损伤加剧，同时，对光波导本体1010刻蚀时因刻蚀工艺中侧壁电荷对等离子体(plasma)的作用以及等离子体微观负载效应(plasma micro loading)，尖端区域容易刻断，且刻蚀的边缘处会出现不规则的缺口，即鼠齿(mouse bite)现象，如图4中的区域A所示。同样的，对于光波导本体1010中需要被刻蚀掉的部分1010a而言，因刻蚀工艺中侧壁电荷对等离子体的作用、等离子体微观负载效应，尖端区域容易残留，通常采用过刻的方法将残留的部分去除，然而，过刻(over etch，OE)又会导致光波导本体1010中未被刻蚀掉的部分1010b的尖端被刻蚀断裂的风险。基于此可以看出，相关技术制备光波导101的工艺困难，难以稳定量产。
为了解决相关技术制备光波导101的过程中存在光波导101尖端易被刻蚀断裂的问题，本申请实施例提供一种光芯片10及其制备方法，光芯片10包括光波导101，光芯片10的制备方法包括光波导101的制备方法。其中，本申请实施例提供的光芯片10可以应用于上述的通信设备1中。以下通过几个具体的实施例对本申请提供的光芯片10及其制备方法进行示例性介绍。
实施例一
实施例一提供一种光芯片10，如图5所示，光芯片10主要包括衬底100、第一介质层107、光波导101以及第二介质层108；其中，第一介质层107设置在衬底100上，第一介质层107包括第一通孔109；第一通孔109内填充有光波导101和第二介质层108。其中，光波导101在衬底100上的投影呈条状，光波导101包括第一子光波导101a，第一子光波导101a在衬底100上的投影的至少部分的宽度逐渐减小，即光波导101的至少部分的形状为楔形；光波导101与第一通孔109的侧壁和第二介质层108的侧面均接触，第二介质层108的另一侧面还与第一通孔109的另一侧壁接触。光芯片10 还包括设置在第一介质层107远离衬底100一侧的第三介质层110；第三介质层110包括第二通孔111。第二通孔111内填充有第二介质层108。
此处，第一子光波导101a在衬底100上的投影的至少部分的宽度逐渐减小，可以是第一子光波导101a在衬底100上的投影的宽度逐渐减小，也可以是第一子光波导101a在衬底100上的投影的部分的宽度逐渐减小。也就是说，光波导101的至少部分的形状为楔形，可以是光波导101的整体的形状为楔形；也可以是光波导101的部分的形状为楔形。
可以理解的是，第二介质层108包括靠近衬底100的表面(即图5中第二介质层108的下表面)、远离衬底100的表面(即图5中第二介质层108的上表面)以及侧面。
如图6所示，制备如图5所示的光芯片10可以包括步骤S10～S19：S10、如图7所示，在衬底100上形成条状的光波导本体1010。此处，对于在衬底100上形成的光波导本体1010的数量不进行限定，可以是一条或多条。图7以在在衬底100上形成一条光波导本体1010为例进行示意。
在一些示例中，步骤S10可以包括：
S100、提供如图8所示的底板11；其中，底板11包括层叠设置的衬底100和光波导层1011。
在一些示例中，衬底100包括层叠设置的第一子衬底1001和第二子衬底1002，第二子衬底1002相对于第一子衬底1001靠近光波导层1011。
上述第一子衬底1001的材料例如可以包括氮化硅(SiNx)、氮氧化硅(SiOxNy)、硅(Si)、锗(Ge)、锗化硅(SixGey)、磷化铟(InP)中的一种或多种。
上述第二子衬底1002的材料例如可以包括氧化硅(SiOx)，氧化硅例如可以为二氧化硅(SiO2)。
上述光波导层1011的材料例如可以包括氮化硅、氮氧化硅、硅、锗、锗化硅、磷化铟中的一种或多种。
在一些示例中，第一子衬底1001的材料为硅，第二子衬底1002的材料为氧化硅，氧化硅例如可以为二氧化硅，光波导层1011的材料为硅，在此情况下，底板11可以称为硅晶圆(silicon on insulator wafer，SOI wafer)。
另外，在一些示例中，第一子衬底1001的厚度范围可以为500μm～725μm。示例的，第一子衬底1001的厚度可以为500μm、600μm、700μm或725μm等。
在一些示例中，第二子衬底1002的厚度范围可以为2μm～3μm。示例的，第二子衬底1002的厚度可以为2μm、2.5μm或3μm等。在一些示例中，光波导层1011的厚度范围可以为200nm～300nm。示例的，光波导层1011的厚度可以为200nm、250nm或300nm等。
S101、如图9所示，在底板11上形成保护层1012。
需要说明的是，步骤S101是可选的步骤，例如，在一些示例中，步骤S101可以省略。
此处，保护层1012的材料例如可以包括氧化硅，氧化硅例如可以为二氧化硅。
示例的，步骤S101可以采用以下两种方式实现：第一种，可以对光波导层1011 远离衬底100的表面进行热氧化处理，以形成保护层1012。示例的，在光波导层1011的材料为硅的情况下，可以对光波导层1011远离衬底100的表面进行热氧化处理，得到保护层1012，保护层1012的材料为氧化硅。另一种，可以在底板11上直接形成保护层1012。在此情况下，可以利用化学气相沉积(chemical vapor deposition，CVD)、溅射等方法形成保护层1012。在一些示例中，保护层1012的厚度范围为5nm～20nm。保护层1012的厚度例如可以为5nm、10nm、15nm或20nm等。
S102、如图10所示，在保护层1012上形成阻挡层1013。需要说明的是，步骤S102是可选的步骤，例如，在一些示例中，步骤S102可以省略。在一些示例中，可以通过化学气相沉积、溅射等方法在保护层1012上形成阻挡层1013。此处，阻挡层1013的材料例如可以为氮化硅。此外，阻挡层1013的厚度范围例如可以为20nm～100nm。阻挡层1013的厚度例如可以为20nm、40nm、60nm、80nm或100nm等。
S103、对上述光波导层1011、保护层1012以及阻挡层1013进行构图，形成如图7所示的条状的光波导本体1010。可以理解的是，在步骤S10包括步骤S101和步骤S102的情况下，光波导本体1010包括依次层叠设置的光波导层1011、保护层1012以及阻挡层1013，光波导层1011相对于阻挡层1013靠近衬底100。在步骤S10省略步骤S101的情况下，光波导本体1010包括依次层叠设置的光波导层1011和阻挡层1013，光波导层1011相对于阻挡层1013靠近衬底100。在步骤S10省略步骤S102的情况下，光波导本体1010包括依次层叠设置的光波导层1011和保护层1012，光波导层1011相对于保护层1012靠近衬底100。此外，在光波导本体1010包括保护层1012的情况下，保护层1012可以用于保护光波导层1011。需要说明的是，对上述光波导层1011、保护层1012以及阻挡层1013进行构图包括涂覆光刻胶、掩膜曝光、显影以及刻蚀等工序。
在一些示例中，如图13所示，光波导本体1010在衬底100上投影的形状为矩形。当光波导本体1010在衬底100上投影的形状为矩形时，由于光波导本体1010不存在尖端，因而可以在刻蚀形成光波导本体1010的过程中降低光波导本体1010的制作难度，且光波导本体1010不容易断裂。
在光波导本体1010在衬底100上投影的形状为矩形的情况下，在一些示例中，矩形的宽度可以大于90nm，例如，矩形的宽度可以为90nm或100nm。当矩形的宽度大于90nm时，可以在刻蚀形成光波导本体1010的过程中进一步降低光波导本体1010的制作难度，降低对光刻设备的要求。
需要说明的是，如图11所示，上述光波导本体1010包括相互接触的第一子光波导101a和第二子光波导101b；第一子光波导101a的至少部分沿远离第二子光波导101b的方向宽度逐渐减小。请继续参考图11，上述光波导本体1010还包括设置在第一子光波导101a远离第二子光波导101b一侧，且与第一子光波导101a接触的第三子光波导101c。
可以理解的是，由于光波导本体1010包括相互接触的第一子光波导101a和第三子光波导101c，第一子光波导101a和第三子光波导101c构成一个互补的图形，而第一子光波导101a的至少部分沿远离第二子光波导101b的方向宽度逐渐减小，即第一子光波导101a的至少部分沿靠近第三子光波导101c的方向宽度逐渐减小，因而在光 波导本体1010为矩形的情况下，第三子光波导101c的至少部分沿靠近第一子光波导101a的方向宽度也是逐渐减小的，即第一子光波导101a和第三子光波导101c均包括尖端区域。
需要说明的是，在本实施例一中，第一子光波导101a的至少另一部分沿靠近第三子光波导101c的方向宽度逐渐减小，对于第一子光波导101a沿远离第三子光波导101c的方向宽度不进行限定，可以是宽度逐渐减小，也可以是宽度逐渐增大；当然还可以宽度相同。
S11、如图12所示，在光波导本体1010远离衬底100的一侧形成第一介质薄膜103。此处，第一介质薄膜103的材料例如可以包括氧化硅，氧化硅例如可以为二氧化硅。此外，可以通过化学气相沉积、溅射等方法形成第一介质薄膜103。在一些示例中，第一介质薄膜103的厚度大于或等于光波导本体1010的厚度。
S12、如图13所示，对第一介质薄膜103进行磨平处理形成第一介质层107，光波导本体1010远离衬底100的表面露出于第一介质层107，以形成第一介质层107内的第一通孔109，光波导本体1010位于第一通孔109内。
由于光波导本体1010位于第一通孔109内，因此光波导本体1010在衬底100上的投影的形状与第一通孔109在衬底100上的投影的形状相同。示例的，在光波导本体1010在衬底100上的投影的形状为矩形的情况下，第一通孔109在衬底100上的投影也为矩形。示例性地，可以采用化学机械抛光(chemical mechanical polishing，CMP)工艺对第一介质薄膜103进行磨平处理。
需要说明的是，在光波导本体1010包括阻挡层1013的情况下，对第一介质薄膜103进行磨平处理时，当将光波导本体1010中阻挡层1013上方的第一介质薄膜103打磨完之后，即打磨至光波导本体1010的阻挡层1013时，由于光波导本体1010包括阻挡层1013，而通常阻挡层1013的硬度较大(例如阻挡层1013的材料为氮化硅，氮化硅硬度较大)，因而阻挡层1013可以迫使在打磨至阻挡层1013时打磨停止，避免打磨过程中保护层1012和光波导层1011受到损坏。
可以理解的是，在第一介质薄膜103的厚度大于或等于光波导本体1010的厚度的情况下，如图13所示，对第一介质薄膜103进行磨平处理后，形成的第一介质层107远离衬底100的表面与光波导本体1010远离衬底100的表面齐平。
S13、如图14所示，去除阻挡层1013。需要说明的是，步骤S13是可选的步骤，例如，在上述步骤S10不包括S102的情况下，步骤S13可以省略。此处，可以通过化学或物理方法去除阻挡层1013。在一些示例中，在阻挡层1013的材料为氮化硅时，由于氮化硅遇到热磷酸后被腐蚀，因而可以利用热磷酸去除阻挡层1013。
S14、如图15所示，在第一介质层107上形成牺牲层104和辅助图案(也可以称为虚拟图案，dummy)；其中，如图16所示，辅助图案105在光波导本体1010上的投影与光波导本体1010无重叠区域。如图16和图17所示，牺牲层104在光波导本体1010上的投影覆盖光波导本体1010中的第一子光波导101a，且不覆盖光波导本体1010中的第二子光波导101b和第三子光波导101c，第一子光波导101a的至少部分沿靠近第三子光波导101c的方向宽度逐渐减小。
此处，步骤S14例如可以包括：S140、如图18所示，在第一介质薄膜103上形成 牺牲薄膜1040。此处，可以利用化学气相沉积、溅射等方法形成牺牲薄膜1040。
S141、如图16所示，对牺牲薄膜1040进行构图形成牺牲层104和辅助图案105；如图17所示，牺牲层104在光波导本体1010上的投影覆盖第一子光波导101a，且不覆盖第二子光波导101b和第三子光波导101c。如图16所示，辅助图案105在光波导本体1010上的投影与光波导本体1010无重叠区域。
此处，为了便于构图形成牺牲层104，牺牲层104的尺寸可以设置的较大，牺牲层104的形状以能覆盖第一子光波导101a，且便于构图为准。示例的，牺牲层104在衬底100上投影的形状可以为梯形、矩形、多边形、圆形、其它规则或不规则的形状等。图16和图17中以牺牲层104为梯形为例。
此外，为了便于构图形成辅助图案105，辅助图案105的尺寸可以设置的较大，且以便于构图为准。示例的，辅助图案105在衬底100上的投影的形状例如梯形、矩形、多边形、圆形、其它规则或不规则的形状等。图16中以辅助图案105的形状为矩形为例。
可以理解的是，可以形成一个或多个辅助图案105。在形成多个辅助图案105的情况下，可以在相邻两个光波导本体1010之间设置辅助图案105。另外，在形成有多个辅助图案105的情况下，多个辅助图案105的形状可以相同，也可以不完全相同。
在一些示例中，牺牲层104和辅助图案105的材料可以包括多晶硅(poly silicon，P-Si)、非晶硅(amorphous-Si，a-Si)、氮化硅、氮氧化硅中的一种或多种。
在制备光芯片10时，由于光芯片10中的其它功能器件，例如MOS(metal oxide semiconductor，金属氧化物半导体型场效应)管在制备时，也需要形成多晶硅层或非晶硅层，因而在牺牲层104和辅助图案105的材料为多晶硅或非晶硅的情况下，可以在形成MOS管中的多晶硅层或非晶硅层的同时形成牺牲层104和辅助图案105，也就是说牺牲层104和辅助图案105可与现有工艺兼容，例如与现有的多层光栅(ploy grating)结构的SOI(silicon-on-insulator，绝缘层上的硅)工艺兼容，因此本实施例一在制作光芯片10的过程中增加牺牲层104和辅助图案105并不会增加工艺成本，产品灵活性高。
S15、如图19所示，在牺牲层104上形成第二介质薄膜106。需要说明的是，步骤S15是可选的步骤，例如在一些示例中，步骤S15可以省略。此处，第二介质薄膜106的材料例如可以为氧化硅，氧化硅例如可以为二氧化硅。另外，第一介质薄膜103的材料和第二介质薄膜106的材料可以相同，也可以不相同。此外，形成第二介质薄膜106的方法可以参考步骤S11，此处不再赘述。
S16、如图20所示，对第二介质薄膜106进行构图形成第三介质层110，第三介质层110包括第二通孔111。如图21所示，牺牲层104和第三子光波导101c露出于第二通孔111，即第二通孔111在衬底100上的投影覆盖牺牲层104和第三子光波导101c在衬底100上的投影。如图21所示，第三介质层110还包括第三通孔114，辅助图案105露出于第三通孔114，第三通孔114在衬底100上的投影与光波导本体1010在衬底100上的投影无重叠区域。
在一些示例中，第二通孔111在衬底100上的投影还覆盖第一介质层107的部分在衬底100上的投影。需要说明的是，由于牺牲层104在光波导本体1010上的投影覆 盖第一子光波导101a，因而第二通孔111在衬底100上的投影覆盖第一子光波导101a和第三子光波导101c在衬底100上的投影。需要说明的是，第三介质层110的材料和第一介质层107的材料可以相同，也可以不相同。
此外，步骤S16例如可以包括：S160、如图22所示，在第二介质薄膜106上形成抗反射涂层(bottom anti reflection coating，BARC)112。可以理解的是，步骤S160为可选的步骤，例如在一些示例中，步骤S160可以省略。
S161、如图23所示，在抗反射涂层112上形成光刻胶薄膜113。S162、如图24所示，对抗反射涂层112和光刻胶薄膜113进行光刻工艺(例如掩膜曝光、显影等工艺)形成镂空区域。S163、如图25所示，对第二介质薄膜106进行刻蚀形成第三介质层110。S164、如图20所示，去除抗反射涂层112和光刻胶薄膜113。此处，步骤S16也可以称为对第二介质薄膜106进行开窗处理。应当理解到，步骤S16是可选的步骤，在光芯片10的制备方法不包括步骤S15的情况下，步骤S16可以省略。需要说明的是，可以通过选取第二介质薄膜106的材料和牺牲层104的材料的性能差异，以使步骤S16中对第二介质薄膜106进行刻蚀时不会刻蚀到牺牲层104。
S17、如图20所示，去除第三子光波导101c上的保护层1012，以露出第三子光波导101c远离衬底100的表面。需要说明的是，步骤S17为可选的步骤，例如在步骤S10不包括S101时，即不包括形成保护层1012的步骤时，步骤S17可以省略。
需要说明的是，步骤S16和步骤S17可以同时执行，即在对第二介质薄膜106进行刻蚀时的同时，将第三子光波导101c上的保护层1012刻蚀去除掉。当然，也可以先执行步骤S16，再执行步骤S17，即在对第二介质薄膜106刻蚀完成后，再将第三子光波导101c上的保护层1012刻蚀去除，以露出第三子光波导101c远离衬底100的表面。
S18、如图26所示，对牺牲层104、辅助图案105和第三子光波导101c进行刻蚀，去除牺牲层104、辅助图案105和第三子光波导101c，以形成如图27所示的光波导101，由于第三子光波导101c被刻蚀掉，因而如图27所示，光波导101包括第一子光波导101a和第二子光波导101b。
由于步骤S14在形成牺牲层104的同时形成了辅助图案105，辅助图案105的材料与牺牲层104的材料相同，因而在步骤S18中，在对牺牲层104进行刻蚀时，也对辅助图案105进行刻蚀，而在刻蚀过程中，由于辅助图案105可以消耗除牺牲层104以外的区域的刻蚀时等离子体产生的能量，即可以增加刻蚀的面积，这样一来，能够大大改善刻蚀时等离子体的微观负载效应，刻蚀工艺稳定性好，容差大。
此处，在对牺牲层104和第三子光波导101c进行刻蚀时，可以根据牺牲层104和第三子光波导101c的刻蚀速率，调整牺牲层104和第三子光波导101c厚度，以使刻蚀完牺牲层104的同时，第三子光波导101c也刚好被完全刻蚀掉。
需要说明的是，由于牺牲层104覆盖第一子光波导101a，且第二介质层108覆盖第二子光波导101b，因而对牺牲层104和第三子光波导101c进行刻蚀时，被牺牲层104覆盖的第一子光波导101a和被第二介质层108覆盖的第二子光波导101b会留下来，第三子光波导101c被刻蚀去除，从而形成上述的光波导101。
可以理解的是，由于光波导本体1010填充在第一介质层107的第一通孔109内， 因而去除光波导本体1010中的第三子光波导101c后，第一通孔109内的部分区域没有被填充。
应当理解到，如图27所示，由于第一子光波导101a的至少部分沿靠近第三子光波导101c的方向宽度逐渐减小，因而形成的光波导101包括宽度逐渐减小的部分，即形成的光波导101的至少部分的形状为楔形，也就是说，形成的光波导101包括尖端。
图28示意出了在衬底100上形成的楔形的光波导101。另外，图28以在衬底100上形成一个楔形的光波导101为例，在一些示例中，如图29所示，还可以在衬底100上同时形成多个光波导101。
可以理解的是，由于第三通孔114在衬底100上的投影与光波导本体1010在衬底100上的投影无重叠区域，因而第三通孔114在衬底100上的投影与最终形成的光波导101在衬底100上的投影无重叠区域。
需要说明的是，在光波导本体1010包括层叠设置的光波导层1011和保护层1012的情况下，最终形成的光波导101包括层叠设置的光波导层1011和保护层1012，即第一子光波导101a和第二子光波导101b包括层叠设置的光波导层1011和保护层1012，且光波导层1011相对于保护层1012靠近衬底100。在光波导本体1010不包括保护层1012的情况下，最终形成的光波导101包括仅包括光波导层1011，不包括保护层1012，即第一子光波导101a和第二子光波导101b包括仅包括光波导层1011，不包括保护层1012。
S19、如图30所示，在第一通孔109、第二通孔111和第三通孔114内形成第二介质层108，也就是说，第一通孔109、第二通孔111和第三通孔114内均填充有第二介质层108。此时，光波导101与第一通孔109的侧壁和第二介质层108的侧面均接触，第二介质层108的另一侧面与第一通孔109的另一侧壁接触。需要说明的是，图30和图31中均未示意出第三通孔114。
需要说明的是，在一些示例中，如图30所示，第二介质层108仅填充在第一通孔109、第二通孔111和第三通孔114内，在此情况下，可以先形成第二介质层108，再对第二介质层108进行磨平处理，以使第二介质层108远离衬底100的表面与第三介质层110远离衬底100的表面平齐。在另一些示例中，如图31所示，第二介质层108填充在第一通孔109、第二通孔111和第三通孔114内，且还形成在第三介质层110远离衬底100的一侧。
由于第二通孔111在衬底100上的投影覆盖第三子光波导101c，而在第一通孔109内去除第三子光波导101c的位置处填充了第二介质层108，因而第二通孔111在衬底100上的投影覆盖位于第一通孔109内的第二介质层108。
此处，第二介质层108的材料和第一介质层107的材料可以相同，也可以不相同。此外，第二介质层108的材料和第三介质层110的材料可以相同，也可以不相同。
基于上述可知，在本实施例一中，在制作光芯片10的过程中，形成光芯片10中的光波导101时，是将光波导本体1010中的第三子光波导101c刻蚀掉，光波导本体1010中的第一子光波导101a和第二子光波导101b保留作为光波导101。由于第一子光波导101a的至少部分沿靠近第三子光波导101c的方向宽度逐渐减小，因而形成的光波导101包括宽度逐渐减小的部分，即形成的光波导101的至少部分的形状为楔形， 也就是说，形成的光波导101包括尖端。
在此基础上，在制作光波导101的过程中，由于光波导本体1010包括相互接触的第一子光波导101a和第三子光波导101c，第一子光波导101a和第三子光波导101c构成一个互补的图形，例如矩形，而第一子光波导101a的至少部分沿靠近第三子光波导101c的方向宽度逐渐减小，因而第三子光波导101c的至少部分沿靠近第一子光波导101a的方向宽度也逐渐减小，即第一子光波导101a和第三子光波导101c均包括尖端区域。由于第三子光波导101c包括尖端区域，因而相对于仅对第三子光波导101c进行刻蚀时，保留的第一子光波导101a的尖端区域容易断裂，第三子光波导101c的尖端区域容易残留而言，由于本实施例一是对牺牲层104和第三子光波导101c同时进行刻蚀，利用牺牲层104将光波导本体1010需要刻蚀的尖端区域(即第三子光波导101c所在的区域)补充成没有尖端的区域，因而对牺牲层104和第三子光波导101c同时进行刻蚀时，被刻蚀的部分和未被刻蚀掉的部分均不存在尖角区域，这样一来，未刻蚀的部分不会出现残留，被刻蚀的部分不会出现刻断的风险以及鼠齿现象，也就是需要去除的第三子光波导101c会被完全去除掉，不存在残留，保留的第一子光波导101a的尖端不存在被刻断的风险及鼠齿现象，此外，因被刻蚀的部分和未被刻蚀掉的部分均不存在尖角区域，从而可以避免小线宽效应。
上述实施例一是以光波导本体1010包括第一子光波导101a、第二子光波导101b和第三子光波导101c，最终形成的光波导101包括第一子光波导101a和第二子光波导101b为例进行的说明。在一些示例中，光波导本体1010包括第一子光波导101a和第三子光波导101c，不包括第二子光波导101b，这样最终制备得到的光波导101的结构如图32所示，仅包括第一子光波导101a，不包括第二子光波导101b。
在上述在光芯片10的制备方法不包括步骤S15和S16的情况下，步骤S19包括：在第一通孔109内形成第二介质层108。在此情况下，制备得到的光芯片10的结构如图33所示。
在上述光芯片10的制备方法不包括步骤S101的情况下，最终制备得到的光芯片10如图34所示，从图34中可以看出，最终制备得到的光芯片10中的光波导101包括光波导层1011，不包括保护层1012。
实施例二
实施例二和实施例一提供光芯片10的制备方法的区别之处在于，实施例一中，步骤S18中对牺牲层104和第三子光波导101c进行刻蚀，去除牺牲层104和第三子光波导101c，形成光波导101，而实施例二，除了对牺牲层104和第三子光波导101c同时进行刻蚀外，还同时刻蚀了位于牺牲层下方的第一子光波导101a的部分。
此外，实施例一对于第一子光波导101a沿远离第三子光波导101c的方向宽度不进行限定，例如可以是宽度逐渐减小，也可以是宽度逐渐增大；当然还可以宽度相同，且对于第二子光波导101b沿靠近第一子光波导101a的方向的宽度不进行限定，例如可以是宽度逐渐减小，也可以是宽度逐渐增大；当然还可以宽度相同。而在实施例二中，如图35所示，第一子光波导101a的至少另一部分沿远离第三子光波导101c的方向宽度逐渐减小，即第一子光波导101a的至少部分沿靠近第二子光波导101b的方向 宽度逐渐减小，且第二子光波导101b的至少部分沿靠近第一子光波导101a的方向宽度逐渐减小。
由于第一子光波导101a的至少部分沿靠近第二子光波导101b的方向宽度逐渐减小，且第一子光波导101a的至少部分靠近第三子光波导101c的方向宽度逐渐减小，因而如图35所示，第一子光波导101a沿靠近第二子光波导101b的方向和远离第二子光波导101b的方向宽度均逐渐减小。
实施例二提供一种光芯片10的制备方法，该实施例二提供的光芯片10的制备方法可以参考上述实施例一，且将实施例一中的步骤S18替换为步骤S20，步骤S20包括：
S20、如图36所示，对牺牲层104、位于牺牲层104下方的第一子光波导101a和第三子光波导101c进行刻蚀，去除牺牲层104、第一子光波导101a靠近牺牲层104的部分以及第三子光波导101c，形成光波导101。如图27所示，光波导101包括相互接触的第一子光波导101a和第二子光波导101b。由于去除了第一子光波导101a靠近牺牲层104的部分，因此最终形成的光波导101中第一子光波导101a的厚度小于第二子光波导101b的厚度。
需要说明的是，在对牺牲层104和第三子光波导101c进行刻蚀时，可以根据牺牲层104和第三子光波导101c的刻蚀速率，调整牺牲层104和第三子光波导101c厚度，以使将第三子光波导101c刻蚀完的同时，将牺牲层104以及位于牺牲层104下方的第一子光波导101a的部分同时刻蚀掉。此外，还可以根据需要刻蚀掉的第一子光波导101a的部分的厚度，来调整牺牲层104和第三子光波导101c的厚度。
可以理解的是，在牺牲层104和第三子光波导101c中的保护层1012的材料为二氧化硅，第三子光波导101c中光波导层1011的材料为硅的情况下，可以根据硅与二氧化硅的刻蚀选择比设计出牺牲层104和第三子光波导101c的厚度，以在刻蚀牺牲层104和第三子光波导101c时，还将位于牺牲层104下方的第一子光波导101a的部分刻蚀掉，以使第二子光波导101b与第一子光波导101a之间存在厚度差，其中，厚度差由牺牲层104和第三子光波导101c的厚度差、以及硅与二氧化硅的刻蚀速率决定。
由于在步骤S20中第一子光波导101a靠近牺牲层104的部分被刻蚀掉，因而最终形成的光波导101中第一子光波导101a和第二子光波导101b的厚度不相同，且第二子光波导101b的厚度大于第一子光波导101a的厚度。在一些示例中，第二子光波导101b的厚度和第一子光波导101a的厚度之差的范围为50nm～90nm。示例的，第二子光波导101b的厚度和第一子光波导101a的厚度可以为50nm、60nm、70nm或90nm等。
需要说明的是，实施例二提供的光芯片10的制备方法的其它步骤可以参考实施例一，在此不再赘述。基于上述实施例二和实施例一制备方法的不同，实施例二和实施例一制备得到的光芯片10的结构的区别之处在于，在实施例一中，形成的光波导101中第一子光波导101a和第二子光波导101b的厚度相同，在实施例二中，形成的光波导101中第一子光波导101a和第二子光波导101b的厚度不相同。此外，实施例一对于第一子光波导101a沿远离第三子光波导101c的方向宽度不进行限定，可以是宽度逐渐减小，也可以是宽度逐渐增大；当然还可以宽度相同。而在实施例二中，第一子 光波导101a的至少另一部分沿远离第三子光波导101c的方向宽度逐渐减小，即在本实施例二中，第一子光波导101a沿靠近第二子光波导101b的方向和远离第二子光波导101b的方向宽度均逐渐减小。本实施例二提供的光芯片10，仅对于与实施例一不相同的部分进行介绍，对于与实施例一相同的部分不进行介绍，可以参考实施例一。
由于在本实施例二中，第一子光波导101a沿靠近第二子光波导101b的方向和远离第二子光波导101b的方向宽度均逐渐减小，而光芯片10的制备方法中，牺牲层104在光波导本体1010上的投影覆盖第一子光波导101a，因而牺牲层104在光波导本体1010上的上的投影的形状至少包括如图37所示的与光波导本体1010相交的两个斜边，分别为斜边a和斜边b。示例的，牺牲层104在衬底100上投影的形状可以为如图37所示的不规则的多边形。
在本实施例二中，由于最终形成的光波导101包括第一子光波导101a和第二子光波导101b，且第二子光波导101b的厚度大于第一子光波导101a的厚度，第一子光波导101a和第二子光波导101b的交界处形成台阶，因而实施例二形成的光波导101包括台阶，该台阶可以将光波导101分为层叠设置的两层光波导，如图38所示，分别为第一层光波导101d和第二层光波导101e，第一层光波导101d相对于第二层光波导101e靠近衬底100。
在此基础上，由于第一子光波导101a的至少部分沿远离第二子光波导101b的部分的方向逐渐减小，因而第一层光波导101d包括宽度逐渐减小的部分，即第一层光波导101d的至少部分的形状为楔形。同样的，由于第二子光波导101b的至少部分沿靠近第一子光波导101a的方向宽度逐渐减小，且第二子光波导101b的厚度大于第一子光波导101a的厚度，因而第二层光波导101e包括宽度逐渐减小的部分，即第二层光波导101e的至少部分的形状为楔形。基于此，可以看出，本实施例二形成的光波导101包括两层光波导101，且该两层光波导101的至少部分的形状为楔形，即本实施例二形成的光波导101为双层双斜切结构。
由于本实施例二形成的光波导101包括两层光波导，且该两层光波导的至少部分的形状为楔形，因而在光芯片10和光纤20耦合时，可以进一步增大光芯片10与光纤20耦合处的光场模斑，可以进一步降低耦合损耗和端口反射，从而进一步提高光波导101和光纤20的耦合效率，提高信号传输质量。
相关技术提供一种如图39所示的光芯片10，该光芯片10包括衬底100和设置在衬底100上的光波导101，该光波导101为双层结构，光波导101包括第一层光波导101d和第二层光波导101e，第一层光波导101d的厚度大于第二层光波导101e的厚度。由于相关技术在制备如图39所示的光波导101时，分别进行刻蚀形成第一层光波导101d和第二层光波导101e，而第一层光波导101d和第二层光波导101e都包括尖角，因而第一层光波导101d和第二层光波导101e尖角的部分容易断裂。而本实施例二通过对牺牲层104、位于牺牲层104下方的第一子光波导101a和第三子光波导101c同时进行刻蚀，利用牺牲层104将光波导本体1010需要刻蚀的尖端区域(即第三子光波导101c所在的区域)补充成没有尖端的区域，因而需要去除的第三子光波导101c会被完全去除掉，不存在残留，保留的第一子光波导101a的尖端不存在被刻断的风险及鼠齿现象，这样形成的第一层光波导101d和第二层光波导101e不存在被刻断的风险， 此外，因被刻蚀的部分和未被刻蚀掉的部分均不存在尖角区域，从而可以避免小线宽效应。
实施例三
实施例三和实施例一提供光芯片10的制备方法的不同之处在于，实施例三在第一介质层107上仅形成牺牲层104，未形成辅助图案105。实施例三提供的光芯片10的制备方法可以参考上述实施例一，且将实施例一中的步骤S14替换为步骤S30，将步骤S18替换为步骤S31。
S30、在第一介质层107上形成牺牲层104；如图17所示，牺牲层104在光波导本体1010上的投影覆盖第一子光波导101a，且不覆盖第二子光波导101b和第三子光波导101c。在步骤S30包括步骤S130和步骤S131的情况下，步骤S131替换为步骤S132，步骤S132包括：S132、对牺牲薄膜1031进行构图形成牺牲层104；牺牲层104在光波导本体1010上的投影覆盖第一子光波导101a，且不覆盖第二子光波导101b和第三子光波导101c。
此处，为了便于构图形成牺牲层104，牺牲层104的尺寸可以设置的较大，牺牲层104的形状以能覆盖第一子光波导101a，且便于构图为准。示例的，牺牲层104在衬底100上投影的形状可以为梯形、矩形、多边形、圆形、其它规则或不规则的形状等。图17中以牺牲层104为梯形为例。
S31、对牺牲层104和第三子光波导101c进行刻蚀，去除牺牲层104和第三子光波导101c。可以理解的是，由于实施例三在制备光芯片10的过程中，未形成辅助图案105，因而第三介质层110不包括第三通孔114。实施例三具有与实施例一相同的技术效果，可以参考上述实施例一的相关描述，此处不再赘述。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (21)

  1. 一种光芯片，其特征在于，包括：
    衬底；
    设置在所述衬底上的第一介质层；所述第一介质层包括第一通孔；
    填充在所述第一通孔内的光波导和第二介质层；
    其中，所述光波导在所述衬底上的投影呈条状，所述光波导包括第一子光波导，所述第一子光波导在所述衬底上的投影的至少部分的宽度逐渐减小；
    所述光波导与所述第一通孔的侧壁和所述第二介质层的侧面均接触，所述第二介质层的另一侧面与所述第一通孔的另一侧壁接触。
  2. 根据权利要求1所述的光芯片，其特征在于，所述光波导还包括与所述第一子光波导接触的第二子光波导；所述第一子光波导的至少部分沿远离所述第二子光波导的方向宽度逐渐减小。
  3. 根据权利要求2所述的光芯片，其特征在于，所述第一子光波导的厚度小于所述第二子光波导的厚度；
    其中，所述第二子光波导的至少部分沿靠近所述第一子光波导的方向宽度逐渐减小；所述第一子光波导的至少另一部分沿靠近所述第二子光波导的方向宽度逐渐减小。
  4. 根据权利要求1-3任一项所述的光芯片，其特征在于，所述光芯片还包括设置在所述第一介质层远离所述衬底一侧的第三介质层；
    所述第三介质层包括第二通孔；所述第二通孔在所述衬底上的投影覆盖所述第一子光波导、位于所述第一通孔内的所述第二介质层、以及所述第一介质层的部分在所述衬底上的投影；其中，所述第二通孔内填充有所述第二介质层。
  5. 根据权利要求4所述的光芯片，其特征在于，所述第三介质层还包括第三通孔；所述第三通孔内填充有所述第二介质层；
    其中，所述第三通孔在所述衬底上投影与所述光波导在所述衬底上的投影无重叠区域。
  6. 根据权利要求4或5所述的光芯片，其特征在于，所述第三介质层的材料和所述第一介质层的材料相同。
  7. 根据权利要求1-6任一项所述的光芯片，其特征在于，所述第一通孔在所述衬底上的投影为矩形。
  8. 根据权利要求1-7任一项所述的光芯片，其特征在于，所述光波导包括层叠设置的光波导层和保护层；
    所述光波导层相对于所述保护层靠近所述衬底。
  9. 根据权利要求8所述的光芯片，其特征在于，所述光波导层的材料包括氮化硅、氮氧化硅、硅、锗、锗化硅、磷化铟中的一种或多种；
    所述保护层的材料包括氧化硅。
  10. 根据权利要求1-9任一项所述的光芯片，其特征在于，所述第一介质层和所述第二介质层的材料包括氧化硅。
  11. 一种通信设备，其特征在于，包括光纤和如权利要求1-10任一项所述的光芯片；其中，所述光芯片中光波导与所述光纤耦合。
  12. 一种光芯片的制备方法，其特征在于，包括：
    在衬底上形成条状的光波导本体；
    在所述光波导本体远离所述衬底的一侧形成第一介质薄膜；
    对所述第一介质薄膜进行磨平处理形成第一介质层，所述光波导本体远离所述衬底的表面露出于所述第一介质层，以形成所述第一介质层内的第一通孔，所述光波导本体位于所述第一通孔内；
    在所述第一介质层上形成牺牲层；所述牺牲层在所述光波导本体上的投影覆盖所述光波导本体中第一子光波导，且不覆盖所述光波导本体中第三子光波导，所述第一子光波导的至少部分沿靠近所述第三子光波导的方向宽度逐渐减小；
    对所述牺牲层和所述第三子光波导进行刻蚀，去除所述牺牲层和所述第三子光波导，以形成光波导，所述光波导包括所述第一子光波导；
    在所述第一通孔内填充第二介质层；所述光波导与所述第一通孔的侧壁和所述第二介质层的侧面均接触，所述第二介质层的另一侧面与所述第一通孔的另一侧壁接触。
  13. 根据权利要求12所述的制备方法，其特征在于，所述光波导本体包括层叠设置的光波导层和保护层；所述光波导层相对于所述保护层靠近所述衬底；
    所述在所述第一介质层上形成牺牲层之后，所述对所述牺牲层和所述第三子光波导进行刻蚀之前，所述制备方法还包括：
    去除所述第三子光波导上的所述保护层。
  14. 根据权利要求13所述的制备方法，其特征在于，所述在所述第一介质层上形成牺牲层之后，去除所述第三子光波导上的保护层之前；所述制备方法还包括：在所述牺牲层上形成第二介质薄膜；
    所述去除所述第三子光波导上的保护层，包括：
    对所述第二介质薄膜进行刻蚀形成第三介质层，所述第三介质层包括第二通孔，所述牺牲层和所述第三子光波导露出于所述第二通孔；
    去除所述第三子光波导上的所述保护层；
    所述在所述第一通孔内填充第二介质层，包括：在所述第一通孔和所述第二通孔内填充所述第二介质层。
  15. 根据权利要求12-14任一项所述的制备方法，其特征在于，所述光波导本体还包括设置在所述第一子光波导远离所述第三子光波导一侧，且与所述第一子光波导接触的所述第二子光波导，所述第二子光波导不需要进行所述刻蚀。
  16. 根据权利要求15所述的制备方法，其特征在于，所述第一子光波导的至少另一部分沿远离所述第三子光波导的方向宽度逐渐减小，所述第二子光波导的至少部分沿靠近所述第一子光波导的方向宽度逐渐减小；
    所述对所述牺牲层和所述第三子光波导进行刻蚀，去除所述牺牲层和所述第三子光波导，包括：
    对所述牺牲层、位于所述牺牲层下方的所述第一子光波导和所述第三子光波导进行刻蚀，去除所述牺牲层、所述第一子光波导靠近所述牺牲层的部分以及所述第三子光波导，所述光波导包括所述第一子光波导和所述第二子光波导；所述第一子光波导的厚度小于所述第二子光波导的厚度。
  17. 根据权利要求12-16任一项所述的制备方法，其特征在于，所述在所述第一介质层上形成牺牲层，包括：
    所述在所述第一介质层上形成牺牲薄膜；
    对所述牺牲薄膜进行构图形成牺牲层和辅助图案；所述辅助图案在所述光波导本体上的投影与所述光波导本体无重叠区域；
    所述对所述牺牲层和所述第三子光波导进行刻蚀，去除所述牺牲层和所述第三子光波导，包括：
    对所述牺牲层、所述辅助图案和所述第三子光波导进行刻蚀，去除所述牺牲层、所述辅助图案和所述第三子光波导。
  18. 根据权利要求17所述的制备方法，其特征在于，所述对所述牺牲薄膜进行构图形成牺牲层和辅助图案之后，去除所述第三子光波导上的保护层之前；所述制备方法还包括：在所述牺牲层上形成第二介质薄膜；
    所述去除所述第三子光波导上的保护层，包括：
    对所述第二介质薄膜进行刻蚀形成第三介质层，所述第三介质层包括第二通孔和第三通孔，所述牺牲层和所述第三子光波导露出于所述第二通孔，所述辅助图案露出于所述第三通孔；
    去除所述第三子光波导上的所述保护层；
    所述在所述第一通孔内填充第二介质层，包括：在所述第一通孔、所述第二通孔和所述第三通孔内填充第二介质层。
  19. 根据权利要求12-18任一项所述的制备方法，其特征在于，所述光波导本体包括层叠设置的光波导层和阻挡层；所述光波导层相对于所述阻挡层靠近所述衬底；
    对所述第一介质薄膜进行磨平处理之后，在所述第一介质层上形成牺牲层之前；所述制备方法还包括：去除所述阻挡层。
  20. 根据权利要求12-19任一项所述的制备方法，其特征在于，所述光波导本体在所述衬底上投影的形状为矩形。
  21. 根据权利要求12-20任一项所述的制备方法，其特征在于，所述牺牲层的材料包括多晶硅、非晶硅、氮化硅、氮氧化硅中的一种或多种。
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