WO2023088001A1 - 射频驱动电路、射频开关及射频芯片 - Google Patents

射频驱动电路、射频开关及射频芯片 Download PDF

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WO2023088001A1
WO2023088001A1 PCT/CN2022/125446 CN2022125446W WO2023088001A1 WO 2023088001 A1 WO2023088001 A1 WO 2023088001A1 CN 2022125446 W CN2022125446 W CN 2022125446W WO 2023088001 A1 WO2023088001 A1 WO 2023088001A1
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transistor
output
radio frequency
gate
source
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PCT/CN2022/125446
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English (en)
French (fr)
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殷嘉程
郭嘉帅
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深圳飞骧科技股份有限公司
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Publication of WO2023088001A1 publication Critical patent/WO2023088001A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits

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  • the utility model relates to the technical field of wireless communication radio frequency chip design, in particular to a radio frequency driving circuit applied to a radio frequency switch, a radio frequency switch and a radio frequency chip.
  • the driving circuit in the related art can generate the required positive and negative voltage signals through the digital control signal, and it is necessary to maintain a high driving capability to maintain the stability of the positive and negative voltages and increase the speed of the switching action.
  • the frequency increases, incomplete switching occurs when the switching load is too high, resulting in adverse effects of leakage or incorrect function.
  • the utility model proposes a radio frequency driving circuit, radio frequency switch and radio frequency chip with good stability and simple structure.
  • the embodiment of the utility model provides a radio frequency drive circuit, including a digital circuit, a drive signal generation circuit and a latch circuit connected in sequence;
  • the digital circuit is used to generate a control signal after receiving an input signal, and output the control signal;
  • the driving signal generation circuit is used to receive the control signal and generate high level and low level and output it;
  • the latch circuit is used to reduce the low level to a negative voltage and output it.
  • the digital circuit includes a first inverter, a second inverter, a first NAND gate and a second NAND gate;
  • the input terminal of the first inverter is used as the input terminal of the digital circuit for connecting the input signal, and the output terminal of the first inverter is connected to the input terminal of the second inverter and the second NAND gate input;
  • the input end of the first NAND gate is connected to the output end of the second inverter and the output end of the second NAND gate respectively; the output end of the first NAND gate generates a first control signal and output;
  • the input end of the second NAND gate is connected to the output end of the first inverter and the output end of the first NAND gate respectively; the output end of the second NAND gate generates a second control signal and output;
  • the output terminal of the first NAND gate and the output terminal of the second NAND gate are jointly used as the output terminal of the digital circuit.
  • the driving signal generating circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a first diode and a second diode;
  • the gate of the first transistor and the gate of the second transistor are jointly used as the input terminal of the driving signal generating circuit, and are connected to the output terminal of the digital circuit to receive the control signal;
  • the first The source of the transistor and the source of the second transistor are respectively connected to a positive voltage source;
  • the drain of the first transistor is respectively connected to the input of the first diode and the source of the second transistor ;
  • the drain of the second transistor is used as the first output pole of the driving signal generating circuit, and is connected to the drain of the sixth transistor, and the gate of the second transistor is connected to the gate of the sixth transistor , the gate of the second transistor is connected to ground;
  • the source of the sixth transistor is connected to the drain of the fifth transistor, the source of the fifth transistor is connected to a negative voltage source, the gate of the fifth transistor is connected to the output of the second diode end connected;
  • the drain of the third transistor is respectively connected to the input terminal of the second diode and the source of the fourth transistor, and the drain of the fourth transistor is used as the second output of the driving signal generating circuit and connected to the drain of the eighth transistor, and the gate of the fourth transistor is connected to the gate of the eighth transistor and connected to ground;
  • the source of the eighth transistor is connected to the drain of the seventh transistor, the source of the seventh transistor is connected to the negative voltage source, the gate of the seventh transistor is connected to the first diode connected to the output of the tube.
  • the latch circuit includes a ninth transistor, a tenth transistor, an eleventh transistor and a twelfth transistor;
  • the source of the ninth transistor and the source of the tenth transistor are connected to a positive voltage source
  • the gate of the ninth transistor, the drain of the tenth transistor, the gate of the eleventh transistor, and the drain of the twelfth transistor are all connected to the output of the first diode end;
  • the gate of the tenth transistor, the drain of the ninth transistor, the gate of the twelfth transistor, and the drain of the eleventh transistor are all connected to the output of the second diode end;
  • Both the source of the eleventh transistor and the source of the twelfth transistor are connected to the negative voltage source.
  • the first transistor, the second transistor, the third transistor, the fourth transistor, the ninth transistor, and the tenth transistor are all PMOS transistors;
  • the fifth transistor, the The sixth transistor, the seventh transistor, the eighth transistor, the eleventh transistor and the twelfth transistor are all NMOS transistors.
  • the embodiment of the utility model also provides a radio frequency switch, including the above-mentioned radio frequency drive circuit provided by the embodiment of the utility model.
  • the embodiment of the utility model also provides a radio frequency chip, including the above-mentioned radio frequency switch provided by the embodiment of the utility model.
  • the radio frequency driving circuit of the present invention includes a digital circuit, a latch circuit and a driving signal generating circuit.
  • the input signal generates a control signal through a digital circuit, and the control signal controls the switch of the transistor in the driving signal generating circuit, so that the first output pole and the second output pole generate high level and low level respectively, and the latch circuit lowers the low level
  • the final output signal is used for the control of the radio frequency switch.
  • the speed of the radio frequency switch using the radio frequency drive circuit is effectively improved, and the stability is effectively improved.
  • FIG. 1 is a structural diagram of a radio frequency driving circuit provided by an embodiment of the present invention.
  • FIG. 1 is a structural diagram of a radio frequency driving circuit provided by an embodiment of the present invention.
  • the embodiment of the present invention provides a radio frequency drive circuit 100 , which includes a digital circuit 1 , a drive signal generation circuit 2 and a latch circuit 3 connected in sequence.
  • the digital circuit 1 is used for generating a control signal after receiving an input signal, and outputting the control signal.
  • the driving signal generating circuit 2 is used for receiving the control signal and generating high level and low level and outputting them.
  • the latch circuit 3 is used to reduce the low level to a negative voltage and output the final output signal for the control of the radio frequency switch. Not only is the structure simple and easy to implement, but also the radio frequency switch using the radio frequency drive circuit The speed and cut-off are effectively improved, thereby effectively improving the stability.
  • the digital circuit 1 includes a first inverter I1, a first inverter I2, a first NAND gate I3 and a first NAND gate I4.
  • the input end of the first inverter I1 is used as the input end of the digital circuit 1 for connecting the input signal, and the output end of the first inverter I1 is connected to the input end of the second inverter and the first An input terminal of the NAND gate I4.
  • the input end of the first NAND gate I3 is connected with the output end of the first inverter I2 and the output end of the first NAND gate I4 respectively; the output end of the first NAND gate I3 generates The first control signal is output.
  • the input end of the first NAND gate I4 is respectively connected with the output end of the first inverter I1 and the output end of the first NAND gate I3; the output end of the first NAND gate I4 generates The second control signal is output.
  • the output terminal of the first NAND gate I3 and the output terminal of the first NAND gate I4 are jointly used as the output terminal of the digital circuit.
  • the digital circuit 1 composed of the first inverter I1, the first inverter I2, the first NAND gate I3 and the first NAND gate I4, when the input signal CTRL received by the input terminal of the digital circuit 1 is When the level is high, the output end of the first NAND gate I3 generates a first control signal L which is low level, and the output end of the first NAND gate I4 generates a second control signal H which is high level.
  • the input signal CTRL is at a low level
  • the output terminal of the first NAND gate I3 generates a first control signal L which is at a high level VDD
  • the output terminal of the first NAND gate I4 produces a second control signal H as Low level GND.
  • the power terminals of all digital circuits 1 are connected to VDD, and the ground terminals are connected to GND.
  • the latch circuit 3 includes a ninth transistor MP5, a tenth transistor MP6, an eleventh transistor MN5 and a twelfth transistor MN6.
  • the source of the ninth transistor MP5 and the source of the tenth transistor MP6 are connected to a positive voltage source.
  • the gate of the ninth transistor MP5, the drain of the tenth transistor MP6, the gate of the eleventh transistor MN5, and the drain of the twelfth transistor MN6 are all connected to the first two The output terminal of the pole tube C1.
  • the gate of the tenth transistor MP6, the drain of the ninth transistor MP5, the gate of the twelfth transistor MN6, and the drain of the eleventh transistor MN5 are all connected to the second two The output terminal of the pole tube C2.
  • Both the source of the eleventh transistor MN5 and the source of the twelfth transistor MN6 are connected to the negative voltage source.
  • the eleventh transistor MN5 and the twelfth transistor MN6 when the drains of the eleventh transistor MN5 and the ninth transistor MP5 are at a high level VDD , the twelfth transistor MN6 is turned on, and the tenth transistor MP6 is turned off, so that the drains of the twelfth transistor MN6 and the tenth transistor MP6 are reduced to a low level VNEG, the eleventh transistor MN5 is turned off, and the ninth transistor MP5 conduction.
  • the eleventh transistor MN5 When the drains of the twelfth transistor MN6 and the tenth transistor MP6 are at a high level VDD, the eleventh transistor MN5 is turned on, and the ninth transistor MP5 is turned off, so that the drains of the eleventh transistor MN5 and the ninth transistor MP5 are lowered. is low level VNEG, the tenth transistor MN6 is turned off, and the tenth transistor MP6 is turned on.
  • the driving signal generation circuit includes a first transistor MP1, a second transistor MP2, a third transistor MP3, a fourth transistor MP4, a fifth transistor MN1, a sixth transistor MN2, a seventh transistor MN3, an eighth transistor MN4, a first two Diode C1 and second diode C2.
  • the gate of the first transistor MP1 and the gate of the second transistor MP2 are jointly used as the input terminal of the driving signal generating circuit, and are connected to the output terminal of the digital circuit to receive the control signal;
  • the source of the first transistor MP1 and the source of the second transistor MP2 are respectively connected to a positive voltage source; the drain of the first transistor MP1 is respectively connected to the input terminal of the first diode C1 and the Source of the second transistor MP2.
  • the drain of the second transistor MP2 is used as the first output pole of the driving signal generating circuit, and is connected to the drain of the sixth transistor MN2, and the gate of the second transistor MP2 is connected to the sixth transistor The gate of MN2, the gate of the second transistor MP2 is connected to ground.
  • the source of the sixth transistor MN2 is connected to the drain of the fifth transistor MN1, the source of the fifth transistor MN1 is connected to a negative voltage source, the gate of the fifth transistor MN1 is connected to the second two The output terminal of the pole tube C2 is connected.
  • the drain of the third transistor MP3 is respectively connected to the input terminal of the second diode C2 and the source of the fourth transistor MP4, and the drain of the fourth transistor is used as the driving signal generating circuit.
  • the second output electrode is connected to the drain of the eighth transistor MN4, and the gate of the fourth transistor MP4 is connected to the gate of the eighth transistor MN4 and connected to ground.
  • the source of the eighth transistor MN4 is connected to the drain of the seventh transistor MN3, the source of the seventh transistor MN3 is connected to the negative voltage source, and the gate of the seventh transistor MN3 is connected to the drain of the seventh transistor MN3.
  • the output terminal of the first diode C1 is connected.
  • the source of the second transistor MP2 is pulled up to the positive voltage VDD
  • the third transistor MP3 is turned off
  • the first diode C1 The drain of the twelfth transistor MN6 and the drain of the tenth transistor MP6 can be pulled up to the voltage of the positive voltage source VDD, and now the drain of the ninth transistor MP5 and the drain of the twelfth transistor MN5 are pulled down to Negative voltage VNEG, the fifth transistor MN1 is turned off, the seventh transistor MN3 is turned on, and the source of the eighth transistor MN4 is pulled down to the negative voltage VNEG.
  • the ground GND signal can make the second transistor MP2 and the eighth transistor MN4 turn on.
  • the drain of the second transistor MP2 is used as the first output pole SG of the driving signal generating circuit 2 to output a high level VDD
  • the drain of the fourth transistor MP4 is used as the first output of the driving signal generating circuit 2.
  • the output of the two output poles PG is low level VNEG.
  • the source of the fourth transistor MP4 is pulled up to VDD
  • the first transistor MP1 is turned off
  • the eleventh transistor MN5 can be turned on through the second diode C2
  • the drain and the drain of the ninth transistor MP5 are pulled up to VDD, at this time the drain of the twelfth transistor MN6 and the drain of the tenth transistor MP6 are pulled down to VNEG, the seventh transistor MN3 is turned off, and the fifth transistor MN1 is turned on, and the source of the sixth transistor MN2 is pulled down to VNEG.
  • the GND signal can make the fourth transistor MP4 and the sixth transistor MN2 turn on, and finally the first output pole SG outputs a low level VNEG, and the second The output pole PG output is high level VDD.
  • the high level, the positive voltage and the positive voltage source are represented by VDD
  • the low level, the negative voltage and the negative voltage source are represented by VNEG
  • GND represents the ground
  • the first transistor MP1, the second transistor MP2, the third transistor MP3, the fourth transistor MP4, the ninth transistor MP5 and the tenth transistor MP6 are all PMOS transistors .
  • the fifth transistor MN1 , the sixth transistor MN2 , the seventh transistor MN3 , the eighth transistor MN4 , the eleventh transistor MN5 and the twelfth transistor MN6 are all NMOS transistors.
  • the embodiment of the utility model also provides a radio frequency switch, including the above-mentioned radio frequency drive circuit provided by the embodiment of the utility model.
  • the embodiment of the utility model also provides a radio frequency chip, including the above-mentioned radio frequency switch provided by the embodiment of the utility model.
  • the radio frequency driving circuit of the present invention includes a digital circuit, a latch circuit and a driving signal generating circuit.
  • the input signal generates a control signal through a digital circuit, and the control signal controls the switch of the transistor in the driving signal generating circuit, so that the first output pole and the second output pole generate high level and low level respectively, and the latch circuit lowers the low level
  • the final output signal is used for the control of the radio frequency switch.
  • the speed of the radio frequency switch using the radio frequency drive circuit is effectively improved, and the stability is effectively improved.

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  • Computer Hardware Design (AREA)
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Abstract

本实用新型提供了一种射频驱动电路，包括依次连接的数字电路、驱动信号产生电路以及锁存电路；所述数字电路用于接收输入信号后产生控制信号，并将所述控制信号输出；所述驱动信号产生电路用于接收所述控制信号并产生高电平和低电平并输出；所述锁存电路用于将所述低电平降至负压并输出。本实用新型还提供一种射频开关及射频芯片。与现有技术相比，本实用新型的射频驱动电路、射频开关及射频芯片稳定性好且结构简单。

Description

射频驱动电路、射频开关及射频芯片 技术领域
本实用新型涉及无线通信射频芯片设计技术领域，尤其涉及一种运用于射频开关的射频驱动电路、射频开关及射频芯片。
背景技术
目前，无线通信系统中通常有很多输入输出端口，在工作时需要对各种输入输出信号进行切换，而射频开关中的驱动电路会直接影响到信号切换速度的好坏。
相关技术中的驱动电路可通过数字控制信号产生所需要的正、负电压信号，要保持较高的驱动能力来维持正负电压的稳定性以及提高开关动作的速度。然而，随着频率的提高，当开关负载太大时会出现切换不完全的情况，产生漏电或功能不正确的不良影响。
实用新型内容
针对以上相关技术的不足，本实用新型提出一种稳定性好且结构简单的射频驱动电路、射频开关及射频芯片。
为了解决上述技术问题，本实用新型实施例提供了一种射频驱动电路，包括依次连接的数字电路、驱动信号产生电路以及锁存电路；
所述数字电路用于接收输入信号后产生控制信号，并将所述控制信号输出；
所述驱动信号产生电路用于接收所述控制信号并产生高电平和低电平并输出；
所述锁存电路用于将所述低电平降至负压并输出。
优选的，所述数字电路包括第一反向器、第二反向器、第一与非 门及第二与非门；
所述第一反向器的输入端作为所述数字电路的输入端，用于连接输入信号，所述第一反向器的输出端连接至第二反相器的输入端和第二与非门的输入端；
所述第一与非门的输入端分别与所述第二反向器的输出端及所述第二与非门的输出端相连；所述第一与非门的输出端产生第一控制信号并输出；
所述第二与非门的输入端分别与所述第一反向器的输出端及所述第一与非门的输出端相连；所述第二与非门的输出端产生第二控制信号并输出；
所述第一与非门的输出端与所述第二与非门的输出端共同作为所述数字电路的输出端。
优选的，所述驱动信号产生电路包括第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管、第八晶体管、第一二极管以及第二二极管；
所述第一晶体管的栅极和所述第二晶体管的栅极共同作为所述驱动信号产生电路的输入端，并连接至所述数字电路的输出端以接收所述控制信号；所述第一晶体管的源极和所述第二晶体管的源极分别连接至正电压源；所述第一晶体管的漏极分别连接至所述第一二极管的输入端和所述第二晶体管的源极；
所述第二晶体管的漏极作为所述驱动信号产生电路的第一输出极，并连接至所述第六晶体管的漏极，所述第二晶体管栅极连接至所述第六晶体管的栅极，所述第二晶体管的栅极连接至接地；
所述第六晶体管的源极连接至所述第五晶体管的漏极，所述第五晶体管的源极连接至负电压源，所述第五晶体管栅极与所述第二二极管的输出端相连；
所述第三晶体管的漏极分别连接至所述第二二极管的输入端和所述第四晶体管的源极，所述第四晶体管的漏极作为所述驱动信号产生 电路的第二输出极，并与所述第八晶体管的漏极相连，所述第四晶体管的栅极与所述第八晶体管的栅极相连并连接至接地；
所述第八晶体管的源极与所述第七晶体管的漏极连接，所述第七晶体管的源极连接至所述负电压源，所述第七晶体管的栅极与所述第一二极管的输出端相连。
优选的，所述锁存电路包括第九晶体管、第十晶体管、第十一晶体管和第十二晶体管；
所述第九晶体管的源极和所述第十晶体管的源极连接至正电压源；
所述第九晶体管的栅极，所述第十晶体管的漏极，所述第十一晶体管的栅极，以及所述第十二晶体管的漏极均连接至所述第一二极管的输出端；
所述第十晶体管的栅极，所述第九晶体管的漏极，所述第十二晶体管的栅极，以及所述第十一晶体管的漏极均连接至所述第二二极管的输出端；
所述第十一晶体管的源极及所述第十二晶体管的源极均连接到所述负电压源。
优选的，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第九晶体管以及所述第十晶体管均为PMOS管；所述第五晶体管、所述第六晶体管、所述第七晶体管、所述第八晶体管、所述第十一晶体管以及所述第十二晶体管均为NMOS管。
本实用新型实施例还提供一种射频开关，包括本实用新型实施例提供的上述射频驱动电路。
本实用新型实施例还提供一种射频芯片，包括本实用新型实施例提供的上述射频开关。
与现有技术相比，本实用新型的射频驱动电路及运用该射频驱动电路的射频开关及射频芯片中，射频驱动电路包括数字电路、锁存电路以及驱动信号产生电路。输入信号经由数字电路产生控制信号，控 制信号控制驱动信号产生电路中晶体管的开关，使其第一输出极和第二输出极分别产生高电平和低电平，锁存电路则将低电平降至负压，最终输出信号用于射频开关的控制，不仅结构简单易实现，且使得运用该射频驱动电路的射频开关的导通与截止的速度有效提升，进而有效提高了稳定性。
附图说明
下面结合附图详细说明本实用新型。通过结合以下附图所作的详细描述，本实用新型的上述或其他方面的内容将变得更清楚和更容易理解。附图中：
图1为本实用新型实施例提供的射频驱动电路的结构图。
具体实施方式
下面结合附图详细说明本实用新型的具体实施方式。
在此记载的具体实施方式/实施例为本实用新型的特定的具体实施方式，用于说明本实用新型的构思，均是解释性和示例性的，不应解释为对本实用新型实施方式及本实用新型范围的限制。除在此记载的实施例外，本领域技术人员还能够基于本申请权利要求书和说明书所公开的内容采用显而易见的其它技术方案，这些技术方案包括采用对在此记载的实施例的做出任何显而易见的替换和修改的技术方案，都在本实用新型的保护范围之内。
以下各实施例的说明是参考附加的图式，用以例示本实用新型可用以实施的特定实施例。本实用新型所提到的方向用语，例如上、下、前、后、左、右、内、外、侧面等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本实用新型，而非用以限制本实用新型。
请参图1所示，为本实用新型实施例提供的射频驱动电路的结构图。本实用新型实施例提供了一种射频驱动电路100，包括依次连接的数字电路1、驱动信号产生电路2以及锁存电路3。
所述数字电路1用于接收输入信号后产生控制信号，并将所述控制信号输出。所述驱动信号产生电路2用于接收所述控制信号并产生高电平和低电平并输出。所述锁存电路3用于将所述低电平降至负压并输出，最终输出信号用于射频开关的控制，不仅结构简单易实现，且使得运用该射频驱动电路的射频开关的导通与截止的速度有效提升，进而有效提高了稳定性。
具体的，所述数字电路1包括第一反向器I1、第一反向器I2、第一与非门I3及第一与非门I4。
所述第一反向器I1的输入端作为所述数字电路1的输入端，用于连接输入信号，所述第一反向器I1的输出端连接至第二反相器的输入端和第一与非门I4的输入端。
所述第一与非门I3的输入端分别与所述第一反向器I2的输出端及所述第一与非门I4的输出端相连；所述第一与非门I3的输出端产生第一控制信号并输出。
所述第一与非门I4的输入端分别与所述第一反向器I1的输出端及所述第一与非门I3的输出端相连；所述第一与非门I4的输出端产生第二控制信号并输出。
所述第一与非门I3的输出端与所述第一与非门I4的输出端共同作为所述数字电路的输出端。
第一反向器I1、第一反向器I2、第一与非门I3及第一与非门I4共同组成的数字电路1中，当所述数字电路1的输入端接收的输入信号CTRL为高电平时，所述第一与非门I3的输出端产生第一控制信号L为低电平，所述第一与非门I4的输出端产生第二控制信号H为高电平。当输入信号CTRL为低电平时，所述第一与非门I3的输出端产生第一控制信号L为高电平VDD，所述第一与非门I4的输出端产生第二控制信号H为低电平GND。
需要说明的是，所有数字电路1的电源端连接VDD，地端连接GND。
所述锁存电路3包括第九晶体管MP5、第十晶体管MP6、第十一晶体管MN5和第十二晶体管MN6。
所述第九晶体管MP5的源极和所述第十晶体管MP6的源极连接至正电压源。
所述第九晶体管MP5的栅极，所述第十晶体管MP6的漏极，所述第十一晶体管MN5的栅极，以及所述第十二晶体管MN6的漏极均连接至所述第一二极管C1的输出端。
所述第十晶体管MP6的栅极，所述第九晶体管MP5的漏极，所述第十二晶体管MN6的栅极，以及所述第十一晶体管MN5的漏极均连接至所述第二二极管C2的输出端。
所述第十一晶体管MN5的源极及所述第十二晶体管MN6的源极均连接到所述负电压源。
第九晶体管MP5、第十晶体管MP6、第十一晶体管MN5和第十二晶体管MN6共同组成的所述锁存电路3中：当第十一晶体管MN5和第九晶体管MP5的漏极为高电平VDD时，第十二晶体管MN6导通，第十晶体管MP6断开，使第十二晶体管MN6和第十晶体管MP6的漏极降为低电平VNEG，第十一晶体管MN5断开，第九晶体管MP5导通。
当第十二晶体管MN6和第十晶体管MP6的漏极为高电平VDD时，第十一晶体管MN5导通，第九晶体管MP5断开，使第十一晶体管MN5和第九晶体管MP5的漏极降为低电平VNEG，第十晶体管MN6断开，第十晶体管MP6导通。
所述驱动信号产生电路包括第一晶体管MP1、第二晶体管MP2、第三晶体管MP3、第四晶体管MP4、第五晶体管MN1、第六晶体管MN2、第七晶体管MN3、第八晶体管MN4、第一二极管C1以及第二二极管C2。
所述第一晶体管MP1的栅极和所述第二晶体管MP2的栅极共同作为所述驱动信号产生电路的输入端，并连接至所述数字电路的输出 端以接收所述控制信号；所述第一晶体管MP1的源极和所述第二晶体管MP2的源极分别连接至正电压源；所述第一晶体管MP1的漏极分别连接至所述第一二极管C1的输入端和所述第二晶体管MP2的源极。
所述第二晶体管MP2的漏极作为所述驱动信号产生电路的第一输出极，并连接至所述第六晶体管MN2的漏极，所述第二晶体管MP2栅极连接至所述第六晶体管MN2的栅极，所述第二晶体管MP2的栅极连接至接地。
所述第六晶体管MN2的源极连接至所述第五晶体管MN1的漏极，所述第五晶体管MN1的源极连接至负电压源，所述第五晶体管MN1栅极与所述第二二极管C2的输出端相连。
所述第三晶体管MP3的漏极分别连接至所述第二二极管C2的输入端和所述第四晶体管MP4的源极，所述第四晶体管的漏极作为所述驱动信号产生电路的第二输出极，并与所述第八晶体管MN4的漏极相连，所述第四晶体管MP4的栅极与所述第八晶体管MN4的栅极相连并连接至接地。
所述第八晶体管MN4的源极与所述第七晶体管MN3的漏极连接，所述第七晶体管MN3的源极连接至所述负电压源，所述第七晶体管MN3的栅极与所述第一二极管C1的输出端相连。
第一晶体管MP1、第二晶体管MP2、第三晶体管MP3、第四晶体管MP4、第五晶体管MN1、第六晶体管MN2、第七晶体管MN3、第八晶体管MN4、第一二极管C1以及第二二极管C2共同组成的所述驱动信号产生电路2中：
第一控制信号L为低电平GND，第二控制信号H为高电平VDD时，二晶体管MP2的源极拉高至正电压VDD，第三晶体管MP3断开，通过第一二极管C1可使第十二晶体管MN6的漏极和第十晶体管MP6的漏极拉高到正电压源VDD的电压，此时第九晶体管MP5的漏极和第十二晶体管MN5的漏极被拉低至负电压VNEG，第五晶体管MN1断开，第七晶体管MN3导通，第八晶体管MN4的源极被拉低到负电 压VNEG，此时接地GND信号可使第二晶体管MP2和第八晶体管MN4导通，最终第二晶体管MP2的漏极作为所述驱动信号产生电路2的第一输出极SG输出为高电平VDD，所述第四晶体管MP4的漏极作为所述驱动信号产生电路2的第二输出极PG输出为低电平VNEG。
第二控制信号H为GND，第一控制信号L为VDD时，第四晶体管MP4的源极拉高至VDD，第一晶体管MP1断开，通过第二二极管C2可使第十一晶体管MN5的漏极和第九晶体管MP5的漏极拉高到VDD，此时第十二晶体管MN6的漏极与第十晶体管MP6的漏极被拉低至VNEG，第七晶体管MN3断开，第五晶体管MN1导通，第六晶体管MN2的源极被拉低到VNEG，此时GND信号可使第四晶体管MP4和第六晶体管MN2导通，最终第一输出极SG输出为低电平VNEG，第二输出极PG输出为高电平VDD。
需要说明的是，本实施方式中，高电平与正电压及正电压源均为VDD表示，低电平、负电压及负电压源均为VNEG表示，GND表示接地。
本实施方式中，所述第一晶体管MP1、所述第二晶体管MP2、所述第三晶体管MP3、所述第四晶体管MP4、所述第九晶体管MP5以及所述第十晶体管MP6均为PMOS管。
所述第五晶体管MN1、所述第六晶体管MN2、所述第七晶体管MN3、所述第八晶体管MN4、所述第十一晶体管MN5以及所述第十二晶体管MN6均为NMOS管。
本实用新型实施例还提供一种射频开关，包括本实用新型实施例提供的上述射频驱动电路。
本实用新型实施例还提供一种射频芯片，包括本实用新型实施例提供的上述射频开关。
与现有技术相比，本实用新型的射频驱动电路及运用该射频驱动电路的射频开关及射频芯片中，射频驱动电路包括数字电路、锁存电路以及驱动信号产生电路。输入信号经由数字电路产生控制信号，控 制信号控制驱动信号产生电路中晶体管的开关，使其第一输出极和第二输出极分别产生高电平和低电平，锁存电路则将低电平降至负压，最终输出信号用于射频开关的控制，不仅结构简单易实现，且使得运用该射频驱动电路的射频开关的导通与截止的速度有效提升，进而有效提高了稳定性。
需要说明的是，以上参照附图所描述的各个实施例仅用以说明本实用新型而非限制本实用新型的范围，本领域的普通技术人员应当理解，在不脱离本实用新型的精神和范围的前提下对本实用新型进行的修改或者等同替换，均应涵盖在本实用新型的范围之内。此外，除上下文另有所指外，以单数形式出现的词包括复数形式，反之亦然。另外，除非特别说明，那么任何实施例的全部或一部分可结合任何其它实施例的全部或一部分来使用。

Claims (7)

  1. 一种射频驱动电路，其特征在于，包括依次连接的数字电路、驱动信号产生电路以及锁存电路；
    所述数字电路用于接收输入信号后产生控制信号，并将所述控制信号输出；
    所述驱动信号产生电路用于接收所述控制信号并产生高电平和低电平并输出；
    所述锁存电路用于将所述低电平降至负压并输出。
  2. 根据权利要求1所述的射频驱动电路，其特征在于，所述数字电路包括第一反向器、第二反向器、第一与非门及第二与非门；
    所述第一反向器的输入端作为所述数字电路的输入端，用于连接输入信号，所述第一反向器的输出端连接至第二反相器的输入端和第二与非门的输入端；
    所述第一与非门的输入端分别与所述第二反向器的输出端及所述第二与非门的输出端相连；所述第一与非门的输出端产生第一控制信号并输出；
    所述第二与非门的输入端分别与所述第一反向器的输出端及所述第一与非门的输出端相连；所述第二与非门的输出端产生第二控制信号并输出；
    所述第一与非门的输出端与所述第二与非门的输出端共同作为所述数字电路的输出端。
  3. 根据权利要求1所述的射频驱动电路，其特征在于，所述驱动信号产生电路包括第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管、第八晶体管、第一二极管以及第二二极管；
    所述第一晶体管的栅极和所述第二晶体管的栅极共同作为所述驱动信号产生电路的输入端，并连接至所述数字电路的输出端以接收所 述控制信号；所述第一晶体管的源极和所述第二晶体管的源极分别连接至正电压源；所述第一晶体管的漏极分别连接至所述第一二极管的输入端和所述第二晶体管的源极；
    所述第二晶体管的漏极作为所述驱动信号产生电路的第一输出极，并连接至所述第六晶体管的漏极，所述第二晶体管栅极连接至所述第六晶体管的栅极，所述第二晶体管的栅极连接至接地；
    所述第六晶体管的源极连接至所述第五晶体管的漏极，所述第五晶体管的源极连接至负电压源，所述第五晶体管栅极与所述第二二极管的输出端相连；
    所述第三晶体管的漏极分别连接至所述第二二极管的输入端和所述第四晶体管的源极，所述第四晶体管的漏极作为所述驱动信号产生电路的第二输出极，并与所述第八晶体管的漏极相连，所述第四晶体管的栅极与所述第八晶体管的栅极相连并连接至接地；
    所述第八晶体管的源极与所述第七晶体管的漏极连接，所述第七晶体管的源极连接至所述负电压源，所述第七晶体管的栅极与所述第一二极管的输出端相连。
  4. 根据权利要求3所述的射频驱动电路，其特征在于，所述锁存电路包括第九晶体管、第十晶体管、第十一晶体管和第十二晶体管；
    所述第九晶体管的源极和所述第十晶体管的源极连接至正电压源；
    所述第九晶体管的栅极，所述第十晶体管的漏极，所述第十一晶体管的栅极，以及所述第十二晶体管的漏极均连接至所述第一二极管的输出端；
    所述第十晶体管的栅极，所述第九晶体管的漏极，所述第十二晶体管的栅极，以及所述第十一晶体管的漏极均连接至所述第二二极管的输出端；
    所述第十一晶体管的源极及所述第十二晶体管的源极均连接到所述负电压源。
  5. 根据权利要求4所述的射频驱动电路，其特征在于，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第九晶体管以及所述第十晶体管均为PMOS管；所述第五晶体管、所述第六晶体管、所述第七晶体管、所述第八晶体管、所述第十一晶体管以及所述第十二晶体管均为NMOS管。
  6. 一种射频开关，其特征在于，包括如权利要求1-5任意一项所述的射频驱动电路。
  7. 一种射频芯片，其特征在于，包括如权利要求6所述的射频开关。
PCT/CN2022/125446 2021-11-18 2022-10-14 射频驱动电路、射频开关及射频芯片 WO2023088001A1 (zh)

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102474242A (zh) * 2009-07-22 2012-05-23 高通股份有限公司 电平移位器和高电压逻辑电路
US20160126956A1 (en) * 2014-10-10 2016-05-05 Seong-Young Ryu Negative-level shifting circuit and a source driver and a display device using the circuit
CN105846810A (zh) * 2014-11-14 2016-08-10 瑞鼎科技股份有限公司 驱动电路的电平转换器
CN110875736A (zh) * 2018-08-29 2020-03-10 联咏科技股份有限公司 低功耗负压电平移位器
CN113050507A (zh) * 2021-03-26 2021-06-29 广州穗源微电子科技有限公司 一种应用于低电源电压射频开关的控制电路
CN216390968U (zh) * 2021-11-18 2022-04-26 深圳飞骧科技股份有限公司 射频驱动电路、射频开关及射频芯片

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102474242A (zh) * 2009-07-22 2012-05-23 高通股份有限公司 电平移位器和高电压逻辑电路
US20160126956A1 (en) * 2014-10-10 2016-05-05 Seong-Young Ryu Negative-level shifting circuit and a source driver and a display device using the circuit
CN105846810A (zh) * 2014-11-14 2016-08-10 瑞鼎科技股份有限公司 驱动电路的电平转换器
CN110875736A (zh) * 2018-08-29 2020-03-10 联咏科技股份有限公司 低功耗负压电平移位器
CN113050507A (zh) * 2021-03-26 2021-06-29 广州穗源微电子科技有限公司 一种应用于低电源电压射频开关的控制电路
CN216390968U (zh) * 2021-11-18 2022-04-26 深圳飞骧科技股份有限公司 射频驱动电路、射频开关及射频芯片

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