WO2023078064A1 - 射频开关正向偏置加速建立电路及射频开关 - Google Patents

射频开关正向偏置加速建立电路及射频开关 Download PDF

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WO2023078064A1
WO2023078064A1 PCT/CN2022/125445 CN2022125445W WO2023078064A1 WO 2023078064 A1 WO2023078064 A1 WO 2023078064A1 CN 2022125445 W CN2022125445 W CN 2022125445W WO 2023078064 A1 WO2023078064 A1 WO 2023078064A1
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terminal
radio frequency
frequency switch
circuit
transistor
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PCT/CN2022/125445
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English (en)
French (fr)
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苏俊华
郭嘉帅
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深圳飞骧科技股份有限公司
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Publication of WO2023078064A1 publication Critical patent/WO2023078064A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/04—Modifications for accelerating switching
    • H03K17/041—Modifications for accelerating switching without feedback from the output circuit to the control circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Definitions

  • the utility model relates to the technical field of wireless communication radio frequency switches, in particular to a radio frequency switch forward bias acceleration circuit and a radio frequency switch.
  • RF switches are widely used in wireless communication equipment, and are used in occasions where RF signals need to be turned on or off, such as transmitting and receiving switches, channel selection switches, tuning switches, and reversing switches.
  • wireless communication equipment usually uses silicon substrate-buried oxide layer-outer edge silicon (SOI) technology, and metal oxide field effect transistor (MOS) devices are grown on outer edge silicon to make radio frequency switch circuits.
  • SOI silicon substrate-buried oxide layer-outer edge silicon
  • MOS metal oxide field effect transistor
  • the normal voltage analog power supply of the RF switch is usually omitted, and only the low voltage digital power supply of the serial control interface is reserved. Therefore, the RF switch needs to use a low voltage power supply to provide bias for the RF device working at normal voltage.
  • the conversion power supply voltage usually uses a low-dropout linear regulator to stabilize the voltage at half of the normal voltage, and then uses a positive double charge pump to boost it to the required level of the RF device. Voltage.
  • the serial control interface will turn off all control circuits and only keep the power supply of the interface.
  • the RF switch automatically receives the serial After a long period of time after the enabling signal of the line control, the correct function cannot be provided, and the response speed is slow.
  • the utility model proposes a radio frequency switch forward bias acceleration circuit and radio frequency switch with small delay and fast response.
  • the embodiment of the utility model provides a radio frequency switch forward bias accelerated establishment circuit, including:
  • Enable signal input terminal used to connect external enable signal
  • a reference voltage generation circuit used to generate a reference voltage, the input end of the reference voltage generation circuit is connected to the enable signal input end, the power supply end of the reference voltage generation circuit is connected to the power supply voltage, and the reference voltage generation circuit
  • the ground terminal of is connected to ground;
  • a low-dropout linear regulator the input of the low-dropout linear regulator is respectively connected to the power supply voltage, the output terminal of the reference voltage generating circuit, and the enable signal input terminal;
  • the input terminal of the oscillator is connected to the enable signal input terminal, the power supply terminal of the oscillator is connected to a power supply voltage, and the ground terminal of the oscillator is connected to ground;
  • the first input of the positive double charge pump is connected to the output of the oscillator, and the second input of the positive double charge pump is connected to the low dropout linear the output terminal of the voltage regulator, the ground terminal of the positive double charge pump is connected to the ground;
  • the high voltage bias output terminal is connected to the output terminal of the positive double charge pump
  • a bias voltage stabilizing capacitor the positive electrode of the bias voltage stabilizing capacitor is connected to the output terminal of the positive double charge pump, and the negative electrode of the bias voltage stabilizing capacitor is connected to ground;
  • a logic inversion detection circuit the input terminal of the logic inversion detection circuit is connected to the enable signal input end, the power supply terminal of the logic inversion detection circuit is connected to the power supply voltage, and the ground terminal of the logic inversion detection circuit is connected to to ground;
  • the acceleration establishment circuit includes an acceleration pull-up transistor and a diode, the gate of the acceleration pull-up transistor is connected to the output terminal of the logic inversion detection circuit, and the source of the acceleration pull-up transistor is connected to the The power supply voltage, the drain of the acceleration pull-up transistor is connected to the positive terminal of the diode, and the negative terminal of the diode is connected to the output terminal of the positive double charge pump.
  • the acceleration pull-up transistor is a PMOSFET triode.
  • the low dropout linear voltage regulator includes a dual operational amplifier, a power transistor, a first inductor and a second inductor; the drain of the power transistor is connected in series with the first inductor and the second inductor in sequence and then connected to Grounded, and the drain of the power transistor is used as the output terminal of the low dropout linear voltage regulator, the source of the power transistor is connected to the power supply voltage, and the gate of the power transistor is connected to the dual operation
  • the output terminal of the amplifier; the first operational amplifier of the dual operational amplifier is connected between the first inductance and the second inductance, and the first operational amplifier inverting input terminal of the dual operational amplifier is connected To the output end of the reference voltage generation circuit, the second op-amp input end of the dual operational amplifier is connected to the enable signal input end, and the power supply end of the dual operational amplifier is connected to the power supply voltage,
  • the ground terminals of the dual operational amplifiers are connected to ground.
  • the radio frequency switch forward bias acceleration establishment circuit also includes a reference voltage stabilizing capacitor, the anode of the reference voltage stabilizing capacitor is connected to the output terminal of the low dropout linear regulator, and the reference voltage stabilizing The second output end of the piezoelectric capacitor is connected to ground.
  • the power transistor is a PMOSFET transistor.
  • the embodiment of the utility model also provides a radio frequency switch, which includes the circuit for accelerating the establishment of the forward bias of the radio frequency switch provided by the embodiment of the utility model.
  • an acceleration establishment circuit is arranged, and the acceleration establishment circuit includes an acceleration pull-up transistor and a diode, and the gate of the acceleration pull-up transistor The pole is connected to the output terminal of the logic inversion detection circuit, the source of the accelerated pull-up transistor is connected to the power supply voltage, the drain of the accelerated pull-up transistor is connected to the positive terminal of the diode, and the diode The negative end of the negative terminal is connected to the output terminal of the positive double charge pump, so that the logic inversion detection circuit detects the inversion of the enable signal, thereby outputting a pulse of a certain length as the signal to start the acceleration circuit.
  • Fig. 1 is the circuit schematic diagram of the radio frequency switch forward bias accelerating the establishment circuit of the related art
  • FIG. 2 is a schematic diagram of voltage signal changes of a radio frequency switch forward bias acceleration and establishment circuit in the related art
  • Fig. 3 is the schematic circuit diagram of the radio frequency switch forward bias acceleration circuit provided by the embodiment of the present invention.
  • Fig. 4 is a schematic diagram of voltage signal changes of the radio frequency switch forward bias accelerated establishment circuit provided by the embodiment of the present invention.
  • FIG. 3 is a circuit diagram of a radio frequency switch forward bias acceleration circuit provided by an embodiment of the present invention.
  • the utility model provides a radio frequency switch forward bias acceleration circuit 100, comprising: an enable signal input terminal Ein, a reference voltage generating circuit 1, a low dropout linear voltage regulator 2, an oscillator 3, and a forward double charge pump 4 , high voltage bias output terminal Vout, bias voltage stabilizing capacitor C1 , logic inversion detection circuit 5 and acceleration establishment circuit 6 .
  • the enable signal input terminal Ein is used for connecting an external enable signal.
  • the reference voltage generation circuit 1 is used to generate a reference voltage, the input end of the reference voltage generation circuit 1 is connected to the enable signal input end, the power supply end of the reference voltage generation circuit 1 is connected to the power supply voltage Vcc, and the reference voltage generation circuit 1 is connected to the power supply voltage Vcc.
  • the ground terminal of the voltage generating circuit 1 is connected to the ground.
  • the input of the low dropout linear regulator 2 is respectively connected to the power supply voltage Vcc, the output terminal of the reference voltage generating circuit 1, and the enable signal input terminal Ein.
  • the low dropout linear regulator 2 includes a dual operational amplifier 21, a power transistor Q1, a first inductor L1 and a second inductor L2.
  • the power transistor Q1 is a PMOSFET triode.
  • the drain of the power transistor Q1 is sequentially connected to the ground after connecting the first inductor L1 and the second inductor L2 in series, and the drain of the power transistor Q1 is used as the output terminal of the low dropout linear regulator 2 .
  • the source of the power transistor Q1 is connected to the power supply voltage Vcc.
  • the gate of the power transistor Q1 is connected to the output terminal of the dual operational amplifier 21 .
  • the first operational amplifier non-inverting input terminal of the dual operational amplifier 21 is connected between the first inductor L1 and the second inductor L2, and the first operational amplifier inverting input terminal of the dual operational amplifier 21 is connected to The output terminal of the reference voltage generating circuit 1, the second operational amplifier non-inverting input terminal of the dual operational amplifier 21 is connected to the enable signal input terminal Ein, and the power supply terminal of the dual operational amplifier 21 is connected to the The power supply voltage Vcc, the ground terminal of the dual operational amplifier 21 is connected to the ground.
  • the input terminal of the oscillator 3 is connected to the enable signal input terminal Ein, the power supply terminal of the oscillator 3 is connected to the power supply voltage Vcc, and the ground terminal of the oscillator 3 is connected to ground.
  • the first input end of the positive double charge pump 4 is connected to the output end of the oscillator 3, and the second input end of the positive double charge pump 4 is connected to the low dropout linear voltage regulator 2
  • the output terminal of the positive double charge pump 4 is connected to the ground.
  • the high voltage bias output terminal Fout is connected to the output terminal of the forward double charge pump 4 .
  • the anode of the bias voltage stabilizing capacitor C1 is connected to the output terminal of the forward double charge pump 4 , and the cathode of the bias voltage stabilizing capacitor C1 is connected to ground.
  • the input terminal of the logic inversion detection circuit 5 is connected to the enable signal input terminal Ein, the power supply terminal of the logic inversion detection circuit 5 is connected to the power supply voltage Vcc, and the ground terminal of the logic inversion detection circuit 5 is connected to to ground.
  • the acceleration establishment circuit 6 includes an acceleration pull-up transistor Q2 and a diode D, the gate of the acceleration pull-up transistor Q2 is connected to the output terminal of the logic inversion detection circuit 5, and the source of the acceleration pull-up transistor Q2 is connected to To the power supply voltage Vcc, the drain of the acceleration pull-up transistor Q2 is connected to the positive terminal of the diode D, and the negative terminal of the diode D is connected to the output terminal of the forward double charge pump 4 .
  • the acceleration pull-up transistor Q2 is a PMOSFET triode.
  • the radio frequency switch forward bias acceleration establishment circuit 100 further includes a reference voltage stabilizing capacitor C2, the anode of the reference voltage stabilizing capacitor C2 is connected to the low dropout linear regulator 2, which is connected to the drain of the power transistor Q1, and the second output terminal of the reference voltage stabilizing capacitor is connected to ground.
  • the logic inversion detection circuit 5 When the above-mentioned radio frequency switch forward bias accelerates the establishment circuit 100 to work, after the enable signal at the enable signal input terminal Ein is reversed, the reference voltage generating circuit 1, the low dropout linear regulator 2 and the oscillator 3 change from the off state to In the working state, before the three modules are started, the logic inversion detection circuit 5 outputs a pulse of a certain length as the signal for accelerating the establishment of the circuit 6 due to detection of the inversion of the enable signal.
  • the accelerated pull-up transistor Q2 After the starting signal is reversed, the accelerated pull-up transistor Q2 is turned on, and after deducting a diode D voltage drop, it charges the bias voltage stabilizing capacitor 7 of the forward double charge pump 4, making it work at a low voltage
  • the intermediate level can be obtained before the differential linear regulator 2 and the oscillator 3 work, and as the pulse of the logic inversion detection circuit 5 ends and the output of the low dropout linear regulator 2 tends to be normal, the forward double charge pump 4 It is only necessary to raise the output level on the basis of the middle level.
  • Figure 2 is a schematic diagram of the voltage signal change of the RF switch forward bias acceleration circuit of the related art
  • Figure 4 is the RF switch forward bias acceleration circuit provided by the embodiment of the present invention Schematic diagram of the voltage signal change.
  • Fig. 2 and Fig. 4 it can be seen that the stable output time of the positive double charge pump 4 of the radio frequency switch forward bias acceleration establishment circuit of the present invention is obviously shortened, that is, the radio frequency switch forward bias acceleration establishment is effectively shortened.
  • the response time of the circuit and the radio frequency switch realizes the purpose of a simple circuit with a small delay and a fast response.
  • the output level is higher than the power supply voltage Vcc after normal operation.
  • the drain is connected in series
  • the diode D provides it with a unidirectional conduction characteristic. During normal operation, the diode D is in a reverse bias mode and cannot pass current, thereby improving circuit reliability.
  • the embodiment of the utility model also provides a radio frequency switch, which includes the radio frequency switch forward bias acceleration establishment circuit 100 provided in the embodiment of the utility model.
  • the technical effect achieved by the radio frequency switch is the same as that of the radio frequency switch forward bias acceleration
  • the establishment of the circuit 100 is the same and will not be repeated here.
  • an acceleration establishment circuit is arranged, and the acceleration establishment circuit includes an acceleration pull-up transistor and a diode, and the gate of the acceleration pull-up transistor The pole is connected to the output terminal of the logic inversion detection circuit, the source of the accelerated pull-up transistor is connected to the power supply voltage, the drain of the accelerated pull-up transistor is connected to the positive terminal of the diode, and the diode The negative end of the negative terminal is connected to the output terminal of the positive double charge pump, so that the logic inversion detection circuit detects the inversion of the enable signal, thereby outputting a pulse of a certain length as the signal to start the acceleration circuit.

Abstract

本实用新型提供了一种射频开关正向偏置加速建立电路，包括使能信号输入端、基准电压产生电路、低压差线性稳压器、振荡器、正向二倍电荷泵、高电压偏置输出端、偏置稳压电容、逻辑翻转检测电路以及加速建立电路，加速建立电路包括加速上拉晶体管和二极管，加速上拉晶体管的栅极连接至逻辑翻转检测电路的输出端，加速上拉晶体管的源极连接至电源电压，加速上拉晶体管的漏极连接至二极管的正极端，二极管的负极端连接至正向二倍电荷泵的输出端。本实用新型还提供一种射频开关，包括上述射频开关正向偏置加速建立电路。与现有技术相比，本实用新型的射频开关正向偏置加速建立电路及射频开关延迟小、响应速度快。

Description

射频开关正向偏置加速建立电路及射频开关 技术领域
本实用新型涉及无线通信射频开关技术领域，尤其涉及射频开关正向偏置加速建立电路及射频开关。
背景技术
射频开关广泛应用于无线通信设备中，使用在需要对射频信号进行导通或截止的场合，例如发射接收开关、通道选择开关、调谐开关、换向开关等。目前综合成本和性能的考量，无线通信设备中通常使用硅衬底-掩埋氧化层-外沿硅(SOI)技术，在外沿硅上生长金属氧化物场效应晶体管(MOS)器件来制作射频开关电路。现今的手持设备中为提高集成度，通常省略射频开关的常压模拟电源，仅保留串行控制接口的低压数字电源，因此射频开关需要使用低压电源为常压工作的射频器件提供偏置。
现有的射频开关中，如图1所示，转换电源电压通常使用低压差线性稳压器将电压稳定在常压的一半，然后用正向二倍电荷泵将其提升至射频器件所需的电压。同时为了低功耗的需求，在不需要该射频开关链路工作时串行控制接口将关闭所有的控制电路仅保留接口的供电。但是每当需要启动时，如图2所示，由于基准电压产生电路和低压差线性稳压器本身的响应慢，加上振荡器和二倍电荷泵的响应延迟，使得射频开关自收到串行控制的使能信号后有较长的时间内无法提供正确的功能，响应速度慢。
因此，有必要提供一种新的射频开关正向偏置加速建立电路及射频开关以解决上述技术问题。
实用新型内容
针对以上相关技术的不足，本实用新型提出一种延迟小、响应速度快的射频开关正向偏置加速建立电路及射频开关。
为了解决上述技术问题，本实用新型实施例提供了一种射频开关正向偏置加速建立电路，包括：
使能信号输入端，用于连接外部使能信号；
基准电压产生电路，用于产生基准电压，所述基准电压产生电路的输入端与所述使能信号输入端连接，所述基准电压产生电路的电源端与电源电压连接，所述基准电压产生电路的接地端连接至接地；
低压差线性稳压器，所述低压差线性稳压器的输入分别连接至所述电源电压、所述基准电压产生电路的输出端、所述使能信号输入端；
振荡器，所述振荡器的输入端连接至所述使能信号输入端，所述振荡器的电源端连接至电源电压，所述振荡器的接地端连接至接地；
正向二倍电荷泵，所述正向二倍电荷泵的第一输入端连接至所述振荡器的输出端，所述正向二倍电荷泵的第二输入端连接至所述低压差线性稳压器的输出端，所述正向二倍电荷泵的接地端连接至接地；
高电压偏置输出端，所述高电压偏置输出端连接至所述正向二倍电荷泵的输出端；
偏置稳压电容，所述偏置稳压电容的正极连接至所述正向二倍电荷泵的输出端，所述偏置稳压电容的负极连接至接地；
逻辑翻转检测电路，所述逻辑翻转检测电路的输入端连接至所述使能信号输入端，所述逻辑翻转检测电路的电源端连接至所述电源电压，所述逻辑翻转检测电路的接地端连接至接地；以及，
加速建立电路，所述加速建立电路包括加速上拉晶体管和二极管，所述加速上拉晶体管的栅极连接至所述逻辑翻转检测电路的输出端，所述加速上拉晶体管的源极连接至所述电源电压，所述加速上拉晶体管的漏极连接至所述二极管的正极端，所述二极管的负极端连接至所述正向二倍电荷泵的输出端。
优选的，所述加速上拉晶体管为PMOSFET三极管。
优选的，所述低压差线性稳压器包括双运算放大器、功率晶体管、第一电感和第二电感；所述功率晶体管的漏极依次串联所述第一电感和所述第二电感后连接至接地，且所述功率晶体管的漏极作为所述低压差线性稳压器的输出端，所述功率晶体管的源极连接至所述电源电压，所述功率晶体管的栅极连接至所述双运算放大器的输出端；所述双运算放大器的第一运放同向输入端连接至所述第一电感与所述第二电感之间，所述双运算放大器的第一运放反向输入端连接至所述基准电压产生电路的输出端，所述双运算放大器的第二运放同向输入端连接至所述使能信号输入端，所述双运算放大器的电源端连接至所述电源电压，所述双运算放大器的接地端连接至接地。
优选的，所述射频开关正向偏置加速建立电路还包括参考电压稳压电容，所述参考电压稳压电容的正极连接至所述低压差线性稳压器的输出端，所述参考电压稳压电容的第二输出端连接至接地。
优选的，所述功率晶体管为PMOSFET三级管。
本实用新型实施例还提供一种射频开关，其包括本实用新型实施例提供的上述射频开关正向偏置加速建立电路。
与现有技术相比，本实用新型的射频开关正向偏置加速建立电路及射频开关中，设置了加速建立电路，加速建立电路包括加速上拉晶体管和二极管，所述加速上拉晶体管的栅极连接至所述逻辑翻转检测电路的输出端，所述加速上拉晶体管的源极连接至所述电源电压，所述加速上拉晶体管的漏极连接至所述二极管的正极端，所述二极管的负极端连接至所述正向二倍电荷泵的输出端，从而，逻辑翻转检测电路由于检测到使能信号翻转，从而输出一定长度的脉冲作为加速电路启动的信号，该信号经过反相后使加速建立的所述加速上拉晶体管导通，在扣减一个二极管压降后，为电荷泵的偏置稳压电容充电，使其在低压差线性稳压器和振荡器工作之前即能得到中间电平，而随着逻辑翻转检测电路的脉冲结束和低压差线性稳压器的输出趋于正常，电荷泵仅需在中间电平的基础上抬升输出的电平即可，从而有效的缩短 了射频开关正向偏置加速建立电路及射频开关的响应时间，实现了简单电路达到延迟小，响应快的目的。
附图说明
下面结合附图详细说明本实用新型。通过结合以下附图所作的详细描述，本实用新型的上述或其他方面的内容将变得更清楚和更容易理解。附图中：
图1为相关技术的射频开关正向偏置加速建立电路的电路原理图；
图2为相关技术的射频开关正向偏置加速建立电路的电压信号变化示意图；
图3为本实用新型实施例提供的射频开关正向偏置加速建立电路的电路原理图；
图4为本实用新型实施例提供的射频开关正向偏置加速建立电路的电压信号变化示意图。
具体实施方式
下面结合附图详细说明本实用新型的具体实施方式。
在此记载的具体实施方式/实施例为本实用新型的特定的具体实施方式，用于说明本实用新型的构思，均是解释性和示例性的，不应解释为对本实用新型实施方式及本实用新型范围的限制。除在此记载的实施例外，本领域技术人员还能够基于本申请权利要求书和说明书所公开的内容采用显而易见的其它技术方案，这些技术方案包括采用对在此记载的实施例的做出任何显而易见的替换和修改的技术方案，都在本实用新型的保护范围之内。
以下各实施例的说明是参考附加的图式，用以例示本实用新型可用以实施的特定实施例。本实用新型所提到的方向用语，例如上、下、前、后、左、右、内、外、侧面等，仅是参考附加图式的方向。因此， 使用的方向用语是用以说明及理解本实用新型，而非用以限制本实用新型。
请参图3所示，为本实用新型实施例提供的射频开关正向偏置加速建立电路的电路图。本实用新型提供了一种射频开关正向偏置加速建立电路100，包括：使能信号输入端Ein、基准电压产生电路1、低压差线性稳压器2、振荡器3、正向二倍电荷泵4、高电压偏置输出端Vout、偏置稳压电容C1、逻辑翻转检测电路5以及加速建立电路6。
使能信号输入端Ein，用于连接外部使能信号。
基准电压产生电路1用于产生基准电压，所述基准电压产生电路1的输入端与所述使能信号输入端连接，所述基准电压产生电路1的电源端与电源电压Vcc连接，所述基准电压产生电路1的接地端连接至接地。
所述低压差线性稳压器2的输入分别连接至所述电源电压Vcc、所述基准电压产生电路1的输出端、所述使能信号输入端Ein。
具体的，本实施方式中，所述低压差线性稳压器2包括双运算放大器21、功率晶体管Q1、第一电感L1和第二电感L2。
本实施方式中，所述功率晶体管Q1为PMOSFET三级管。
所述功率晶体管Q1的漏极依次串联所述第一电感L1和所述第二电感L2后连接至接地，且所述功率晶体管Q1的漏极作为所述低压差线性稳压器2的输出端。
所述功率晶体管Q1的源极连接至所述电源电压Vcc。
所述功率晶体管Q1的栅极连接至所述双运算放大器21的输出端。
所述双运算放大器21的第一运放同向输入端连接至所述第一电感L1与所述第二电感L2之间，所述双运算放大器21的第一运放反向输入端连接至所述基准电压产生电路1的输出端，所述双运算放大器21的第二运放同向输入端连接至所述使能信号输入端Ein，所述双运算放大器21的电源端连接至所述电源电压Vcc，所述双运算放大器21的接地端连接至接地。
所述振荡器3的输入端连接至所述使能信号输入端Ein，所述振荡器3的电源端连接至电源电压Vcc，所述振荡器3的接地端连接至接地。
所述正向二倍电荷泵4的第一输入端连接至所述振荡器3的输出端，所述正向二倍电荷泵4的第二输入端连接至所述低压差线性稳压器2的输出端，所述正向二倍电荷泵4的接地端连接至接地。
所述高电压偏置输出端Fout连接至所述正向二倍电荷泵4的输出端。
所述偏置稳压电容C1的正极连接至所述正向二倍电荷泵4的输出端，所述偏置稳压电容C1的负极连接至接地。
所述逻辑翻转检测电路5的输入端连接至所述使能信号输入端Ein，所述逻辑翻转检测电路5的电源端连接至所述电源电压Vcc，所述逻辑翻转检测电路5的接地端连接至接地。
所述加速建立电路6包括加速上拉晶体管Q2和二极管D，所述加速上拉晶体管Q2的栅极连接至所述逻辑翻转检测电路5的输出端，所述加速上拉晶体管Q2的源极连接至所述电源电压Vcc，所述加速上拉晶体管Q2的漏极连接至所述二极管D的正极端，所述二极管D的负极端连接至所述正向二倍电荷泵4的输出端。
本实施方式中，所述加速上拉晶体管Q2为PMOSFET三极管。
更优的，本实施方式中，所述射频开关正向偏置加速建立电路100还包括参考电压稳压电容C2，所述参考电压稳压电容C2的正极连接至所述低压差线性稳压器2的输出端，即连接至所述功率晶体管Q1的漏极，所述参考电压稳压电容的第二输出端连接至接地。
上述射频开关正向偏置加速建立电路100工作时，使能信号输入端Ein的使能信号翻转后，基准电压产生电路1，低压差线性稳压器2以及振荡器3由关断状态变为工作状态，在这三个模块完成启动之前，逻辑翻转检测电路5由于检测到使能信号翻转，从而输出一定长度的脉冲作为加速建立电路6启动的信号，本实施方式中，作为加速建立 电路6启动的信号经过反相后使加速建立的加速上拉晶体管Q2导通，在扣减一个二极管D压降后，为正向二倍电荷泵4的偏置稳压电容7充电，使其在低压差线性稳压器2和振荡器3工作之前即能得到中间电平，而随着逻辑翻转检测电路5的脉冲结束和低压差线性稳压器2的输出趋于正常，正向二倍电荷泵4仅需在中间电平的基础上抬升输出的电平即可。
请结合图2和图4所示，图2为相关技术的射频开关正向偏置加速建立电路的电压信号变化示意图；图4为本实用新型实施例提供的射频开关正向偏置加速建立电路的电压信号变化示意图。由图2和图4比较可知，本实用新型的射频开关正向偏置加速建立电路的正向二倍电荷泵4的稳定输出时间明显缩短，即有效的缩短了射频开关正向偏置加速建立电路及射频开关的响应时间，实现了简单电路达到延迟小，响应快的目的。
由于加速建立的加速上拉晶体管Q2本身是源级和漏极等价的，在正常工作后输出电平要高于电源电压Vcc，为避免加速上拉晶体管Q2反向漏电，串联在漏极的二极管D为其提供单向导通特性，正常工作时该二极管D处于反向偏置模式，无法通过电流，从而提高了电路可靠性。
本实用新型实施例还提供一种射频开关，其包括本实用新型实施例提供的上述射频开关正向偏置加速建立电路100，所述射频开关实现的技术效果与上述射频开关正向偏置加速建立电路100相同，在此不再赘述。
与现有技术相比，本实用新型的射频开关正向偏置加速建立电路及射频开关中，设置了加速建立电路，加速建立电路包括加速上拉晶体管和二极管，所述加速上拉晶体管的栅极连接至所述逻辑翻转检测电路的输出端，所述加速上拉晶体管的源极连接至所述电源电压，所述加速上拉晶体管的漏极连接至所述二极管的正极端，所述二极管的负极端连接至所述正向二倍电荷泵的输出端，从而，逻辑翻转检测电 路由于检测到使能信号翻转，从而输出一定长度的脉冲作为加速电路启动的信号，该信号经过反相后使加速建立的所述加速上拉晶体管导通，在扣减一个二极管压降后，为电荷泵的偏置稳压电容充电，使其在低压差线性稳压器和振荡器工作之前即能得到中间电平，而随着逻辑翻转检测电路的脉冲结束和低压差线性稳压器的输出趋于正常，电荷泵仅需在中间电平的基础上抬升输出的电平即可，从而有效的缩短了射频开关正向偏置加速建立电路及射频开关的响应时间，实现了简单电路达到延迟小，响应快的目的。
需要说明的是，以上参照附图所描述的各个实施例仅用以说明本实用新型而非限制本实用新型的范围，本领域的普通技术人员应当理解，在不脱离本实用新型的精神和范围的前提下对本实用新型进行的修改或者等同替换，均应涵盖在本实用新型的范围之内。此外，除上下文另有所指外，以单数形式出现的词包括复数形式，反之亦然。另外，除非特别说明，那么任何实施例的全部或一部分可结合任何其它实施例的全部或一部分来使用。

Claims (6)

  1. 一种射频开关正向偏置加速建立电路，其特征在于，包括，
    使能信号输入端，用于连接外部使能信号；
    基准电压产生电路，用于产生基准电压，所述基准电压产生电路的输入端与所述使能信号输入端连接，所述基准电压产生电路的电源端与电源电压连接，所述基准电压产生电路的接地端连接至接地；
    低压差线性稳压器，所述低压差线性稳压器的输入分别连接至所述电源电压、所述基准电压产生电路的输出端、所述使能信号输入端；
    振荡器，所述振荡器的输入端连接至所述使能信号输入端，所述振荡器的电源端连接至电源电压，所述振荡器的接地端连接至接地；
    正向二倍电荷泵，所述正向二倍电荷泵的第一输入端连接至所述振荡器的输出端，所述正向二倍电荷泵的第二输入端连接至所述低压差线性稳压器的输出端，所述正向二倍电荷泵的接地端连接至接地；
    高电压偏置输出端，所述高电压偏置输出端连接至所述正向二倍电荷泵的输出端；
    偏置稳压电容，所述偏置稳压电容的正极连接至所述正向二倍电荷泵的输出端，所述偏置稳压电容的负极连接至接地；
    逻辑翻转检测电路，所述逻辑翻转检测电路的输入端连接至所述使能信号输入端，所述逻辑翻转检测电路的电源端连接至所述电源电压，所述逻辑翻转检测电路的接地端连接至接地；以及，
    加速建立电路，所述加速建立电路包括加速上拉晶体管和二极管，所述加速上拉晶体管的栅极连接至所述逻辑翻转检测电路的输出端，所述加速上拉晶体管的源极连接至所述电源电压，所述加速上拉晶体管的漏极连接至所述二极管的正极端，所述二极管的负极端连接至所述正向二倍电荷泵的输出端。
  2. 根据权利要求1所述的射频开关正向偏置加速建立电路，其特征在于，所述加速上拉晶体管为PMOSFET三极管。
  3. 根据权利要求1所述的射频开关正向偏置加速建立电路，其特征在于，所述低压差线性稳压器包括双运算放大器、功率晶体管、第一电感和第二电感；所述功率晶体管的漏极依次串联所述第一电感和所述第二电感后连接至接地，且所述功率晶体管的漏极作为所述低压差线性稳压器的输出端，所述功率晶体管的源极连接至所述电源电压，所述功率晶体管的栅极连接至所述双运算放大器的输出端；所述双运算放大器的第一运放同向输入端连接至所述第一电感与所述第二电感之间，所述双运算放大器的第一运放反向输入端连接至所述基准电压产生电路的输出端，所述双运算放大器的第二运放同向输入端连接至所述使能信号输入端，所述双运算放大器的电源端连接至所述电源电压，所述双运算放大器的接地端连接至接地。
  4. 根据权利要求3所述的射频开关正向偏置加速建立电路，其特征在于，还包括参考电压稳压电容，所述参考电压稳压电容的正极连接至所述低压差线性稳压器的输出端，所述参考电压稳压电容的第二输出端连接至接地。
  5. 根据权利要求3所述的射频开关正向偏置加速建立电路，其特征在于，所述功率晶体管为PMOSFET三级管。
  6. 一种射频开关，其特征在于，包括如权利要求1-5任意一项所述的射频开关正向偏置加速建立电路。
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