WO2023087368A1 - 一种基于时间交织adc的通道随机化电路及方法 - Google Patents

一种基于时间交织adc的通道随机化电路及方法 Download PDF

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WO2023087368A1
WO2023087368A1 PCT/CN2021/133566 CN2021133566W WO2023087368A1 WO 2023087368 A1 WO2023087368 A1 WO 2023087368A1 CN 2021133566 W CN2021133566 W CN 2021133566W WO 2023087368 A1 WO2023087368 A1 WO 2023087368A1
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channel
clock
output
data
time
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PCT/CN2021/133566
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English (en)
French (fr)
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王翊舟
刘璐
徐代果
朱璨
蒋和全
李儒章
王健安
陈光炳
付东兵
俞宙
张正平
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重庆吉芯科技有限公司
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Priority to US18/603,189 priority Critical patent/US20240223203A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/1205—Multiplexed conversion systems
    • H03M1/121—Interleaved, i.e. using multiple converters or converter parts for one channel
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
    • H03M1/0624—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by synchronisation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
    • H03M1/0634—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale
    • H03M1/0656—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale in the time domain, e.g. using intended jitter as a dither signal
    • H03M1/066—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale in the time domain, e.g. using intended jitter as a dither signal by continuously permuting the elements used, i.e. dynamic element matching
    • H03M1/0673—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale in the time domain, e.g. using intended jitter as a dither signal by continuously permuting the elements used, i.e. dynamic element matching using random selection of the elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise
    • H03M1/0836—Continuously compensating for, or preventing, undesired influence of physical parameters of noise of phase error, e.g. jitter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/1205—Multiplexed conversion systems
    • H03M1/121—Interleaved, i.e. using multiple converters or converter parts for one channel
    • H03M1/1215—Interleaved, i.e. using multiple converters or converter parts for one channel using time-division multiplexing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
    • H03M1/1245—Details of sampling arrangements or methods

Definitions

  • the invention relates to the technical field of analog-to-digital converters, in particular to a channel randomization circuit and method based on a time-interleaved ADC.
  • each channel in the multi-channel interleaving structure cannot be completely the same, which will lead to a mismatch between the channels.
  • the mismatch is mainly offset mismatch, gain mismatch, sampling time mismatch, bandwidth mismatch, etc.
  • SAR structure pipelined structure
  • this series of mismatches will greatly affect the dynamic performance of the ADC, making the effective number of bits (Effective Numbers of Bits, ENOB) and spurious-free dynamic range (Spurious-free Dynamic Range, SFDR) of the ADC )decline.
  • the present invention proposes a channel randomization circuit and method based on a time-interleaved ADC, which mainly solves the problem that existing circuits are difficult to achieve channel randomization without affecting the performance of the original time-interleaved ADC.
  • a channel randomization circuit based on time-interleaved ADC comprising:
  • the channel selection module is used to output M clock receiving control signals and encoded N data receiving control signals according to the main clock and the generated random number; wherein, M and N are positive integers, and M is greater than N;
  • a multi-phase clock distribution module configured to generate N multi-phase clocks according to the sampling master clock, and redistribute the multi-phase clocks according to the clock reception control signal, and output M redistributed clock signals;
  • Time-interleaved ADC module for outputting M output data and corresponding number of channel quantization completion signals according to the redistribution clock signal
  • An adjustable delay module configured to set the delay of the data receiving control signal
  • the timing distribution control module is respectively connected with the output end of the adjustable delay module and the output end of the time interleaving ADC module, and is used to control the The output data is output sequentially in chronological order.
  • the channel selection module includes: a pseudo-random number generation circuit and a channel selection circuit;
  • the pseudo-random number generation circuit receives the master clock and a group of random number output enable signals, and outputs a group of random number output signals; the channel selection circuit receives the random number output signal and the master clock, and outputs The clock reception control signal and the data reception control signal.
  • the channel selection circuit includes:
  • the clock status register has N addresses, each address represents a multi-phase clock, and the value stored in each address represents the access channel of the multi-phase clock corresponding to the address;
  • the channel status register has M addresses, each address represents a channel, and the value stored in each address represents the multi-phase clock connected to the channel of the corresponding address;
  • the free channel register is used to store channels that are not connected to the multi-phase clock
  • the channel stored in the corresponding address in the clock status register is exchanged with the channel stored in the free channel register;
  • each of the data receiving control signals includes K-bit binary coded signals, then 2 K is greater than or equal to M.
  • the multi-phase clock distribution module includes: a multi-phase clock generation circuit and a clock redistribution transmission gate array circuit;
  • the multi-phase clock generating circuit is formed by cascading N D flip-flops, and the output end of the last D flip-flop is connected to the input end of the first D flip-flop to form a loop, each of the The output terminals of the D flip-flop respectively output multi-phase clocks corresponding to different channels; and,
  • the clock redistribution transmission gate array circuit has M output terminals, and each of the output terminals is composed of M transmission switches connected in parallel, and each of the transmission switches includes an input terminal, an output terminal and a control terminal, and the transmission switch
  • the input terminal of the transmission switch receives one of the multi-phase clocks as an input
  • the control terminal of the transmission switch receives one bit of the clock reception control signal of the corresponding channel.
  • the transmission switch includes:
  • the transmission gate is composed of a PMOS transistor and an NMOS transistor, the source of the PMOS transistor is short-circuited with the source of the NMOS transistor as the input end of the transmission gate, and the drain of the PMOS transistor is connected to the NMOS transistor The drain of the transistor is short-circuited to be the output end of the transmission gate, and the gate of the NMOS transistor is used as the control end of the transmission gate to receive the clock reception control signal; and,
  • the input terminal of the inverter receives the clock receiving control signal, and the gate of the PMOS is connected to the output terminal of the inverter.
  • the time-interleaved ADC module includes M time-interleaved ADC circuits, and each of the time-interleaved ADC circuits outputs output data of one channel and a quantization completion signal;
  • the current time-interleaved ADC circuit When the redistribution clock input to the current time-interleaved ADC circuit is at a high level, if the channel quantization completion signal of the current time-interleaved ADC circuit is at a low level, then the current time-interleaved ADC circuit has not completed quantization, if the current If the channel quantization completion signal of the time-interleaved ADC circuit is at a high level, then the current time-interleaved ADC circuit has completed quantization.
  • the adjustable delay module includes a plurality of delay units, and each input signal is connected to one of the delay units;
  • the delay unit includes: a first inverter, a second inverter, an S A delay control NMOS tube and S delay capacitors, wherein, S corresponds to the number of digits of the delay control word of the input delay unit;
  • the output end of the first inverter is connected to the input end of the second inverter, the output end of the second inverter is used as the output end of the corresponding delay unit, and the output end of the first inverter is The input end is used as the input end of the corresponding delay unit; each of the delay control NMOS transistors is connected in parallel, and the drain of each of the delay control NMOS transistors is connected to the first inverter through one of the delay capacitors On the connection path between the output end of the MOS transistor and the input end of the second inverter, the gate of each delay control MOS transistor is connected to one bit of the delay control word.
  • the timing allocation control module includes:
  • the channel addressing decoder circuit is used to decode the delayed data receiving control signal into a thermometer code signal with M digits;
  • Data redistribution transmission gate array circuit used to receive control signals and the output data of the time-interleaved ADC module and the channel quantization completion signal according to the decoded data, and output the redistributed output data and the redistributed channel quantization completion signal;
  • a data output D flip-flop circuit configured to use the redistributed output data as input and the redistributed channel quantization completion signal as a clock to output reordered output data.
  • the data redistribution transmission gate array circuit is composed of a transmission switch array, the transmission switch includes an input terminal, an output terminal and a control terminal, and each input signal corresponds to one transmission switch; each time interleaving Each data bit of the output data of the ADC module is respectively connected to an input terminal of the transmission switch, and each decoded data receiving control signal is connected to R control terminals of the transmission switch, wherein R is the output the number of bits of data;
  • the channel quantization completion signal of each of the time-interleaved ADC modules is connected to an input terminal of the transmission switch, and each of the decoded data reception control signals is connected to the control terminal of the corresponding transmission switch;
  • the output end of the transmission switch outputs the redistributed output data or the redistributed channel quantization completion signal.
  • the data output D flip-flop circuit is composed of N groups of flip-flop arrays, each group of flip-flop arrays includes R D flip-flops, and the input end of each of the D flip-flops receives one of the reallocated One bit of the output data is used as an input, each group of the flip-flop array receives a channel quantization completion signal after the redistribution as a clock terminal input, and each group of the flip-flop array output outputs a said reordered Output Data.
  • the master clock has the same frequency as the sampling master clock; or, the frequency of the master clock is an integer frequency division multiple of the sampling master clock frequency and the frequency division multiple is equal to the redundant channel removal The number of remaining channels after is relatively prime.
  • a channel randomization method based on time-interleaved ADC comprising:
  • a channel randomization circuit and method based on time-interleaved ADC of the present invention has the following beneficial effects.
  • the AD accepts the data reception control signal too early and the data is output in advance.
  • the output data of the ADC whose order is scrambled is controlled to be output in time order, which effectively improves the spurious-free performance of the time-interleaved ADC. Dynamic Range.
  • FIG. 1 is a schematic diagram of channel randomization in an embodiment of the present invention.
  • FIG. 2 is a schematic diagram of channel randomization with redundant channels in an embodiment of the present invention.
  • FIG. 3 is a schematic circuit diagram of a channel randomization circuit based on a time-interleaved ADC in an embodiment of the present invention.
  • FIG. 4 is a logic function diagram of a channel selection circuit in an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of the operation process of the channel selection circuit on the clock status register and the channel status register in an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of the corresponding relationship between the output signal of the channel selection circuit and the value stored in the register in an embodiment of the present invention.
  • FIG. 7 is a schematic diagram of a multi-phase clock generation circuit in an embodiment of the present invention.
  • FIG. 8 is a circuit schematic diagram of a clock redistribution transmission gate array in an embodiment of the present invention.
  • FIG. 9 is a schematic diagram of a circuit structure of a delay unit in an embodiment of the present invention.
  • FIG. 10 is a schematic circuit diagram of a data redistribution transmission gate array in an embodiment of the present invention.
  • FIG. 11 is a schematic diagram of a data output D flip-flop circuit in an embodiment of the present invention.
  • FIG. 12 is a spectrum diagram of a time-interleaved ADC in an example without randomization after adding mismatch according to an embodiment of the present invention.
  • FIG. 13 is a spectrum diagram of a time-interleaved ADC in an example after adding mismatch and performing randomization according to an embodiment of the present invention.
  • FIG. 1 The conceptual diagram of channel randomization is shown in Figure 1, a four-channel time-interleaved ADC
  • the normal working sequence of the channel is channel 1, channel 2, channel 3, channel 4, channel 1... cyclically, but after the channel is randomized, the original working sequence of 1, 2, 3, 4 is disrupted and becomes 1, 4, 1, 3, 2... in random order.
  • the total number of channels remains the same, while disrupting the work order, it may happen that a certain channel has not completed the previous quantization, and the next quantization will be performed.
  • the conventional design idea is that the quantization time of a single channel is four times the quantization time of the entire time-interleaved ADC, and the regular channel work sequence can ensure that at least four quantization cycles are required after channel 1 starts quantization The time (the time when channels 1, 2, 3, and 4 complete quantization in turn), channel 1 starts quantizing the next input signal again. Once the working order of the channels is randomly disrupted, there may be a situation where channel 1 is used again in less than four cycles.
  • the randomization implementation circuit usually adds an additional channel to ensure that the quantization time of each channel is sufficient.
  • the specific principle is shown in Figure 2.
  • the channel that is more than 4 clock cycles away from the last quantization is marked as an idle channel and placed in the idle channel area to distinguish the channel that is being quantized from the channel that is not quantized (idle channel). Every time a new quantization is started, the channel that is more than 4 cycles away from the previous quantization is first marked as an idle channel and placed in the idle channel area, and then an idle channel is randomly selected from the idle channel area to start this quantization. It is guaranteed that at least two channels can be randomly selected in each quantization to achieve the effect of randomization.
  • the present invention provides a channel randomization circuit based on time-interleaved ADC.
  • the circuit includes the following modules: a channel selection module, which is used to output M clock reception control signals and encoded N data reception control signals according to the main clock and the generated random number; wherein, M and N are positive integers, and M is greater than N; the multiphase clock distribution module is used to generate N multiphase clocks according to the sampling master clock, and redistribute the multiphase clocks according to the clock receiving control signal, and output M redistributed clock signals; time The interleaving ADC module is used to output M output data and the corresponding number of channel quantization completion signals according to the redistribution clock signal; the adjustable delay module is used to set the delay size of the data receiving control signal; and, timing distribution A control module, connected to the output end of the adjustable delay module and the output end of the time-interleaved ADC module, for controlling the output data according to the delayed data reception control signal and the channel quantization completion signal
  • the channel selection module can include a pseudo-random number generation circuit and a channel selection circuit;
  • the multiphase clock distribution module includes: a multiphase clock generation circuit and a clock redistribution transmission gate array circuit; time-interleaved ADC
  • the module includes an M-channel time-interleaved ADC circuit;
  • the timing distribution control module includes: a channel address decoder circuit, a data redistribution transmission gate array circuit and a data output D flip-flop circuit.
  • the M value in the following description includes the number of channels of the multi-channel interleaved ADC under redundant channels.
  • the number of redundant channels can be configured according to actual application requirements, and there is no limitation here. The following embodiments are described only by taking the case where the number of redundant channels is 1 as an example, so the value of N is set to be the total number of channels minus 1 (ie M-1).
  • the pseudo-random number generating circuit is realized by a linear feedback shift register (LFSR), and its input is a digital circuit main clock CLK1 and a random number output enable signal RANDOM_EN, and the output is a random number output signal RANDOM_OUT, which can be output by a random number.
  • LFSR linear feedback shift register
  • the main clock of the digital circuit is normally input, if the RANDOM_EN signal is high level, RANDOM_OUT normally outputs pseudo-random numbers, and if the RANDOM_EN signal is low level, RANDOM_OUT only outputs low level and does not output random numbers.
  • the pseudo-random number generation circuit can be implemented by digital synthesis, because the randomness of the required pseudo-random number must be as large as possible to meet the requirements of performance optimization.
  • the taps of the LFSR are greater than 40, and the data generated by the LFSR is generally For a multi-bit signal with a bit width larger than the tap, the highest bit of the signal is used as the output of the pseudo-random number generation circuit.
  • Verilog to write digital circuits and implementing the LFSR in a comprehensive way will greatly save chip area and improve design efficiency.
  • the channel selection circuit can be realized by digital synthesis, and its input is the random number output signal RandomOut output by the pseudo-random number generation circuit and the main clock CLK1 of the digital circuit. Its output has two parts, one part is N+1 (that is, M) channel clock receiving control signal CH1_CLK_CONTROL ⁇ N:1> ⁇ CH M_CLK_CONTROL ⁇ N:1>, a total of M N-bit control signals; the other part is N Channel data receiving control signals CH1_DATA_CONTROL ⁇ K:1> ⁇ CHN_DATA_CONTROL ⁇ K:1>, a total of N K-bit control signals, K is the number of encoding bits, its value is determined by the number of channels M, and its purpose is to reduce the control signal
  • the number of transmission bits, the coding can be binary coding, the data reception control signal can be using thermometer code before coding, each signal has M bits, and K bits after coding.
  • the logic function of the channel selection circuit is shown in Figure 4.
  • the number of redundant channels is 1, so it is assumed that channel 1 to channel N are the number of channels required by the interleaved ADC without randomization, and the redundant channel is channel M.
  • the channel selection circuit mainly operates on three registers: the first one is the clock status register, which has N addresses, and each address represents a multi-phase clock (for example, address 1 represents multi-phase clock 1, and address N represents multi-phase clock N), since the multi-phase clock does not require redundancy, there are only N multi-phase clocks at most, so the maximum address of the clock status register is N.
  • each address represents the channel connected to the multi-phase clock indicated by the address (for example, CHANNEL1 stored in address 1 means that multi-phase clock 1 is connected to channel 1, and CHANNELN stored in address N means that multi-phase clock N is connected. in the channel N); the second is the channel status register, which has M addresses, and each address represents each channel (for example, address 1 represents channel 1, address N represents channel N, and address M represents channel M), since there are 1 redundant channels, so the number of addresses of channel status registers (M) is 1 more than the number of addresses of clock status registers (N).
  • the value stored in each address represents the multi-phase clock connected to the channel indicated by the address (for example, CLK1 stored in address 1 indicates that multi-phase clock 1 is connected to channel 1, and CLKN stored in address N indicates multi-phase clock N Access to channel N), due to the existence of redundant channels, the address of the channel status register will be one more than the number of multi-phase clocks, which will inevitably lead to a channel without multi-phase clock access, so it is represented by NOCLK (for example The NOCLK stored in the address M indicates that the channel M is not connected to the multi-phase clock and is in a redundant state), and in the actual circuit, the NOCLK is a constant low level; the third is the idle channel register, which stores no multi-phase clock connected input channel (for example, CHANNELM in the free channel register indicates that the M channel has no multi-phase clock access and is in an idle state).
  • the clock status register stores CHANNEL1 ⁇ CHANNELN in address 1 ⁇ address N sequentially.
  • the channel status register stores CLK1 ⁇ CLKN in address 1 ⁇ address N in sequence, and stores NOCLK in address M.
  • CHANNELM is stored in the free channel register. They indicate that when the system is powered on and starts to work, each multi-phase clock corresponds to a channel in sequence, and redundant channels without multi-phase clocks become idle channels.
  • the channel selection circuit operates on the address 1 of the clock status register. Specifically, the channel selection circuit controls the value stored in address 1 according to the random number input from the outside (that is, the random number output signal RandomOUT).
  • the channel selection circuit stores The value of is exchanged with the value stored in the free channel register.
  • the channel status register determines which two address values in the channel status register need to be exchanged according to the value in the clock status register address 1 that has been exchanged and the value in the free channel register (for example, CHANNEL1 in the clock status register address 1 Exchanged with the CHANNELM of the idle channel register, then the value stored in the address 1 of the channel status register and the value stored in the address M need to be exchanged), the process is shown in Figure 5, after the exchange is completed, wait for the next master clock to come.
  • RandomOut is low level, then no operation is performed on the clock status register, and the same channel status register remains unchanged to wait for the next master clock of the digital circuit.
  • the channel selection circuit performs an exchange operation on the address 2 of the clock status register.
  • the operation on address N is completed, the operation on address 1 is performed again when the next clock comes, and so on.
  • the channel selection circuit outputs corresponding signals according to the values stored in the clock status register and the channel status register. According to the channel status register, the channel selection circuit will output M N-bit thermometer code signals CH1_CLK_CONTROL ⁇ N:1> ⁇ CHM_CLK_CONTROL ⁇ N:1>.
  • the signal is N-bit thermometer code 00000...01, if the value of the channel status register is CLK2, then the signal is N-bit thermometer code 00000...10, and so on, if CLKN, then the signal is N-bit thermometer code 10000...00, if it is NOCLK, then the signal is N-bit all zero 00000...00.
  • the channel selection circuit will output N K-bit binary code signals CH1_DATA_CONTROL ⁇ K:1> ⁇ CH1N_DATA_CONTROL ⁇ K:1>, the value of K is determined by the number of channels M, and they satisfy the binary relationship, that is, two K times The power must be greater than or equal to M (for example, M is 8, K is at least 3; M is 17, K is at least 5, and so on), and these N K-bit binary code signals correspond to clock status register address 1 to address N respectively.
  • M for example, M is 8, K is at least 3; M is 17, K is at least 5, and so on
  • these N K-bit binary code signals correspond to clock status register address 1 to address N respectively.
  • Value if the value of the clock status register is CHANNEL1, then the signal is 00...01, if the value of the clock status register is CHANNEL2, then the signal is 00...10, and their corresponding relationship is shown in Figure 6.
  • the multi-phase clock generating circuit is formed by cascading N D flip-flops, and the output of the last D flip-flop is to be fed to the input of the first D flip-flop to form a loop. Its function is to provide N multi-phase clocks for the time-interleaved ADC circuit.
  • the input signal of the multi-phase clock generation circuit is the sampling main clock CLK_SAMPLE. The frequency of this main clock is often consistent with the sampling frequency of the interleaved ADC.
  • Its output signal is N multi-phase clock signals CLKIN ⁇ 1> ⁇ CLKIN ⁇ N>.
  • the CLK_SAMPLE signal is input to the clock input terminals of all D flip-flops, the signal output by the first D flip-flop data output terminal Dout is input to the data input terminal Din of the next D flip-flop, and the first D flip-flop data output terminal
  • the output signal of Dout is also used as the output CLKIN ⁇ 1> of the multi-phase clock generation circuit.
  • the signal output by the output terminal Dout of the second D flip-flop is input to the data input terminal Din of the third D flip-flop, and at the same time
  • the output signal of the data output terminal Dout of the two D flip-flops is also used as the output CLKIN ⁇ 2> of the multi-phase clock circuit generation circuit, and so on, until the last D flip-flop, the input signal of the last D flip-flop is the previous one
  • the signal output by the output terminal of the D flip-flop, the signal output by its output terminal Dout is input to the input terminal of the first D flip-flop, and the signal output by the output terminal of the last D flip-flop is also used as the multi-phase clock generation circuit.
  • the clock redistribution transmission gate array circuit is mainly composed of a transmission switch array, and the input of the clock redistribution transmission gate array circuit is the N-channel multiphase clock CLKIN ⁇ 1> ⁇ CLKIN ⁇ N generated by the multiphase clock generation circuit. >And the N+1 (that is, M) channel clock output by the channel selection circuit receives the control signal CH1_CLK_CONTROL ⁇ N:1> ⁇ CHM_CL K_CONTROL ⁇ N:1>, and the output of the clock redistribution transmission gate array circuit is the redistributed M channel Multi-phase clock CLKOUT ⁇ 1> ⁇ CLK OUT ⁇ M>.
  • the function of the clock redistribution transmission gate array circuit is to receive control signals according to the input M-channel clock, and distribute the input N-channel multi-phase clock to each time-interleaved ADC circuit.
  • the circuit structure of the clock redistribution transmission gate array circuit is shown in FIG. 8 .
  • the clock redistribution transmission gate array circuit is composed of a plurality of transmission switches, and the transmission switches include an input terminal, a control terminal and an output terminal.
  • the clock redistribution transmission gate array circuit has M output signals, and each output signal is composed of the outputs of N transmission switches connected in parallel.
  • the input terminals of the N transmission switches are respectively multi-phase clocks CLKIN ⁇ 1 > ⁇ CLKIN ⁇ N>, and the control terminal is different according to the output signal.
  • the control terminals are CH1_CLK_CONTROL ⁇ 1> ⁇ CH1_CLK_CONTROL ⁇ N>, if the output signal is CLKOUT ⁇ 2>, then the control terminals are CH2_CLK_CONTROL ⁇ 1> ⁇ CH2_CLK_CONTROL ⁇ N>,
  • the control signals are CHM_CLK_CONTROL ⁇ 1> ⁇ CHM_CLK_CONTROL ⁇ N> in sequence, and a total of N*M transmission switches are required.
  • the transmission switch is composed of a transmission gate and an inverter.
  • the transmission gate is composed of a PMOS transistor and an NMOS transistor whose source and source, drain and drain are short-circuited.
  • the control signal is directly connected to the gate of the transmission gate NMOS, and is also connected to the input terminal of the inverter, and the output of the inverter is connected to the gate of the transmission gate PMOS transistor.
  • the M-channel time-interleaved ADC circuit is a time-interleaved ADC containing M channels, and it does not refer to a specific type of ADC, as long as it contains M channels and can output the data of each channel And a time-interleaved ADC that quantizes the done signal is fine.
  • Its input signal is the redistributed M channel multiple clocks CLKOUT ⁇ 1> ⁇ CLKOUT ⁇ M> output by the clock redistribution transfer gate array circuit, and its output signal is the M channel quantization completion signal Q ⁇ M:1> and M channels output data DATA1OUT ⁇ DATAMOUT.
  • the channel quantization completion signal indicates whether the channel has completed quantization.
  • the channel output data refers to the output result of the ADC of each channel, which is usually multi-bit data, and the number of bits depends on the resolution of the ADC.
  • the adjustable delay module circuit is composed of an inverter, an NMOS transistor and a capacitor, and its input signal is the N-channel data receiving control signal CH1_DATA_CONTROL ⁇ K:1> ⁇ CHN_DATA_CONTROL ⁇ K output by the channel selection circuit :1> and the delay control word DELAY ⁇ S:1> used to control the delay size, S represents the number of digits of the delay control word, the more digits, the higher the delay control accuracy, its output The signal is the delayed N-channel data receiving control signal CH1_DATA_CONTROL_DELAY ⁇ K:1> ⁇ CHN_DATA_CONTROL_DELAY ⁇ K:1>.
  • the delay unit is composed of two inverters, S delay control NMOS transistors and S delay capacitors.
  • the single-bit input signal INPUT is connected to the input terminal of the inverter.
  • S capacitors are connected in parallel, and the other end of each capacitor is respectively connected to a delay control NMOS transistor drain terminal.
  • the delay Control the gate terminal of the NMOS transistor to access the corresponding delay control word.
  • the control word controls the delay control NMOS tubes of all delay units together.
  • the output terminal of the inverter is connected to the input terminal of the next inverter, and the output terminal of the next inverter is the output terminal of the delay unit.
  • the size and quantity of the delay capacitor together determine the range and precision of the delay, and the delay is controlled by controlling the delay control word.
  • the channel address decoder circuit is composed of logic gates, its input is the delayed N-channel data receiving control signal CH1_DATA_CONTROL_DELAY ⁇ K:1> ⁇ CHN_DATA_CONTROL_DELAY ⁇ K:1>, and the output is the decoded Coded N-channel data receiving control signals CH1_DATA_EN ⁇ M:1> ⁇ CHN_DATA_EN ⁇ M:1>.
  • the function of the channel address decoder circuit is to decode the binary N channel data receiving signal delayed by the adjustable delay module into a thermometer code with M digits.
  • the N-channel data receiving control signal is directly output using the M-bit thermometer code, the wiring of the layout will be too long and complicated. Therefore, the N-channel data receiving signal is first used.
  • the K-bit binary code output after the adjustable delay module circuit, reaches the position closer to the data output terminal, and then uses the channel address decoder circuit to decode the K-bit binary code into M-bit thermometer code, the channel address
  • the specific circuit of the decoder depends on the value of M.
  • the data redistribution transmission gate array circuit is mainly composed of a transmission switch array, and the structure of the transmission switch is the same as that of the clock redistribution transmission gate array circuit.
  • the input of the data redistribution transmission gate array circuit has three parts, the first part is the channel quantization completion signal Q ⁇ M:1> output by the M channel time-interleaved ADC circuit, which is M single-bit signals; the second part is The channel output data DATA1OUT ⁇ DATAMOUT output by the M-channel time-interleaved ADC circuit is M multi-bit signals, and the number of bits depends on the resolution of the time-interleaved ADC; the third part is the output of the channel address decoder circuit The decoded N-channel data receive control signals CH1_DATA_EN ⁇ M:1> ⁇ CHN_DATA_EN ⁇ M:1>.
  • the output of the data redistribution transmission gate array circuit has two parts.
  • the first part is the N-channel output data after redistribution, which is N multi-bit signals, and the number of bits depends on the resolution of the time-interleaved ADC;
  • the second part is the redistributed N-channel quantization completion signal QOUT ⁇ N:1>, which is N single-bit signals.
  • the function of the data redistribution transmission gate array circuit is to redistribute the output data of the input M channels and the channel quantization completion signal to the N channels.
  • the circuit diagram of the data redistribution transmission gate array circuit is shown in Figure 10.
  • the resolution (number of bits) of the time-interleaved ADC is R bits, so the input DATA1OUT ⁇ DATAMOUT is expressed as DATA1OUT ⁇ R:1> ⁇ DATAMOUT ⁇ R:1>, the N-channel output data after output redistribution is expressed as CH1OUT ⁇ R:1> ⁇ CHNOUT ⁇ R:1>.
  • the first part of the input signal DATA1OUT ⁇ R:1> ⁇ DATAMOUT ⁇ R:1> is connected to the input terminal of the transmission switch, and the input decoded N-channel data receiving control signal is connected to the control of different transmission switches according to the different input signals.
  • each control signal needs to be connected to the control terminals of R transmission switches.
  • the control signal CH1_DATA_EN ⁇ 1> is connected to the control end of the transmission switch with DATA1OUT ⁇ 1> ⁇ DATA1OUT ⁇ R> as the input signal
  • the control signal CH1_DATA_EN ⁇ 2> is connected to the transmission switch with DATA2OUT ⁇ 1> ⁇ DATA2OUT ⁇ R> as the input signal.
  • control terminal of the signal transmission switch ...the control signal CH1_DATA_EN ⁇ M> is connected to the control terminal of the transmission switch with DATAMOUT ⁇ 1> ⁇ DATAMOUT ⁇ R> as the input signal.
  • control signal CH2_DATA_EN ⁇ 1> to the control signal CHM_DATA_EN ⁇ 1> are respectively connected to the control terminal of the transmission switch with DATA1OUT ⁇ 1> ⁇ DATA1OUT ⁇ R> as the input signal
  • control signal CH2_DATA_EN ⁇ M > to the control signal CHM_DATA_EN ⁇ M> are respectively connected to the control end of the transmission switch with DATAMOUT ⁇ 1> ⁇ DATAMOUT ⁇ R> as the input signal, and so on.
  • the second part of the input signal QOUT ⁇ M:1> is similar to the first part of the input signal, and is also connected to the input of the transmission switch, and the input decoded N-channel data receiving control signal is also connected to the input signal according to different input signals.
  • the difference is that each control signal only needs to be connected to one control terminal of the transmission switch.
  • the control signal CH1_DATA_EN ⁇ 1> is connected to the control terminal of Q ⁇ 1> as the input signal
  • the control signal CH1_DATA_EN ⁇ 2> is connected to the control terminal of the transmission switch with Q ⁇ 2> as the input signal
  • Control signal CH1_DATA_EN ⁇ M> Connected to the control end of the transmission switch with Q ⁇ M> as the input signal.
  • control signals are the same, CH2_DATA_EN ⁇ M:1> to control signal CHM_DATA_EN ⁇ M:1> are respectively connected to the control terminals of the transmission switch with Q ⁇ M> to Q ⁇ 1> as the input signal, so the total required M *(R+1)*N transmission switches.
  • the first part of the output signal CH1OUT ⁇ R:1> ⁇ CHNOUT ⁇ R:1> is respectively connected to the output end of the corresponding transmission switch according to the input signal and control signal of the transmission switch, and each output signal must be connected to M transmission switches on the output terminal.
  • the output signals CH1OUT ⁇ 1> ⁇ CH1OUT ⁇ R> are respectively connected to DATAMOUT ⁇ 1> ⁇ DATA1OUT ⁇ 1>, DATAMOUT ⁇ 2> ⁇ DATA1OUT ⁇ 2>...DATAMOUT ⁇ R> ⁇ DATA1OUT ⁇ R> as input terminals
  • CH1_DATA_EN ⁇ M:1> is used as the output of the transmission switch of the control terminal
  • the output signals CH2OUT ⁇ 1> ⁇ CH2OUT ⁇ R> are respectively connected to DATAMOUT ⁇ 1> ⁇ DATA1OUT ⁇ 1>
  • ...DATAMOUT ⁇ R> ⁇ DATA1OUT ⁇ R> is used as the input terminal
  • CH2_DATA_EN ⁇ M:1> is used as the output terminal of the transmission switch of the control terminal
  • CHNOUT ⁇ 1> ⁇ CHNOUT ⁇ R> are respectively connected to the DATAMOUT ⁇ 1> ⁇ DATA1OUT ⁇ 1>, DATAMOUT ⁇ 2> ⁇ DATA1OUT ⁇ 2>...DATAMOUT ⁇ R> ⁇ DATA1
  • QOUT ⁇ 1> is connected to the output terminal of the control switch with Q ⁇ M> ⁇ Q ⁇ 1> as the input terminal and CH1_DATA_EN ⁇ M> ⁇ CH1_DATA_EN ⁇ 1> as the control terminal
  • QOUT ⁇ 2> is connected to the output terminal of the control switch controlled by Q ⁇ M> > ⁇ Q ⁇ 1> is used as the input terminal
  • CH2_DATA_EN ⁇ M> ⁇ CH2_DATA_EN ⁇ 1> is used as the output terminal of the control switch
  • QOUT ⁇ N> is connected to Q ⁇ M> ⁇ Q ⁇ 1> as the input terminal, CHM_DATA_EN ⁇ M> ⁇ CHM_DATA_EN ⁇ 1> as the output terminal of the control switch of the control terminal.
  • the data output D flip-flop circuit is mainly composed of a D flip-flop array, and its input signal is the redistributed N-channel quantization completion signal QOUT ⁇ N:1 output by the data redistribution transmission gate array circuit > and redistributed N-channel output data CH1OUT ⁇ CHNOUT, where QOUT ⁇ N:1> is an N-bit single-bit signal, CH1OUT ⁇ CHNOUT is a multi-bit signal, and the number of bits depends on the resolution of the time-interleaved ADC.
  • the output signal is the final output data CH1_OUT_DIFF ⁇ CHN_OUT_DIFF of N channels.
  • the structure of the data output D flip-flop circuit is shown in Figure 11, assuming that the resolution of the time-interleaved ADC is R (that is, the number of bits of N-channel output data after reallocation is R).
  • the input signals CH1OUT ⁇ R:1> ⁇ CHNOUT ⁇ R:1> are respectively connected to the Din input terminals (data input terminals) of R D flip-flops, and the quantization completion signals are correspondingly connected to each of the CH1OUT ⁇ R:1> ⁇ CHNOUT ⁇ R:1> is used as the CLK terminal of the input signal of the D flip-flop data input terminal (for example, QOUT ⁇ 1> is connected to the CLK terminal of the D flip-flop with CH1OUT ⁇ R:1> as the data input terminal, and QOUT ⁇ 2> is connected to the CLK terminal of the D flip-flop as the data input terminal.
  • CH2OUT ⁇ R:1> is used as the CLK terminal of the D flip-flop as the data input terminal, similarly, QOUT ⁇ N> is connected to the CLK terminal of the D flip-flop with CHNOUT ⁇ R:1> as the data input terminal), so the total required R *N D flip flops.
  • the output signals CH1OUT_DIFF ⁇ R:1> ⁇ CHNOUT_DIFF ⁇ R:1> are correspondingly connected to each data output port (Dout port) where CH1OUT ⁇ R:1> ⁇ CHNOUT ⁇ R:1> is used as the input signal of the D flip-flop data input port (For example, CH1OUT_DIFF ⁇ R:1> is respectively connected to the Dout end of the D flip-flop with CH1OUT ⁇ R:1> as the data input port, and CH2OUT_DIFF ⁇ R:1> is respectively connected to the Dout end with CH2OUT ⁇ R:1> as the data input port.
  • CHNOUT_DIFF ⁇ R:1> respectively corresponding to the Dout end of the D flip-flop with CHNOUT ⁇ R:1> as the data input end).
  • the master clock of the digital circuit is usually consistent with the sampling master clock (that is, has the same frequency).
  • the frequency of the sampling master clock is extremely high (above 1 GHz)
  • the digitally synthesized circuit cannot Carrying such a high frequency
  • the frequency of the main clock of the digital circuit can be reduced.
  • the reduced frequency needs to meet the following conditions: the first condition is that the reduced frequency must be an integral frequency division of the sampling main clock (for example, it is reduced to 2 of the sampling frequency.
  • the second condition is that the frequency division multiple must be mutually prime with the number of channels remaining after removing redundant channels (for example, the number of channels after removing redundant channels is 8 channel time
  • the frequency of the main clock of the digital circuit can be divided by 3 or 5, but it cannot be divided by 2 or 4, because 2 or 4 and 8 are not mutually prime).
  • the frequency of the main clock of the digital circuit can be reduced.
  • a sampling master clock is 4GHz, and the resolution is 12 bits (the number of bits of the ADC is redundant with 3 bits) , the number of actual output data is 15 bits), Vpp is 0.8V, and the total number of channels is 17 (16 interleaved channels and 1 redundant channel for randomization) time-interleaved SAR ADC, using the above time-based Channel randomization circuitry for interleaved ADCs.
  • the sampling main clock is determined to be 4GHz
  • the number of multiple clocks output by the multi-phase clock generation circuit is 16
  • the frequency-divided single-channel multi-phase clock speed is 250MHz
  • the digital circuit main clock is 800MHz.
  • the number of bits of LFSR in the pseudo-random number generation circuit is 42, and its tap is [41,20,1].
  • the channel selector outputs 17 channel clock reception control signals with 16 digits and 16 channel data reception control signals with 5 digits, the number of delay control words is 5, and the size of the control word and capacitor is adjusted to ensure the delay
  • the size is at least 1.25ns, the number of digits of the channel quantization completion signal is 17, the channel output data is 17 digits of 15 data, the number of channel quantization completion signals after redistribution is 16, and the channel output data after redistribution is 16 data with a digit of 15.
  • the data of the final output signal is data with 16 digits of 15.
  • the channel address decoding circuit Since there are 17 channels, the number of digits of the channel data receiving control signal is 5, use the lower 4 bits of the 5-bit binary code 1111 ⁇ 0000 to represent channel 16 to channel 1, and use the highest bit to represent channel 17 and non-channel 17, Therefore, in the channel address decoding circuit, a 4-16 decoder is used to convert the lower 4 bits into a 16-bit thermometer code, and at the same time, whether it is channel 17 is directly judged by whether the highest bit is 1. If it is 17, then The thermometer code of the 17th bit is 1, otherwise it is 0, the combination of the two completes the decoding, and converts the 5-bit binary code into a 17-bit thermometer code.
  • the present invention also provides a channel randomization method based on time-interleaved ADC, which is used to implement the channel randomization circuit based on time-interleaved ADC described in the foregoing circuit embodiments. Since the technical principle of the method embodiment is similar to that of the aforementioned circuit embodiment, the same technical details will not be described repeatedly.
  • the channel randomization method based on time-interleaved ADC includes: outputting M clock receiving control signals and encoded N data receiving control signals according to the master clock and generated random numbers; wherein, M and N is a positive integer, and M is greater than N; generate N multi-phase clocks according to the sampling master clock, and redistribute the multi-phase clocks according to the clock receiving control signal, and output M redistributed clock signals; according to the redistribution Distribute the clock signal to output M output data and the corresponding number of channel quantization completion signals; set the delay size of the data receiving control signal, and control the output data according to the delayed data receiving control signal and the channel quantization completion signal The output is sorted sequentially in chronological order.
  • a channel randomization circuit and method based on a time-interleaved ADC of the present invention while realizing channel randomization, does not affect the performance of the original time-interleaved ADC, and improves the performance in the case of mismatch by means of randomization.
  • SFDR of a time-interleaved ADC Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial application value.

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Abstract

本发明提出一种基于时间交织ADC的通道随机化电路及方法，包括：通道选择模块，用于根据主时钟和生成的随机数输出M个时钟接收控制信号和经过编码后的N个数据接收控制信号；多相时钟分配模块，用于根据采样主时钟生成N个多相时钟，并根据所述时钟接收控制信号对所述多相时钟进行重分配，输出M个重分配时钟信号；时间交织ADC模块，用于根据所述重分配时钟信号输出M个输出数据以及对应数量的通道量化完成信号；可调延时模块，用于设置所述数据接收控制信号延时大小；以及，时序分配控制模块，用于根据延时后的数据接收控制信号和所述通道量化完成信号控制所述输出数据按照时间顺序依次排列输出。

Description

一种基于时间交织ADC的通道随机化电路及方法 技术领域
本发明涉及模数转换器技术领域，尤其涉及一种基于时间交织ADC的通道随机化电路及方法。
背景技术
近年来，随着集成电路制造技术和5G技术等的不断发展，军用和民用领域对超高速高精度的高性能ADC的需求越来越多，为了实现超高速(1GHz采样率以上)的高分辨率(10Bit以上)ADC，时间交织结构由于其原理简单，性能优良逐渐成为了设计者的首选结构，它通过按照通道顺序分时复用的方式来提高ADC的整体采样率。
时间交织结构虽然能够极大的提升采样率，但是由于集成电路工艺的特性，多通道交织结构里面的每一个通道不可能做到完全的一模一样，这就会导致各个通道之间存在失配，常见的失配主要是失调失配、增益失配、采样时间失配、带宽失配等，不仅如此，在某些单通道ADC结构中(SAR结构、pipelined结构)同样存在着因为电容不匹配引起的通道间的失配，这一系列的失配会极大的影响ADC的动态性能，使ADC的有效位数(Effective Numbers of Bits，ENOB)和无杂散动态范围(Spurious-free Dynamic Range，SFDR)下降。
发明内容
鉴于以上现有技术存在的问题，本发明提出一种基于时间交织ADC的通道随机化电路及方法，主要解决现有电路难以在实现通道随机化的同时不影响原有时间交织ADC的性能。
为了实现上述目的及其他目的，本发明采用的技术方案如下。
一种基于时间交织ADC的通道随机化电路，包括：
通道选择模块，用于根据主时钟和生成的随机数输出M个时钟接收控制信号和经过编码后的N个数据接收控制信号；其中，M和N为正整数，且M大于N；
多相时钟分配模块，用于根据采样主时钟生成N个多相时钟，并根据所述时钟接收控制信号对所述多相时钟进行重分配，输出M个重分配时钟信号；
时间交织ADC模块，用于根据所述重分配时钟信号输出M个输出数据以及 对应数量的通道量化完成信号；
可调延时模块，用于设置所述数据接收控制信号延时大小；以及，
时序分配控制模块，分别与所述可调延时模块的输出端和所述时间交织ADC模块的输出端连接，用于根据延时后的数据接收控制信号和所述通道量化完成信号控制所述输出数据按照时间顺序依次排列输出。
可选地，所述通道选择模块包括：伪随机数产生电路和通道选择电路；
所述伪随机数产生电路接收所述主时钟和一组随机数输出使能信号，并输出一组随机数输出信号；所述通道选择电路接收所述随机数输出信号和所述主时钟，输出所述时钟接收控制信号和所述数据接收控制信号。
可选地，所述通道选择电路包括：
时钟状态寄存器，具有N个地址，每个地址代表一个多相时钟，每个地址中存放的值代表对应地址的多相时钟接入的通道；
通道状态寄存器，具有M个地址，每个地址代表一个通道，每个地址中存放的值代表对应地址的通道接入的多相时钟；以及，
空闲通道寄存器，用于存放没有接入多相时钟的通道；
当所述主时钟来临时，根据所述随机数输出信号判断是否将所述时钟状态寄存器中当前处理的地址中存放的通道与所述空闲通道寄存器中存放的通道进行交换；所述通道状态寄存器根据所述时钟状态寄存器寄存器和所述空闲通道寄存器的交换结果进行对应地址中存放值的交换；
根据所述通道状态寄存器中存放的值输出对应的时钟接收控制信号，同时，根据所述时钟状态寄存器中存放的值输出所述数据接收控制信号。
可选地，当所述随机数输出信号为高电平时，执行所述时钟状态寄存器中对应地址存放的通道与所述空闲通道寄存器中存放的通道的交换；
当所述随机数输出信号为低电平时，不执行交换动作。
可选地，记每个所述数据接收控制信号包含K位二进制编码信号，则2 K大于或等于M。
可选地，所述多相时钟分配模块包括：多相时钟产生电路和时钟重分配传输门阵列电路；
所述多相时钟产生电路，由N个D触发器级联构成，且最后一个所述D触 发器的输出端与第一个所述D触发器的输入端连接形成环路，每个所述D触发器的输出端分别输出对应不同通道的多相时钟；以及，
所述时钟重分配传输门阵列电路，具有M个输出端，每一个所述输出端由M个传输开关并联组成，每个所述传输开关包括输入端、输出端和控制端，所述传输开关的输入端接收一个所述多相时钟作为输入，所述传输开关的控制端接收对应通道的一位所述时钟接收控制信号。
可选地，所述传输开关包括：
传输门，由一个PMOS管和一个NMOS管组成，所述PMOS管的源极与所述NMOS管的源极短接作为所述传输门的输入端，所述PMOS管的漏极与所述NMOS管的漏极短接所为所述传输门的输出端，所述NMOS管的栅极作为所述传输门的控制端接收所述时钟接收控制信号；以及，
反相器，所述反相器的输入端接收所述时钟接收控制信号，所述PMOS的栅极与所述反相器的输出端连接。
可选地，所述时间交织ADC模块包括M个时间交织ADC电路，每个所述时间交织ADC电路输出一个通道的输出数据以及量化完成信号；
当输入当前时间交织ADC电路的重分配时钟为高电平时，若所述当前时间交织ADC电路的通道量化完成信号为低电平，则所述当前时间交织ADC电路未完成量化，若所述当前时间交织ADC电路的通道量化完成信号为高电平，则所述当前时间交织ADC电路已完成量化。
可选地，所述可调延时模块包括多个延时单元，每个输入信号对接一个所述延时单元；所述延时单元包括：第一反相器、第二反相器、S个延时控制NMOS管和S个延时电容，其中，S对应输入延时单元的延时控制字的位数；
所述第一反相器的输出端与所述第二反相器的输入端连接，所述第二反相器的输出端作为对应延时单元的输出端，所述第一反相器的输入端作为对应延时单元的输入端；各所述延时控制NMOS管并联，且每个所述延时控制NMOS管的漏极通过一个所述延时电容连接到所述第一反向器的输出端与所述第二反相器的输入端的连接路径上，每个所述延时控制MOS管的栅极接入一位所述延时控制字。
可选地，所述时序分配控制模块包括：
通道选址译码器电路，用于将经过延时后的数据接收控制信号译码成位数为M的温度计码信号；
数据重分配传输门阵列电路，用于根据经过译码后的数据接收控制信号和所述时间交织ADC模块的输出数据以及通道量化完成信号，输出重分配后的输出数据以及重分配后的通道量化完成信号；以及，
数据输出D触发器电路；用于以所述重分配后的输出数据作为输入，以所述重分配后的通道量化完成信号作为时钟，输出重新排序后的输出数据。
可选地，所述数据重分配传输门阵列电路由传输开关阵列构成，所述传输开关包括输入端、输出端和控制端，每个输入信号对应一个所述传输开关；每个所述时间交织ADC模块的输出数据的各数据位分别对接一个所述传输开关的输入端，每个经过译码后的数据接收控制信号接入R个所述传输开关的控制端，其中，R为所述输出数据的位数；
每个所述时间交织ADC模块的通道量化完成信号对接一个所述传输开关的输入端，每一个所述经过译码后的数据接收控制信号接入对应传输开关的控制端；
所述传输开关的输出端输出所述重分配后的输出数据或重分配后的通道量化完成信号。
可选地，所述数据输出D触发器电路由N组触发器阵列构成，每组触发器阵列包含R个D触发器，每个所述D触发器的输入端接收一个所述重分配后的输出数据中的一位作为输入，每组所述触发器阵列接收一个所述重分配后的通道量化完成信号作为时钟端输入，每组所述触发器阵列输出端输出一个所述重新排序后的输出数据。
可选地，所述主时钟与所述采样主时钟具有相同的频率；或者，所述主时钟的频率为所述采样主时钟频率的整数分频倍且所述分频倍数与去除冗余通道后的剩余通道数互质。
一种基于时间交织ADC的通道随机化方法，包括：
根据主时钟和生成的随机数输出M个时钟接收控制信号和经过编码后的N个数据接收控制信号；其中，M和N为正整数，且M大于N；
根据采样主时钟生成N个多相时钟，并根据所述时钟接收控制信号对所述多相时钟进行重分配，输出M个重分配时钟信号；
根据所述重分配时钟信号输出M个输出数据以及对应数量的通道量化完成信号；
设置所述数据接收控制信号延时大小，根据延时后的数据接收控制信号和所述通道量化完成信号控制所述输出数据按照时间顺序依次排列输出。
如上所述，本发明一种基于时间交织ADC的通道随机化电路及方法，具有以下有益效果。
通过引入延时避免AD过早接受数据接收控制信号导致数据提前输出，通过通道选择和多相时钟分配控制被打乱顺序的ADC输出数据按照时间顺序进行输出，有效提高时间交织ADC的无杂散动态范围。
附图说明
图1为本发明一实施例中通道随机化的示意图。
图2为本发明一实施例中含有冗余通道的通道随机化原理图。
图3为本发明一实施例中基于时间交织ADC的通道随机化电路的电路原理图。
图4为本发明一实施例中通道选择电路的逻辑功能图。
图5为本发明一实施例中通道选择电路对时钟状态寄存器和通道状态寄存器的操作过程示意图。
图6为本发明一实施例中通道选择电路输出信号与寄存器存放值的对应关系示意图。
图7为本发明一实施例中多相时钟产生电路原理图。
图8为本发明一实施例中时钟重分配传输门阵列电路原理图。
图9为本发明一实施例中延时单元的电路结构示意图。
图10为本发明一实施例中数据重分配传输门阵列的电路原理图。
图11为本发明一实施例中数据输出D触发器电路原理图。
图12为本发明一实施例中加入失配后未进行随机化的实例中时间交织ADC的频谱图。
图13为本发明一实施例中加入失配并进行随机化后的实例中时间交织ADC的频谱图。
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。需说明的是，在不冲突的情况下，以下实施例及实施例中的特征可以相互组合。
需要说明的是，以下实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图式中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。
为了解决失配对时间交织ADC性能的影响，学术界和工业界提出了非常多的校正算法来校正通道间的失配，然而校正的效果往往不理想，无法做到将所有的失配消除。在这个基础上，为了更进一步提高时间交织ADC的性能，就需要用到通道随机化这种方案，它通过打乱各个通道ADC的工作顺序，将通道间失配所引起的杂散平坦化到噪底来提高时间交织ADC的无杂散动态范围(SFDR)，并且不会影响时间交织ADC本身的有效位数(ENOB)，通道随机化概念图如图1所示，一个四通道时间交织ADC的正常工作顺序为通道1、通道2、通道3、通道4、通道1……循环进行，但是当经过通道随机化之后，原本的1、2、3、4工作顺序被打乱，变成了1、4、1、3、2……的随机顺序。当总的通道数不变的情况下，在打乱工作顺序的同时，有可能出现某通道还没有完成上一次量化，就又要进行下一次量化的情况。以四通道时间交织ADC为例，常规的设计思路为单通道的量化时间为整个时间交织ADC量化时间的4倍，规律的通道工作顺序能够保证在通道1开始量化之后，至少要四个量化周期的时间(1、2、3、4通道依次完成量化的时间)，1通道再次开始量化下一个输入信号。一旦随机打乱通道工作顺序，那么可能出现不到四个周期，1通道就再一次被使用的情况。为了避免这个问题，保证打乱各个单通道工作顺序的同时，每个单通道ADC的量化时间足够，随机化实现电路通常会额外增加一个通道，来保证每个通道的量化时间足够。其具体原理如图2所示，将距离上一次量化超过4个时钟周期的通道标记为空闲通道并放入空闲通道区，以此来区分量化中的通道和没有量化的通道(空闲通道)，每一次新的量化开启时，首先将距离上一次量化超过4个周期的通道 标记为空闲通道并放入空闲通道区，然后随机从空闲通道区中选取一个空闲通道开始这一次的量化。保证每一次量化中至少有两个通道可以随机选择，达到随机化的效果。
为了实现上述通道随机化功能，本发明提供一种基于时间交织ADC的通道随机化电路。电路包括以下几个模块：通道选择模块，用于根据主时钟和生成的随机数输出M个时钟接收控制信号和经过编码后的N个数据接收控制信号；其中，M和N为正整数，且M大于N；多相时钟分配模块，用于根据采样主时钟生成N个多相时钟，并根据所述时钟接收控制信号对所述多相时钟进行重分配，输出M个重分配时钟信号；时间交织ADC模块，用于根据所述重分配时钟信号输出M个输出数据以及对应数量的通道量化完成信号；可调延时模块，用于设置所述数据接收控制信号延时大小；以及，时序分配控制模块，分别与所述可调延时模块的输出端和所述时间交织ADC模块的输出端连接，用于根据延时后的数据接收控制信号和所述通道量化完成信号控制所述输出数据按照时间顺序依次排列输出。
请参阅图3，在一实施例中，通道选择模块可包括伪随机数产生电路和通道选择电路；多相时钟分配模块包括：多相时钟产生电路和时钟重分配传输门阵列电路；时间交织ADC模块包括M通道时间交织ADC电路；时序分配控制模块包括：通道选址译码器电路、数据重分配传输门阵列电路以及数据输出D触发器电路。
为了便于说明，后面叙述中的M值为包含冗余通道下多通道交织ADC的通道数量，冗余通道数量可根据实际应用需求进行配置，这里不作限制。以下实施例仅以冗余通道数量为1的情况为例进行阐述，因此设定N值为总通道数量减1(即M‐1)。
所述伪随机数产生电路采用线性反馈移位寄存器(LFSR)实现，它的输入为数字电路主时钟CLK1和随机数输出使能信号RANDOM_EN，输出为随机数输出信号RANDOM_OUT，该随机数输出信号可设置为1bit信号。当数字电路主时钟正常输入时，如果RANDOM_EN信号为高电平，RANDOM_OUT正常输出伪随机数，如果RANDOM_EN信号为低电平，RANDOM_OUT就只输出低电平，不输出随机数。伪随机数产生电路可采用数字综合实现，因为所需的伪随机数的随机性必须要尽可能的大才能满足性能优化的要求，通常该LFSR的抽头都会大于40， LFSR所产生的数据一般是位宽比抽头大的多bit信号，用该信号的最高位来当作伪随机数产生电路的输出。采用Verilog编写数字电路并通过综合的方式进行该LFSR的实现会极大的节约芯片面积并提高设计效率。
在一实施例中，通道选择电路可采用数字综合实现，它的输入为伪随机数产生电路输出的随机数输出信号RandomOut和数字电路主时钟CLK1。它的输出有两个部分，一部分为N+1(即M)通道时钟接收控制信号CH1_CLK_CONTROL<N:1>～CH M_CLK_CONTROL<N:1>，共M个N比特控制信号；另外一个部分为N通道数据接收控制信号CH1_DATA_CONTROL<K:1>～CHN_DATA_CONTROL<K:1>，共N个K比特控制信号，K为编码位数，它的值由通道数目M决定，它的目的是减小控制信号的传输位数，编码可采用二进制编码，编码前该数据接收控制信号可采用温度计码，每个信号有M位，编码后为K位。通道选择电路的逻辑功能如图4所示。通常冗余通道的数量为1，因此假定通道1～通道N为不随机化情况下交织ADC所需要的通道数量，冗余通道为通道M。该通道选择电路主要对三个寄存器进行操作：第一个是时钟状态寄存器，它有N个地址，每一个地址代表一个多相时钟(例如地址1代表多相时钟1，地址N代表多相时钟N)，由于多相时钟并不需要冗余，因此多相时钟最多只有N个，因此时钟状态寄存器的最大地址为N。每一个地址中存放的值代表该地址表示的多相时钟接入的通道(例如地址1中存放的CHANNEL1代表多相时钟1接到了通道1中，地址N中存放的CHANNELN代表多相时钟N接到了通道N中)；第二个是通道状态寄存器，它有M个地址，每一个地址代表各个通道(例如地址1代表通道1，地址N代表通道N，地址M代表通道M)，由于存在1个冗余通道，因此通道状态寄存器的地址数量(M个)比时钟状态寄存器的地址数量(N个)多1。每一个地址中存放的值代表该地址表示的通道接入的多相时钟(例如地址1中存放的CLK1表示多相时钟1接入到通道1上，地址N中存放的CLKN表示多相时钟N接入到通道N上)，由于存在冗余通道，因此通道状态寄存器的地址会比多相时钟的数目多一个，这会导致必然存在一个通道没有多相时钟接入，因此用NOCLK表示(例如地址M中存放的NOCLK表示通道M不接入多相时钟，处于冗余状态)，在实际电路中该NOCLK为恒定的低电平；第三个是空闲通道寄存器，它存放没有多相时钟接入的通道(例如空闲通道寄存器里面的CHANNELM表示M通道没有多相时钟接入，处于空闲状态)。
在初始状态下，时钟状态寄存器依次按照顺序存放CHANNEL1～CHANNELN在地址1～地址N里。通道状态寄存器依次按照顺序存放CLK1～CLKN在地址1～地址N里，并存放NOCLK在地址M里。空闲通道寄存器中存放CHANNELM。它们表示在系统上电开始工作时候，每一个多相时钟按照顺序依次对应一个通道，而冗余通道没有多相时钟对应成为空闲通道。当数字电路主时钟第一次来临时，通道选择电路对时钟状态寄存器的地址1进行操作。具体地，通道选择电路根据外部输入的随机数(即随机数输出信号RandomOUT)来控制地址1中存放的值，如果外部输入的随机数为高电平，那么通道选择电路就把地址1中存放的值与空闲通道寄存器中存放的值进行交换。与此同时，通道状态寄存器根据已经交换的时钟状态寄存器地址1中的值和空闲通道寄存器中的值来确定通道状态寄存器中哪两个地址的值需要交换(例如时钟状态寄存器地址1中的CHANNEL1和空闲通道寄存器的CHANNELM互换了，则通道状态寄存器的地址1中的值和地址M中存放的值需要交换)，该过程如图5所示，交换完毕后等待下一次主时钟来临。如果RandomOut为低电平，那么不对时钟状态寄存器进行任何操作，同样的通道状态寄存器也保持不变等待下一次数字电路主时钟。当数字电路主时钟第二次来临时，通道选择电路则对时钟状态寄存器的地址2进行交换操作，当地址N完成操作后，下一次时钟来临就又对地址1进行操作，如此不断循环。在三个寄存器不断变化的同时，通道选择电路根据时钟状态寄存器和通道状态寄存器存放的值输出对应的信号。根据通道状态寄存器，通道选择电路会输出M个N位温度计码信号CH1_CLK_CONTROL<N:1>～CHM_CLK_CONTROL<N:1>，这M个信号的值分别对应通道状态寄存器地址1～地址M中存放的值，如果通道状态寄存器的值为CLK1，那么该信号为N位温度计码00000…01，如果通道状态寄存器的值为CLK2，那么该信号为N位温度计码00000…10，以此类推，如果为CLKN，那么该信号为N位温度计码10000…00，如果为NOCLK，那么该信号为N位全零00000…00。根据时钟状态寄存器，通道选择电路会输出N个K位二进制码信号CH1_DATA_CONTROL<K:1>～CH1N_DATA_CONTROL<K:1>，K的值由通道数量M决定，它们满足二进制关系，即二的K次幂必须大于或等于M(例如M为8，K至少为3；M为17，K至少为5，以此类推)，这N个K位二进制码信号分别对应时钟状态寄存器地址1～地址N的值，如果时钟状态寄存器的值为CHANNEL1，那么该信号为00…01，如果时钟状态寄存器的值为CHANNEL2，那么该信号为00…10，它们的对应关系如图6所示。
请参阅图7，在一实施例中，多相时钟产生电路由N个D触发器级联构成，并且最后一个D触发器的输出要给到第一个D触发器的输入形成环路。它的功能是为时间交织ADC电路提供N个多相时钟。多相时钟产生电路的输入信号为采样主时钟CLK_SAMPLE，这个主时钟的频率往往和交织ADC的采样频率一致，它的输出信号为N个多相时钟信号CLKIN<1>～CLKIN<N>。CLK_SAMPLE信号输入到所有的D触发器的时钟输入端，第一个D触发器数据输出端Dout输出的信号输入到下一个D触发器的数据输入端Din，同时第一个D触发器数据输出端Dout的输出信号也作为多相时钟产生电路的输出CLKIN<1>，同理，第二个D触发器的输出端Dout输出的信号输入到第三个D触发器的数据输入端Din，同时第二个D触发器数据输出端Dout的输出信号也作为多相时钟电路产生电路的输出CLKIN<2>，以此类推，直到最后一个D触发器，最后一个D触发器的输入端信号为上一个D触发器的输出端输出的信号，它的输出端Dout输出的信号输入到第一个D触发器的输入端，同时最后一个D触发器的输出端输出的信号也作为多相时钟产生电路的输出CLKIN<N>。
在一实施例中，时钟重分配传输门阵列电路主要由传输开关阵列构成，时钟重分配传输门阵列电路的输入是多相时钟产生电路产生的N通道多相时钟CLKIN<1>～CLKIN<N>和通道选择电路输出的N+1(即M)通道时钟接收控制信号CH1_CLK_CONTROL<N:1>～CHM_CL K_CONTROL<N:1>，时钟重分配传输门阵列电路的输出是重分配后的M通道多相时钟CLKOUT<1>～CLK OUT<M>。时钟重分配传输门阵列电路的功能是根据输入的M通道时钟接收控制信号，将输入的N通道多相时钟分配到各个时间交织ADC电路中去。时钟重分配传输门阵列电路的电路结构如图8所示，时钟重分配传输门阵列电路由多个传输开关组成，传输开关包括输入端、控制端和输出端。时钟重分配传输门阵列电路有M个输出信号，每一个输出信号都是由N个传输开关的输出并联到一起组成的，这N个传输开关的输入端都分别依次为多相时钟CLKIN<1>～CLKIN<N>，而控制端则根据输出信号的不同而不同。如果输出信号是CLKOUT<1>，那么控制端则依次为CH1_CLK_CONTROL<1>～CH1_CLK_CONTROL<N>，如果输出信号是CLKOUT<2>，那么控制端则依次为CH2_CLK_CONTROL<1>～CH2_CLK_CONTROL<N>，以此类推，如果输出信号是CLKOUT<M>，那么控制信号则依次为CHM_CLK_CONTROL<1>～CHM_CLK_CONTROL<N>，一共需要N*M个传输开关。传输开关由传输门和反相器组成，传输门由源和源、漏和漏短接的PMOS管和NMOS管组成，NMOS管和 PMOS管的源极短接作为传输门的输入端，漏端作为输出端，控制信号直接接到传输门NMOS的栅极，同时也接到反相器的输入端，反相器的输出接到传输门PMOS管的栅极。
在一实施例中，M通道时间交织ADC电路就是含有M个通道的时间交织ADC，它并不特指某一种特定类型的ADC，只要是含有M个通道的并且能够输出每一个通道的数据和量化完成信号的时间交织ADC都可以。它的输入信号为时钟重分配传输门阵列电路输出的重分配后的M通道多项时钟CLKOUT<1>～CLKOUT<M>，它的输出信号为M个通道量化完成信号Q<M:1>和M个通道输出数据DATA1OUT～DATAMOUT。通道量化完成信号表示该通道是否完成量化，当输入该通道的多项时钟变为高电平的时候，该通道的通道量化完成信号为低电平，表示该通道正在量化，还未完成量化，当该通道完成量化后，通道量化完成信号变为高电平，表示该通道已经完成量化。通道输出数据指各个通道ADC的输出结果，它通常是多位数据，位数取决于ADC的分辨率。
在一实施例中，可调延时模块电路由反相器、NMOS管和电容组成，它的输入信号为通道选择电路所输出的N通道数据接收控制信号CH1_DATA_CONTROL<K:1>～CHN_DATA_CONTROL<K:1>和用于控制延时大小的延时控制字DELAY<S:1>，S代表的是延时控制字的位数，位数越多，延时的控制精度越高，它的输出信号为延时后的N通道数据接收控制信号CH1_DATA_CONTROL_DELAY<K:1>～CHN_DATA_CONTROL_DELAY<K:1>。它的功能为调整数据接收控制字的延迟，使数据接收控制字不要太快到达后续电路，保证ADC快要量化完的时候才接收控制信号，避免太早接收控制信号导致数据提前输出。它由许多个延时单元组成，每一位输入信号需要一个延时单元，延时单元具体结构如图9所示。延时单元由两个反相器、S个延时控制NMOS管和S个延时电容组成。单比特输入信号INPUT接在反相器的输入端，在此输出端路径上，并联上S个电容，每个电容的另一端都分别接到一个延时控制NMOS管漏端，同时该延时控制NMOS管的栅端接入对应的延时控制字。控制字一起控制所有延时单元的延时控制NMOS管。反相器的输出端接在下一个反相器的输入端，下一个反相器的输出端就是延时单元的输出端。延时电容的大小和数量一起决定了延时的范围和精度，通过控制延时控制字来控制延时的大小。
在一实施例中，通道选址译码器电路由逻辑门构成，它的输入是延时后的N通道数据接收控制信号CH1_DATA_CONTROL_DELAY<K:1>～CHN_DATA_CONTROL_ DELAY<K:1>，输出是译码后的N通道数据接收控制信号CH1_DATA_EN<M:1>～CHN_DATA_EN<M:1>。通道选址译码器电路的功能是将可调延时模块延时后的二进制N通道数据接收信号译码成位数为M的温度计码。由于通常情况下通道选择电路和数据输出端的版图物理距离较远，如果N通道数据接收控制信号直接采用M位温度计码输出，会导致版图走线过于冗长和繁杂，因此N通道数据接收信号首先采用K位二进制码输出，经过可调延时模块电路后到达离数据输出端较近的位置，再采用通道选址译码器电路将K位二进制码译码成M位温度计码，该通道选址译码器的具体电路取决于M的值。
在一实施例中，数据重分配传输门阵列电路主要由传输开关阵列构成，传输开关的结构和时钟重分配传输门阵列电路中作用的是一样的。数据重分配传输门阵列电路的输入有三个部分，第一个部分是M通道时间交织ADC电路输出的通道量化完成信号Q<M:1>，它是M个单bit信号；第二个部分是M通道时间交织ADC电路输出的通道输出数据DATA1OUT～DATAMOUT，它是M个多bit信号，其bit位数取决于时间交织ADC的分辨率；第三个部分是通道选址译码器电路输出的译码后的N通道数据接收控制信号CH1_DATA_EN<M:1>～CHN_DATA_EN<M:1>。数据重分配传输门阵列电路的输出有两个部分，第一个部分是重分配后的N通道输出数据，它是N个多bit信号，其bit位数取决于时间交织ADC的分辨率；第二个部分是重分配后的N通道量化完成信号QOUT<N:1>，它是N个单bit信号。数据重分配传输门阵列电路的功能是将输入的M个通道的输出数据和通道量化完成信号重分配到N个通道上去，这是因为通道的工作次序被打乱，各个通道的输出数据并不是按照时间顺序依次排列，所以需要把打乱的信号按照工作的次序重新分配，使得最终输出的数据是按照时间顺序依次排列的。数据重分配传输门阵列电路的电路图如图10所示，为了便于说明，假设时间交织ADC的分辨率(位数)为R位，因此输入的DATA1OUT～DATAMOUT表示为DATA1OUT<R:1>～DATAMOUT<R:1>，输出的重分配后的N通道输出数据表示为CH1OUT<R:1>～CHNOUT<R:1>。第一部分输入信号DATA1OUT<R:1>～DATAMOUT<R:1>都接在传输开关的输入端，输入的译码后的N通道数据接收控制信号根据输入信号的不同接在不同传输开关的控制端上，每一个控制信号要接入R个传输开关的控制端。例如，控制信号CH1_DATA_EN<1>接在以DATA1OUT<1>～DATA1OUT<R>为输入信号的传输开关的控制端，控制信号CH1_DATA_EN<2>接在以DATA2OUT<1>～DATA2OUT<R>为输入信号的传输开关的控制端……控制信号 CH1_DATA_EN<M>接在以DATAMOUT<1>～DATAMOUT<R>为输入信号的传输开关的控制端。后续的控制信号同理，控制信号CH2_DATA_EN<1>到控制信号CHM_DATA_EN<1>分别都接在以DATA1OUT<1>～DATA1OUT<R>为输入信号的传输开关的控制端……控制信号CH2_DATA_EN<M>到控制信号CHM_DATA_EN<M>分别都接在以DATAMOUT<1>～DATAMOUT<R>为输入信号的传输开关的控制端，以此类推。第二部分输入信号QOUT<M:1>和第一部分的输入信号类似，同样都接在传输开关的输入端，并且输入的译码后的N通道数据接收控制信号也根据不同的输入信号接在不同传输开关的控制端上，不同的是每一个控制信号都只需要接1个传输开关的控制端。例如控制信号CH1_DATA_EN<1>接在Q<1>为输入信号的控制端，控制信号CH1_DATA_EN<2>接在以Q<2>为输入信号的传输开关的控制端……控制信号CH1_DATA_EN<M>接在以Q<M>为输入信号的传输开关的控制端。后续的控制信号同理，CH2_DATA_EN<M:1>到控制信号CHM_DATA_EN<M:1>分别对应接在Q<M>到Q<1>为输入信号的传输开关的控制端，故一共所需M*(R+1)*N个传输开关。第一部分输出信号CH1OUT<R:1>～CHNOUT<R:1>根据传输开关的输入信号和控制信号分别对应接到对应传输开关的输出端上，每一个输出信号都要接到M个传输开关的输出端上。例如输出信号CH1OUT<1>～CH1OUT<R>分别对应接在由DATAMOUT<1>～DATA1OUT<1>、DATAMOUT<2>～DATA1OUT<2>……DATAMOUT<R>～DATA1OUT<R>作为输入端，CH1_DATA_EN<M:1>作为控制端的传输开关的输出端上，输出信号CH2OUT<1>～CH2OUT<R>分别对应接在由DATAMOUT<1>～DATA1OUT<1>、DATAMOUT<2>～DATA1OUT<2>……DATAMOUT<R>～DATA1OUT<R>作为输入端，CH2_DATA_EN<M:1>作为控制端的传输开关的输出端上，以此类推，CHNOUT<1>～CHNOUT<R>分别对应接在由DATAMOUT<1>～DATA1OUT<1>、DATAMOUT<2>～DATA1OUT<2>……DATAMOUT<R>～DATA1OUT<R>作为输入端，CH2_DATA_EN<M:1>作为控制端的传输开关的输出端上。类似的，另一部分输出信号QOUT<N>根据传输开关的输入信号和经过译码后的数据接收控制信号分别接到对应传输开关的输出端上，每一个输出信号都要接到M个传输开关的输出端上。例如QOUT<1>接在由Q<M>～Q<1>作为输入端、CH1_DATA_EN<M>～CH1_DATA_EN<1>作为控制端的控制开关的输出端上，QOUT<2>接在由Q<M>～Q<1>作为输入端、CH2_DATA_EN<M>～CH2_DATA_EN<1>作为控制端的控制开关的输出端上，以此类推QOUT<N>接在由Q<M>～Q<1>作为输入端、 CHM_DATA_EN<M>～CHM_DATA_EN<1>作为控制端的控制开关的输出端上。
在一实施例中，所述数据输出D触发器电路主要由D触发器阵列构成，它的输入信号为数据重分配传输门阵列电路输出的重分配后的N通道量化完成信号QOUT<N:1>和重分配后的N通道输出数据CH1OUT～CHNOUT，其中QOUT<N:1>为N位单bit信号，CH1OUT～CHNOUT为多bit信号，其bit位数取决于时间交织ADC的分辨率。输出信号为N通道最终输出数据CH1_OUT_DIFF～CHN_OUT_DIFF。数据输出D触发器电路的结构如图11所示，假设时间交织ADC的分辨率为R(即重分配后的N通道输出数据的位数为R)。输入信号CH1OUT<R:1>～CHNOUT<R:1>分别对应接到R个D触发器的Din输入端(数据输入端)，量化完成信号对应接入各个由CH1OUT<R:1>～CHNOUT<R:1>作为D触发器数据输入端输入信号的CLK端(例如QOUT<1>接入由CH1OUT<R:1>作为数据输入端的D触发器的CLK端，QOUT<2>接入由CH2OUT<R:1>作为数据输入端的D触发器的CLK端，类似的，QOUT<N>接入由CHNOUT<R:1>作为数据输入端的D触发器的CLK端)，故一共所需R*N个D触发器。输出信号CH1OUT_DIFF<R:1>～CHNOUT_DIFF<R:1>对应接入各个由CH1OUT<R:1>～CHNOUT<R:1>作为D触发器数据输入端输入信号的数据输出端(Dout端)(例如CH1OUT_DIFF<R:1>分别对应接入由CH1OUT<R:1>作为数据输入端的D触发器的Dout端，CH2OUT_DIFF<R:1>分别对应接入由CH2OUT<R:1>作为数据输入端的D触发器的Dout端，以此类推，CHNOUT_DIFF<R:1>分别对应接入由CHNOUT<R:1>作为数据输入端的D触发器的Dout端)。
在一实施例中，数字电路主时钟通常情况下和采样主时钟保持一致(即具有相同的频率)，在采样主时钟的频率极高的情况下(1GHz以上)，由于数字综合出来的电路无法承载如此高的频率，可以降低数字电路主时钟的频率，降低的频率需要满足如下条件：第一个条件是降低后的频率必须为采样主时钟的整数分频倍(例如降低为采样频率的2分频、3分频、4分频……)，第二个条件是该分频倍数必须与去除冗余通道外剩余的通道数目互质(例如对于去掉冗余通道后通道数目为8通道时间交织ADC，数字电路主时钟降低的频率可以是3分频、5分频，但不能是2分频、4分频，因为2或者4和8不互质)。在满足这两个条件的基础上，可以降低数字电路主时钟的频率。
在一实施例中，为了进一步验证本发明的基于时间交织ADC的通道随机化电路性能，在28nm CMOS工艺下，对一个采样主时钟为4GHz，分辨率12位(ADC的位数冗余3位，实际输出数据的位数为15位)，Vpp为0.8V，通道总数量为 17(16个交织通道和1个用于实现随机化的冗余通道)的时间交织SAR ADC，采用上述基于时间交织ADC的通道随机化电路。
根据上述指标确定采样主时钟为4GHz，多相时钟产生电路输出的多项时钟数目为16个，分频出来的单通道多相时钟速度为250MHz，数字电路主时钟为800MHz。伪随机数产生电路中LFSR的位数为42位，其抽头为[41,20,1]。通道选择器分别输出17个位数为16的通道时钟接收控制信号和16个位数为5的通道数据接收控制信号，延时控制字的数量为5，调整控制字和电容的大小保证延时大小至少为1.25ns，通道量化完成信号的位数为17，通道输出数据为17个位数为15的数据，重分配后的通道量化完成信号数量为16个，重分配后的通道输出数据为16个位数为15的数据。最后输出信号的数据为16个位数为15的数据。由于有17个通道，通道数据接收控制信号的位数为5，用这5位二进制码的低4位1111～0000来表示通道16～通道1，用最高位来表示通道17和非通道17，因此在通道选址译码电路中对于低4位采用4‐16译码器将其转换成16位的温度计码，同时通过最高位是否为1来直接判断是否是通道17，如果是17，则第17位的温度计码为1，反之为0，两者组合完成译码，将5位的二进制码转换成17位温度计码。
完成电路搭建后，在各个单通道ADC中的比较器中加入范围在‐500uV～+500uV内的随机失调值，以模拟非理想因素导致的失配。未开启随机化和开启随机化的频谱仿真结果分别如图12和图13所示。从这两个频谱结果可以看出，开启随机化后，原有时间交织ADC性能的性能没有受到影响(ENOB基本一致)，时间交织ADC的SFDR无杂散动态范围(Spurious‐freeDynamicRange，SFDR)提高了近10个dB，充分说明了本技术实现了通道随机化，提升了时间交织ADC的性能。
在一实施例中，本发明还提供了一种基于时间交织ADC的通道随机化方法，用于执行前述电路实施例中所述的基于时间交织ADC的通道随机化电路。由于方法实施例的技术原理与前述电路实施例的技术原理相似，因而不再对同样的技术细节做重复性赘述。
在一实施例中，基于时间交织ADC的通道随机化方法，包括：根据主时钟和生成的随机数输出M个时钟接收控制信号和经过编码后的N个数据接收控制信号；其中，M和N为正整数，且M大于N；根据采样主时钟生成N个多相时 钟，并根据所述时钟接收控制信号对所述多相时钟进行重分配，输出M个重分配时钟信号；根据所述重分配时钟信号输出M个输出数据以及对应数量的通道量化完成信号；设置所述数据接收控制信号延时大小，根据延时后的数据接收控制信号和所述通道量化完成信号控制所述输出数据按照时间顺序依次排列输出。
综上所述，本发明一种基于时间交织ADC的通道随机化电路和方法，在实现通道随机化的同时，不影响原有时间交织ADC的性能，并通过随机化手段提高在失配情况下时间交织ADC的SFDR。所以，本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (14)

  1. 一种基于时间交织ADC的通道随机化电路，其特征在于，包括：
    通道选择模块，用于根据主时钟和生成的随机数输出M个时钟接收控制信号和经过编码后的N个数据接收控制信号；其中，M和N为正整数，且M大于N；
    多相时钟分配模块，用于根据采样主时钟生成N个多相时钟，并根据所述时钟接收控制信号对所述多相时钟进行重分配，输出M个重分配时钟信号；
    时间交织ADC模块，用于根据所述重分配时钟信号输出M个输出数据以及对应数量的通道量化完成信号；
    可调延时模块，用于设置所述数据接收控制信号延时大小；以及，
    时序分配控制模块，分别与所述可调延时模块的输出端和所述时间交织ADC模块的输出端连接，用于根据延时后的数据接收控制信号和所述通道量化完成信号控制所述输出数据按照时间顺序依次排列输出。
  2. 根据权利要求1所述的基于时间交织ADC的通道随机化电路，其特征在于，所述通道选择模块包括：伪随机数产生电路和通道选择电路；
    所述伪随机数产生电路接收所述主时钟和一组随机数输出使能信号，并输出一组随机数输出信号；所述通道选择电路接收所述随机数输出信号和所述主时钟，输出所述时钟接收控制信号和所述数据接收控制信号。
  3. 根据权利要求2所述的基于时间交织ADC的通道随机化电路，其特征在于，所述通道选择电路包括：
    时钟状态寄存器，具有N个地址，每个地址代表一个多相时钟，每个地址中存放的值代表对应地址的多相时钟接入的通道；
    通道状态寄存器，具有M个地址，每个地址代表一个通道，每个地址中存放的值代表对应地址的通道接入的多相时钟；以及，
    空闲通道寄存器，用于存放没有接入多相时钟的通道；
    当所述主时钟来临时，根据所述随机数输出信号判断是否将所述时钟状态寄存器中当前处理的地址中存放的通道与所述空闲通道寄存器中存放的通道进行交换；所述通道状态寄存器根据所述时钟状态寄存器寄存器和所述空闲通道寄存器的交换结果进行对应地址中存放值的交换；
    根据所述通道状态寄存器中存放的值输出对应的时钟接收控制信号，同时， 根据所述时钟状态寄存器中存放的值输出所述数据接收控制信号。
  4. 根据权利要求3所述的基于时间交织ADC的通道随机化电路，其特征在于，
    当所述随机数输出信号为高电平时，执行所述时钟状态寄存器中对应地址存放的通道与所述空闲通道寄存器中存放的通道的交换；
    当所述随机数输出信号为低电平时，不执行交换动作。
  5. 根据权利要求3所述的基于时间交织ADC的通道随机化电路，其特征在于，记每个所述数据接收控制信号包含K位二进制编码信号，则2 K大于或等于M。
  6. 根据权利要求1所述的基于时间交织ADC的通道随机化电路，其特征在于，所述多相时钟分配模块包括：多相时钟产生电路和时钟重分配传输门阵列电路；
    所述多相时钟产生电路，由N个D触发器级联构成，且最后一个所述D触发器的输出端与第一个所述D触发器的输入端连接形成环路，每个所述D触发器的输出端分别输出对应不同通道的多相时钟；以及，
    所述时钟重分配传输门阵列电路，具有M个输出端，每一个所述输出端由M个传输开关并联组成，每个所述传输开关包括输入端、输出端和控制端，所述传输开关的输入端接收一个所述多相时钟作为输入，所述传输开关的控制端接收对应通道的一位所述时钟接收控制信号。
  7. 根据权利要求1所述的基于时间交织ADC的通道随机化电路，其特征在于，所述传输开关包括：
    传输门，由一个PMOS管和一个NMOS管组成，所述PMOS管的源极与所述NMOS管的源极短接作为所述传输门的输入端，所述PMOS管的漏极与所述NMOS管的漏极短接所为所述传输门的输出端，所述NMOS管的栅极作为所述传输门的控制端接收所述时钟接收控制信号；以及，
    反相器，所述反相器的输入端接收所述时钟接收控制信号，所述PMOS的栅极与所述反相器的输出端连接。
  8. 根据权利要求1所述的基于时间交织ADC的通道随机化电路，其特征在于，所述时间交织ADC模块包括M个时间交织ADC电路，每个所述时间交织ADC电路输出一个通道的输出数据以及量化完成信号；
    当输入当前时间交织ADC电路的重分配时钟为高电平时，若所述当前时间交织ADC电路的通道量化完成信号为低电平，则所述当前时间交织ADC电路未 完成量化，若所述当前时间交织ADC电路的通道量化完成信号为高电平，则所述当前时间交织ADC电路已完成量化。
  9. 根据权利要求1所述的基于时间交织ADC的通道随机化电路，其特征在于，所述可调延时模块包括多个延时单元，每个输入信号对接一个所述延时单元；所述延时单元包括：第一反相器、第二反相器、S个延时控制NMOS管和S个延时电容，其中，S对应输入延时单元的延时控制字的位数；
    所述第一反相器的输出端与所述第二反相器的输入端连接，所述第二反相器的输出端作为对应延时单元的输出端，所述第一反相器的输入端作为对应延时单元的输入端；各所述延时控制NMOS管并联，且每个所述延时控制NMOS管的漏极通过一个所述延时电容连接到所述第一反向器的输出端与所述第二反相器的输入端的连接路径上，每个所述延时控制MOS管的栅极接入一位所述延时控制字。
  10. 根据权利要求1所述的基于时间交织ADC的通道随机化电路，其特征在于，所述时序分配控制模块包括：
    通道选址译码器电路，用于将经过延时后的数据接收控制信号译码成位数为M的温度计码信号；
    数据重分配传输门阵列电路，用于根据经过译码后的数据接收控制信号和所述时间交织ADC模块的输出数据以及通道量化完成信号，输出重分配后的输出数据以及重分配后的通道量化完成信号；以及，
    数据输出D触发器电路；用于以所述重分配后的输出数据作为输入，以所述重分配后的通道量化完成信号作为时钟，输出重新排序后的输出数据。
  11. 根据权利要求10所述的基于时间交织ADC的通道随机化电路，其特征在于，所述数据重分配传输门阵列电路由传输开关阵列构成，所述传输开关包括输入端、输出端和控制端，每个输入信号对应一个所述传输开关；每个所述时间交织ADC模块的输出数据的各数据位分别对接一个所述传输开关的输入端，每个经过译码后的数据接收控制信号接入R个所述传输开关的控制端，其中，R为所述输出数据的位数；
    每个所述时间交织ADC模块的通道量化完成信号对接一个所述传输开关的输入端，每一个所述经过译码后的数据接收控制信号接入对应传输开关的控制端；
    所述传输开关的输出端输出所述重分配后的输出数据或重分配后的通道量化完成信号。
  12. 根据权利要求10所述的基于时间交织ADC的通道随机化电路，其特征在于，所述数据输出D触发器电路由N组触发器阵列构成，每组触发器阵列包含R个D触发器，每个所述D触发器的输入端接收一个所述重分配后的输出数据中的一位作为输入，每组所述触发器阵列接收一个所述重分配后的通道量化完成信号作为时钟端输入，每组所述触发器阵列输出端输出一个所述重新排序后的输出数据。
  13. 根据权利要求1所述的基于时间交织ADC的通道随机化电路，其特征在于，所述主时钟与所述采样主时钟具有相同的频率；或者，所述主时钟的频率为所述采样主时钟频率的整数分频倍且所述分频倍数与去除冗余通道后的剩余通道数互质。
  14. 一种基于时间交织ADC的通道随机化方法，其特征在于，包括：
    根据主时钟和生成的随机数输出M个时钟接收控制信号和经过编码后的N个数据接收控制信号；其中，M和N为正整数，且M大于N；
    根据采样主时钟生成N个多相时钟，并根据所述时钟接收控制信号对所述多相时钟进行重分配，输出M个重分配时钟信号；
    根据所述重分配时钟信号输出M个输出数据以及对应数量的通道量化完成信号；
    设置所述数据接收控制信号延时大小，根据延时后的数据接收控制信号和所述通道量化完成信号控制所述输出数据按照时间顺序依次排列输出。
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CN104038226A (zh) * 2014-06-25 2014-09-10 华为技术有限公司 多通道时间交织模数转换器
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CN104038226A (zh) * 2014-06-25 2014-09-10 华为技术有限公司 多通道时间交织模数转换器
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