WO2023084978A1 - シリコンウェーハの評価方法及びシリコンウェーハの加工変質層除去方法 - Google Patents

シリコンウェーハの評価方法及びシリコンウェーハの加工変質層除去方法 Download PDF

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Publication number
WO2023084978A1
WO2023084978A1 PCT/JP2022/037864 JP2022037864W WO2023084978A1 WO 2023084978 A1 WO2023084978 A1 WO 2023084978A1 JP 2022037864 W JP2022037864 W JP 2022037864W WO 2023084978 A1 WO2023084978 A1 WO 2023084978A1
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Prior art keywords
silicon wafer
silicon
affected layer
maximum depth
work
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PCT/JP2022/037864
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English (en)
French (fr)
Japanese (ja)
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佑宜 田中
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信越半導体株式会社
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Priority to CN202280072025.5A priority Critical patent/CN118176571A/zh
Publication of WO2023084978A1 publication Critical patent/WO2023084978A1/ja

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor

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  • the present invention relates to a method for evaluating silicon wafers and a method for removing damaged layers of silicon wafers.
  • Patent Document 2 describes a method of increasing sensitivity by shifting the focal position of an objective lens above or below a sample to be analyzed when analyzing foreign matter adhering to the surface of a wafer in microscopic Raman spectroscopy. It is
  • Patent Document 3 describes a method for judging the acceptance level of continued use by measuring and comparing the Raman spectra of the surface of a quartz crucible, a crystalline layer, and an amorphous layer.
  • Patent Document 4 describes a method of measuring the width of a terrace on a flat surface by peak shift of Raman scattered light.
  • Patent Document 5 describes a method of measuring strain (damage) in a silicon thin film on an SOS (silicon on sapphire) substrate by using the peak shift method of Raman scattered light after peeling and polishing, and a method of measuring strain (damage) in the silicon thin film. (damage) and the correlation between the peak shift is described.
  • Patent Document 6 describes a method for measuring the strain level in a strained silicon thin film using Raman spectroscopy peak shifting in a silicon thin film on an SSOI (strained silicon on insulator) substrate.
  • the above method was not a method capable of accurately estimating the maximum depth of the process-affected layer remaining on the bare silicon wafer.
  • the present invention has been made to solve the above problems, and provides a silicon wafer evaluation method capable of accurately estimating the maximum depth of a process-affected layer remaining on a bare silicon wafer, and a process-affected layer remaining. It is an object of the present invention to provide a method for removing a work-affected layer of a silicon wafer capable of reliably removing a work-affected layer from a bare silicon wafer.
  • the present invention provides a silicon wafer evaluation method, Obtaining the primary Raman peak positions of silicon using a Raman spectroscopic microscope at a plurality of locations in the surface of the bare silicon wafer where the work-affected layer remains; generating a histogram of peak shifts from the first-order Raman peak positions of the silicon obtained at the plurality of locations; calculating an average value A and a standard deviation S from the histogram; A method for evaluating a silicon wafer, comprising estimating a maximum depth D of a process-affected layer remaining in the silicon wafer from the average value A and the standard deviation S.
  • a silicon wafer evaluation method of the present invention it is possible to accurately and non-destructively estimate the maximum depth of a process-affected layer remaining on a bare silicon wafer (especially a wafer after lapping or grinding). Also, based on this estimate, the etching allowance and/or the polishing allowance can be determined just enough.
  • the maximum depth of the work-affected layer can be estimated more accurately.
  • the silicon wafer having a surface roughness of 1 nm or more in a field of view of 100 ⁇ m ⁇ 100 ⁇ m can be evaluated.
  • the evaluation target is not particularly limited as long as it is a bare silicon wafer with a process-affected layer remaining, but for example, a silicon wafer with a surface roughness of 1 nm or more in a 100 ⁇ m ⁇ 100 ⁇ m field of view can be evaluated.
  • the light source wavelength used in the Raman spectroscopic microscope is preferably 532 nm.
  • the maximum depth D of the work-affected layer can be estimated more accurately.
  • the maximum depth D of the work-affected layer can be estimated more accurately by setting the number of locations for obtaining the primary Raman peak positions of silicon to 200 or more.
  • a method for removing a damaged layer of a silicon wafer comprising: Provided is a method for removing a process-affected layer of a silicon wafer, characterized by subjecting the silicon wafer to etching and/or polishing with a machining allowance exceeding the maximum depth D estimated by the silicon wafer evaluation method of the present invention.
  • the process-affected layer remaining on the bare silicon wafer is reliably removed. can be done.
  • the work-affected layer it is possible to obtain a silicon wafer that satisfies the standard for the number of localized light scatter (LLS) defects after etching and/or polishing, for example.
  • LLS localized light scatter
  • a work-affected layer of a silicon wafer of the present invention can be reliably removed from a bare silicon wafer in which the work-affected layer remains.
  • the machining allowance is not excessive, it contributes to the improvement of productivity and yield.
  • FIG. 4 is a graph showing the relationship between the removal amount from polishing and the average number of defects in Examples 1 and 2 and Comparative Examples 1 and 2.
  • FIG. 4 is a graph showing the relationship between the removal amount from polishing and the average number of defects in Examples 1 and 2 and Comparative Examples 1 and 2.
  • a silicon wafer evaluation method capable of accurately estimating the maximum depth of a work-affected layer remaining on a bare silicon wafer, and a method for reliably removing a work-affected layer from a bare silicon wafer having a work-affected layer remain.
  • a method for removing the work-affected layer of silicon wafers that can be removed.
  • the present inventors obtained the primary Raman peak positions of silicon using a Raman spectroscopic microscope at multiple locations in the surface of a bare silicon wafer in which a process-affected layer remained. Generate a peak shift histogram from the silicon primary Raman peak position obtained at the point, consider the generated peak shift histogram to be a normal distribution, calculate the average value and standard deviation, and calculate the average value and standard By estimating the maximum depth D of the work-affected layer based on the deviation, the maximum depth D of the work-affected layer remaining in the bare silicon wafer to be evaluated can be accurately estimated. completed.
  • the present invention is a method for evaluating a silicon wafer, Obtaining the primary Raman peak positions of silicon using a Raman spectroscopic microscope at a plurality of locations in the surface of the bare silicon wafer where the work-affected layer remains; generating a histogram of peak shifts from the first-order Raman peak positions of the silicon obtained at the plurality of locations; calculating an average value A and a standard deviation S from the histogram; A method for evaluating a silicon wafer, comprising estimating, from the average value A and the standard deviation S, a maximum depth D of a process-affected layer remaining in the silicon wafer.
  • the present invention also provides a method for removing a damaged layer of a silicon wafer, A process-affected layer removal method for a silicon wafer, characterized in that the silicon wafer is subjected to etching and/or polishing with a machining allowance exceeding the maximum depth D estimated by the silicon wafer evaluation method of the present invention.
  • Silicon wafers to be evaluated by the method for evaluating silicon wafers of the present invention are bare silicon wafers in which a process-affected layer remains. More specifically, it is a bare silicon wafer in a process before etching, for example, a bare silicon wafer after slicing, lapping, or grinding.
  • the process-affected layer is a layer in which stress due to these processes remains in the silicon wafer. Quantitatively expressing this, for example, it can be expressed as a silicon wafer having a surface roughness of 1 nm or more in a field of view of 100 ⁇ m ⁇ 100 ⁇ m.
  • the upper limit of the surface roughness of the silicon wafer to be evaluated is not particularly limited. If it is equal to or less than this upper limit, it is possible to reliably prevent an out-of-focus area from appearing in the observation field of the microscope, thereby preventing deterioration in measurement accuracy.
  • the primary Raman peak position of silicon is obtained by fitting with the Lorentz function, and the peak shift value is obtained from one data point.
  • the peak shift value was measured at 1000 points on bare silicon wafers after various processing such as free abrasive slicing, fixed abrasive slicing, lapping, and grinding with a grindstone, and the standard deviation S was A small one was 0.031 cm ⁇ 1 . With more than 180 measurement points, this number can be obtained with 99% confidence in the interval ⁇ 0.005 cm ⁇ 1 . By setting the number of measurement points to 200 or more, this numerical value can be obtained with higher reliability. Although the preferable upper limit of the measurement points is not particularly limited, it can be, for example, 10,000 points or less. By setting the number of measurement points to 180 or more and 10000 or less, it is possible to obtain sufficient measurement accuracy without taking much measurement time.
  • a peak shift histogram is generated from the primary Raman peak positions of silicon obtained at a plurality of locations on the bare silicon wafer to be evaluated, and the average value A and the standard deviation are obtained from the generated histogram. S is calculated.
  • FIG. 1 an example of a peak shift histogram that can be obtained in the silicon wafer evaluation method of the present invention is shown by a solid line.
  • a dashed line indicates this histogram approximated to a normal distribution.
  • the solid-line peak shift histogram can be regarded as a normal distribution indicated by a dashed line, and the average value A and the standard deviation S can be calculated from this normal distribution.
  • the mean A is 0.989 cm ⁇ 1 and the standard deviation S is 0.030 cm ⁇ 1 .
  • the maximum depth D of the process-affected layer remaining on the silicon wafer is estimated from the average value A and standard deviation S calculated as described above.
  • the coefficient K is a coefficient that varies depending on the instrumental difference of the measuring instrument to be used, the number of local light scattering (LLS) defects on the wafer surface, etc., and can be determined, for example, by experience and/or experimentation.
  • LLS local light scattering
  • the remaining process-affected layer is An appropriate stock allowance that can be reliably removed can be determined.
  • the silicon wafer is subjected to etching and/or polishing with a machining allowance exceeding the maximum depth D estimated by the silicon wafer evaluation method of the present invention.
  • the process-affected layer remaining on the bare silicon wafer can be reliably removed.
  • the work-affected layer it is possible to obtain a silicon wafer that satisfies the standard for the number of local light scattering (LLS) defects after etching and/or polishing, for example.
  • LLS local light scattering
  • Examples 1 and 2 and Comparative Examples 1 and 2> [About wafers] As wafers to be evaluated, 10 sample wafers A and 10 sample wafers B were prepared by cutting a p-type silicon single crystal with a diameter of 300 mm by a free abrasive grain method with a count of 1000 and lapping with a count of 1500. .
  • the average surface roughness of sample wafer A was 351 nm in a field of view of 100 ⁇ m ⁇ 100 ⁇ m.
  • the average surface roughness of sample wafer B was 226 nm in a field of view of 100 ⁇ m ⁇ 100 ⁇ m.
  • a histogram of peak shifts for each of sample wafers A and B was generated from the primary Raman peak positions of silicon obtained at a total of 200 locations.
  • the average value A and the standard deviation S were calculated from the generated histogram.
  • the sample wafer A subjected to free abrasive slicing had an average value A of 1.021 cm ⁇ 1 and a standard deviation S of 0.052 cm ⁇ 1 .
  • the lapped sample wafer B had an average value A of 0.784 cm ⁇ 1 and a standard deviation S of 0.042 cm ⁇ 1 .
  • a reference wafer was prepared by surface grinding with a 2000-grit grindstone.
  • the primary Raman peak positions of silicon were obtained at a total of 200 points in the plane in the same procedure as for the sample wafers A and B, and the primary Raman peak positions of silicon obtained at a total of 200 points were obtained.
  • a histogram of peak shifts was generated from the Raman peak positions.
  • An average value A0 and a standard deviation S0 were calculated from the generated histogram. The average value A0 was 0.381 cm -1 and the standard deviation S0 was 0.065 cm -1 .
  • the ground surface of the reference wafer was polished by a thickness of 0.5 ⁇ m.
  • the polishing machine was DSP-20B manufactured by Nachi-Fujikoshi Machinery Industry Co., Ltd. with foamed polyurethane pads attached, the carrier was a titanium substrate using FRP with glass fibers impregnated with epoxy resin as inserts, and the slurry contained silica abrasive grains with an average particle size of 35 nm. A KOH-based one was used.
  • the number of local light scattering (LLS) defects on the polished surface was measured with a KLA particle measuring instrument SP1 every time 0.5 ⁇ m was polished.
  • the total machining allowance when the number of local light scattering (LLS) defects having a grain size of 500 nm or more measured each time was less than 10 was defined as D0.
  • the total machining allowance D0 was 8.6 ⁇ m.
  • the coefficient K was 14.9 ⁇ m/cm ⁇ 1 .
  • LLS local light scattering
  • the polishing conditions were the same as the polishing conditions for obtaining the coefficient K.
  • the polishing conditions were the same as the polishing conditions for obtaining the coefficient K.
  • the polishing conditions were the same as the polishing conditions for obtaining the coefficient K.
  • the polishing conditions were the same as the polishing conditions for obtaining the coefficient K.
  • FIG. 2 shows a graph of the relationship between the polishing allowance and the average number of defects in Examples 1 and 2 and Comparative Examples 1 and 2.
  • Example 2 in which the polishing was performed with , the average number of defects achieved the standard of 10 or less.
  • the present invention is not limited to the above embodiments.
  • the above-described embodiment is an example, and any device having substantially the same configuration as the technical idea described in the claims of the present invention and exhibiting the same effect is the present invention. included in the technical scope of

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Investigating, Analyzing Materials By Fluorescence Or Luminescence (AREA)
PCT/JP2022/037864 2021-11-15 2022-10-11 シリコンウェーハの評価方法及びシリコンウェーハの加工変質層除去方法 WO2023084978A1 (ja)

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DE102023129379A1 (de) 2022-11-07 2024-05-08 Aoyama Seisakusho Co., Ltd Metallelement, Verbindungsstruktur zwischen Metallelement und Metallplatte, Verbindungsstruktur zwischen Metallelement und Platten aus ungleichem Material die aus Harz, Metall und dergleichen hergestellt sind, verbundener Artikel und Verfahren zum Herstellen eines verbundenen Artikels

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08114548A (ja) * 1994-10-18 1996-05-07 Sony Corp 結晶性評価方法
JP2001358099A (ja) * 2000-06-13 2001-12-26 Sumitomo Osaka Cement Co Ltd シリコンウエハの高速鏡面研磨方法
JP2004296912A (ja) * 2003-03-27 2004-10-21 Kyocera Corp ウェハ支持基板
JP2010124006A (ja) * 1999-01-06 2010-06-03 Tokyo Seimitsu Co Ltd 平面加工装置及び方法
JP2022149234A (ja) * 2021-03-25 2022-10-06 株式会社ノリタケカンパニーリミテド ウェハ研磨方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08114548A (ja) * 1994-10-18 1996-05-07 Sony Corp 結晶性評価方法
JP2010124006A (ja) * 1999-01-06 2010-06-03 Tokyo Seimitsu Co Ltd 平面加工装置及び方法
JP2001358099A (ja) * 2000-06-13 2001-12-26 Sumitomo Osaka Cement Co Ltd シリコンウエハの高速鏡面研磨方法
JP2004296912A (ja) * 2003-03-27 2004-10-21 Kyocera Corp ウェハ支持基板
JP2022149234A (ja) * 2021-03-25 2022-10-06 株式会社ノリタケカンパニーリミテド ウェハ研磨方法

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