WO2023077691A1 - 一种适应性噪声成形逐次逼近型数据转换器 - Google Patents

一种适应性噪声成形逐次逼近型数据转换器 Download PDF

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WO2023077691A1
WO2023077691A1 PCT/CN2022/077522 CN2022077522W WO2023077691A1 WO 2023077691 A1 WO2023077691 A1 WO 2023077691A1 CN 2022077522 W CN2022077522 W CN 2022077522W WO 2023077691 A1 WO2023077691 A1 WO 2023077691A1
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signal
stage
input
data converter
loop filter
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French (fr)
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陈烨侃
赵博
罗宇轩
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浙江大学
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
    • H03M1/462—Details of the control circuitry, e.g. of the successive approximation register
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/002—Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed

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  • the invention belongs to the technical field of CMOS bias circuits, in particular to an adaptive noise shaping successive approximation data converter.
  • Analog-to-Digital Converter (Analog-to-Digital Converter, ADC) is an electronic device that can convert analog signals into digital signals. Since most physical signals in nature exist in the form of analog signals, computer systems are good at high Efficient processing of digital signals, so for efficient processing of physical signals, an analog-to-digital converter is essential.
  • Analog-to-digital converters can be divided into different types according to their conversion mechanism, among which the successive approximation (Successive Approximation Register, SAR) ADC is a low-power, medium-precision ADC structure.
  • the SAR ADC is a Nyquist sampling rate ADC whose sampling rate obeys the Nyquist sampling law; on the other hand, the circuit practice of the SAR ADC usually does not need to use any op
  • the device realizes multi-bit digital quantization, so it has better energy efficiency.
  • the conversion accuracy of SAR ADCs is limited due to the mismatch of electronic components (such as capacitors) that becomes more apparent in high-bit ADCs and introduces errors.
  • Noise shaping technology helps to improve the conversion accuracy of ADC.
  • noise shaping SAR ADC has been proposed to significantly improve the conversion accuracy of SAR ADC.
  • Noise-shaping SAR ADCs are different from conventional SAR ADCs in that they have two features: oversampling and noise shaping. Oversampling is characterized by the fact that the sampling frequency of the ADC is higher than the Nyquist sampling rate. Noise-shaping is characterized by its use of the control loop The circuit processes the input signal and quantization noise, and provides gain to the signal of a specific frequency band through the loop filter to improve the signal-to-noise ratio in the specific frequency band during the analog-to-digital conversion process.
  • the loop filter often has circuits such as integrators, filters, or resonators, and these circuits usually include operational amplifiers with high power consumption; in addition, the existing noise-shaping SAR ADCs require that each conversion process will turn on Loop filter, and work under the condition of oversampling, because the loop filter and oversampling will bring additional power consumption, so the power consumption of the existing noise shaping SAR ADC is usually higher than that of the conventional SAR ADC.
  • an ADC with event-driven capability can be used for analog-to-digital signal conversion to reduce the power consumption of the analog-to-digital converter; there are currently two types of ADC with event-driven capability, one is level-triggered ADC, the other is a pipelined ADC.
  • the level-triggered ADC is only driven when the input voltage changes by more than 1 minimum quantization step, and the input signal is sampled, and when the input signal does not change, it maintains a low-power standby state, so the level-triggered ADC can be in Significantly reduces system power consumption when processing sparsity signals.
  • the trigger probability of the level-triggered ADC will increase with the increase of its conversion precision, so this solution is only suitable for systems with low conversion precision.
  • the pipelined ADC can use the output of the first-stage circuit to judge the input event, and decide whether to turn on the second-stage circuit for high-precision quantization according to the judgment result.
  • the pipelined ADC can achieve higher conversion accuracy through multi-stage conversion, however This scheme requires a high-gain interstage amplifier to ensure the linearity of the residual amplification, which reduces its power consumption.
  • the current ADC with event-driven capability is difficult to balance the contradiction between accuracy and power consumption.
  • the existing SAR ADC has low energy consumption, its conversion accuracy is limited; on the other hand, the existing The noise-shaping SAR ADC has high conversion accuracy, but its power consumption is high.
  • an adaptive noise-shaping successive approximation data converter with event-driven capability is proposed, which can efficiently process sparse signals.
  • the present invention provides an adaptive noise shaping successive approximation data converter, which is suitable for processing sparse signals and has the advantages of high precision and low energy consumption.
  • An adaptive noise-shaping successive approximation data converter comprising:
  • the switched capacitor array uses the digital control signal provided by the control logic circuit to successively approximate the input analog signal and then outputs it to the switch circuit;
  • the switch circuit selects the analog signal output by the switched capacitor array to be input to the comparator through the power gating loop filter or directly to the comparator according to the control signal provided by the event detection logic circuit;
  • a power-gated loop filter for integrating and filtering the input signal
  • Comparator which compares the input signal and generates an output result
  • the control logic circuit generates a corresponding digital signal output according to the output result of the comparator, and simultaneously generates a digital control signal for controlling the switched capacitor array;
  • the event detection logic circuit judges whether an input event occurs currently according to the digital signal output by the control logic circuit, and configures the switch circuit and the power gating loop filter according to the input event.
  • the analog-to-digital converter works in a conventional successive approximation mode; when the event detection logic circuit detects that an input event occurs, the analog-to-digital converter operates in a noise-shaping successive approximation mode type mode; when the event detection logic circuit detects that the input event is completed, the analog-to-digital converter works in a conventional successive approximation type mode.
  • the input events include the following categories:
  • the analog-to-digital conversion process of the data converter includes a residual error processing stage, a sampling stage, a conversion stage and an event detection stage; in the residual error processing stage, the power-gated loop filter integrates the input residual error signal And filter processing, and output a residual analog signal; in the sampling stage, the switched capacitor array collects the input analog signal, and adds or subtracts it to the residual analog signal; in the conversion stage, the control logic circuit according to the result of the comparator , to control the switched capacitor array and generate an analog-to-digital conversion result; in the event detection phase, the event detection logic circuit judges whether an input event occurs.
  • the present invention can be realized through a differential structure, and can also be simply modified into a single-ended structure; the switched capacitor array and the power gating loop filter described in the differential structure are both front and rear two-stage structures, and the input of the front-stage switched capacitor array is Analog signal, the output signal of the pre-stage switched capacitor array is directly provided to the pre-stage power gating loop filter, and the output signal of the pre-stage power gating loop filter is provided to the post-stage switched capacitor array and the post-stage power supply through the switch circuit
  • the output of the switched capacitor array in the subsequent stage is connected to the power gated loop filter in the subsequent stage, and the output of the power gated loop filter in the subsequent stage is used as the input of the comparator.
  • the power-gated loop filter adopts an IIR filter, which includes a power-gated amplifier and a capacitor, and the capacitor is connected across the input and output ends of the power-gated amplifier in the form of negative feedback.
  • the loop filter is controlled by a power gating signal, and when the power gating signal is detected, the loop filter is turned off, consuming little power.
  • the data converter of the present invention works in a conventional successive approximation mode and detects whether an input event occurs. At this time, since the loop filter is in an off state, the data converter consumes less energy; When an input event is detected, the data converter of the present invention operates in a noise-shaping successive approximation mode, thereby converting the input signal with high precision. Therefore, the present invention can dynamically adapt to sparse signals, and realize the advantages of low power consumption standby and high-precision conversion.
  • Fig. 1 is a system block diagram of the data converter of the present invention.
  • FIG. 2 is a schematic structural diagram of a specific implementation of the data converter of the present invention.
  • Fig. 3(a) is a schematic structural diagram of the data converter of the present invention working in a conventional SAR mode.
  • FIG. 3( b ) is a schematic structural diagram of the data converter of the present invention working in the noise-shaping SAR mode.
  • FIG. 4 is a schematic diagram of the workflow of the data converter of the present invention.
  • Figure 5(a) is a schematic diagram of event triggering or completion when the system works in the conventional successive approximation state when the static signal is input, and in the noise-shaping successive approximation state when the dynamic signal is input.
  • Figure 5(b) is a schematic diagram of event triggering or completion when the system works in the noise-shaping successive approximation state when the static signal is input, and in the conventional successive approximation state when the dynamic signal is input.
  • FIG. 6 is a schematic diagram of a simulation result of the data converter of the present invention.
  • FIG. 7 is a schematic diagram of a specific implementation structure of an event detection logic circuit in the present invention.
  • the adaptive noise shaping successive approximation data converter of the present invention includes a switched capacitor array, a power gating loop filter, a comparator, a control logic circuit and an event detection logic circuit.
  • the data converter operates in the noise-shaping successive-approximation mode in the reset state, and the switched capacitor array samples the input analog signal and performs successive approximation; when the data converter operates in the noise-shaping successive-approximation mode, the power-gated loop filter
  • the input information at this time and the last conversion information will be integrated, filtered, etc., and the output signal will be sent to the comparator; the comparator can judge the signal size of its non-inverting input terminal and out-of-phase input terminal.
  • the control logic circuit When the signal at the in-phase input terminal is greater than When the input signal is out of phase, the comparator outputs a high level, otherwise, it outputs a low level; the control logic circuit will quantify the output signal of the integrator according to the judgment result of the comparator, and output the digital conversion result; the event detection logic The circuit will judge whether there is an input event at this time according to the digital quantization result and the previous digital quantization result; if the event detection logic circuit detects that an input event has occurred at this time, the data converter maintains the operation in the noise shaping successive approximation mode; If the event detection logic circuit detects that no input event occurs at this time, and the duration exceeds the set time window, the data converter works in the conventional successive approximation mode; when the data converter works in the regular successive approximation mode, The power gating loop filter will be turned off, no signal processing will be performed, and almost no energy will be consumed; the control logic circuit will quantify the voltage value output by the switched capacitor array according to the judgment result of the comparator, and
  • Input events include the detection of a reset signal; the detection of a change in the current A/D conversion result compared to the previous A/D conversion result and the signal change exceeds/below a set threshold; Compared with the result, the result changes and the pattern of the signal change appears the set rule; it is detected that the current analog-to-digital conversion result is compared with the previous analog-to-digital conversion result, and the signal change is lower than/exceeding the set threshold and the duration exceeds The set time window; it is detected that the current analog-to-digital conversion result is compared with the previous analog-to-digital conversion result, and the signal does not change according to the set rule and the duration exceeds the set time window.
  • Fig. 2 is a kind of specific embodiment of the present invention, and it mainly has two-stage switched capacitor integrators as loop filter, a comparator, a control logic circuit, an event detection logic circuit and a group of reconfiguration switches to constitute;
  • the switched capacitor integrator filter consists of a switched capacitor array and an IIR filter;
  • the IIR filter includes a power-gated amplifier and a capacitor, and the capacitor is connected across the input and output terminals of the power-gated amplifier in the form of negative feedback;
  • the analog The input signal is connected to the first-stage switched capacitor integrator through sampling, the analog input signal is sampled through the switched capacitor array, and the other end of the switched capacitor array is connected to the IIR filter, and the signal integration is completed;
  • the output of the first-stage switched capacitor integrator connected to the second-stage switched capacitor integrator through two reconstruction switches;
  • the output of the second-stage switched capacitor integrator is connected to the input terminal of the voltage comparator, and the output terminal of the voltage comparator is connected to the control logic circuit
  • the specific implementation structure of the event detection logic circuit in this embodiment is as shown in Figure 7.
  • the digital signal read will enter the feature matching circuit, and the feature matching circuit will generate a circuit from the feature signal (for example, a preset ROM, from the ROM Read the data of the characteristic signal) to obtain the data of the characteristic signal, and then perform signal matching. If the matching is successful at a certain moment, the signal will be sent to the control circuit, and the control circuit will control the counting circuit to open, and the counting circuit will start working to record the signal matching. Duration, when the preset time threshold is exceeded, a signal will be sent to the control circuit to indicate that an event has occurred, and the control circuit will then generate PG and ⁇ NS_SAR signals to the system.
  • ⁇ NS_SAR is equivalent to Figure 2 and Figure 3 Signal.
  • the working principle of this embodiment is: the analog signal is connected to the first-stage switched capacitor array through sampling, wherein the charge amount collected by the switched capacitor array represents the information of the analog signal; the other end of the switched capacitor array is connected to the first-stage integrator, and the integrated
  • the device is composed of a differential amplifier, whose input and output form a feedback loop through an integrating capacitor, and the other feedback loop is composed of a switch, whose function is to short-circuit this level of integrator and make it in a closed state; the first level of integrator
  • the output of the output is connected to the second-stage integrator through two forms of circuits, one is directly connected to the second-stage integrator through a pair of switches, and the other is connected to a pair of switched capacitor arrays through a switch , the other end of the switched capacitor array is connected to the second-stage integrator, and the turn-on times of the two circuits are complementary, corresponding to two operating modes respectively.
  • the composition of the second-stage integrator is the same as that of the first-stage integrator.
  • the output of the second-stage integrator is connected to a two-input comparator, and the output of the comparator is connected to the control logic circuit.
  • the control logic circuit is a Mealey-type finite state machine, which The function is to output the control signal correspondingly according to the current state and the output of the comparator, control the operation of the whole circuit, and output the corresponding converted digital signal at the same time.
  • the switch control logic is fed back to the two-stage switched capacitor array through the control line, and the digital signal is also transmitted to the event detection logic circuit. Output, to determine whether there is a change in the event type, output the corresponding control signal, and feed back to the two-stage amplifier and the corresponding switch in the circuit through the signal line.
  • This embodiment has reconfiguration capabilities.
  • the data converter does not detect an input event, it will be reconfigured into a conventional successive approximation mode. Its structure is shown in Figure 3(a).
  • the ⁇ SAR signal is high level, The signal is low level, and the PG signal is not enabled; the input analog signal is sampled to the first-stage switched capacitor array, and is directly connected to the two-input comparator through the route of the closed switch effectively controlled by ⁇ SAR .
  • the circuit connection is the same as the overall frame connection of the circuit system; the event detection logic circuit turns off the active amplifier in the loop filter through the power gating signal, and the IIR filter in the loop filter does not work, so as to save energy the goal of.
  • the data converter When the data converter detects an input event, it will be reconstructed into a noise-shaping successive approximation mode, and its structure is shown in Figure 3(b).
  • the ⁇ SAR signal is low, The signal is high level, and the PG signal is enabled; the input analog signal is sampled to the first-stage switched capacitor array, and the other end of the switched capacitor array is connected to the first-stage integrator; the output of the first-stage integrator is connected to the second The second-stage switched capacitor array, the other end of the second-stage switched capacitor array is connected to the second-stage integrator, the composition of the second-stage integrator is the same as that of the first-stage integrator, and the output of the second-stage integrator is connected to a two-input comparator,
  • the circuit connection after the comparator is the same as the overall frame connection of the circuit system; the IIR filter in the loop filter will work normally, and the input signal will be integrated and filtered to realize noise shaping and improve conversion accuracy.
  • the present invention combines the advantages of SAR and NS SAR circuits, and the designed analog-to-digital converter is composed of these two structural parts, which can be configured between the two modes, making full use of the low power consumption of SAR circuits and NS SAR The advantage of high precision.
  • Figure 5(a) shows that when a static signal is input, the data converter works in a conventional successive approximation state, while when a dynamic signal is input, the data converter works in a noise-shaping successive approximation state;
  • Figure 5(b) shows Because when a static signal is input, the data converter works in a noise-shaping successive approximation state, and when a dynamic signal is input, the data converter works in a conventional successive approximation state.
  • Figure 6 shows the spectrum of this example working in different modes. It can be seen that this example can perform dynamic processing on the noise, and obtain a higher signal-to-noise ratio in the noise shaping successive approximation mode. It can be seen from the above examples that the present invention brings adaptability to the system, and judges whether an input event occurs through the event detection logic circuit, thereby achieving dynamic adaptation to sparse signals, realizing the advantages of low power consumption standby, and high-precision conversion .

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Abstract

本发明公开了一种适应性噪声成形逐次逼近型数据转换器，包括：开关电容阵列、开关电路、电源门控环路滤波器、比较器、控制逻辑电路以及事件检测逻辑电路。当未检测到输入事件时，本发明数据转换器工作在常规逐次逼近模式待机，并检测是否有输入事件发生，此时，由于环路滤波器处于关断状态，数据转换器消耗能耗较少；当检测到输入事件时，本发明数据转换器工作在噪声成形逐次逼近模式，从而实现高精度转换输入信号。因此，本发明可对稀疏性信号进行动态适应，实现低功耗待机，高精度转换的优点。

Description

一种适应性噪声成形逐次逼近型数据转换器 技术领域
本发明属于CMOS偏置电路技术领域，具体涉及一种适应性噪声成形逐次逼近型数据转换器。
背景技术
模数转换器(Analog-to-Digital Converter，ADC)是一种能将模拟信号转换成数字信号的电子器件，由于自然界中的大部分物理信号以模拟信号的形式存在，而计算机系统擅于高效率处理数字信号，因此为了对物理信号进行高效率处理，模数转换器必不可少。
模数转换器根据其转换机理可以分为不同的类型，其中逐次逼近型(Successive Approximation Register，SAR)ADC是一种低功耗、中等精度的ADC结构。一方面，SAR ADC是一种奈奎斯特采样率ADC，其采样率遵从奈奎斯特采样定律；另一方面，SAR ADC的电路实践中通常不需要使用任何运算放大器，并可通过单个比较器实现多比特的数字量化，因此其具备较好的能量效率。然而，由于电子器件(如电容器)的失配在高比特模数转换器中会越发明显并引入误差，这使得SAR ADC转换精度受到了限制。
噪声成形技术有助于提升ADC的转换精度，近年来噪声成形SAR ADC被人们提出以显著提高SAR ADC的转换精度。噪声成形SAR ADC不同于常规的SAR ADC在于两个特征即过采样以及噪声成形，过采样的特征表现于ADC的采样频率高于奈奎斯特采样率，噪声成形的特征表现于其利用控制环路，对输入信号以及量化噪声进行处理，通过环路滤波器为特定频段的信号提供增益，提高模数转换过程中特定频段内的信噪比。其中，环路滤波器往往具备积分器、滤波器或谐振器等电路，这些电路通常包含有高功耗的运算放大器；此外，现有的噪声成形SAR ADC均要求每一次转换过程中都将开启环路滤波器，并工作在过采样的条件下，由于环路滤波器以及过采样都将带来额外的功耗，因此现 有的噪声成形SAR ADC功耗通常高于常规的SAR ADC。
对于具备稀疏性的模拟输入信号，可以采用具备事件驱动能力的ADC进行模数信号转换，以降低模数转换器的功耗；目前有两类具备事件驱动能力的ADC，一类为电平触发ADC，另一类为流水线型ADC。首先，电平触发ADC仅在输入电压变化超过1个最小量化台阶时受到驱动，对输入信号进行采样，而在输入信号不发生改变时，保持低功耗待机状态，因此电平触发ADC可在处理稀疏性信号时显著降低系统功耗。然而，电平触发ADC的触发概率会随其转换精度的增高而增高，因此该方案仅适用于低转换精度的系统。流水线型ADC可利用第一级电路的输出对输入事件进行判断，并根据判断结果决定是否开启第二级电路进行高精度量化，尽管流水线型ADC可通过多级转换实现较高的转换精度，然而该方案要求高增益的级间放大器以确保残差放大的线性度，这使得其功耗水平下降。
综上所述，当前的具备事件驱动能力的ADC难以平衡精度与功耗之间的矛盾，虽然现有的SAR ADC具备较低的能耗，然而其转换精度有限；而另一方面，现有的噪声成形SAR ADC具备较高的转换精度，然而其能耗较高。注意到常规的SAR ADC与噪声成形SAR ADC架构上有很强的内在联系，因此提出一种具备事件驱动能力的适应性噪声成形逐次逼近型数据转换器，能够高效率地处理稀疏性信号。
发明内容
鉴于上述，本发明提供了一种适应性噪声成形逐次逼近型数据转换器，适用于处理稀疏性信号，具有高精度、低能耗的优点。
一种适应性噪声成形逐次逼近型数据转换器，包括：
开关电容阵列，利用控制逻辑电路提供的数字控制信号对输入模拟信号逐次逼近后输出至开关电路；
开关电路，根据事件检测逻辑电路提供的控制信号，选择开关电容阵列输出的模拟信号通过电源门控环路滤波器输入至比较器或直接输入至比较器；
电源门控环路滤波器，用于对输入信号进行积分及滤波处理；
比较器，对输入信号进行比较后产生输出结果；
控制逻辑电路，根据比较器的输出结果生成相应的数字信号输出，同时生成数字控制信号用于控制开关电容阵列；
事件检测逻辑电路，根据控制逻辑电路输出的数字信号判别当前是否有输入事件发生，并根据输入事件对开关电路以及电源门控环路滤波器进行配置。
进一步地，所述事件检测逻辑电路未检测到输入事件发生时，模数转换器工作在常规逐次逼近型模式；事件检测逻辑电路检测到输入事件发生时，模数转换器工作在噪声成形逐次逼近型模式；事件检测逻辑电路检测到输入事件完成时，模数转换器工作在常规逐次逼近型模式。
进一步地，所述输入事件包括以下几类：
①检测到复位信号；
②检测到当前模数转换结果与之前转换结果相比发生改变，且变化量超过或低于所设定的阈值；
③检测到当前模数转换结果与之前转换结果相比发生改变，且信号结果的改变形式在所设定的规律范畴(如频率变化、带宽变化、振幅变化)内；
④检测到当前模数转换结果与之前转换结果相比发生改变，变化量低于或超过所设定的阈值，且持续时间超过了所设定的时间窗口；
⑤检测到当前模数转换结果与之前转换结果相比发生改变，但信号结果的改变形式不在所设定的规律范畴内，且持续时间超过了所设定的时间窗口。
进一步地，所述数据转换器的模数转换过程包括余差处理阶段、采样阶段、转换阶段和事件检测阶段；在余差处理阶段，电源门控环路滤波器将输入的余差信号进行积分及滤波处理，并输出一个余差模拟信号；在采样阶段，开关电容阵列采集输入模拟信号，并将其与余差模拟信号相加或相减；在转换阶段，控制逻辑电路根据比较器的结果，控制开关电容阵列并生成模数转换结果；在事件检测阶段，事件检测逻辑电路判断是否有输入事件发生。
本发明既可以通过差分结构实现，也可以简单修正为单端结构；差分结构中所述的开关电容阵列以及电源门控环路滤波器均为前后两级结构，前级开关电容阵列的输入为模拟信号，前级开关电容阵列的输出信号直接提供给前级电源门控环路滤波器，前级电源门控环路滤波器的输出信号经过开关电路提供给后级开关电容阵列和后级电源门控环路滤波器，后级开关电容阵列的输出连接 至后级电源门控环路滤波器，后级电源门控环路滤波器的输出作为比较器的输入。
进一步地，所述的电源门控环路滤波器采用IIR滤波器，其包含一个电源门控放大器以及一个电容器，电容器以负反馈形式跨接在电源门控放大器的输入和输出端。环路滤波器通过电源门控信号进行控制，在检测到电源门控信号时，环路滤波器被关断，几乎不消耗能量。
当未检测到输入事件时，本发明数据转换器工作在常规逐次逼近模式待机，并检测是否有输入事件发生，此时由于环路滤波器处于关断状态，数据转换器消耗能耗较少；当检测到输入事件时，本发明数据转换器工作在噪声成形逐次逼近模式，从而实现高精度转换输入信号。因此，本发明可对稀疏性信号进行动态适应，实现低功耗待机，高精度转换的优点。
附图说明
图1为本发明数据转换器的系统框图。
图2为本发明数据转换器的具体实施结构示意图。
图3(a)为本发明数据转换器工作在常规SAR模式下的结构示意图。
图3(b)为本发明数据转换器工作在噪声成形SAR模式下的结构示意图。
图4为本发明数据转换器的工作流程示意图。
图5(a)为静态信号输入时系统工作在常规逐次逼近状态，而动态信号输入时系统工作在噪声成形逐次逼近型状态的事件触发或完成示意图。
图5(b)为静态信号输入时系统工作在噪声成形逐次逼近状态，而动态信号输入时系统工作在常规逐次逼近型状态的事件触发或完成示意图。
图6为本发明数据转换器的仿真结果示意图。
图7为本发明中事件检测逻辑电路的具体实现结构示意图。
具体实施方式
为了更为具体地描述本发明，下面结合附图及具体实施方式对本发明的技术方案进行详细说明。
如图1所示，本发明适应性噪声成形逐次逼近型数据转换器，包括开关电容阵列、电源门控环路滤波器、比较器、控制逻辑电路以及事件检测逻辑电路。
数据转换器在复位状态下工作在噪声成形逐次逼近型模式，开关电容阵列对输入模拟信号采样并进行逐次逼近；当数据转换器工作在噪声成形逐次逼近型模式时，电源门控环路滤波器将会对此时的输入信息以及上一次的转化信息进行积分、滤波等处理，输出信号给比较器；比较器可判断其同相输入端和异相输入端的信号大小，当其同相输入端信号大于异相输入端信号时，比较器输出高电平，反之，则输出低电平；控制逻辑电路将会根据比较器判定结果，对积分器输出信号进行量化，并输出数字转换结果；事件检测逻辑电路将会根据此次数字量化结果以及之前数字量化结果判断此时是否有输入事件发生；如果事件检测逻辑电路检测到此时有输入事件发生，数据转换器维持工作在噪声成型逐次逼近型模式；如果事件检测逻辑电路检测到此时没有输入事件发生，且持续时间超过了所设定的时间窗口，数据转换器工作在常规逐次逼近型模式；当数据转换器工作在常规逐次逼近型模式时，电源门控环路滤波器将会被关断，不进行信号处理，几乎不消耗能量；控制逻辑电路将会根据所述比较器判定结果，对开关电容阵列输出的电压值进行量化，并输出数字转换结果。
输入事件包括检测到复位信号；检测到当前模数转换结果与之前模数转换结果相比发生改变且信号改变超过/低于所设定的阈值；检测到当前模数转换结果与之前模数转换结果相比发生改变且信号改变的形式出现了所设定的规律；检测到当前模数转换结果与之前模数转换结果相比，信号改变低于/超过所设定的阈值且持续时间超过了所设定的时间窗口；检测到当前模数转换结果与之前模数转换结果相比，信号不以所设定的规律发生改变且持续时间超过了所设定的时间窗口。
图2为本发明的一种具体实施例，其主要有两级开关电容积分器作为环路滤波器、一个比较器、一个控制逻辑电路、一个事件检测逻辑电路以及一组重构开关所构成；开关电容积分器滤波器包含一个开关电容阵列以及一个IIR滤波器所构成；IIR滤波器包含一个电源门控放大器以及一个电容器，电容器以负反馈形式跨接在电源门控放大器的输入输出端；模拟输入信号通过采样连接到第一级开关电容积分器，通过开关电容阵列对模拟输入信号进行采样，开关电容 阵列另一端连接至IIR滤波器，并完成信号积分；第一级开关电容积分器的输出，通过两个重构开关连接至第二级开关电容积分器；第二级开关电容积分器输出连接至电压比较器输入端，电压比较器输出端连接到控制逻辑电路，对模数转换器进行控制；若电压比较器同相输入端大于等于反相输入端，电压比较器输出高电平，反之，则输出低电平；控制逻辑电路具有两类输出信号，即SAR逻辑控制信号、输出数字信号，控制逻辑电路通过逻辑控制信号连接至开关电容阵列，以完成模数转换；控制逻辑电路的输出数字信号与事件检测逻辑电路，事件检测电路将通过电源门控信号(PG)及电路重构信号(Φ SAR及
Figure PCTCN2022077522-appb-000001
)与电源门控放大器及重构开关相连接，从而实现电路连接的重构。
本实施例中事件检测逻辑电路的具体实现结构如图7所示，读取到的数字信号会进入特征匹配电路，特征匹配电路会从特征信号产生电路(例如是一个预设的ROM，从ROM中读取特征信号的数据)获取特征信号的数据，进而进行信号匹配，若某一时刻匹配成功，将发送信号至控制电路，控制电路控制计数电路开启，计数电路开始工作，以记录信号匹配的时长，当超过预设的时间阈值后，将发送信号至控制电路，表示事件发生，控制电路随之产生PG及Φ NS_SAR信号至系统，Φ NS_SAR等效于图2和图3中的
Figure PCTCN2022077522-appb-000002
信号。
本实施例的工作原理为：模拟信号通过采样连接到第一级开关电容阵列，其中开关电容阵列采集到的电荷量表征模拟信号的信息；开关电容阵列另一端连接至第一级积分器，积分器的构成为一个差分放大器，其输入输出通过一个积分电容器形成反馈回路，另外一条反馈回路是由开关构成，其作用是将这一级积分器短路，使其处于关闭状态；第一级积分器的输出通过两种形式的电路与第二级积分器相连，一种形式为直接通过一对开关与第二级积分器相连，另一种形式为通过一个开关后再与一对开关电容阵列相连，开关电容阵列的另一端连接至第二级积分器，这两条电路的开启时间是互补的，分别对应两种工作模式。第二级积分器构成与第一级积分器相同，第二级积分器的输出连接至一个二输入比较器，比较器输出连接至控制逻辑电路，控制逻辑电路为一个米利型有限状态机，其作用是根据当前状态及比较器的输出，对应地输出控制信号，控制整体电路的运行，同时输出相应的转换后的数字信号。其中开关控制逻辑通过控制线反馈到两级开关电容阵列，数字信号同时还会传输到事件检测逻辑 电路，事件检测逻辑电路同样是一个米利型有限状态机，其作用是根据当前状态及数字信号的输出，判断是否存在事件类型的改变，输出相应的控制信号，通过信号线反馈到两级放大器以及电路中相应的开关。
本实施例具备重构能力，当数据转换器没有检测到输入事件时，将会被重构为常规逐次逼近模式，其结构如图3(a)所示，在该模式下Φ SAR信号为高电平，
Figure PCTCN2022077522-appb-000003
信号为低电平，PG信号为不使能；输入的模拟信号被采样至第一级开关电容阵列，通过由Φ SAR有效控制的闭合开关的路线直接连接至二输入比较器，比较器之后的电路连接情况与电路系统整体框架连接相同；其中事件检测逻辑电路通过电源门控信号将环路滤波器中的有源放大器关断，环路滤波器中的IIR滤波器不工作，达到节省能耗的目的。
当数据转换器检测到输入事件时，将会被重构为噪声成形逐次逼近模式，其结构如图3(b)所示，在该模式下Φ SAR信号为低电平，
Figure PCTCN2022077522-appb-000004
信号为高电平，PG信号为使能；输入的模拟信号被采样至第一级开关电容阵列，开关电容阵列另一端连接至第一级积分器；第一级积分器的输出连接至第二级开关电容阵列，第二级开关电容阵列的另一端连接至第二级积分器，第二级积分器的构成同第一级积分器，第二级积分器的输出连接至二输入比较器，比较器之后的电路连接情况与电路系统整体框架连接相同；其中环路滤波器中的IIR滤波器将正常工作，对其输入信号进行积分、滤波等处理，实现噪声成形，达到提升转换精度的目的。由此可见，本发明结合利用SAR和NS SAR电路的优点，所设计的模数转换器是这两个结构部分构成，可在两个模式间进行配置，充分利用SAR电路低功耗以及NS SAR高精度的优势。
本实施例的工作流程如图4所示，其具备四种工作模式：
(1)数据转换器工作在常规逐次逼近型状态时，其电源门控信号(PG)会将环路滤波器中的有源放大器关断，开关阵列将通过Φ SAR以及Φ NS_SAR信号调整电路结构为常规逐次逼近型，其中Φ NS_SAR信号等效于图2和图3中的
Figure PCTCN2022077522-appb-000005
信号；数据转换器工作在常规逐次逼近型状态时，其转换周期具备采样、比较以及事件检测三个阶段；其中，采样阶段通过开关电容阵列对输入模拟信号进行采样；比较阶段的比较次数由开关电容阵列的位数决定；事件检测阶段没有检测到事件触发时，数据转换器将维持其常规逐次逼近型工作状态。
(2)数据转换器工作在常规逐次逼近型状态时，当事件检测阶段检测到事件触发时，数据转换器将在下一个转换周期切换至噪声成形工作状态。
(3)数据转换器工作在噪声成形逐次逼近型状态时，其电源门控信号(PG)将会闭合，使有源放大器进行正常工作，开关阵列将通过Φ SAR以及Φ NS_SAR信号调整电路结构为噪声成形逐次逼近型；数据转换器工作在常规逐次逼近型状态时，其转换周期具备余差处理、采样、比较以及事件检测四个阶段；其中，余差处理阶段将会对上一次转换的残差信号进行积分、滤波等处理，其处理结果存储在环路滤波器中；采样阶段通过开关电容阵列对输入模拟信号进行采样，并与上一次转换的残差信号进行整合；比较阶段的比较次数由开关电容阵列的位数决定；事件检测阶段有检测到事件触发时，数据转换器将维持其噪声成形逐次逼近型工作状态。
(4)数据转换器工作在噪声成形逐次逼近型状态时，当事件检测阶段检测到没有事件触发时，数据转换器将在下一个转换周期切换至常规逐次逼近工作状态。
图5(a)所示为当静态信号输入时，数据转换器工作在常规逐次逼近状态，而当动态信号输入时，数据转换器工作在噪声成形逐次逼近型状态；图5(b)所示为当静态信号输入时，数据转换器工作在噪声成形逐次逼近状态，而当动态信号输入时，数据转换器工作在常规逐次逼近型状态。
图6所示了本实例工作在不同模式下的频谱，可以看到，本实例可对噪声进行动态处理，在噪声成形逐次逼近模式下获得更高的信噪比。由以上示例可以看出，本发明为该系统带来适应性，通过事件检测逻辑电路判断是否由输入事件发生，达到了对稀疏性信号的动态适应，实现低功耗待机，高精度转换的优点。
上述对实施例的描述是为便于本技术领域的普通技术人员能理解和应用本发明，熟悉本领域技术的人员显然可以容易地对上述实施例做出各种修改，并把在此说明的一般原理应用到其他实施例中而不必经过创造性的劳动。因此，本发明不限于上述实施例，本领域技术人员根据本发明的揭示，对于本发明做出的改进和修改都应该在本发明的保护范围之内。

Claims (6)

  1. 一种适应性噪声成形逐次逼近型数据转换器，其特征在于，包括：
    开关电容阵列，利用控制逻辑电路提供的数字控制信号对输入模拟信号逐次逼近后输出至开关电路；
    开关电路，根据事件检测逻辑电路提供的控制信号，选择开关电容阵列输出的模拟信号通过电源门控环路滤波器输入至比较器或直接输入至比较器；
    电源门控环路滤波器，用于对输入信号进行积分及滤波处理；
    比较器，对输入信号进行比较后产生输出结果；
    控制逻辑电路，根据比较器的输出结果生成相应的数字信号输出，同时生成数字控制信号用于控制开关电容阵列；
    事件检测逻辑电路，根据控制逻辑电路输出的数字信号判别当前是否有输入事件发生，并根据输入事件对开关电路以及电源门控环路滤波器进行配置。
  2. 根据权利要求1所述的适应性噪声成形逐次逼近型数据转换器，其特征在于：所述事件检测逻辑电路未检测到输入事件发生时，模数转换器工作在常规逐次逼近型模式；事件检测逻辑电路检测到输入事件发生时，模数转换器工作在噪声成形逐次逼近型模式；事件检测逻辑电路检测到输入事件完成时，模数转换器工作在常规逐次逼近型模式。
  3. 根据权利要求2所述的适应性噪声成形逐次逼近型数据转换器，其特征在于：所述输入事件包括以下几类：
    ①检测到复位信号；
    ②检测到当前模数转换结果与之前转换结果相比发生改变，且变化量超过或低于所设定的阈值；
    ③检测到当前模数转换结果与之前转换结果相比发生改变，且信号结果的改变形式在所设定的规律范畴内；
    ④检测到当前模数转换结果与之前转换结果相比发生改变，变化量低于或超过所设定的阈值，且持续时间超过了所设定的时间窗口；
    ⑤检测到当前模数转换结果与之前转换结果相比发生改变，但信号结果的改变形式不在所设定的规律范畴内，且持续时间超过了所设定的时间窗口。
  4. 根据权利要求1所述的适应性噪声成形逐次逼近型数据转换器，其特征在于：所述数据转换器的模数转换过程包括余差处理阶段、采样阶段、转换阶段和事件检测阶段；在余差处理阶段，电源门控环路滤波器将输入的余差信号进行积分及滤波处理，并输出一个余差模拟信号；在采样阶段，开关电容阵列采集输入模拟信号，并将其与余差模拟信号相加或相减；在转换阶段，控制逻辑电路根据比较器的结果，控制开关电容阵列并生成模数转换结果；在事件检测阶段，事件检测逻辑电路判断是否有输入事件发生。
  5. 根据权利要求1所述的适应性噪声成形逐次逼近型数据转换器，其特征在于：所述的开关电容阵列以及电源门控环路滤波器均为前后两级结构，前级开关电容阵列的输入为模拟信号，前级开关电容阵列的输出信号直接提供给前级电源门控环路滤波器，前级电源门控环路滤波器的输出信号经过开关电路提供给后级开关电容阵列和后级电源门控环路滤波器，后级开关电容阵列的输出连接至后级电源门控环路滤波器，后级电源门控环路滤波器的输出作为比较器的输入。
  6. 根据权利要求1所述的适应性噪声成形逐次逼近型数据转换器，其特征在于：所述的电源门控环路滤波器采用IIR滤波器，其包含一个电源门控放大器以及一个电容器，电容器以负反馈形式跨接在电源门控放大器的输入和输出端。
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