WO2023077546A1 - 拼接显示面板和显示装置 - Google Patents

拼接显示面板和显示装置 Download PDF

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Publication number
WO2023077546A1
WO2023077546A1 PCT/CN2021/130297 CN2021130297W WO2023077546A1 WO 2023077546 A1 WO2023077546 A1 WO 2023077546A1 CN 2021130297 W CN2021130297 W CN 2021130297W WO 2023077546 A1 WO2023077546 A1 WO 2023077546A1
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WO
WIPO (PCT)
Prior art keywords
layer
display
driving
metal
connection terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2021/130297
Other languages
English (en)
French (fr)
Inventor
魏屈平
鲜于文旭
张春鹏
马蹄遥
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Original Assignee
Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority to US17/618,457 priority Critical patent/US12205929B2/en
Publication of WO2023077546A1 publication Critical patent/WO2023077546A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/302—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements characterised by the form or geometrical disposition of the individual elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/857—Interconnections, e.g. lead-frames, bond wires or solder balls
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/18—Tiled displays

Definitions

  • the present application relates to the field of display technology, in particular to a spliced display panel and a display device.
  • OLED Organic Light Emitting Diode
  • LTPS low temperature polysilicon
  • the present application also provides a display device including the spliced display panel.
  • This application provides a spliced display panel, including:
  • a display component comprising a display substrate and a plurality of first connection terminals electrically connected to the display substrate;
  • the driving backplane; the display component is arranged on the driving backplane; the driving backplane includes a connection circuit layer located in the display area; the connection circuit layer includes a plurality of the specified second connection terminal; and
  • the driving integrated circuit sequentially transmits signals to the first connection terminal and the display substrate through the second connection terminal, so as to drive the display substrate to emit light.
  • the first connection terminal and the second connection terminal are electrically connected together through a conductive material.
  • the conductive material is one or more of conductive film, conductive adhesive, metal solder, solder paste, and liquid metal.
  • the conductive adhesive is a polymer conductive adhesive or a conductive adhesive doped with conductive particles.
  • the doped conductive particles are one of metal particles, graphene, carbon nanotubes, and carbon fibers; Metal alloy particles composed of elemental particles, metal oxide particles composed of at least one elemental metal particle and oxygen, and metal composite materials, the elemental metal particles include one of gold, silver, copper, and aluminum, the Metal composite materials are composite materials composed of at least two of metal oxides, metal alloys and metal elemental particles, or composite materials composed of different types of metal oxides, or composite materials composed of different types of metal alloys.
  • the metal solder is an alloy solder composed of at least two metals of Bi-based, In-based, Sn-based, and Pb-based metals.
  • the spliced display panel further includes a display area and a non-display area located outside the display area; both the communication circuit layer and the display component are located in the display area;
  • the driving backplane further includes a base material layer, and both the communication circuit layer and the driving integrated circuit are formed on the base material layer.
  • the communication circuit layer further includes connecting wires located in the display area, a first interlayer insulating layer, and a second interlayer insulating layer, and the first interlayer insulating layer formed on the substrate layer, the connecting wiring is formed on the first interlayer insulating layer, the second interlayer insulating layer is formed on the connecting wiring, and the second connecting terminal passes through A first via hole penetrating through the second interlayer insulating layer electrically connects the connection wiring and the second connection terminal, the driving integrated circuit is located in the non-display area and electrically connects the connection wiring, The orthographic projections of the driving integrated circuit and the connecting wires on the substrate layer do not overlap.
  • the display substrate includes:
  • a driving circuit layer disposed on a side of the base substrate away from the driving backplane; the driving circuit layer is electrically connected to the first connection terminal;
  • a light-emitting functional layer located on the surface of the base substrate facing the driving backplane and is electrically connected to the light-emitting functional layer.
  • the communication circuit layer further includes a driving function layer located in the display area, and the second connection terminal is connected to the first via hole in the communication circuit layer.
  • the driving function layer is electrically connected, the driving integrated circuit is located in the non-display area and is in electrical contact with the driving function layer, and the orthographic projections of the driving integrated circuit and the driving function layer on the substrate layer do not overlap .
  • the communication circuit layer further includes a driving function layer located in the display area, and the second connection terminal is electrically connected to the driving function layer through the first via hole,
  • the driving integrated circuit is formed on the substrate layer located in the display area, the communication circuit layer is located on the driving integrated circuit; a sixth via hole is opened on the communication circuit layer, the The driving integrated circuit is electrically connected to the driving function layer through the sixth via hole.
  • the present application also provides a display device, including:
  • a housing formed with an accommodating chamber
  • the splicing display panel is arranged in the accommodating cavity.
  • a plurality of display components with light-emitting functions are bound to a driving backplane with a driving function, first connection terminals are arranged on the display components, and signal lines are arranged on the driving backplane and the second connection terminal, electrically connect the second connection terminal and the first connection terminal through a signal line, and then electrically connect the signal line through a driving integrated circuit, so as to transmit the signal to the display component to drive the display component to emit light, splicing
  • Fig. 1 is a top view of a spliced display panel provided by the first embodiment of the present application
  • Fig. 2 is a simple sectional view along II-II in Fig. 1;
  • FIG. 3 is a schematic cross-sectional view of the spliced display panel with the film layer structure of the driving backplane shown in FIG. 2;
  • FIG. 4 is a detailed schematic diagram of the film layer of the display component shown in FIG. 3;
  • Fig. 5 is a simple cross-section of a spliced display panel with a driving backplane film structure provided by the second embodiment of the present application;
  • FIG. 6 is a top view of the spliced display panel provided by the third embodiment of the present application.
  • FIG. 7 is a schematic cross-sectional view of the spliced display panel shown in FIG. 6;
  • FIG. 8 is a cross-sectional view of a display device provided by the present application.
  • This application aims at the technical problems of large borders and complex procedures of the spliced display panel of the existing display device.
  • This application binds a plurality of display components with light-emitting function Set the first connection terminal, set the second connection terminal on the driving backplane, the second connection terminal is electrically connected to the first connection terminal, and the driving integrated circuit is electrically connected to the second connecting terminal, so as to transmit the signal in the driving integrated circuit to the display component
  • the splicing process is less, and multiple small-sized display components can be easily spliced together, and multiple small-sized display components can be spliced into various shapes according to actual needs to achieve large Size seamless splicing display and multi-modal splicing display; in addition, by not setting the driving function layer or setting the driving function layer and/or the driving integrated circuit in the connecting circuit layer of the driving backplane, the size of the frame can be reduced, and even the Zero bezel stitching.
  • the first embodiment of the present application provides a tiled display panel 100 , the tiled display panel 100 includes a display area 101 and a non-display area 102 outside the display area 101 .
  • the mosaic display panel 100 further includes a plurality of display components 110 , a driving backplane 120 and a driving integrated circuit 130 .
  • a plurality of display components 110 are located in the display area 101 , and each display component 110 includes a plurality of first connection terminals 2 and a display substrate 1 electrically connected to the first connection terminals 2 .
  • the first connection terminals 2 are located on the surface of the display substrate 1 facing the driving backplane 120 .
  • a plurality of the display components 110 are arranged in an array on the driving backplane 120 .
  • the driving backplane 120 includes a communication circuit layer 70 located in the display area 101, the communication circuit layer 70 includes a plurality of second connection terminals 72, the first connection terminals 2 and the second connection terminals 72 Electrically connected, the driving integrated circuit 130 is electrically connected to the second connection terminal 72 .
  • the driving integrated circuit 130 sequentially transmits signals to the first connecting terminal 2 and the display substrate 1 through the second connecting terminal 72 to drive the display substrate 1 to emit light.
  • FIG. 1 Please refer to FIG. 1 again.
  • there is an assembly gap 140 between two adjacent display components 110 because a plurality of the driving integrated circuits 130 are located in the non-display area 102 instead of It is arranged in the assembly gap 140, so that the assembly gap 140 can be reduced, and even seamless splicing can be realized.
  • multiple display components 110 in the same column correspond to one driving integrated circuit 130 . That is, one driving integrated circuit 130 can simultaneously control multiple display components 110 in the same column to emit light of the same color and brightness.
  • one driver integrated circuit 130 can simultaneously control all or part of the display components 110 to emit light of the same color and brightness. Specifically, it can be set according to actual conditions.
  • connection circuit layer 70 also includes a connecting wire 73, a first interlayer insulating layer 74, a second interlayer insulating layer 75 and a sealant layer 76, and the connecting wire 73 is formed on the first interlayer insulating layer 74, the second interlayer insulating layer 75 is formed on the connecting wiring 73, and a plurality of first vias are opened on the second interlayer insulating layer 75.
  • connection terminal 72 is disposed on the second interlayer insulating layer 75 and is electrically connected to the connection wiring 73 through the first via hole 71, and the sealant layer 76 is disposed on the Between the second interlayer insulating layer 75 and the display substrate 1 and wrapping the second connecting terminal 72 and the first connecting terminal 2 .
  • the connection wire 73 is electrically connected to the second connection terminal 72 .
  • the sealant layer 76 is used for bonding the display assembly 110 and the driving backplane 120 , and fixing the first connecting terminal 2 and the second connecting terminal 72 .
  • the sealing layer 76 is an anisotropic conductive adhesive film (Anisotropic Conductive Film, ACF).
  • the driving integrated circuit 130 is located in the non-display area 102 and is electrically connected to the connecting wiring 73, and the orthographic projection of the driving integrated circuit 130 and the connecting wiring 73 on the substrate layer 60 Do not overlap.
  • the driving integrated circuit 130 sequentially transmits signals to the second connection terminal 72 , the first connection terminal 2 and the display substrate 1 through the connection wiring 73 to drive the display substrate 1 to emit light.
  • the driving backplane 120 further includes a substrate layer 60 on which the communication circuit layer 70 and the driving integrated circuits 130 are formed. . Specifically, the first interlayer insulating layer 74 is formed on the substrate layer 60 , and the driving integrated circuit 130 is located in the non-display area 102 and outside the communication circuit layer 70 .
  • the material of the substrate layer 60 can be selected from glass, polyimide (polyimide, PI), polyethylene terephthalate (polyethylene terephthalate, PET), non-woven fabrics, laminated film layers at least one of the other materials.
  • the display substrate 1 includes a base substrate 10 , a driving circuit layer 20 and a light emitting function layer 30 disposed on the side of the base substrate 10 away from the driving backplane 120 , and the first A connecting terminal 2 is located on the surface of the base substrate 10 facing the driving backplane 120 and is electrically connected to the light emitting functional layer 30 .
  • the driving circuit layer 20 is used to provide a driving voltage to the light-emitting functional layer 30 to make the light-emitting functional layer 30 emit light.
  • the display component 110 further includes an encapsulation layer 40 .
  • the base substrate 10 includes a first barrier layer 12 and a first substrate 13 stacked on the first connection terminal 2, and the first substrate 13 is located between the driving circuit layer 20 and the first Between barrier layers 12.
  • the first connection terminal 2 is arranged on the surface of the first barrier layer 12 away from the first substrate 13, in other embodiments, the first barrier layer 12 can also be The first connection terminal 2 is covered, and the lower surface of the first connection terminal 2 is exposed, that is, the first connection terminal 2 is embedded in the first barrier layer 12 and the first connection terminal 2 The lower surface is exposed.
  • the lower surface of the first connection terminal 2 refers to the surface of the first connection terminal 2 away from the first barrier layer 12 , and the lower surface is exposed for electrical connection with the driving backplane 120 .
  • the first connection terminal 2 can be made of a metal or alloy with strong oxidation resistance and low resistivity, or a metal laminate structure, metal oxide, conductive oxide, etc., such as MO, AL and other metals, so as to ensure that the first The stability of the connection terminal 2 and the reliability of the connection with the driving backplane 120 .
  • the base substrate 10 further includes a second barrier layer 14 disposed on a side of the first substrate 13 away from the first barrier layer 12 and a second barrier layer 14 disposed on a side away from the first barrier layer 12 .
  • the first barrier layer 12, the second barrier layer 14 and the first buffer layer 15 can be formed of inorganic materials such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), etc. , to prevent unwanted impurities or contaminants (eg moisture, oxygen, etc.) from diffusing from the first substrate 13 into devices that may be damaged by these impurities or contaminants.
  • the material of the first substrate 13 includes polyimide (Polyimide, PI) and other flexible film materials.
  • the first buffer layer 15 can also provide a flat top surface, so as to facilitate the preparation of the driving circuit layer 20 on the base substrate 10 .
  • the base substrate 10 of the present application is not limited thereto, and the base substrate 10 of the present application may include more or less inorganic film layers.
  • the driving circuit layer 20 is a transistor including a double-gate structure.
  • the driving circuit layer 20 includes a first semiconductor layer 21, a third interlayer insulating layer 22, a first gate 23, a fourth interlayer insulating layer 24, a second gate 27, a fifth interlayer insulating layer 28 and source and drain layers 25, the first semiconductor layer 21 is disposed on the base substrate 10, more specifically, the first semiconductor layer 21 is disposed on the first buffer layer 15, the first A semiconductor layer 21 includes a channel region 211 and a source region 212 and a drain region 213 located on opposite sides of the channel region 211 .
  • the third interlayer insulating layer 22 covers the first semiconductor layer 21 and the base substrate 10 .
  • the driving circuit layer 20 may also be a transistor including a single gate structure.
  • the first gate 23 is disposed on the third interlayer insulating layer 22 , and the first gate 23 is disposed corresponding to the channel region 211 of the first semiconductor layer 21 .
  • the fourth interlayer insulating layer 24 covers the first gate 23 and the third interlayer insulating layer 22 .
  • the second gate 27 is disposed on the fourth interlayer insulating layer 24 and is disposed corresponding to the first gate 23, and a capacitance is formed between the second gate 27 and the first gate 23 , the fifth interlayer insulating layer 28 covers the second gate 27 and the fourth interlayer insulating layer 24, and the source-drain layer 25 is disposed on the fifth interlayer insulating layer 28 , pattern the source-drain layer 25 to form a source 251, a drain 252, and a data line 253, etc., and the source 251 and the drain 252 are respectively connected to the corresponding source of the first semiconductor layer 21.
  • the region 212 is electrically connected to the drain region 213
  • the data line 253 is electrically connected to the corresponding first connection terminal 2 .
  • the driving circuit layer 20 further includes a second via hole 241, and the second via hole 241 penetrates through the fifth interlayer insulating layer 28, the fourth interlayer insulating layer 24, the third layer Inter-insulation layer 22, the first buffer layer 15, the second barrier layer 14, the first substrate 13 and the first barrier layer 12, so as to expose the part of the first connection terminal 2 Surface, the upper surface of the first connection terminal 2 refers to the surface parallel to and opposite to the lower surface of the first connection terminal 2 .
  • the data line 253 is electrically connected to the first connection terminal 2 through the second via hole 241, and at the same time, the data line 253 is also electrically connected to the source electrode 251 or the drain electrode 252.
  • the electrical connection between the data line 253 and the source electrode 251 is taken as an example for illustration.
  • the driving circuit layer 20 further includes a third via hole 242 and a fourth via hole 243, the third via hole 242 and the fourth via hole 243 both penetrate through the fifth interlayer insulating layer 28,
  • the fourth interlayer insulating layer 24 and part of the third interlayer insulating layer 22 are used to expose part of the first semiconductor layer 21 respectively, and the source 251 is connected to the third via hole 242 through the third via hole 242.
  • the source region of the first semiconductor layer 21 is electrically connected, and the drain 252 is electrically connected to the drain region of the first semiconductor layer 21 through the fourth via hole 243 .
  • the driving circuit layer 20 further includes a planarization layer 26 covering the source-drain layer 25 and the fifth interlayer insulating layer 28 .
  • the structure of the driving circuit layer 20 in the present application is not limited to that shown in this embodiment, the driving circuit layer 20 of the present application may also include more or fewer film layers, and the positional relationship of each film layer is not limited to this embodiment. Illustrated by example.
  • the light emitting functional layer 30 includes a pixel electrode 31 , a pixel definition layer 32 , a light emitting unit 33 and a cathode 34 .
  • the pixel electrode 31 is disposed on the planarization layer 26, and is electrically connected to the source electrode 251 or the drain electrode 252 through the via hole of the planarization layer 26.
  • the electrical connection between the data line 253 and the source electrode 251 is described as an example, and correspondingly, this embodiment is described by taking the electrical connection between the pixel electrode 31 and the drain electrode 252 as an example.
  • the pixel definition layer 32 is disposed on the pixel electrode 31 and the planarization layer 26, and the pixel definition layer 32 is patterned to form a pixel opening, and the pixel opening exposes part of the pixel electrode 31, so as to The installation area of the light emitting unit 33 is defined.
  • the light-emitting unit 33 is formed by vapor-depositing or printing the light-emitting material in the pixel opening of the pixel definition layer 32 , and the light-emitting material of different colors forms the light-emitting unit 33 of different colors.
  • the light-emitting unit 33 may include a red light-emitting unit formed by a red light-emitting material, a green light-emitting unit formed by a green light-emitting material, and a blue light-emitting unit formed by a blue light-emitting material.
  • the red light-emitting unit emits red light
  • the green light-emitting unit emits green light.
  • light the blue light-emitting unit emits blue light.
  • the cathode 34 covers the light emitting unit 33 and the pixel definition layer 32 .
  • the light emitting unit 33 emits light under the joint action of the pixel electrode 31 and the cathode 34 , and the light emitting unit 33 of different colors emits light of different colors, thereby realizing the pixel display of the display component 110 .
  • the pixel electrode 31 may be a transparent electrode or a reflective electrode. If the pixel electrode 31 is a transparent electrode, the pixel electrode 31 may be made of, for example, indium tin oxide (ITO), indium zinc oxide (IZO), Formation of ZnO or In2O3. If the pixel electrode 31 is a reflective electrode, the pixel electrode 31 may include, for example, a reflective layer formed of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr or a combination thereof and a reflective layer made of ITO , IZO, ZnO or In2O3 layer. However, the pixel electrode 31 is not limited thereto, and the pixel electrode 31 may be formed of various materials, and may also be formed in a single-layer or multi-layer structure.
  • the pixel electrode 31 is a transparent electrode or a reflective electrode depends on the light emitting direction of the tiled display panel 100.
  • the pixel electrode 31 can be a transparent electrode.
  • reflective electrodes of course, when reflective electrodes are used, the utilization rate of light emitted by the light emitting unit 33 can be improved; when the spliced display panel 100 adopts bottom emission, the pixel electrodes 31 use transparent electrodes to increase the transmittance of light.
  • the spliced display panel 100 adopts top emission as an example for illustration.
  • the cathode 34 needs to be formed of a transparent conductive material.
  • the cathode 34 may be formed of transparent conductive oxide (Transparent Conductive Oxide, TCO) such as ITO, IZO, ZnO or In2O3.
  • TCO Transparent Conductive Oxide
  • the light-emitting functional layer 30 may also include a hole injection layer (HIL, not shown in the figure), a hole transport layer (HTL, not shown in the figure) disposed between the light-emitting unit 33 and the pixel electrode 31. and an electron injection layer (EIL, not shown) and an electron transport layer (ETL, not shown) disposed between the light emitting unit 33 and the cathode 34 .
  • HIL hole injection layer
  • HTL hole transport layer
  • ETL electron transport layer
  • the hole injection layer receives the holes transmitted by the pixel electrode 31, and the holes are transmitted to the light emitting unit 33 through the hole transport layer, and the electron injection layer receives the electrons transmitted by the cathode 34, and the electrons are transmitted to the light emitting unit 33 through the electron transport layer, and the holes and The electrons combine at the position of the light emitting unit 33 to generate excitons, and the excitons transition from the excited state to the ground state to release energy and emit light.
  • the encapsulation layer 40 covers the light-emitting functional layer 30 and is used to protect the light-emitting unit 33 of the light-emitting functional layer 30 and prevent the light-emitting unit 33 from failing due to intrusion of water and oxygen.
  • the encapsulation layer 40 can be encapsulated with a thin film, for example, the encapsulation layer 40 can be a laminated structure formed by sequentially laminating three layers of thin films of a first inorganic encapsulation layer, an organic encapsulation layer and a second inorganic encapsulation layer or more Multilayer laminated structure.
  • the display component 110 further includes a gate driving circuit (not shown), the gate driving circuit is electrically connected to the driving circuit layer 20 for providing scanning signals.
  • the mosaic display panel 100 sequentially transmits the signals in the driving integrated circuit 130 to the second connecting terminal 72, the second connecting terminal 72, A connection terminal 2, the driving circuit layer 20 and the light-emitting functional layer 30, and cooperate with the gate drive circuit located in the display component 110 to drive the display component 110 to emit light, because in this embodiment, multiple display components 110 share
  • One drive integrated circuit 130 compared with the corresponding setting of one drive integrated circuit for each display component in the prior art, can effectively reduce the frame area occupied by the drive integrated circuit; in addition, the connecting route connecting the display component 110 and the drive integrated circuit 130
  • the line 73 is provided on the connecting circuit layer 70 of the driving backplane 120, and it does not need to occupy the area of the frame area. Compared with the fan-out wiring connecting the display component and the driving integrated circuit in the prior art, which needs to occupy a certain frame area, it can effectively The area of the peripheral circuit is reduced, so that small frame mosaic display can be realized.
  • first connection terminal 2 and the second connection terminal 72 are electrically connected together through a conductive material 80 .
  • the conductive material 80 includes, but is not limited to, one or more of conductive film, conductive adhesive, metal solder, solder paste, liquid metal, and the like.
  • the conductive adhesive includes but not limited to at least one of a polymer conductive adhesive, a conductive adhesive doped with conductive particles, and the like.
  • the conductive particles to be doped include but are not limited to metal particles, graphene, carbon nanotubes, carbon fibers and other simple conductive particles and at least one of composite materials composed of at least two simple conductive particles.
  • the metal particles include, but are not limited to, metal element particles, metal alloy particles composed of at least two kinds of metal element particles, metal oxide particles composed of at least one metal element particle and oxygen, and metal composite particles. one of the materials.
  • the metal elemental particles include, but are not limited to, conductive metal particles such as gold, silver, copper, and aluminum.
  • the metal composite material may be a metal composite material composed of at least two of the metal oxide, the metal alloy, and the metal elemental particles, or may be a metal composite composed of different types of metal oxides.
  • the composite material may also be a metal composite material composed of different kinds of metal alloys.
  • the metal solder is an alloy solder composed of at least two metals of Bi-based, In-based, Sn-based, and Pb-based metals.
  • the second embodiment of the present application provides a spliced display panel 200 , the structure of the spliced display panel 200 is similar to that of the spliced display panel 100 , the difference lies in:
  • the communication circuit layer 70 of the tiled display panel 200 further includes a driving function layer 701 located in the display area 101 , and the driving function layer 701 is formed on the substrate layer 60 located in the display area 101 Above, the second connection terminal 72 is electrically connected to the driving function layer 701 through the first via hole 71 , and the driving integrated circuit 130 is electrically connected to the driving function layer 701 . Orthographic projections of the driving integrated circuit 130 and the driving function layer 701 on the substrate layer 60 do not overlap.
  • the driving function layer 701 includes a plurality of driving transistors with a double-gate structure.
  • the driving function layer 701 includes a second buffer layer 77 formed on the first interlayer insulating layer 74, a second semiconductor layer 710 formed on the second buffer layer 77, a second semiconductor layer 710 formed on the The sixth interlayer insulating layer 78 on the second buffer layer 77 and covering the second semiconductor layer 710 , the sixth interlayer insulating layer 78 formed on the sixth interlayer insulating layer 78 and opposite to the second semiconductor layer 710
  • the gate 730 , the second interlayer insulating layer 75 is formed on the seventh interlayer insulating layer 79 and covers the fourth gate 730 .
  • the first via hole 71 penetrates through the second interlayer
  • the driving function layer 701 further includes a plurality of fifth via holes 740, a plurality of fifth via holes 740 located at one end of the fifth via holes 740 away from the second semiconductor layer 710 and electrically connected to the fifth via holes 740.
  • the connected third connection terminal 750 and the fourth connection terminal 760, the fourth connection terminal 760 is an extension of the third connection terminal 750 or both are electrically connected, the third connection terminal 750 and the first connection terminal 750
  • the two connection terminals 72 constitute the source and drain of the driving function layer 701 .
  • Each of the fifth via holes 740 passes through the second interlayer insulating layer 75 , the seventh interlayer insulating layer 79 and part of the sixth interlayer insulating layer 78 and is electrically connected to the second semiconductor layer 710 .
  • the driving integrated circuit 130 is electrically connected to the third connection terminal 750 through the fourth connection terminal 760 .
  • the driving function layer 701 may also include a driving transistor with a single gate structure.
  • the driving integrated circuit 130 is located in the non-display area 102, and the driving signal from the driving integrated circuit 130 passes through the fourth connection terminal 760, the third connection terminal 750, the The fifth via hole 740, the second semiconductor layer 710, the first via hole 71, the second connection terminal 72 and the first connection terminal 2 are transmitted into the display substrate 1 to drive the display substrate 1 glow.
  • the structure of the driving function layer 701 is not limited to the structure described above.
  • disposing the driving function layer 701 in the display area 101 can further reduce the area of peripheral circuits, and realize narrow frame splicing display.
  • the third embodiment of the present application provides a tiled display panel 300 , the structure of the tiled display panel 300 is similar to that of the tiled display panel 200 , the difference lies in: the driving function layer 701 Excluding the fourth connecting terminal 760, the driving integrated circuit 130 is disposed on the substrate layer 60 in the display area 101, and the communication circuit layer 70 is located on the driving integrated circuit 130, specifically Ground, the first interlayer insulating layer 74 is located on the driving integrated circuit 130, the driving function layer 701 is electrically connected to the driving integrated circuit 130, and the second connection terminal 72 is connected to the driving function layer 701 electrical connection.
  • the driving function layer 701 serves as a gate driving circuit (GOA circuit) of the spliced display panel 300 .
  • GAA circuit gate driving circuit
  • the driving function layer 701 further includes a plurality of sixth via holes 770, each of the sixth via holes 770 is electrically connected to one of the third connection terminals 750 and penetrates through the second interlayer insulating layer 75 , the seventh interlayer insulating layer 79 , the sixth interlayer insulating layer 78 , the second buffer layer 77 and the first interlayer insulating layer 74 are electrically connected to the driving integrated circuit 130 .
  • the peripheral area can be further reduced.
  • the area of the circuit is reduced to realize a narrow border splicing display.
  • the present application also provides a display device 1000, the display device 1000 includes a housing 2000 and a spliced display panel 100 or 200 or 300 in one of the above embodiments, the housing 2000 is formed with an accommodating cavity 201 , the spliced display panel 100 or 200 or 300 is disposed in the accommodation cavity 201 .
  • the splicing display panel of the display device provided by the present application, 1) bind a plurality of display components with light-emitting function on the drive backplane with driving function, set the first connection terminal on the display component, and set The second connection terminal, the second connection terminal is electrically connected to the first connection terminal, and the driving integrated circuit is electrically connected to the second connection terminal, so as to transmit the signal in the driving integrated circuit to the display component to drive the display component to emit light, and the splicing process is less , and multiple display components can be easily spliced together.
  • the signals in the driving integrated circuit are sequentially connected through the driving integrated circuit and the connecting wiring. transmitted to the second connection terminal, the first connection terminal, the driving circuit layer, and the light-emitting functional layer, and cooperate with the gate drive circuit located in the display component to drive the display component to emit light.
  • the components share a driver integrated circuit.
  • the frame area occupied by the driver integrated circuit can be effectively reduced; in addition, the connection wiring connecting the display component and the driver integrated circuit It is set on the connecting circuit layer of the driving backplane, and it does not need to occupy the area of the frame area.
  • the fan-out wiring connecting the display component and the driving integrated circuit in the prior art which needs to occupy a certain frame area, it can effectively reduce the peripheral circuit area. area, so as to realize small border splicing display.
  • disposing the driving function layer in the display area can further reduce the area of peripheral circuits and realize narrow-frame mosaic display.
  • the driving function layer in the display area, and simultaneously forming the driving integrated circuit on the substrate in the display area in the form of a film layer, the area of the peripheral circuit can be further reduced, and narrow Border mosaic display.

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Abstract

一种显示装置（1000）及拼接显示面板（100,200,300），拼接显示面板（100,200,300）包括：显示组件（110），显示组件（110）包括显示基板（1）及与显示基板（1）电连接的第一连接端子（2）；驱动背板（120），显示组件（110）设置在驱动背板（120）上；驱动背板（120）包括位于显示区（101）内的连通电路层（70），连通电路层（70）包括与第一连接端子（2）绑定的第二连接端子（72）；及驱动集成电路（130），与第二连接端子（72）电连接。

Description

拼接显示面板和显示装置 技术领域
本申请涉及显示技术领域，尤其涉及一种拼接显示面板和显示装置。
 背景技术
随着显示技术的发展，高分辨率与高刷新率的柔性有机发光二极管(Organic Light Emitting Diode，OLED)技术逐渐成为主流显示技术，目前，OLED技术已广泛应用于手机、平板、笔记本电脑等领域，但由于柔性OLED的低温多晶硅(low temperature poly-silicon，LTPS)器件特性，导致OLED最大尺寸在20寸以下，无法适用于大尺寸家电、电子产品、汽车、医疗等领域。
目前大尺寸OLED显示主要以拼接技术方式实现，现有发明中存在边框较大，技术实现困难，工序复杂等问题。
 技术问题
因此，现有大尺寸拼接显示屏的边框较大、工序复杂等问题是本案需要解决的。
 技术解决方案
本申请还提供一种包括所述拼接显示面板的显示装置。
为解决上述问题，本申请提供的技术方案如下：
本申请提供一种拼接显示面板，包括：
显示组件，所述显示组件包括一显示基板及与所述显示基板电连接的多个第一连接端子；
驱动背板；所述显示组件设置在所述驱动背板上；所述驱动背板包括位于所述显示区内的连通电路层；所述连通电路层包括多个与所述第一连接端子绑定的第二连接端子；及
驱动集成电路，与所述第二连接端子电连接；
其中，所述驱动集成电路通过所述第二连接端子将信号依次传输到所述第一连接端子及所述显示基板，以驱动所述显示基板发光。
在本申请一可选实施例中，所述第一连接端子和所述第二连接端子通过导电材料电连接在一起。
在本申请一可选实施例中，所述导电材料为导电胶膜、导电胶黏剂、金属焊料、锡膏、液态金属中的一种或多种。
在本申请一可选实施例中，所述导电胶黏剂为聚合物导电胶黏剂或掺杂导电粒子的导电胶黏剂。
在本申请一可选实施例中，掺杂的所述导电粒子为金属粒子、石墨烯、碳纳米管及碳纤维中的一种；所述金属粒子包括金属单质粒子、由至少两种所述金属单质粒子组成的金属合金粒子、由至少一种所述金属单质粒子和氧组成的金属氧化物粒子以及金属复合材料，所述金属单质粒子包括金、银、铜、铝中的一种，所述金属复合材料为由金属氧化物、金属合金及金属单质粒子中的至少两种构成的复合材料或为由不同种类的金属氧化物组成的复合材料或为由不同种类的金属合金组成的复合材料。
在本申请一可选实施例中，所述金属焊料为Bi系、In系、Sn系、Pb系金属中的至少两种金属组成的合金焊料。
在本申请一可选实施例中，所述拼接显示面板还包括显示区及位于所述显示区外侧的非显示区；所述连通电路层及所述显示组件均位于所述显示区内；所述驱动背板还包括基材层，所述连通电路层及所述驱动集成电路均形成在所述基材层上。
在本申请一可选实施例中，所述连通电路层还包括位于所述显示区内的连接走线、第一层间绝缘层及第二层间绝缘层，所述第一层间绝缘层形成在所述基材层上，所述连接走线形成在所述第一层间绝缘层上，所述第二层间绝缘层形成在所述连接走线上，所述第二连接端子通过一贯穿所述第二层间绝缘层的第一过孔电连接所述连接走线和所述第二连接端子，所述驱动集成电路位于所述非显示区且电连接所述连接走线，所述驱动集成电路及所述连接走线在所述基材层上的正投影不重叠。
在本申请一可选实施例中，所述显示基板包括：
衬底基板；
设置于所述衬底基板的远离所述驱动背板一侧的驱动电路层；所述驱动电路层与所述第一连接端子电连接；及
发光功能层；所述第一连接端子位于所述衬底基板的面向所述驱动背板的表面上且与所述发光功能层电连接。
在本申请一可选实施例中，所述连通电路层还包括位于所述显示区内的驱动功能层，所述第二连接端子通过开设于所述连通电路层内的第一过孔与所述驱动功能层电连接，所述驱动集成电路位于非显示区内且与所述驱动功能层电接触，所述驱动集成电路及所述驱动功能层在所述基材层上的正投影不重叠。
在本申请一可选实施例中，所述连通电路层还包括位于所述显示区内的驱动功能层，所述第二连接端子通过所述第一过孔与所述驱动功能层电连接，所述驱动集成电路形成在位于所述显示区内的所述基材层上，所述连通电路层位于所述驱动集成电路上；所述连通电路层上还开设有第六过孔，所述驱动集成电路通过所述第六过孔与所述驱动功能层电连接。
本申请还提供一种显示装置，包括：
壳体，形成有容纳腔；及
如上所述的拼接显示面板，所述拼接显示面板设置在所述容纳腔内。
 有益效果
本申请提供的显示装置的拼接显示面板，将多个具有发光功能的显示组件绑定在具有驱动功能的驱动背板上，在显示组件上设置第一连接端子，在驱动背板上设置信号线和第二连接端子，通过信号线电连接第二连接端子并电连接第一连接端子，再通过一驱动集成电路电连接信号线，从而将信号传输到显示组件上，以驱动显示组件发光，拼接工序较少，且可以轻易将多个小尺寸的显示组件拼接在一起，且可以根据实际需要将多个小尺寸的显示组件拼接成各种形状，以实现大尺寸无缝拼接显示以及多形态拼接显示；另外，通过不设置驱动功能层或将驱动功能层及/或驱动集成电路设置在驱动背板的连通电路层内，可以减小边框的尺寸，甚至实现零边框拼接。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1为本申请第一实施例提供的一种拼接显示面板的俯视图；
图2为沿图1中的II-II的简单剖面示意图；
图3为图2所示的带有驱动背板的膜层结构的拼接显示面板的简单剖面示意图；
图4为图3所示的显示组件的详细膜层示意图；
图5为本申请第二实施例提供的带有驱动背板的膜层结构的拼接显示面板的简单剖面；
图6为本申请第三实施例提供的拼接显示面板的俯视图；
图7为图6所示的拼接显示面板的简单剖面示意图；及
图8为本申请提供的一种显示装置的剖视图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要理解的是，术语“上”、“下”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体地限定。
本申请可以在不同实施中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。
本申请针对现有的显示装置的拼接显示面板的边框较大、工序复杂的技术问题，本申请将多个具有发光功能的显示组件绑定在具有驱动功能的驱动背板上，在显示组件上设置第一连接端子，在驱动背板上设置第二连接端子，第二连接端子电连接第一连接端子，驱动集成电路电连接第二连接端子，从而将驱动集成电路中的信号传输到显示组件上，以驱动显示组件发光，拼接工序较少，且可以轻易将多个小尺寸的显示组件拼接在一起，且可以根据实际需要将多个小尺寸的显示组件拼接成各种形状，以实现大尺寸无缝拼接显示以及多形态拼接显示；另外，通过不设置驱动功能层或将驱动功能层及/或驱动集成电路设置在驱动背板的连通电路层内，可以减小边框的尺寸，甚至实现零边框拼接。
以下将结合具体实施例对本申请的拼接显示面板及显示装置进行详细描述。
请参阅图1-2，本申请第一实施例提供一种拼接显示面板100，所述拼接显示面板100包括显示区101及位于所述显示区101外侧的非显示区102。所述拼接显示面板100还包括多个显示组件110、驱动背板120及驱动集成电路130。多个所述显示组件110位于所述显示区101内，每个所述显示组件110包括多个第一连接端子2及与所述第一连接端子2电连接的显示基板1。所述第一连接端子2位于所述显示基板1的面向所述驱动背板120的表面上。多个所述显示组件110阵列排布在所述驱动背板120上。所述驱动背板120包括位于所述显示区101内的连通电路层70，所述连通电路层70包括多个第二连接端子72，所述第一连接端子2与所述第二连接端子72电连接，所述驱动集成电路130与所述第二连接端子72电连接。所述驱动集成电路130通过所述第二连接端子72将信号依次传输到所述第一连接端子2及所述显示基板1，以驱动所述显示基板1发光。
请再次参阅图1，在本实施例中，相邻的两个所述显示组件110之间具有组装间隙140，由于多个所述驱动集成电路130均位于所述非显示区102内，而非设置在所述组装间隙140内，从而能够减小所述组装间隙140，甚至实现无缝拼接。在本实施例中，同一列多个所述显示组件110对应一个所述驱动集成电路130。也即，一个所述驱动集成电路130可以同时控制同一列多个所述显示组件110发出同样颜色和亮度的光。
当然，在其他实施例中，一个所述驱动集成电路130可以同时控制所有或部分所述显示组件110发出同样颜色和亮度的光。具体地，可根据实际情况进行设定。
请参阅图3，在本实施例中，所述连通电路层70还包括连接走线73、第一层间绝缘层74、第二层间绝缘层75及封胶层76，所述连接走线73形成在所述第一层间绝缘层74上，所述第二层间绝缘层75形成在所述连接走线73上，所述第二层间绝缘层75上开设有多个第一过孔71，所述第二连接端子72设置在所述第二层间绝缘层75上且通过所述第一过孔71与所述连接走线73电连接，所述封胶层76设置在所述第二层间绝缘层75和所述显示基板1之间且包裹所述第二连接端子72及所述第一连接端子2。所述连接走线73与所述第二连接端子72电连接。
其中，所述封胶层76用于粘结所述显示组件110及所述驱动背板120，并固定所述第一连接端子2和所述第二连接端子72。在本实施例中，所述封胶层76为异方性导电胶膜(Anisotropic Conductive Film，ACF)。
具体地，所述驱动集成电路130位于所述非显示区102且电连接所述连接走线73，所述驱动集成电路130及所述连接走线73在所述基材层60上的正投影不重叠。所述驱动集成电路130通过所述连接走线73将信号依次传输到所述第二连接端子72、所述第一连接端子2及所述显示基板1，以驱动所述显示基板1发光。
请参阅图2及图3，在本实施例中，所述驱动背板120还包括基材层60，所述连通电路层70及所述驱动集成电路130均形成在所述基材层60上。具体地，所述第一层间绝缘层74形成在所述基材层60上，所述驱动集成电路130位于所述非显示区102内且位于所述连通电路层70的外侧。
其中，所述基材层60的材质可以选自玻璃、聚酰亚胺(polyimide，PI)、聚对苯二甲酸乙二醇酯(polyethylene terephthalate，PET)、无纺布、符合叠构膜层等材料中的至少一种。
其中，请参阅图4，所述显示基板1包括衬底基板10、设置于所述衬底基板10的远离所述驱动背板120一侧的驱动电路层20及发光功能层30，所述第一连接端子2位于所述衬底基板10的面向所述驱动背板120的表面上且与所述发光功能层30电连接。所述驱动电路层20用于给所述发光功能层30提供驱动电压，以使所述发光功能层30发光。而为了保护所述发光功能层30的可靠性，避免水氧入侵导致发光功能层30失效，所述显示组件110还包括封装层40。
所述衬底基板10包括层叠设置在所述第一连接端子2上的第一阻隔层12和第一衬底13，所述第一衬底13位于所述驱动电路层20和所述第一阻隔层12之间。在本实施例中，所述第一连接端子2设置在所述第一阻隔层12的远离所述第一衬底13的表面上，在其他实施例中，所述第一阻隔层12还可以覆盖所述第一连接端子2，且所述第一连接端子2的下表面裸露，也即，所述第一连接端子2嵌在所述第一阻隔层12内且所述第一连接端子2的下表面裸露。其中，所述第一连接端子2的下表面是指所述第一连接端子2的远离所述第一阻隔层12的表面，该下表面裸露用于与所述驱动背板120电连接。所述第一连接端子2可使用抗氧化性强且电阻率低的金属或合金或金属叠层结构、金属氧化物、导电氧化物等制备，如MO、AL等金属，以保证所述第一连接端子2的稳定性以及与所述驱动背板120连接的可靠性。
可选地，所述衬底基板10还包括设置于所述第一衬底13的远离所述第一阻隔层12一侧的第二阻隔层14以及设置于所述第二阻隔层14远离所述第一衬底13一侧的第一缓冲层15。其中，所述第一阻隔层12、所述第二阻隔层14以及所述第一缓冲层15均可由氧化硅（SiOx）、氮化硅（SiNx）、氮氧化硅（SiON）等无机材料形成，以防止不期望的杂质或污染物（例如湿气、氧气等）从所述第一衬底13扩散至可能因这些杂质或污染物而受损的器件中。而所述第一衬底13的材料包括聚酰亚胺（Polyimide，PI）等柔性薄膜材料。同时所述第一缓冲层15还可以提供平坦的顶表面，以利于在所述衬底基板10上制备所述驱动电路层20。当然地，本申请的所述衬底基板10不限于此，本申请的衬底基板10可包括更多或更少的无机膜层。
可选地，在本实施例中，所述驱动电路层20为包括双栅结构的晶体管。具体地，所述驱动电路层20包括第一半导体层21、第三层间绝缘层22、第一栅极23、第四层间绝缘层24、第二栅极27、第五层间绝缘层28以及源漏极层25，所述第一半导体层21设置于所述衬底基板10上，更具体地，所述第一半导体层21设置于所述第一缓冲层15上，所述第一半导体层21包括沟道区211以及位于所述沟道区211相对两侧的源极区212和漏极区213。所述第三层间绝缘层22覆于所述第一半导体层21及所述衬底基板10上。当然，在其他实施例中，所述驱动电路层20还可以为包括单栅结构的晶体管。
其中，所述第一栅极23设置于所述第三层间绝缘层22上，所述第一栅极23与所述第一半导体层21的沟道区211对应设置。所述第四层间绝缘层24覆于所述第一栅极23及所述第三层间绝缘层22上。所述第二栅极27设置于所述第四层间绝缘层24上且与所述第一栅极23对应设置，所述第二栅极27与所述第一栅极23之间形成电容，所述第五层间绝缘层28覆于所述第二栅极27及所述第四层间绝缘层24上，所述源漏极层25设置于所述第五层间绝缘层28上，图案化所述源漏极层25形成有源极251、漏极252以及数据线253等，所述源极251和所述漏极252分别与对应的所述第一半导体层21的源极区212和漏极区213电连接，所述数据线253与对应的所述第一连接端子2电连接。
具体地，所述驱动电路层20还包括第二过孔241，所述第二过孔241贯穿所述第五层间绝缘层28、所述第四层间绝缘层24、所述第三层间绝缘层22、所述第一缓冲层15、所述第二阻隔层14、所述第一衬底13以及所述第一阻隔层12，以裸露出所述第一连接端子2的部分上表面，所述第一连接端子2的上表面是指与所述第一连接端子2的所述下表面平行相对的一面。所述数据线253通过所述第二过孔241与所述第一连接端子2电连接，同时所述数据线253还与所述源极251或所述漏极252电连接，本申请以所述数据线253与所述源极251电连接为例说明。
进一步地，所述驱动电路层20还包括第三过孔242及第四过孔243，所述第三过孔242及所述第四过孔243均贯穿所述第五层间绝缘层28、所述第四层间绝缘层24以及部分所述第三层间绝缘层22，以分别裸露出部分所述第一半导体层21，所述源极251通过所述第三过孔242与所述第一半导体层21的源极区电连接，所述漏极252通过所述第四过孔243与所述第一半导体层21的漏极区电连接。
同时为了给所述驱动电路层20提供平坦的表面，所述驱动电路层20还包括覆于所述源漏极层25以及所述第五层间绝缘层28上的平坦化层26。
当然，本申请中驱动电路层20的结构不限于本实施例示意的，本申请的驱动电路层20还可包括更多或更少的膜层，且各膜层的位置关系也不限于本实施例示意的。
具体地，所述发光功能层30包括像素电极31、像素定义层32、发光单元33以及阴极34。所述像素电极31设置在所述平坦化层26上，并通过所述平坦化层26的过孔与所述源极251或所述漏极252电连接，当然地，由于本实施例以所述数据线253与所述源极251电连接为例说明，则相对应地，本实施例以所述像素电极31与所述漏极252电连接为例说明。所述像素定义层32设置于所述像素电极31以及所述平坦化层26上，且所述像素定义层32图案化形成有像素开口，所述像素开口裸露出部分所述像素电极31，以定义出发光单元33的设置区域。
所述发光单元33是由蒸镀或打印在所述像素定义层32的像素开口内的发光材料形成，不同颜色的发光材料形成不同颜色的发光单元33。比如发光单元33可以包括由红色发光材料形成的红色发光单元，由绿色发光材料形成的绿色发光单元，由蓝色发光材料形成的蓝色发光单元，红色发光单元发出红光，绿色发光单元发出绿光，蓝色发光单元发出蓝光。
所述阴极34覆盖所述发光单元33以及所述像素定义层32。所述发光单元33在所述像素电极31和所述阴极34的共同作用下发光，不同颜色的发光单元33发射不同颜色的光，进而实现所述显示组件110的像素显示。
可选地，所述像素电极31可以是透明电极或反射电极，如果所述像素电极31是透明电极，则所述像素电极31可以由例如氧化铟锡(ITO)、氧化铟锌(IZO)、ZnO或In2O3形成。如果所述像素电极31是反射电极，则所述像素电极31例如可以包括由Ag、Mg、Al、Pt、Pd、Au、Ni、Nd、Ir、Cr或它们的组合形成的反射层以及由ITO、IZO、ZnO或In2O3形成的层。然而，像素电极31不限于此，像素电极31可以由各种材料形成，并且也可以形成为单层或多层结构。
需要说明的是，所述像素电极31具体是采用透明电极还是反射电极需取决于所述拼接显示面板100的出光方向，当拼接显示面板100采用顶发光时，所述像素电极31可以是透明电极或反射电极，当然地，采用反射电极时能够提高发光单元33发出光线的利用率；当拼接显示面板100采用底发光时，所述像素电极31采用透明电极，以提高光线的透过率。本实施例以所述拼接显示面板100采用顶发光为例说明，如此，为了提高光线的透过率，所述阴极34需采用透明导电材料形成。例如所述阴极34可由ITO、IZO、ZnO或In2O3等透明导电氧化物（Transparent Conductive Oxide，TCO）形成。
可选地，所述发光功能层30还可包括设置于所述发光单元33与所述像素电极31之间的空穴注入层(HIL，图未示)、空穴传输层(HTL，图未示)；以及设置于所述发光单元33与所述阴极34之间的电子注入层(EIL，图未示)、电子传输层(ETL，图未示)。空穴注入层接收像素电极31传输的空穴，空穴经由空穴传输层传输至发光单元33，电子注入层接收阴极34传输的电子，电子经由电子传输层传输至发光单元33，空穴和电子在发光单元33位置结合后产生激子，激子由激发态跃迁至基态释放能量并发光。
所述封装层40覆盖所述发光功能层30，用于保护所述发光功能层30的发光单元33，避免水氧入侵导致发光单元33失效。可选地，所述封装层40可采用薄膜封装，比如所述封装层40可以为由第一无机封装层、有机封装层及第二无机封装层三层薄膜依次层叠形成的叠层结构或更多层的叠层结构。
在本实施例中，所述显示组件110还包括栅极驱动电路(图未示)，所述栅极驱动电路与所述驱动电路层20电连接，用于提供扫描信号。
在本实施例中，所述拼接显示面板100靠所述驱动集成电路130以及所述连接走线73将所述驱动集成电路130中的信号依次传输到所述第二连接端子72、所述第一连接端子2、驱动电路层20及所述发光功能层30，并配合位于所述显示组件110内的栅极驱动电路驱动所述显示组件110发光，由于本实施例中多个显示组件110共用一个驱动集成电路130，相较于现有技术中每个显示组件对应设置一个驱动集成电路，可以有效减少驱动集成电路所占用的边框面积；此外，连接显示组件110和驱动集成电路130的连接走线73是设置在驱动背板120的连通电路层70，其无需占用边框区域的面积，相较于现有技术中连接显示组件和驱动集成电路的扇出走线需要占用一定的边框面积，可以有效减少了外围电路的面积，从而能够实现小边框拼接显示。
在本申请一可选实施例中，所述第一连接端子2和所述第二连接端子72通过导电材料80电连接在一起。
在本申请一可选实施例中，所述导电材料80包括但不局限于导电胶膜、导电胶黏剂、金属焊料、锡膏、液态金属等中的一种或多种。
其中，所述导电胶黏剂包括但不局限于聚合物导电胶黏剂及掺杂导电粒子的导电胶黏剂等中的至少一种。掺杂的所述导电粒子包括但不局限于金属粒子、石墨烯、碳纳米管、碳纤维等导电粒子单质以及由至少两种所述导电粒子单质组成的复合材料中的至少一种。其中，所述金属粒子包括但不局限于金属单质粒子、由至少两种所述金属单质粒子组成的金属合金粒子、由至少一种所述金属单质粒子和氧组成的金属氧化物粒子以及金属复合材料中的一种。所述金属单质粒子包括但不局限于金、银、铜、铝等导电金属粒子。所述金属复合材料可以为由所述金属氧化物、所述金属合金及所述金属单质粒子中的至少两种构成的金属复合材料，也可以为由不同种类的所述金属氧化物构成的金属复合材料，还可以为由不同种类的所述金属合金构成的金属复合材料。
其中，所述金属焊料为Bi系、In系、Sn系、Pb系金属中的至少两种金属组成的合金焊料。
请参阅图5，本申请第二实施例提供一种拼接显示面板200，所述拼接显示面板200的结构与所述拼接显示面板100的结构相似，其区别在于：
所述拼接显示面板200的所述连通电路层70还包括位于所述显示区101内的驱动功能层701，所述驱动功能层701形成在位于所述显示区101内的所述基材层60上，所述第二连接端子72通过所述第一过孔71与所述驱动功能层701电连接，所述驱动集成电路130与所述驱动功能层701电连接。所述驱动集成电路130及所述驱动功能层701在所述基材层60上的正投影不重叠。
在本实施例中，所述驱动功能层701包括多个具有双栅结构的驱动晶体管。具体地，所述驱动功能层701包括形成在所述第一层间绝缘层74上的第二缓冲层77、形成在所述第二缓冲层77上的第二半导体层710、形成在所述第二缓冲层77上且包覆所述第二半导体层710的第六层间绝缘层78、形成在所述第六层间绝缘层78上且与所述第二半导体层710位置相对的第三栅极720、形成在所述第六层间绝缘层78上且覆盖所述第三栅极720的第七层间绝缘层79及形成在所述第七层间绝缘层79上的第四栅极730，所述第二层间绝缘层75形成在所述第七层间绝缘层79上且包覆所述第四栅极730。所述第一过孔71贯穿所述第二层间绝缘层75、所述第七层间绝缘层79及部分第六层间绝缘层78且与所述第二半导体层710电连接。
其中，所述驱动功能层701还包括多个第五过孔740、多个位于所述第五过孔740的远离所述第二半导体层710的一端的且与所述第五过孔740电连接的第三连接端子750以及第四连接端子760，所述第四连接端子760为所述第三连接端子750的延长部分或者二者保持电连接，所述第三连接端子750与所述第二连接端子72构成了所述驱动功能层701的源漏极。每个所述第五过孔740贯穿所述第二层间绝缘层75、所述第七层间绝缘层79及部分第六层间绝缘层78且与所述第二半导体层710电连接。所述驱动集成电路130通过所述第四连接端子760与所述第三连接端子750电连接。
在其他实施例中，所述驱动功能层701还可以包括具有单栅结构的驱动晶体管。
在本实施例中，所述驱动集成电路130位于非显示区102内，来自于所述驱动集成电路130的驱动信号依次通过所述第四连接端子760、所述第三连接端子750、所述第五过孔740、所述第二半导体层710、所述第一过孔71、所述第二连接端子72及所述第一连接端子2传输至所述显示基板1内，以驱动显示基板1发光。在其他实施例中，所述驱动功能层701的结构并不局限于如上所述的结构。
其中，将所述驱动功能层701设置在显示区101内，可以进一步减小外围电路的面积，实现窄边框拼接显示。
请参阅图6-7，本申请第三实施例提供一种拼接显示面板300，所述拼接显示面板300的结构与所述拼接显示面板200的结构相似，其区别在于：所述驱动功能层701不包括所述第四连接端子760，所述驱动集成电路130设置在位于所述显示区101内的所述基材层60上，所述连通电路层70位于所述驱动集成电路130上，具体地，所述第一层间绝缘层74位于所述驱动集成电路130上，所述驱动功能层701与所述驱动集成电路130电连接，所述第二连接端子72与所述驱动功能层701电连接。其中，所述驱动功能层701作为所述拼接显示面板300的栅极驱动电路(GOA电路)。
具体地，所述驱动功能层701还包括多个第六过孔770，每个所述第六过孔770与一个所述第三连接端子750电连接且贯穿所述第二层间绝缘层75、所述第七层间绝缘层79、所述第六层间绝缘层78、所述第二缓冲层77及所述第一层间绝缘层74并与所述驱动集成电路130电连接。
本实施例通过将所述驱动功能层701设置在显示区101内，并同时将所述驱动集成电路130以膜层的形式形成在显示区101内的基材层60上，可以进一步减小外围电路的面积，实现窄边框拼接显示。
请参阅图8，本申请还提供一种显示装置1000，所述显示装置1000包括壳体2000和上述实施例其中之一的拼接显示面板100或200或300，所述壳体2000形成有容纳腔201，所述拼接显示面板100或200或300设置在所述容纳腔201内。本申请提供的显示装置的拼接显示面板，1)将多个具有发光功能的显示组件绑定在具有驱动功能的驱动背板上，在显示组件上设置第一连接端子，在驱动背板上设置第二连接端子，第二连接端子电连接第一连接端子，驱动集成电路电连接第二连接端子，从而将驱动集成电路中的信号传输到显示组件上，以驱动显示组件发光，拼接工序较少，且可以轻易将多个显示组件拼接在一起。
另外，通过不在所述驱动背板内设置驱动功能层，而是通过在驱动背板内设置驱动集成电路以及连接走线，通过驱动集成电路和连接走线将所述驱动集成电路中的信号依次传输到所述第二连接端子、所述第一连接端子、驱动电路层及所述发光功能层，并配合位于所述显示组件内的栅极驱动电路驱动所述显示组件发光，由于多个显示组件共用一个驱动集成电路，相较于现有技术中每个显示组件对应设置一个驱动集成电路，可以有效减少驱动集成电路所占用的边框面积；此外，连接显示组件和驱动集成电路的连接走线是设置在驱动背板的连通电路层，其无需占用边框区域的面积，相较于现有技术中连接显示组件和驱动集成电路的扇出走线需要占用一定的边框面积，可以有效减少了外围电路的面积，从而能够实现小边框拼接显示。
另外，将所述驱动功能层设置在显示区内，可以进一步减小外围电路的面积，实现窄边框拼接显示。
再者，通过将所述驱动功能层设置在显示区内，并同时将所述驱动集成电路以膜层的形式形成在显示区内的基材上，可以进一步减小外围电路的面积，实现窄边框拼接显示。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种拼接显示面板，其中，包括：
    显示组件，所述显示组件包括一显示基板及与所述显示基板电连接的多个第一连接端子；
    驱动背板；所述显示组件设置在所述驱动背板上；所述驱动背板包括连通电路层；所述连通电路层包括多个与所述第一连接端子绑定的第二连接端子；及
    驱动集成电路，与所述第二连接端子电连接；
    其中，所述驱动集成电路通过所述第二连接端子将信号依次传输到所述第一连接端子及所述显示基板，以驱动所述显示基板发光。
  2. 如权利要求1所述的拼接显示面板，其中，所述第一连接端子和所述第二连接端子通过导电材料电连接在一起。
  3. 如权利要求2所述的拼接显示面板，其中，所述导电材料为导电胶膜、导电胶黏剂、金属焊料、锡膏、液态金属中的一种或多种。
  4. 如权利要求3所述的拼接显示面板，其中，所述导电胶黏剂为聚合物导电胶黏剂或掺杂导电粒子的导电胶黏剂。
  5. 如权利要求4所述的拼接显示面板，其中，掺杂的所述导电粒子为金属粒子、石墨烯、碳纳米管及碳纤维中的一种；所述金属粒子包括金属单质粒子、由至少两种所述金属单质粒子组成的金属合金粒子、由至少一种所述金属单质粒子和氧组成的金属氧化物粒子以及金属复合材料，所述金属单质粒子包括金、银、铜、铝中的一种，所述金属复合材料为由金属氧化物、金属合金及金属单质粒子中的至少两种构成的复合材料或为由不同种类的金属氧化物组成的复合材料或为由不同种类的金属合金组成的复合材料。
  6. 如权利要求3所述的拼接显示面板，其中，所述金属焊料为Bi系、In系、Sn系、Pb系金属中的至少两种金属组成的合金焊料。
  7. 如权利要求1所述的拼接显示面板，其中，所述拼接显示面板还包括显示区及位于所述显示区外侧的非显示区；所述连通电路层及所述显示组件均位于所述显示区内；所述驱动背板还包括基材层，所述连通电路层及所述驱动集成电路均形成在所述基材层上。
  8. 如权利要求7所述的拼接显示面板，其中，所述连通电路层还包括位于所述显示区内的连接走线、第一层间绝缘层及第二层间绝缘层，所述第一层间绝缘层形成在所述基材层上，所述连接走线形成在所述第一层间绝缘层上，所述第二层间绝缘层形成在所述连接走线上，所述第二连接端子通过一贯穿所述第二层间绝缘层的第一过孔电连接所述连接走线和所述第二连接端子，所述驱动集成电路位于所述非显示区且电连接所述连接走线，所述驱动集成电路及所述连接走线在所述基材层上的正投影不重叠。
  9. 如权利要求1所述的拼接显示面板，其中，
    所述显示基板包括：
    衬底基板；
    设置于所述衬底基板的远离所述驱动背板一侧的驱动电路层；所述驱动电路层与所述第一连接端子电连接；及
    发光功能层；所述第一连接端子位于所述衬底基板的面向所述驱动背板的表面上且与所述发光功能层电连接。
  10. 如权利要求7所述的拼接显示面板，其中，所述连通电路层还包括位于所述显示区内的驱动功能层，所述第二连接端子通过开设于所述连通电路层内的第一过孔与所述驱动功能层电连接，所述驱动集成电路位于非显示区内且与所述驱动功能层电接触，所述驱动集成电路及所述驱动功能层在所述基材层上的正投影不重叠。
  11. 如权利要求7所述的拼接显示面板，其中，所述连通电路层还包括位于所述显示区内的驱动功能层，所述第二连接端子通过所述第一过孔与所述驱动功能层电连接，所述驱动集成电路形成在位于所述显示区内的所述基材层上，所述连通电路层位于所述驱动集成电路上；所述连通电路层上还开设有第六过孔，所述驱动集成电路通过所述第六过孔与所述驱动功能层电连接。
  12. 一种显示装置，其中，包括：
    壳体，形成有容纳腔；及
    拼接显示面板，所述拼接显示面板设置在所述容纳腔内；所述拼接显示面板包括：
    显示组件，所述显示组件包括一显示基板及与所述显示基板电连接的多个第一连接端子；
    驱动背板；所述显示组件设置在所述驱动背板上；所述驱动背板包括连通电路层；所述连通电路层包括多个与所述第一连接端子绑定的第二连接端子；及
    驱动集成电路，与所述第二连接端子电连接；
    其中，所述驱动集成电路通过所述第二连接端子将信号依次传输到所述第一连接端子及所述显示基板，以驱动所述显示基板发光。
  13. 如权利要求12所述的显示装置，其中，所述第一连接端子和所述第二连接端子通过导电材料电连接在一起。
  14. 如权利要求13所述的显示装置，其中，所述导电材料为导电胶膜、导电胶黏剂、金属焊料、锡膏、液态金属中的一种或多种。
  15. 如权利要求14所述的显示装置，其中，所述导电胶黏剂为聚合物导电胶黏剂或掺杂导电粒子的导电胶黏剂。
  16. 如权利要求15所述的显示装置，其中，掺杂的所述导电粒子为金属粒子、石墨烯、碳纳米管及碳纤维中的一种；所述金属粒子包括金属单质粒子、由至少两种所述金属单质粒子组成的金属合金粒子、由至少一种所述金属单质粒子和氧组成的金属氧化物粒子以及金属复合材料，所述金属单质粒子包括金、银、铜、铝中的一种，所述金属复合材料为由金属氧化物、金属合金及金属单质粒子中的至少两种构成的复合材料或为由不同种类的金属氧化物组成的复合材料或为由不同种类的金属合金组成的复合材料。
  17. 如权利要求14所述的显示装置，其中，所述金属焊料为Bi系、In系、Sn系、Pb系金属中的至少两种金属组成的合金焊料。
  18. 如权利要求13所述的显示装置，其中，所述导电材料为导电胶膜、导电胶黏剂、金属焊料、锡膏、液态金属中的一种或多种。
  19. 如权利要求12所述的显示装置，其中，所述拼接显示面板还包括显示区及位于所述显示区外侧的非显示区；所述连通电路层及所述显示组件均位于所述显示区内；所述驱动背板还包括基材层，所述连通电路层及所述驱动集成电路均形成在所述基材层上。
  20. 如权利要求19所述的显示装置，其中，所述连通电路层还包括位于所述显示区内的连接走线、第一层间绝缘层及第二层间绝缘层，所述第一层间绝缘层形成在所述基材层上，所述连接走线形成在所述第一层间绝缘层上，所述第二层间绝缘层形成在所述连接走线上，所述第二连接端子通过一贯穿所述第二层间绝缘层的第一过孔电连接所述连接走线和所述第二连接端子，所述驱动集成电路位于所述非显示区且电连接所述连接走线，所述驱动集成电路及所述连接走线在所述基材层上的正投影不重叠。
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