WO2023071984A1 - 一种集成mems热电堆红外探测器芯片以及芯片制作方法 - Google Patents

一种集成mems热电堆红外探测器芯片以及芯片制作方法 Download PDF

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WO2023071984A1
WO2023071984A1 PCT/CN2022/127045 CN2022127045W WO2023071984A1 WO 2023071984 A1 WO2023071984 A1 WO 2023071984A1 CN 2022127045 W CN2022127045 W CN 2022127045W WO 2023071984 A1 WO2023071984 A1 WO 2023071984A1
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chip
thermopile
infrared detector
infrared
substrate
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PCT/CN2022/127045
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English (en)
French (fr)
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李萍萍
胡维
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苏州敏芯微电子技术股份有限公司
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Publication of WO2023071984A1 publication Critical patent/WO2023071984A1/zh

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    • E—FIXED CONSTRUCTIONS
    • E01—CONSTRUCTION OF ROADS, RAILWAYS, OR BRIDGES
    • E01H—STREET CLEANING; CLEANING OF PERMANENT WAYS; CLEANING BEACHES; DISPERSING OR PREVENTING FOG IN GENERAL CLEANING STREET OR RAILWAY FURNITURE OR TUNNEL WALLS
    • E01H1/00—Removing undesirable matter from roads or like surfaces, with or without moistening of the surface
    • E01H1/10—Hydraulically loosening or dislodging undesirable matter; Raking or scraping apparatus ; Removing liquids or semi-liquids e.g., absorbing water, sliding-off mud
    • E01H1/108—Removing liquids or semi- liquids, e.g. absorbing rain water, sucking-off mud
    • C—CHEMISTRY; METALLURGY
    • C02—TREATMENT OF WATER, WASTE WATER, SEWAGE, OR SLUDGE
    • C02F—TREATMENT OF WATER, WASTE WATER, SEWAGE, OR SLUDGE
    • C02F9/00—Multistage treatment of water, waste water or sewage
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F04—POSITIVE - DISPLACEMENT MACHINES FOR LIQUIDS; PUMPS FOR LIQUIDS OR ELASTIC FLUIDS
    • F04C—ROTARY-PISTON, OR OSCILLATING-PISTON, POSITIVE-DISPLACEMENT MACHINES FOR LIQUIDS; ROTARY-PISTON, OR OSCILLATING-PISTON, POSITIVE-DISPLACEMENT PUMPS
    • F04C14/00—Control of, monitoring of, or safety arrangements for, machines, pumps or pumping installations
    • F04C14/08—Control of, monitoring of, or safety arrangements for, machines, pumps or pumping installations characterised by varying the rotational speed
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F04—POSITIVE - DISPLACEMENT MACHINES FOR LIQUIDS; PUMPS FOR LIQUIDS OR ELASTIC FLUIDS
    • F04C—ROTARY-PISTON, OR OSCILLATING-PISTON, POSITIVE-DISPLACEMENT MACHINES FOR LIQUIDS; ROTARY-PISTON, OR OSCILLATING-PISTON, POSITIVE-DISPLACEMENT PUMPS
    • F04C2/00—Rotary-piston machines or pumps
    • F04C2/08—Rotary-piston machines or pumps of intermeshing-engagement type, i.e. with engagement of co-operating members similar to that of toothed gearing
    • F04C2/12—Rotary-piston machines or pumps of intermeshing-engagement type, i.e. with engagement of co-operating members similar to that of toothed gearing of other than internal-axis type
    • F04C2/14—Rotary-piston machines or pumps of intermeshing-engagement type, i.e. with engagement of co-operating members similar to that of toothed gearing of other than internal-axis type with toothed rotary pistons
    • F04C2/18—Rotary-piston machines or pumps of intermeshing-engagement type, i.e. with engagement of co-operating members similar to that of toothed gearing of other than internal-axis type with toothed rotary pistons with similar tooth forms
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F04—POSITIVE - DISPLACEMENT MACHINES FOR LIQUIDS; PUMPS FOR LIQUIDS OR ELASTIC FLUIDS
    • F04C—ROTARY-PISTON, OR OSCILLATING-PISTON, POSITIVE-DISPLACEMENT MACHINES FOR LIQUIDS; ROTARY-PISTON, OR OSCILLATING-PISTON, POSITIVE-DISPLACEMENT PUMPS
    • F04C2/00—Rotary-piston machines or pumps
    • F04C2/30—Rotary-piston machines or pumps having the characteristics covered by two or more groups F04C2/02, F04C2/08, F04C2/22, F04C2/24 or having the characteristics covered by one of these groups together with some other type of movement between co-operating members
    • F04C2/34—Rotary-piston machines or pumps having the characteristics covered by two or more groups F04C2/02, F04C2/08, F04C2/22, F04C2/24 or having the characteristics covered by one of these groups together with some other type of movement between co-operating members having the movement defined in groups F04C2/08 or F04C2/22 and relative reciprocation between the co-operating members
    • F04C2/344—Rotary-piston machines or pumps having the characteristics covered by two or more groups F04C2/02, F04C2/08, F04C2/22, F04C2/24 or having the characteristics covered by one of these groups together with some other type of movement between co-operating members having the movement defined in groups F04C2/08 or F04C2/22 and relative reciprocation between the co-operating members with vanes reciprocating with respect to the inner member
    • F04C2/3441—Rotary-piston machines or pumps having the characteristics covered by two or more groups F04C2/02, F04C2/08, F04C2/22, F04C2/24 or having the characteristics covered by one of these groups together with some other type of movement between co-operating members having the movement defined in groups F04C2/08 or F04C2/22 and relative reciprocation between the co-operating members with vanes reciprocating with respect to the inner member the inner and outer member being in contact along one line or continuous surface substantially parallel to the axis of rotation
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F16—ENGINEERING ELEMENTS AND UNITS; GENERAL MEASURES FOR PRODUCING AND MAINTAINING EFFECTIVE FUNCTIONING OF MACHINES OR INSTALLATIONS; THERMAL INSULATION IN GENERAL
    • F16M—FRAMES, CASINGS OR BEDS OF ENGINES, MACHINES OR APPARATUS, NOT SPECIFIC TO ENGINES, MACHINES OR APPARATUS PROVIDED FOR ELSEWHERE; STANDS; SUPPORTS
    • F16M3/00—Portable or wheeled frames or beds, e.g. for emergency power-supply aggregates, compressor sets
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F16—ENGINEERING ELEMENTS AND UNITS; GENERAL MEASURES FOR PRODUCING AND MAINTAINING EFFECTIVE FUNCTIONING OF MACHINES OR INSTALLATIONS; THERMAL INSULATION IN GENERAL
    • F16M—FRAMES, CASINGS OR BEDS OF ENGINES, MACHINES OR APPARATUS, NOT SPECIFIC TO ENGINES, MACHINES OR APPARATUS PROVIDED FOR ELSEWHERE; STANDS; SUPPORTS
    • F16M7/00—Details of attaching or adjusting engine beds, frames, or supporting-legs on foundation or base; Attaching non-moving engine parts, e.g. cylinder blocks
    • C—CHEMISTRY; METALLURGY
    • C02—TREATMENT OF WATER, WASTE WATER, SEWAGE, OR SLUDGE
    • C02F—TREATMENT OF WATER, WASTE WATER, SEWAGE, OR SLUDGE
    • C02F1/00—Treatment of water, waste water, or sewage
    • C02F1/001—Processes for the treatment of water whereby the filtration technique is of importance
    • C—CHEMISTRY; METALLURGY
    • C02—TREATMENT OF WATER, WASTE WATER, SEWAGE, OR SLUDGE
    • C02F—TREATMENT OF WATER, WASTE WATER, SEWAGE, OR SLUDGE
    • C02F1/00—Treatment of water, waste water, or sewage
    • C02F1/50—Treatment of water, waste water, or sewage by addition or application of a germicide or by oligodynamic treatment
    • C—CHEMISTRY; METALLURGY
    • C02—TREATMENT OF WATER, WASTE WATER, SEWAGE, OR SLUDGE
    • C02F—TREATMENT OF WATER, WASTE WATER, SEWAGE, OR SLUDGE
    • C02F1/00—Treatment of water, waste water, or sewage
    • C02F1/52—Treatment of water, waste water, or sewage by flocculation or precipitation of suspended impurities
    • C02F1/5281—Installations for water purification using chemical agents
    • C—CHEMISTRY; METALLURGY
    • C02—TREATMENT OF WATER, WASTE WATER, SEWAGE, OR SLUDGE
    • C02F—TREATMENT OF WATER, WASTE WATER, SEWAGE, OR SLUDGE
    • C02F2303/00—Specific treatment goals
    • C02F2303/04—Disinfection

Definitions

  • the present application relates to a technical field of MEMS (micro-electromechanical systems), in particular to an integrated MEMS thermopile infrared detector chip and a method for manufacturing the chip.
  • MEMS micro-electromechanical systems
  • micro-electro-mechanical technology has become a mainstream high-tech by adopting advanced semiconductor manufacturing technology to realize batch manufacturing of micro-electro-mechanical system devices.
  • devices manufactured by MEMS have significant advantages in terms of volume, power consumption, price, and weight. Therefore, the use of advanced MEMS to manufacture devices is the main direction of future technology development.
  • MEMS devices generally include at least one sensitive moving part, so the sensitive parts need to be protected by packaging and other technologies during the manufacturing process.
  • MEMS devices are also electrically connected to integrated circuits to form a complete system. Therefore, in the manufacturing process, how to realize the integration of the system is an important issue.
  • the current common integration scheme includes packaging independent MEMS devices and integrated circuits in the same package for multi-chip integration. The two parts are adjacently installed on the same substrate, and then the two parts are electrically connected through leads, and finally integrated with a tube package. A longer lead between two independent devices will introduce greater interference to the device as a whole, thereby affecting the overall performance of the device.
  • thermopile sensors are one of the most commonly used sensing devices.
  • the infrared thermopile sensor is a non-contact thermal sensor that uses a thermopile to receive infrared radiation and converts infrared signals into electrical signals.
  • the infrared receiving film, that is, the thermopile is a sensitive component.
  • the traditional micro-electromechanical infrared thermopile package is generally packaged in a metal tube shell.
  • thermopile chip is placed on the tube base, and the discrete optical system for filtering effective infrared radiation is placed on the tube cap.
  • this packaging structure makes the overall volume of the device larger, and the applicable scenarios are limited, and the optical filter system also increases the cost of the device.
  • the separation and alignment of the optical system will also affect the effectiveness of external infrared radiation reaching the sensitive parts of the thermopile device, thereby reducing the sensitivity and accuracy of the device.
  • thermopile infrared detector chip including a first chip and a second chip electrically bonded to each other; wherein the first chip is a microelectromechanical system infrared detector chip.
  • the thermopile sensor chip, the second chip is an integrated circuit chip; the first electrical bonding point on the first chip is bonded to the second electrical bonding point on the second chip to form an electrical connection;
  • the first packaging ring on the first chip and the second packaging ring on the second chip are bonded to each other to form a cavity; and the first chip includes an infrared thermopile, and at least part of the infrared thermopile is in the A projection of the first chip surface is located within the cavity.
  • the cavity is a closed cavity.
  • the first electrical bonding point is closer to the infrared thermopile than the first packaging ring.
  • an optical system is formed on the first surface of the first chip, and the first surface of the first chip is a surface away from the first electrical bonding point.
  • the optical system includes a grating formed on the first surface of the first chip.
  • the optical system includes a grating on the first surface of the first chip substrate formed by etching.
  • the optical system includes a lens formed on the first surface of the first chip.
  • the second chip includes a substrate and an integrated circuit structure, one end of the integrated circuit structure is electrically connected to the first chip through the second electrical bonding point, and the other end of the integrated circuit structure is connected through the The conductive material in the conductive via of the substrate is electrically connected to an external circuit.
  • the application also proposes a method for preparing an integrated MEMS thermopile infrared detector chip, comprising preparing a first chip, the first chip being a microelectromechanical system infrared thermopile sensor chip; preparing a second chip, the second chip It is an integrated circuit chip; the first chip and the second chip are bonded by electrical bonding, and the first package ring on the first chip and the second chip are passed between the first and second chips.
  • the second packaging rings on the chip are bonded to each other to form a cavity; wherein the first chip includes an infrared thermopile, and at least part of the projection of the infrared thermopile on the surface of the first chip is located between the first chip and the first chip. In the cavity between the two chips.
  • preparing the first chip includes depositing a metal layer on the first surface of the first chip, and the first surface of the first chip is a surface away from the first electrical bonding point; the metal layer to form a grating.
  • preparing the first chip includes etching the substrate where the first surface of the first chip is located to form a grating.
  • preparing the first chip includes forming a mirror on the first surface of the first chip.
  • preparing the second chip includes forming a conductive via hole in the substrate of the second chip and filling it with a conductive material, wherein the conductive via hole opens on the first surface of the second chip; An integrated circuit structure is formed on the first surface of the second chip, and the first end of the conductive via is electrically connected to the integrated circuit structure.
  • preparing the second chip includes thinning the substrate of the second chip from the second surface to expose the second end of the conductive via hole, wherein the second surface of the second chip substrate is the surface opposite to the first surface; an extraction electrode electrically connected to the second end of the conductive via hole is formed.
  • the occupied space of the integrated thermopile infrared detector can be greatly saved, the volume of the thermopile infrared detector can be reduced, and the impact of the connection circuit on the chip caused by the wire bonding process can be reduced at the same time.
  • the cost of the packaged optical system is reduced, the manufacturing process of the thermopile infrared detector is reduced, and at the same time, the problem of low sensor sensitivity caused by the inability of the optical system to align with the sensitive components caused by the packaged optical system is effectively avoided. .
  • thermopile infrared detector chip used in this application can also shorten the distance from the external effective radiation entering the thermopile infrared detector chip to the sensitive parts, and improve the efficiency of infrared signals entering the thermopile infrared detector chip during storage. Problems such as reflection, radiation or attenuation, improve the absorption efficiency of the chip for infrared, and improve the accuracy of the thermopile infrared detector.
  • Fig. 1 is a schematic cross-sectional view of an integrated MEMS thermopile infrared detector chip according to one embodiment of the present application
  • FIGS. 2A to C are schematic cross-sectional views of the first chip in the integrated MEMS thermopile infrared detector chip according to different embodiments of the present application;
  • Fig. 3 is a schematic cross-sectional view of a second chip in an integrated MEMS thermopile infrared detector chip according to an embodiment of the present application;
  • 5A to D are flowcharts of a method for manufacturing an integrated MEMS thermopile infrared detector chip according to an embodiment of the present application.
  • Fig. 1 is a schematic cross-sectional view of an integrated MEMS thermopile infrared detector chip according to an embodiment of the present application.
  • the integrated MEMS thermopile infrared detector chip includes a first chip 10 a and a second chip 10 b electrically bonded to each other, and a cavity is formed between the first chip 10 a and the second chip 10 b through bonding.
  • the first chip 10a can be a MEMS infrared thermopile sensor chip, which can be used to sense the variation of external temperature, and it at least includes an infrared thermopile 112 and a first electrical connection layer, wherein the first electrical connection layer It can be used for electrical connection with the second chip 10b.
  • the first electrical connection layer may include a first electrical bond 14 and a first packaging ring 15 .
  • the second chip 10b can be an integrated circuit chip, which can be electrically connected to the first chip and an external circuit, respectively, and configured to receive the detection result of the first chip 10a and perform signal processing, and convert it into The resulting electrical signal is output to an external circuit.
  • the second chip 10 b includes at least an integrated circuit structure 181 and a second electrical connection layer, which may include a second electrical bonding point 16 and a second packaging ring 17 .
  • the cavity 12 may be formed between the first chip 10a and the second chip 10b by bonding the first packaging ring 15 and the second packaging ring 17.
  • the projection of at least part of the infrared thermopile 112 on the surface of the first chip 10a close to the cavity 12 is located in the cavity 12, which can protect the first chip 10a, especially the infrared thermopile 112, from the outside The environment interferes with the first chip 10a.
  • the electrical connection between the first chip 10a and the second chip 10b can be established by using the electrical bonding of the first electrical bonding point 14 and the second electrical bonding point 16, and the signal generated by the infrared thermopile 112 of the first chip is transferred.
  • corresponding processing is performed for the integrated circuit structure 181.
  • the cavity 12 formed between the first chip 10a and the second chip 10b may be airtight.
  • the airtight cavity 12 can better prevent external interference for the first chip 10 a , especially the infrared thermopile 112 .
  • the first electrical bonding point 14 may be closer to the infrared thermopile 112 than the first packaging ring 15 .
  • the preparation materials of the second electrical bonding point 16 and the second packaging ring 17 of the second chip 10b are selected from the preparation materials of the first electrical bonding point 14 and the first packaging ring 15 of the first chip 10a relevant.
  • the material of the first electrical bonding point 14 and the first packaging ring 15 includes germanium
  • the material of the second electrical bonding point 16 and the second packaging ring 17 may include aluminum
  • the material of the second electrical bonding point 16 and the second packaging ring 17 may include polysilicon.
  • FIGS. 2A to 2C are schematic cross-sectional views of the first chip of the integrated MEMS thermopile infrared detector chip according to different embodiments of the present application.
  • the first chip 210a may include a substrate such as a silicon substrate 2111, and the substrate 2111 may include a cavity 2113, a support portion 214 above the substrate 2111 and the cavity 2113, and a support portion 214 above the support portion 2114.
  • thermopile (wherein, the thermopile may include a first conductive layer 212b and a second conductive layer 212a electrically connected to each other), an insulating layer 215 positioned above the support portion 214 and the thermopile first conductive layer 212b, positioned between the insulating layer 215 and the thermoelectric layer
  • the passivation layer 216 above the second conductive layer 212 a is stacked, and the first electrical connection layer is located above the passivation layer 216 .
  • the materials of the first conductive layer 212b and the second conductive layer 212a are two different electrical conductors or semiconductors, such as polysilicon, metal aluminum, and the like.
  • the end of the first conductive layer 212b and the second conductive layer 212a close to the cavity 2113 can be used as the hot end of the thermopile; the first conductive layer 212b and the second conductive layer 212a are away from the cavity One side of 2113 is used as the cold end of the thermopile.
  • the first electrical connection layer of the first chip 210 a may include a first electrical bonding point 24 and a first encapsulation ring 25 .
  • the first conductive layer 212b and the second conductive layer 212a can be electrically connected to the second chip through the first electrical bonding point 24 for signal transmission.
  • the material of the first electrical bonding point 24 may be germanium or gold.
  • the material of the first encapsulation ring 25 may be the same as or different from the first electrical bond 24 .
  • the optical system 2102 can be directly integrated on the first surface 2121 of the first chip 210a away from the first electrical bonding point, for receiving and filtering effective infrared radiation from the outside.
  • the optical system integrated on the first surface 2121 of the first chip 210a may be other optical structures capable of filtering light and receiving effective radiation.
  • a layer of grating material 2101 may be deposited on a first surface 2121 of a substrate 2111 of a first chip 210 a and patterned to form a grating 2102 .
  • the grating material 2101 may be a metal such as aluminum, or a non-metallic material.
  • the optical system of the first surface 2221 of the substrate 2211 of the first chip 220a may be a grating structure 2202 formed after further etching the substrate 2211 by an etching process.
  • the first surface 2321 of the substrate 2311 of the first chip 230 a may also be processed to form a lens such as a fresnel lens 2302 , as shown in FIG. 2C .
  • the optical structure 2102 can focus the incident infrared rays into the infrared thermopile and the cavity 2113 of the first chip 210a, and deposit
  • the metal layer 2101 of the first surface 2121 limits the field viewing angle of the effective infrared absorption region, reflects the incident light irradiated to the non-transparent region, that is, the metal layer 2101, back into the atmosphere, and confines the incident light to the effective light-transmitting region, thereby further
  • the infrared absorptivity is enhanced, thereby improving the test accuracy and efficiency of the MEMS thermopile infrared detector.
  • Fig. 3 is a schematic cross-sectional view of a second chip in the integrated MEMS thermopile infrared detector chip according to an embodiment of the present application.
  • the second chip 30 b may include a substrate 382 and an integrated circuit structure 381 under the substrate 382 .
  • the lower surface of the substrate 382 serves as the first surface 323 of the second chip 30b
  • the upper surface of the integrated circuit structure 381 is coupled and fixed to the first surface 323
  • the upper surface of the substrate 382 serves as the second surface of the second chip 30b.
  • Surface 324 is a schematic cross-sectional view of a second chip in the integrated MEMS thermopile infrared detector chip according to an embodiment of the present application.
  • the second chip 30 b may include a substrate 382 and an integrated circuit structure 381 under the substrate 382 .
  • the lower surface of the substrate 382 serves as the first surface 323 of the second chip 30b
  • the upper surface of the integrated circuit structure 381 is coupled and fixed to the first surface 323
  • the second chip 30 b may further include a conductive via 330 penetrating the substrate 382 , which is opened on the second surface 324 of the substrate, and whose other end is coupled to the integrated circuit structure 381 .
  • the conductive via 330 may be filled with a conductive material 331 and an insulating layer 332 (such as silicon oxide) disposed between the sidewall of the conductive via 330 and the conductive material 331 .
  • One end of the conductive material 331 is electrically connected to the integrated circuit structure 381 .
  • the second chip 30b may further include a mask layer 383 located above the second surface 324, the mask layer 383 may cover the second surface 324 for protecting the chip, and at the same time be patterned above the conductive via 330 An opening is provided for realizing electrical connection between the conductive material 331 and an external circuit.
  • the second chip 30 b may further include a patterned metal conductive layer 384 located above the mask layer 383 and electrically connected to the conductive material 331 in the conductive via 330 .
  • the second chip 30 b may further include a passivation layer 385 located above the conductive metal layer 384 , and the passivation layer 385 has an opening above the conductive metal layer 384 .
  • the optional second chip 30b may further include metal balls 386 formed in the openings of the passivation layer 385 electrically connected to the metal conductive layer 384, and the metal balls 386 may be used to electrically connect with external circuits.
  • the metal conductive layer or the metal ball can be used as the lead-out electrode of the second chip.
  • the second chip 30 b may further include a second electrical connection layer for bonding, and the second electrical connection layer may include a second electrical bonding point 36 and a second packaging ring 37 .
  • 4A to K are part of the manufacturing flow chart of the integrated MEMS thermopile infrared detector chip according to an embodiment of the present application.
  • 5A to D are flowcharts of a method for manufacturing an integrated MEMS thermopile infrared detector chip according to an embodiment of the present application. The following is only an example of a method. Those skilled in the art know that the sequence of operations or steps in the method is not completely fixed, but can be adjusted as required.
  • a first chip is prepared, and the first chip is a MEMS infrared thermopile sensor chip.
  • preparing the first chip may include: (the existing process of forming a MEMS thermopile infrared detector chip will not be repeated here)
  • step 511 a grating material is deposited on the first surface of the first chip, the first surface of the first chip being the surface away from the first electrical bonding point.
  • an optical system such as a grating or mirror, is formed on the first surface of the first chip using the deposited grating material.
  • the grating may be formed by patterning the grating material, or may be formed by etching the substrate of the first chip.
  • Step 513 forming a first electrical bonding point and a first packaging ring on the second surface of the first chip close to the infrared thermopile for electrical connection and bonding.
  • the first electrical bonding point is electrically connected with the infrared thermopile.
  • a second chip is prepared, and the second chip is an integrated circuit chip.
  • preparing the second chip may include:
  • step 521 as shown in FIG. 4A , a groove that can serve as a conductive via 430 is formed on the first surface 401 of the substrate 422 .
  • step 522 as shown in FIG. 4B , an insulating layer 432 is formed in the conductive via 430 , and an insulating material is formed on the first surface 401 of the substrate 422 outside the opening of the conductive via 430 .
  • the conductive via 430 is filled with a conductive material 431 .
  • step 524 integrated circuit structure 421 is formed on first surface 401 of substrate 422 as shown in FIG. 4D .
  • Conductive material 431 is electrically connected to integrated circuit structure 421 .
  • a metal layer is formed on the surface of the integrated circuit structure 421 away from the conductive via, and it is patterned to form a second electrical bonding point 416 and a second packaging ring 417 for electrical connection and Bond.
  • the second electrical bond 416 is electrically connected to the output location of the integrated circuit structure 421 .
  • step 530 as shown in FIG. 4F, the first chip 40a and the second chip 40b are bonded.
  • the first electrical bonding point 414 is electrically bonded to the second electrical bonding point 416
  • the first package ring 415 is bonded to the second package ring 417 .
  • the second surface of the second chip can be treated, including:
  • step 541 as shown in FIG. 4G, the second surface 402 is thinned, so that the second surface 402 of the substrate 422 can expose the conductive via 430, and the conductive via 430 is located at the opening of the second surface 402 without an insulating layer. cover.
  • it can be realized by CMP (Chemical Mechanical Polishing, chemical mechanical polishing) thinning method.
  • the second chip can be thinned before or after bonding.
  • step 542 the thinned second surface 402 of the substrate 422 is oxidized to form a silicon oxide insulating layer 423 as a mask, and the mask 423 is patterned to expose the conductive via 430 .
  • the conductive material is continuously filled into the conductive via 430 so that the opening on the second surface 402 is flush with the mask layer 423 .
  • step 543 deposit a layer of metal conductive layer 424 on the mask layer 423 and electrically connect with the conductive via 430, the metal conductive layer 424 covers the opening of the conductive via 430 on the second surface 402, Make an electrical connection.
  • the metal conductive layer 424 is patterned so that the metal conductive layers 424 connecting the conductive vias 430 are disconnected from each other.
  • the above-mentioned deposition process may adopt various processes, such as common processes such as low pressure chemical vapor deposition (LPCVD), plasma chemical vapor deposition (PECVD) or thermal oxidation.
  • LPCVD low pressure chemical vapor deposition
  • PECVD plasma chemical vapor deposition
  • thermal oxidation thermal oxidation
  • a passivation layer 425 is deposited on the metal conductive layer 424 to protect the surface of the second chip 40b.
  • the material of the passivation layer can be silicon oxide or silicon nitride to play a role.
  • the function of shielding the surface of the metal conductive layer 424 from external interference is to prevent the metal conductive layer 424 from being damaged due to corrosion, oxidation, aging and the like.
  • photolithography is performed on the passivation layer 425 to form a plurality of openings on the second surface 402, so that a plurality of metal conductive layers 424 disconnected from each other are exposed in the openings of the passivation layer 425 for communicating with the outside.
  • the circuit is electrically connected.
  • step 545 as shown in FIG. 4K, metal balls 426 are planted on the metal conductive layer 424 exposed in the opening of the passivation layer 425 after photolithography for electrical connection with the external circuit, and finally the integrated MEMS thermoelectric after bonding
  • the structure of the stack infrared detector chip is shown in Figure 1.
  • the occupied space of the integrated MEMS chip can be greatly saved, the volume of the MEMS chip can be reduced, and the influence of the wire-bonding process connection circuit on the MEMS chip can be reduced at the same time.
  • the cost of the packaged optical system is reduced, the manufacturing process of the MEMS chip is reduced, and at the same time, the problem of low sensor sensitivity caused by the inability of the optical system to align with the sensitive components caused by the packaged optical system is effectively avoided.
  • the integrated MEMS chip design adopted in this application can also shorten the distance from the external effective radiation entering the MEMS chip to reach the sensitive parts, improve the problems of reflection, radiation or attenuation during the storage process of infrared signals entering the MEMS chip, and improve the chip's sensitivity to infrared radiation.
  • the absorption efficiency improves the accuracy of the MEMS chip.

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Mechanical Engineering (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Hydrology & Water Resources (AREA)
  • Environmental & Geological Engineering (AREA)
  • Water Supply & Treatment (AREA)
  • Chemical & Material Sciences (AREA)
  • Organic Chemistry (AREA)
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  • Filtration Of Liquid (AREA)
  • Photometry And Measurement Of Optical Pulse Characteristics (AREA)

Abstract

本申请涉及一种集成MEMS热电堆红外探测器芯片，包括彼此电气键合的第一芯片和第二芯片；其中所述第一芯片为微机电系统红外热电堆传感器芯片，所述第二芯片为集成电路芯片；位于所述第一芯片上的第一电气键合点与位于所述第二芯片上的第二电气键合点彼此键合形成电连接；位于所述第一芯片上的第一封装环和位于所述第二芯片上的第二封装环彼此键合而形成空腔；以及所述第一芯片包括红外热电堆，并且至少部分所述红外热电堆在所述第一芯片表面的投影位于所述空腔内。本申请还涉及一种集成MEMS热电堆红外探测器芯片的制作方法。

Description

一种集成MEMS热电堆红外探测器芯片以及芯片制作方法 技术领域
本申请涉及一种MEMS(微机电系统)技术领域，特别地涉及一种集成MEMS热电堆红外探测器芯片以及芯片制作方法。
背景技术
随着近年来技术的飞速发展，微机电技术通过采用先进的半导体制造工艺，实现微机电系统器件的批量制造，成为了一种主流的高新技术。此外，和传统制造技术相比，微机电技术制备的器件在体积、功耗、价格及重量等方面都有着显著的优势，因此采用先进的微机电系统制作器件是未来技术发展的主要方向。
微机电系统器件一般包括至少一种敏感的活动部件，因此在制造过程中需要利用封装等技术对敏感部件进行保护。此外，微机电系统器件中除了敏感部件，还要与集成电路电连接以形成一个完整的系统。因此在制作工艺中，如何实现系统的集成化是个重要的问题。目前常见的集成方案包括将独立的微机电器件和集成电路封装在同一管壳内进行多芯片集成化，但在封装过程中，多芯片集成化封装需要先将独立的微机电器件和集成电路芯片相邻安装在同一基板上，再通过引线将两部分电连接，最后用管壳封装完成集成。两个独立器件之间较长的引线会对器件整体引入较大的干扰，从而影响器件的整体性能。
在微机电器件中，红外热电堆传感器是最为常用的传感器件之一。红外热电堆传感器是一种利用热电堆接收红外辐射，将红外信号转化为电信号的非接触型热传感器。其红外接收膜即热电堆就是一种敏感部件，在制造红外热电堆芯片的过程中需要格外注意规避影响热电堆的性能的工艺。目前传统的微机电红外 热电堆封装一般采用金属管壳封装，红外热电堆芯片置于管座上，分立的用于过滤有效红外辐射的光学系统置于管帽上。但这种封装结构使得器件的整体体积较大，可应用场景受到限制，滤光光学系统也增加了器件的成本。光学系统分立在对准也会影响外界红外辐射到达热电堆器件敏感部件的有效性，从而降低器件的灵敏度与准确性。
除了上述在封装的设计过程中出现的问题，传统的半导体封装设备不能直接用于微机电器件的封装，且与现有的半导体封装测试设备不能很好兼容带来成本高昂的问题；传统封装工艺的真空密闭性较差同时会对敏感部件的保护造成影响。除此之外还有器件封装体积大、打线工艺造成封装形式占用空间大等问题。
微型化、集成化和低成本已经成为微机电器件封装的必然发展趋势，因此，如何解决现有技术的缺点并且实现小型化低成本集成化方案已成为亟待解决的课题。
发明内容
针对现有技术中存在的技术问题，本申请提出了一种集成MEMS热电堆红外探测器芯片，包括彼此电气键合的第一芯片和第二芯片；其中所述第一芯片为微机电系统红外热电堆传感器芯片，所述第二芯片为集成电路芯片；位于所述第一芯片上的第一电气键合点与位于所述第二芯片上的第二电气键合点彼此键合形成电连接；位于所述第一芯片上的第一封装环和位于所述第二芯片上第二封装环彼此键合形成空腔；以及所述第一芯片包括红外热电堆，并且至少部分所述红外热电堆在所述第一芯片表面的投影位于所述空腔内。
特别的，所述空腔为密闭空腔。
特别的，所述第一电气键合点比所述第一封装环更靠近所述红外热电堆。
特别的，所述第一芯片的第一表面上形成有光学系统，所述第一芯片的第一 表面为远离所述第一电气键合点的表面。
特别的，所述光学系统包括，在所述第一芯片的第一表面上形成的光栅。
特别的，所述光学系统包括，经刻蚀所述第一芯片衬底形成的位于其第一表面的光栅。
特别的，所述光学系统包括，形成于所述第一芯片第一表面上的镜片。
特别的，所述第二芯片包括衬底和集成电路结构，所述集成电路结构的一端通过所述第二电气键合点与所述第一芯片电连接，所述集成电路结构的另一端通过贯穿所述衬底的导电通孔中的导电材料与外部电路电连接。
本申请还提出了一种制备集成MEMS热电堆红外探测器芯片的方法，包括制备第一芯片，所述第一芯片为微机电系统红外热电堆传感器芯片；制备第二芯片，所述第二芯片为集成电路芯片；利用电气键合方式键合第一芯片和第二芯片，在所述第一和第二芯片之间通过位于所述第一芯片上的第一封装环和位于所述第二芯片上的第二封装环彼此键合形成空腔；其中所述第一芯片包括红外热电堆，并且至少部分所述红外热电堆在所述第一芯片表面的投影位于所述第一芯片和第二芯片之间的空腔内。
特别的，制备所述第一芯片包括，在所述第一芯片的第一表面淀积金属层，所述第一芯片的第一表面是远离所述第一电气键合点的表面；图形化所述金属层，形成光栅。
特别的，制备所述第一芯片包括，对所述第一芯片的第一表面所在的衬底进行刻蚀形成光栅。
特别的，制备所述第一芯片包括，在所述第一芯片的第一表面形成镜片。
特别的，制备所述第二芯片包括在所述第二芯片的衬底中形成导电通孔，并且在其中填充导电材料，其中所述导电通孔开口于所述第二芯片的第一表面；所述第二芯片的第一表面上形成集成电路结构，所述导电通孔的第一端与所述集成电路结构电连接。
特别的，制备所述第二芯片包括对所述第二芯片的衬底自第二表面进行减薄，露出所述导电通孔的第二端，其中所述第二芯片衬底的第二表面是与其第一表面相反的表面；形成与所述导电通孔第二端电连接的引出电极。
采用本申请的方案，可以大幅节省集成热电堆红外探测器的占用空间，缩小热电堆红外探测器的体积，同时减少打线工艺连接电路对芯片造成的影响。同时由于光学系统的直接集成，降低了封装光学系统的成本，减少了热电堆红外探测器的制造工序，同时有效避免了封装光学系统造成的光学系统无法对准敏感部件造成的传感器灵敏度低的问题。此外，本申请采用的集成热电堆红外探测器芯片设计还可以缩短外界有效辐射射入热电堆红外探测器芯片到达敏感部件的距离，改善红外信号射入热电堆红外探测器芯片被储存过程中的反射、辐射或衰减等问题，提高芯片对红外的吸收效率，提高热电堆红外探测器的准确度。
附图说明
下面，将结合附图对本申请的优选实施方式进行进一步详细的说明，其中：
图1是根据本申请一个实施例的集成MEMS热电堆红外探测器芯片的剖面示意图；
图2A至C是根据本申请不同实施例的集成MEMS热电堆红外探测器芯片中第一芯片的剖面示意图；
图3是根据本申请一个实施例的集成MEMS热电堆红外探测器芯片中第二芯片的剖面示意图；
图4A至K是根据本申请一个实施例的集成MEMS热电堆红外探测器芯片部分制造流程图；以及
图5A至D是根据本申请一个实施例的制备集成MEMS热电堆红外探测器芯片制造方法流程图。
具体实施方式
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在以下的详细描述中，可以参看作为本申请一部分用来说明本申请的特定实施例的各个说明书附图。在附图中，相似的附图标记在不同图式中描述大体上类似的组件。本申请的各个特定实施例在以下进行了足够详细的描述，使得具备本领域相关知识和技术的普通技术人员能够实施本申请的技术方案。应当理解，还可以利用其它实施例或者对本申请的实施例进行结构、逻辑或者电性的改变。在本文中“上方”可表示彼此接触或不接触的上下相对位置关系。
图1是根据本申请一个实施例的集成MEMS热电堆红外探测器芯片的剖面示意图。如图1所示，集成MEMS热电堆红外探测器芯片包括彼此电气键合连接的第一芯片10a和第二芯片10b，第一芯片10a和第二芯片10b之间通过键合形成空腔。
根据一个实施例，第一芯片10a可以为微机电系统红外热电堆传感器芯片，可以用于感知外部温度的变化量，其至少包括红外热电堆112和第一电气连接层，其中第一电气连接层可以用于和第二芯片10b进行电连接。根据一个实施例，第一电气连接层可以包括第一电气键合点14和第一封装环15。
根据一个实施例，第二芯片10b可以为集成电路芯片，其可以分别与第一芯片和外部电路电连接，配置为接收第一芯片10a的检测结果并进行信号处理，并将根据温度变化转化而成的电信号输出给外部电路。第二芯片10b至少包括集成电路结构181和第二电气连接层，第二电气连接层可以包括第二电气键合点16和第二封装环17。
根据本申请的一个实施例，可以通过第一封装环15和第二封装环17的键 合在第一芯片10a与第二芯片10b之间形成空腔12。根据一个实施例，至少部分红外热电堆112在第一芯片10a靠近空腔12的表面的投影位于所述空腔12内，可对第一芯片10a尤其红外热电堆112起到保护作用，避免外界环境对第一芯片10a的干扰。另一方面，可以利用第一电气键合点14和第二电气键合点16的电气键合建立第一芯片10a与第二芯片10b的电连接，将第一芯片的红外热电堆112产生的信号传递给集成电路结构181，进行相应的处理。
根据本申请的一个实施例，第一芯片10a与第二芯片10b之间形成的空腔12可以是密闭的。密闭的空腔12可对第一芯片10a尤其是红外热电堆112起到更好地避免外界干扰的作用。
根据本申请的一个实施例，如图1所示，第一电气键合点14可以比第一封装环15更靠近红外热电堆112。
根据本申请的一个实施例，第二芯片10b的第二电气键合点16和第二封装环17的制备材料选择与第一芯片10a的第一电气键合点14和第一封装环15的制备材料相关。当第一电气键合点14和第一封装环15的材料包括锗时，第二电气键合点16和第二封装环17的材料可以包括铝；当第一电气键合点14和第一封装环15的材料包括金时，第二电气键合点16和第二封装环17的材料可以包括多晶硅。这样的组合可以使得电气键合点和封装环的厚度最薄，从而减少集成MEMS热电堆红外探测器芯片的整体体积。
图2A至2C所示为根据本申请不同实施例的集成MEMS热电堆红外探测器芯片中第一芯片的剖面示意图。
如图2A所示，第一芯片210a可以包括衬底例如硅衬底2111，衬底2111中可以包括腔体2113、位于衬底2111和腔体2113上方的支撑部214、位于支撑部214上方的热电堆(其中，热电堆可以包括彼此电连接的第一导电层212b和第二导电层212a)、位于支撑部214和热电堆第一导电层212b上方的绝缘层215、位于绝缘层215和热电堆第二导电层212a上方的钝化层216，以及位于钝化层 216上方的第一电气连接层。
根据一个实施例，第一导电层212b和第二导电层212a的材料为两种不同的电导体或半导体，如多晶硅、金属铝等。根据一个实施例，如图2A所示，第一导电层212b与第二导电层212a靠近腔体2113的一端可以作为热电堆的热端；第一导电层212b与第二导电层212a远离腔体2113的一侧作为热电堆冷端。
根据一个实施例，第一芯片210a的第一电气连接层可以包括第一电气键合点24和第一封装环25。第一导电层212b与第二导电层212a例如可以分别通过第一电气键合点24与第二芯片电连接进行信号传输。根据一个实施例，第一电气键合点24的材料可以是锗或者金。根据其他实施例，第一封装环25的材料可与第一电气键合点24相同或不同。
根据一个实施例，如图2A所示，光学系统2102可直接集成在第一芯片210a的远离第一电气键合点的第一表面2121，用于接收并过滤外界的有效红外辐射。根据本申请的其他实施例，集成在第一芯片210a第一表面2121的光学系统可以为可实现滤光和接收有效辐射的其他光学结构。
如图2A所示，可以在第一芯片210a的衬底2111第一表面2121上沉积一层光栅材料2101，并对其进行图案化形成光栅2102。根据本申请的一个实施例，光栅材料2101可以为金属例如铝，也可以为非金属材料。
根据另一个实施例，如图2B所示，第一芯片220a的衬底2211第一表面2221的光学系统可以为利用刻蚀工艺对衬底2211进一步刻蚀以后制成的光栅结构2202。
根据又一个实施例，如图2C所示，还可以对第一芯片230a的衬底2311的第一表面2321进行加工，形成镜片例如fresnel镜片2302，如图2C所示。
图2A至C中所示的光学结构作用原理相同，如图2A所示，光学结构2102可以将入射红外线聚焦到第一芯片210a的红外热电堆及腔体2113中，同时第一表面2121上沉积的金属层2101对第一表面2121有效红外吸收区的场视角进 行限制，将照射到非透光区即金属层2101的入射光反射回大气中，将入射光限制在有效透光区，从而进一步增强红外吸收率，从而提高所述MEMS热电堆红外探测器的测试精确度与效率。
图3是根据本申请一个实施例的集成MEMS热电堆红外探测器芯片中第二芯片的剖面示意图。如图3所示，第二芯片30b可以包括衬底382，以及衬底382下方的集成电路结构381。根据一个实施例，衬底382的下表面作为第二芯片30b的第一表面323，集成电路结构381的上表面与第一表面323耦合固定，衬底382的上表面作为第二芯片的第二表面324。
根据一个实施例，第二芯片30b还可以包括贯穿衬底382的导电通孔330，其开口于衬底第二表面324，另一端与集成电路结构381耦合。根据一个实施例，导电通孔330中可以填充有导电材料331和设置在导电通孔330侧壁与导电材料331之间的绝缘层332(如：氧化硅)。导电材料331的一端与集成电路结构381电连接。
根据一个实施例，第二芯片30b还可以包括位于第二表面324上方的掩膜层383，掩膜层383可以覆盖第二表面324用于保护芯片，同时经过图形化后在导电通孔330上方设有开口，用于实现导电材料331与外部电路的电连接。
根据一个实施例，第二芯片30b还可以包括位于掩膜层383上方的经图形化的金属导电层384，与导电通孔330中的导电材料331电连接。
根据一个实施例，第二芯片30b还可以包括位于金属导电层384上方的钝化层385，钝化层385在金属导电层384上方设有开口。根据一个实施例，可选择的第二芯片30b还可以包括与金属导电层384电连接的在钝化层385的开口中形成的金属球386，金属球386可用于与外部电路电连接。根据一个实施例，金属导电层或金属球可以作为第二芯片的引出电极。
根据一个实施例，第二芯片30b还可以包括进行键合的第二电气连接层，第二电气连接层可以包括第二电气键合点36和第二封装环37。
图4A至K是根据本申请一个实施例的集成MEMS热电堆红外探测器芯片部分制造流程图。图5A至D为根据本申请一个实施例的制备集成MEMS热电堆红外探测器芯片制造方法流程图。以下只是一种方法的实施例，本领域技术人员知晓的，该方法中的各操作或步骤的前后顺序并不是完全固定不变的，而是可以根据需要调整的。
在步骤510，制备第一芯片，所述第一芯片为微机电系统红外热电堆传感器芯片。
根据一个实施例，如图5B所示，制备第一芯片可以包括：(形成MEMS热电堆红外探测器芯片的现有工艺在此不再赘述)
在步骤511，在第一芯片的第一表面淀积光栅材料，第一芯片的第一表面是远离第一电气键合点的表面。
在步骤512，在第一芯片的第一表面利用淀积的光栅材料形成光学系统，例如光栅或者镜片。根据不同的实施例，光栅可以是通过对光栅材料的图形化形成的，或者可以是通过对第一芯片的衬底刻蚀形成的。
步骤513，在第一芯片靠近红外热电堆的第二表面形成第一电气键合点和第一封装环，用于电连接和键合。其中，第一电气键合点与红外热电堆电连接。
在步骤520，制备第二芯片，所述第二芯片为集成电路芯片。如图5C所示，制备第二芯片可以包括：
在步骤521，如图4A所示，在衬底422的第一表面401形成可以作为导电通孔430的凹槽。
在步骤522，如图4B所示，在导电通孔430中形成绝缘层432,并且在导电通孔430开口以外的衬底422的第一表面401上形成绝缘材料。
在步骤523，使用导电材料431填平导电通孔430。
在步骤524，如图4D所示，在衬底422的第一表面401上形成集成电路结构421。导电材料431与集成电路结构421电连接。
在步骤525，根据图4E所示，在集成电路结构421远离导电通孔的表面形成金属层，并对其进行图形化形成第二电气键合点416和第二封装环417，用于电连接和键合。第二电气键合点416与集成电路结构421的输出位置电连接。
在步骤530，如图4F所示，键合第一芯片40a与第二芯片40b。其中第一电气键合点414与第二电气键合点416电气键合，第一封装环415和第二封装环417键合。
可选择的，在完成第一芯片40a和第二芯片40b的键合后，在步骤540，可以对第二芯片的第二表面进行处理，包括：
在步骤541，如图4G所示，对第二表面402进行减薄，使衬底422的第二表面402可以露出导电通孔430，导电通孔430位于第二表面402的开口处没有绝缘层覆盖。根据一个实施例，可以通过CMP(Chemical Mechanical Polishing，化学机械抛光)的减薄方式来实现。根据一个实施例，可以在键合前或后对第二芯片进行减薄。
在步骤542，根据图4H，对减薄后的衬底422第二表面402进行氧化，形成一层氧化硅绝缘层423作为掩膜，并图形化掩膜423露出导电通孔430。向导电通孔430继续填充导电材料，使其位于第二表面402的开口与掩膜层423平齐。
在步骤543，如图4I所示，在掩膜层423上方淀积一层金属导电层424与导电通孔430电连接，金属导电层424覆盖导电通孔430位于第二表面402上的开口，形成电连接。图形化金属导电层424，使连接各导电通孔430的金属导电层424彼此断开。上述淀积工艺可以采用多种工艺，如低压化学气相沉积(LPCVD)、等离子体化学气相沉积(PECVD)或者热氧化等常见工艺。
在步骤544，如图4J所示，在金属导电层424之上淀积一层钝化层425用于保护第二芯片40b的表面，钝化层材料可以为氧化硅或氮化硅，起到对金属导电层424表面的屏蔽外界干扰的作用，以防止金属导电层424因腐蚀、氧化、 老化等作用遭到破坏。根据一个实施例，对钝化层425进行光刻，在第二表面402上形成多个开口，使多个彼此断开的金属导电层424在钝化层425的开口中露出，用于与外部电路电连接。
在步骤545，如图4K所示，在光刻后的钝化层425开口中裸露出的金属导电层424上种植金属球426，用于与外部电路电连接，最终键合后的集成MEMS热电堆红外探测器芯片结构如图1所示。
采用本申请的方案，可以大幅节省集成MEMS芯片的占用空间，缩小MEMS芯片的体积，同时减少打线工艺连接电路对MEMS芯片造成的影响。同时由于光学系统的直接集成，降低了封装光学系统的成本，减少了MEMS芯片的制造工序，同时有效避免了封装光学系统造成的光学系统无法对准敏感部件造成的传感器灵敏度低的问题。此外，本申请采用的集成MEMS芯片设计还可以缩短外界有效辐射射入MEMS芯片到达敏感部件的距离，改善红外信号射入MEMS芯片被储存过程中的反射、辐射或衰减等问题，提高芯片对红外的吸收效率，提高MEMS芯片的准确度。
上述实施例仅供说明本申请之用，而并非是对本申请的限制，有关技术领域的普通技术人员，在不脱离本申请范围的情况下，还可以做出各种变化和变型，因此，所有等同的技术方案也应属于本申请公开的范畴。

Claims (14)

  1. 一种集成MEMS热电堆红外探测器芯片，包括：
    彼此电气键合的第一芯片和第二芯片；其中所述第一芯片为微机电系统红外热电堆传感器芯片，所述第二芯片为集成电路芯片；
    位于所述第一芯片上的第一电气键合点与位于所述第二芯片上的第二电气键合点彼此键合形成电连接；位于所述第一芯片上的第一封装环和位于所述第二芯片上的第二封装环彼此键合而形成空腔；以及
    所述第一芯片包括红外热电堆，并且至少部分所述红外热电堆在所述第一芯片表面的投影位于所述空腔内。
  2. 如权利要求1所述的集成MEMS热电堆红外探测器芯片，其中
    所述空腔为密闭空腔。
  3. 如权利要求1或2所述的集成MEMS热电堆红外探测器芯片，其中
    所述第一电气键合点比所述第一封装环更靠近所述红外热电堆。
  4. 如权利要求1所述的集成MEMS热电堆红外探测器芯片，其中
    所述第一芯片的第一表面上形成有光学系统，所述第一芯片的第一表面为远离所述第一电气键合点的表面。
  5. 如权利要求4所述的集成MEMS热电堆红外探测器芯片，其中
    所述光学系统包括，在所述第一芯片的第一表面上形成的光栅。
  6. 如权利要求4所述的集成MEMS热电堆红外探测器芯片，其中
    所述光学系统包括，经刻蚀所述第一芯片衬底形成的位于所述第一芯片第一表面的光栅。
  7. 如权利要求4所述的集成MEMS热电堆红外探测器芯片，其中
    所述光学系统包括，形成于所述第一芯片第一表面上的镜片。
  8. 如权利要求1所述的集成MEMS热电堆红外探测器芯片，其中
    所述第二芯片包括衬底和集成电路结构，所述集成电路结构的一端通过所述第二电气键合点与所述第一芯片电连接，所述集成电路结构的另一端通过贯 穿所述衬底的导电通孔中的导电材料与外部电路电连接。
  9. 一种集成MEMS热电堆红外探测器芯片的制作方法，包括
    制备第一芯片，所述第一芯片为微机电系统红外热电堆传感器芯片；
    制备第二芯片，所述第二芯片为集成电路芯片；
    利用电气键合方式键合第一芯片和第二芯片，在所述第一芯片和第二芯片之间通过位于所述第一芯片上的第一封装环和位于所述第二芯片上的第二封装环彼此键合形成空腔；其中所述第一芯片包括红外热电堆，并且至少部分所述红外热电堆在所述第一芯片表面的投影位于所述第一芯片和第二芯片之间的空腔内。
  10. 如权利要求9所述的方法，其中
    制备所述第一芯片包括，
    在所述第一芯片的第一表面淀积金属层，所述第一芯片的第一表面是远离所述第一电气键合点的表面；
    图形化所述金属层，形成光栅。
  11. 如权利要求9所述的方法，其中
    制备所述第一芯片包括，
    对所述第一芯片的第一表面所在的衬底进行刻蚀形成光栅。
  12. 如权利要求9所述的方法，其中
    制备所述第一芯片包括，
    在所述第一芯片的第一表面形成镜片。
  13. 如权利要求9所述的方法，其中
    制备所述第二芯片包括：
    在所述第二芯片的衬底中形成导电通孔，并且在其中填充导电材料，其中所述导电通孔的第一端开口于所述第二芯片衬底的第一表面；
    所述第二芯片衬底的第一表面上形成集成电路结构，所述导电通孔的第一端与所述集成电路结构电连接。
  14. 如权利要求9所述的方法，还包括
    制备所述第二芯片包括：
    对所述第二芯片衬底自所述第二表面进行减薄，露出所述导电通孔的第二端，其中所述第二芯片衬底的第二表面是与其第一表面相反的表面；以及
    形成与所述导电通孔第二端电连接的引出电极。
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102583220A (zh) * 2012-03-29 2012-07-18 江苏物联网研究发展中心 一种晶圆级真空封装的红外探测器及其制作方法
CN104140072A (zh) * 2013-05-09 2014-11-12 苏州敏芯微电子技术有限公司 微机电系统与集成电路的集成芯片及其制造方法
CN112117373A (zh) * 2020-06-30 2020-12-22 中芯集成电路（宁波）有限公司上海分公司 热电堆传感器的制作方法
CN113998658A (zh) * 2021-10-28 2022-02-01 苏州敏芯微电子技术股份有限公司 一种集成mems热电堆红外探测器芯片以及芯片制作方法

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CN102583220A (zh) * 2012-03-29 2012-07-18 江苏物联网研究发展中心 一种晶圆级真空封装的红外探测器及其制作方法
CN104140072A (zh) * 2013-05-09 2014-11-12 苏州敏芯微电子技术有限公司 微机电系统与集成电路的集成芯片及其制造方法
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